Am29LV800B
Data Sheet
RETIRED PRODUCT
This product has been retired and is not recommended for designs. For new and current designs, S29AL008D supersedes Am29LV800B and is the factory-recommended migration path. Please refer to the S29AL008D datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.
Publication Number 21490
Revision G
Amendment 5
Issue Date May 25, 2005
THIS PAGE LEFT INTENTIONALLY BLANK.
PRELIMINARY Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7 Special Handling Instructions for FBGA Package .. 9 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10 Standard Products ................................................ 10 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 11
Table 1. Am29LV800B Device Bus Operations ..........11
(DRAFT) DQ3: Sector Erase Timer ..................................... 24
Table 2. Write Operation Status ..................................25
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 26 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27 CMOS Compatible ............................................... 27
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) .......................................... 28 Figure 10. Typical ICC1 vs. Frequency ........................ 28
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 11. Test Setup.................................................. 29 Table 3. Test Specifications ........................................29
Word/Byte Configuration ...................................... 11 Requirements for Reading Array Data ................. 11 Writing Commands/Command Sequences .......... 11 Program and Erase Operation Status .................. 12 Standby Mode ...................................................... 12 Automatic Sleep Mode ......................................... 12 RESET#: Hardware Reset Pin ............................. 12 Output Disable Mode ............................................ 12
Table 2. Am29LV800BT Top Boot Block Sector Addresses ........................................................13 Table 3. Am29LV800BB Bottom Boot Block Sector Addresses ........................................................13
Key to Switching Waveforms. . . . . . . . . . . . . . . . 29
Figure 12. Input Waveforms and Measurement Levels ................................................... 29
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30 Read Operations .................................................. 30
Figure 13. Read Operations Timings .......................... 30
Hardware Reset (RESET#) .................................. 31
Figure 14. RESET# Timings........................................ 31
Word/Byte Configuration (BYTE#)
..................... 32
Autoselect Mode ................................................... 14
Table 4. Am29LV800B Autoselect Codes (High Voltage Method) ................................................14
Figure 15. BYTE# Timings for Read Operations......... 32 Figure 16. BYTE# Timings for Write Operations ......... 32
Erase/Program Operations ................................... 33
Figure 17. Program Operation Timings ....................... 34 Figure 18. Chip/Sector Erase Operation Timings........ 35 Figure 19. Data# Polling Timings (During Embedded Algorithms)................................................ 36 Figure 20. Toggle Bit Timings (During Embedded Algorithms)................................................ 36 Figure 21. DQ2 vs. DQ6.............................................. 37
Sector Protection/Unprotection ............................ 14 Temporary Sector Unprotect ................................ 14
Figure 1. Temporary Sector Unprotect Operation....... 15 Figure 2. In-System Sector Protect/ Sector Unprotect Algorithms ....................................... 16
Hardware Data Protection .................................... 17 Command Definitions . . . . . . . . . . . . . . . . . . . . . 17 Reading Array Data .............................................. 17 Reset Command .................................................. 17 Autoselect Command Sequence .......................... 17 Word/Byte Program Command Sequence ........... 18
Figure 3. Program Operation ...................................... 18
Temporary Sector Unprotect ................................ 37
Figure 22. Temporary Sector Unprotect Timing Diagram ........................................................... 37 Figure 23. Sector Protect/Unprotect Timing Diagram ........................................................... 38
Alternate CE# Controlled Erase/Program Operations 39
Figure 24. Alternate CE# Controlled Write Operation Timings ....................................................... 40
Chip Erase Command Sequence ......................... 19 Sector Erase Command Sequence ...................... 19 Erase Suspend/Erase Resume Commands ......... 19
Figure 4. Erase Operation........................................... 20 Table 1. Am29LV800B Command Definitions .............21
Write Operation Status . . . . . . . . . . . . . . . . . . . . 22 DQ7: Data# Polling ............................................... 22
Figure 5. Data# Polling Algorithm ............................... 22
RY/BY#: Ready/Busy# ......................................... 22 DQ6: Toggle Bit I .................................................. 23 DQ2: Toggle Bit II ................................................. 23 Reading Toggle Bits DQ6/DQ2 ............................ 23 DQ5: Exceeded Timing Limits .............................. 23
Figure 6. Toggle Bit Algorithm..................................... 24
Erase and Programming Performance . . . . . . . 41 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 41 TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 41 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 42 TS 048—48-Pin Standard TSOP ........................ 42 TSR048—48-Pin Reverse TSOP ........................ 43 FBB 048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm ................................................ 44 SO 044—44-Pin Small Outline Package ............. 45 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46
1
6/1/05
PRELIMINARY
(DRAFT)
6/1/05
2
Am29LV800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
For new designs, S29AL008D supersedes Am29LV800B and is the factory-recommended migration path for this device. Please refer to the S29AL008D Family Datasheet for specifications and ordering information.
DISTINCTIVE CHARACTERISTICS
• Single power supply operation
— 2.7 to 3.6 volt read and write operations for battery-powered applications
• Embedded Algorithms
— Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies data at specified addresses
• Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29LV800 device
• High performance
— Access times as fast as 70 ns
• Minimum 1 million write cycle guarantee per sector • 20-year data retention at 125°C
— Reliable operation for the life of the system
• Ultra low power consumption (typical values at 5 MHz)
— — — — 200 nA Automatic Sleep mode current 200 nA standby mode current 7 mA read current 15 mA program/e+5rase current
• Package option
— — — — 48-ball FBGA 48-pin TSOP 44-pin SO Known Good Die (KGD) (see publication number 21536)
• Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte sectors (byte mode) — One 8 Kword, two 4 Kword, one 16 Kword, and fifteen 32 Kword sectors (word mode) — Supports full chip erase — Sector Protection features:
• Compatibility with JEDEC standards
— Pinout and software compatible with singlepower supply Flash — Superior inadvertent write protection
• Data# Polling and toggle bits
— Provides a software method of detecting program or erase operation completion
A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors • Unlock Bypass Program Command
— Reduces overall programming time when issuing multiple program command sequences
• Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or erase cycle completion
• Erase Suspend/Erase Resume
— Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
• Top or bottom boot block configurations available
• Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array data
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21490 Rev: G Amendment/+5 Issue Date: May 25, 2005
GENERAL DESCRIPTION
The Am29LV800B is an 8 Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The device is also available in Known Good Die (KGD) form. For more information, refer to publication number 21536. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device requires only a single, 3.0 volt VCC supply to perform read, program, and erase operations. A standard EPROM programmer can also be used to program and erase the device. This device is manufactured using AMD’s 0.32 µm process technology, and offers all the features and benefits of the Am29LV800, which was manufactured using 0.5 µm process technology. In addition, the Am29LV800B features unlock bypass programming and in-system sector protection/unprotection. The standard device offers access times of 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal statemachine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. T he s ector erase architecture a llows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the s tandby mode . Power consumption is greatly reduced in both these modes. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
4
Am29LV800B
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7 Special Handling Instructions for FBGA Package .. 9 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10 Standard Products ................................................ 10 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 11
Table 1. Am29LV800B Device Bus Operations ..........11
DQ3: Sector Erase Timer ..................................... 24
Table 2. Write Operation Status ..................................25
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 26 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27 CMOS Compatible ............................................... 27
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) .......................................... 28 Figure 10. Typical ICC1 vs. Frequency ........................ 28
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 11. Test Setup.................................................. 29 Table 3. Test Specifications ........................................29
Word/Byte Configuration ...................................... 11 Requirements for Reading Array Data ................. 11 Writing Commands/Command Sequences .......... 11 Program and Erase Operation Status .................. 12 Standby Mode ...................................................... 12 Automatic Sleep Mode ......................................... 12 RESET#: Hardware Reset Pin ............................. 12 Output Disable Mode ............................................ 12
Table 2. Am29LV800BT Top Boot Block Sector Addresses ........................................................13 Table 3. Am29LV800BB Bottom Boot Block Sector Addresses ........................................................13
Key to Switching Waveforms. . . . . . . . . . . . . . . . 29
Figure 12. Input Waveforms and Measurement Levels ................................................... 29
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30 Read Operations .................................................. 30
Figure 13. Read Operations Timings .......................... 30
Hardware Reset (RESET#) .................................. 31
Figure 14. RESET# Timings........................................ 31
Word/Byte Configuration (BYTE#)
..................... 32
Autoselect Mode ................................................... 14
Table 4. Am29LV800B Autoselect Codes (High Voltage Method) ................................................14
Figure 15. BYTE# Timings for Read Operations......... 32 Figure 16. BYTE# Timings for Write Operations ......... 32
Erase/Program Operations ................................... 33
Figure 17. Program Operation Timings ....................... 34 Figure 18. Chip/Sector Erase Operation Timings........ 35 Figure 19. Data# Polling Timings (During Embedded Algorithms)................................................ 36 Figure 20. Toggle Bit Timings (During Embedded Algorithms)................................................ 36 Figure 21. DQ2 vs. DQ6.............................................. 37
Sector Protection/Unprotection ............................ 14 Temporary Sector Unprotect ................................ 14
Figure 1. Temporary Sector Unprotect Operation....... 15 Figure 2. In-System Sector Protect/ Sector Unprotect Algorithms ....................................... 16
Hardware Data Protection .................................... 17 Command Definitions . . . . . . . . . . . . . . . . . . . . . 17 Reading Array Data .............................................. 17 Reset Command .................................................. 17 Autoselect Command Sequence .......................... 17 Word/Byte Program Command Sequence ........... 18
Figure 3. Program Operation ...................................... 18
Temporary Sector Unprotect ................................ 37
Figure 22. Temporary Sector Unprotect Timing Diagram ........................................................... 37 Figure 23. Sector Protect/Unprotect Timing Diagram ........................................................... 38
Alternate CE# Controlled Erase/Program Operations 39
Figure 24. Alternate CE# Controlled Write Operation Timings ....................................................... 40
Chip Erase Command Sequence ......................... 19 Sector Erase Command Sequence ...................... 19 Erase Suspend/Erase Resume Commands ......... 19
Figure 4. Erase Operation........................................... 20 Table 1. Am29LV800B Command Definitions .............21
Write Operation Status . . . . . . . . . . . . . . . . . . . . 22 DQ7: Data# Polling ............................................... 22
Figure 5. Data# Polling Algorithm ............................... 22
RY/BY#: Ready/Busy# ......................................... 22 DQ6: Toggle Bit I .................................................. 23 DQ2: Toggle Bit II ................................................. 23 Reading Toggle Bits DQ6/DQ2 ............................ 23 DQ5: Exceeded Timing Limits .............................. 23
Figure 6. Toggle Bit Algorithm..................................... 24
Erase and Programming Performance . . . . . . . 41 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 41 TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 41 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 42 TS 048—48-Pin Standard TSOP ........................ 42 TSR048—48-Pin Reverse TSOP ........................ 43 FBB 048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm ................................................ 44 SO 044—44-Pin Small Outline Package ............. 45 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46
Am29LV800B
5
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options Full Voltage Range: VCC = 2.7–3.6 V 70 70 30 -70 90 90 35 Am29LV800B -90 120 120 50 -120
Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE)
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
VCC VSS RESET# RY/BY# Sector Switches Erase Voltage Generator Input/Output Buffers DQ0–DQ15 (A-1)
WE# BYTE#
State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0– A18
6
Am29LV800B
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21536 for more information.
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
Standard TSOP
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Reverse TSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 21490G-1
Am29LV800B
7
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21536 for more information.
RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# VSS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
SO
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
RESET# WE# A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
FBGA Top View, Balls Facing Down
A6 A13 A5 A9 A4 WE# A3 RY/BY# A2 A7 A1 A3
B6 A12 B5 A8 B4 RESET# B3 NC B2 A17 B1 A4
C6 A14 C5 A10 C4 NC C3 A18 C2 A6 C1 A2
D6 A15 D5 A11 D4 NC D3 NC D2 A5 D1 A1
E6 A16 E5 DQ7 E4 DQ5 E3 DQ2 E2 DQ0 E1 A0
F6 BYTE# F5 DQ14 F4 DQ12 F3 DQ10 F2 DQ8 F1 CE#
G6 DQ15/A-1 G5 DQ13 G4 VCC G3 DQ11 G2 DQ9 G1 OE#
H6 VSS H5 DQ6 H4 DQ4 H3 DQ3 H2 DQ1 H1 VSS
8
Am29LV800B
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
PIN CONFIGURATION
A0–A18 = 19 addresses DQ0–DQ14= 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE# CE# OE# WE# RESET# RY/BY# VCC = Selects 8-bit or 16-bit mode = Chip enable = Output enable = Write enable = Hardware reset pin, active low = Ready/Busy# output = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) = Device ground
NC
= Pin not connected internally
LOGIC SYMBOL
19 A0–A18 DQ0–DQ15 (A-1) CE# OE# WE# RESET# BYTE# RY/BY# 16 or 8
VSS
Am29LV800B
9
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
Am29LV800B T -70 E C TEMPERATURE RANGE C = Commercial (0°C to +70°C) D = Commercial (0°C to +70°C) with Pb-free package I = Industrial (–40°C to +85°C) F = Industrial (–40°C to +85°C) with Pb-free package E = Extended (–55°C to +125°C) K = Extended (–55°C to +125°C) with Pb-free package PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048) S = 44-Pin Small Outline Package (SO 044) WB = 48-Ball Fine Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 6 x 9 mm package (FBB048) This device is also available in Known Good Die (KGD) form. See publication number 21536 for more information. SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION Am29LV800B 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory 3.0 Volt-only Read, Program, and Erase
Valid Combinations for TSOP and SO Packages
AM29LV800BT-70, AM29LV800BB-70 AM29LV800BT-90, AM29LV800BB-90 AM29LV800BT-120, AM29LV800BB-120 EC, EI, FC, FI, SC, SI, ED, EF, SD, SF EC, EI, EE, ED, EF FC, FI, FE, SC, SI, SE, SD, SF, EK, SK
Valid Combinations for FBGA Packages Order Number
AM29LV800BT-70, AM29LV800BB-70 AM29LV800BT-90, AM29LV800BB-90 AM29LV800BT-120, AM29LV800BB-120 WBC, WBD, WBI, WBF WBC, WBI, WBD, WBF, WBK, WBE
Package Marking
L800BT70V, L800BB70V L800BT90V, L800BB90V L800BT12V, L800BB12V C, D, I, F
C, I, D, F K, E
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
10
Am29LV800B
DEVICE BUS OPERATIONS
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
Table 1.
Am29LV800B Device Bus Operations
DQ8–DQ15 WE # H L X H X L Addresses (Note 1) AIN AIN X X X Sector Address, A6 = L, A1 = H, A0 = L Sector Address, A6 = H, A1 = H, A0 = L AIN DQ0– DQ7 DOUT DIN High-Z High-Z High-Z DIN BYTE# = VIH DOUT DIN High-Z High-Z High-Z X BYTE# = VIL DQ8–DQ14 = High-Z, DQ15 = A-1 High-Z High-Z High-Z X
Operation Read Write Standby Output Disable Reset Sector Protect (Note 2)
CE# L L VCC ± 0.3 V L X L
OE# L H X H X H
RESET# H H VCC ± 0.3 V H L VID
Sector Unprotect (Note 2) Temporary Sector Unprotect
L X
H X
L X
VID VID
DIN DIN
X DIN
X High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A18:A0 in word mode (BYTE# = VIH), A18:A-1 in byte mode (BYTE# = VIL). 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to Figure 13 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at V IH . The BYTE# pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information.
Am29LV800B
11
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “ Word/Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” s ections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations.
In the DC Characteristics table, ICC3 and ICC4 represents the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram.
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I CC r ead specifications apply. Refer to “ Write Operation Status” for more information, and to “AC Characteristics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed.
Output Disable Mode
12
Am29LV800B
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Table 2. Am29LV800BT Top Boot Block Sector Addresses
Sector Size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 32/16 8/4 8/4 16/8 Address Range (in hexadecimal) (x8) Address Range 00000h–0FFFFh 10000h–1FFFFh 20000h–2FFFFh 30000h–3FFFFh 40000h–4FFFFh 50000h–5FFFFh 60000h–6FFFFh 70000h–7FFFFh 80000h–8FFFFh 90000h–9FFFFh A0000h–AFFFFh B0000h–BFFFFh C0000h–CFFFFh D0000h–DFFFFh E0000h–EFFFFh F0000h–F7FFFh F8000h–F9FFFh FA000h–FBFFFh FC000h–FFFFFh (x16) Address Range 00000h–07FFFh 08000h–0FFFFh 10000h–17FFFh 18000h–1FFFFh 20000h–27FFFh 28000h–2FFFFh 30000h–37FFFh 38000h–3FFFFh 40000h–47FFFh 48000h–4FFFFh 50000h–57FFFh 58000h–5FFFFh 60000h–67FFFh 68000h–6FFFFh 70000h–77FFFh 78000h–7BFFFh 7C000h–7CFFFh 7D000h–7DFFFh 7E000h–7FFFFh
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18
A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1
A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1
A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1
A14 X X X X X X X X X X X X X X X 0 1 1 1
A13 X X X X X X X X X X X X X X X X 0 0 1
A12 X X X X X X X X X X X X X X X X 0 1 X
Table 3.
Am29LV800BB Bottom Boot Block Sector Addresses
Sector Size (Kbytes/ Kwords) 16/8 8/4 8/4 32/16 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Address Range (in hexadecimal) (x8) Address Range 00000h–03FFFh 04000h–05FFFh 06000h–07FFFh 08000h–0FFFFh 10000h–1FFFFh 20000h–2FFFFh 30000h–3FFFFh 40000h–4FFFFh 50000h–5FFFFh 60000h–6FFFFh 70000h–7FFFFh 80000h–8FFFFh 90000h–9FFFFh A0000h–AFFFFh B0000h–BFFFFh C0000h–CFFFFh D0000h–DFFFFh E0000h–EFFFFh F0000h–FFFFFh (x16) Address Range 00000h–01FFFh 02000h–02FFFh 03000h–03FFFh 04000h–07FFFh 08000h–0FFFFh 10000h–17FFFh 18000h–1FFFFh 20000h–27FFFh 28000h–2FFFFh 30000h–37FFFh 38000h–3FFFFh 40000h–47FFFh 48000h–4FFFFh 50000h–57FFFh 58000h–5FFFFh 60000h–67FFFh 68000h–6FFFFh 70000h–77FFFh 78000h–7FFFFh
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18
A18 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A17 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A16 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A15 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A14 0 0 0 1 X X X X X X X X X X X X X X X
A13 0 1 1 X X X X X X X X X X X X X X X X
A12 X 0 1 X X X X X X X X X X X X X X X X
Note for Tables 2 and 3: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section.
Am29LV800B
13
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 4.
Table 4. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Tables 2 and 3). Table 4 shows the remaining address bits that are don’t c are. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 1. This method does not require VID. See “Command Definitions” for details on using the autoselect mode.
Am29LV800B Autoselect Codes (High Voltage Method)
A18 A11 to to WE# A12 A10 H H H H H X X VID X L X L H X X VID X L X L H X X A8 to A7 X A5 to A2 X DQ8 to DQ15 X 22h X 22h X X DQ7 to DQ0 01h DAh DAh 5Bh 5Bh 01h (protected) 00h (unprotected )
Description
Mode
CE# L L L L L
OE# L L L L L
A9 VID
A6 L
A1 L
A0 L
Manufacturer ID: AMD Device ID: Am29LV800B (Top Boot Block) Device ID: Am29LV800B (Bottom Boot Block) Word Byte Word Byte
Sector Protection Verification
L
L
H
SA
X
VID
X
L
X
H
L X
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” f or details. Sector Protection/unprotection can be implemented via two methods. The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 23 shows the timing diagram. This m ethod uses standard microprocessor bus cycle
timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. Publication number 20536 contains further details; contact an AMD representative to request a copy.
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 22 shows the timing diagrams, for this feature.
14
Am29LV800B
START
RESET# = VID (Note 1) Perform Erase or Program Operations
RESET# = VIH
Temporary Sector Unprotect Completed (Note 2)
Notes:
1. All protected sectors unprotected. 2. All previously protected sectors are protected once again.
Figure 1.
Temporary Sector Unprotect Operation
Am29LV800B
15
START PLSCNT = 1 RESET# = VID Wait 1 ms Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address
START PLSCNT = 1 RESET# = VID Wait 1 ms
Temporary Sector Unprotect Mode
No
First Write Cycle = 60h? Yes Set up sector address No
First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address
No
Temporary Sector Unprotect Mode
Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0
Wait 150 μs Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0
Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Reset PLSCNT = 1
Increment PLSCNT
Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0
Read from sector address with A6 = 0, A1 = 1, A0 = 0 No No PLSCNT = 25? Data = 01h?
Increment PLSCNT
Yes
Yes
Read from sector address with A6 = 1, A1 = 1, A0 = 0 No Yes No Data = 00h? Yes Set up next sector address
Device failed
Protect another sector? No Remove VID from RESET#
PLSCNT = 1000? Yes
Device failed Write reset command Sector Unprotect Algorithm
Last sector verified? Yes Remove VID from RESET#
No
Sector Protect Algorithm
Sector Protect complete
Write reset command
Sector Unprotect complete
Figure 2. In-System Sector Protect/ Sector Unprotect Algorithms
16
Am29LV800B
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 1 f or c ommand definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.
prevent unintentional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Low VCC Write Inhibit
When V CC i s less than V LKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V CC i s greater than VLKO . The system must provide the proper signals to the control pins to
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. Table 1 d efines the valid register c ommand sequences. Writing i ncorrect a ddress and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section.
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command. T he reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more information on this mode. The system must issue the reset command to reenable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parameters, and Figure 13 shows the timing diagram.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 1 shows the address and data requirements. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect
Am29LV800B
17
c ommand. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h in word mode (or 02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Tables 2 and 3 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data.
sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles r e q u i r e d i n t h e s t a n d a r d p r o g ra m c o m m a n d sequence, resulting in faster total programming time. Table 1 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data. Figure 3 illustrates the algorithm for the program operation. See the Erase/Program Operations table in “AC Characteristics” for parameters, and to Figure 17 for timing diagrams.
Word/Byte Program Command Sequence
The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is n ot r equired to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 1 shows t he address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See “Write Operation Status” for information on these status bits. A ny commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program ming o perat ion. The progra m comm and sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”.
START
Write Program Command Sequence
Embedded Program algorithm in progress
Data Poll from System
Verify Data?
No
Yes
Increment Address
No
Last Address?
Yes Programming Completed
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command
Note: See Table 1 for program command sequence. Figure 3. Program Operation
18
Am29LV800B
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does n ot r equire the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 1 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a h ardware reset d uring the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See “Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC Characteristics” for parameters, and to Figure 18 for timing diagrams.
between additional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other com mands are ignored. Note that a h ardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to “Write Operation Status” for information on these status bits. Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC Characteristics” section for parameters, and to Figure 18 for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 1 shows the address and data r e q u i r e m e n t s f o r t h e s e c t o r e ra s e c o m m a n d sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. A fter the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together,
Am29LV800B
19
to determine if a sector is actively erasing or is erasesuspended. See “Write Operation Status” for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another v a l i d o p e r a t i o n . S e e “A u t o s e l e c t C o m m a n d Sequence” for more information. The system must write the Erase Resume command (address bits are “don’t care”) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. Notes:
1. See Table 1 for erase command sequence. 2. See “DQ3: Sector Erase Timer” for more information.
START
Write Erase Command Sequence
Data Poll from System Embedded Erase algorithm in progress No Data = FFh?
Yes Erasure Completed
Figure 4.
Erase Operation
20
Am29LV800B
Table 1.
Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Manufacturer ID Autoselect (Note 8) Device ID, Top Boot Block Device ID, Bottom Boot Block Sector Protect Verify (Note 9) Word Byte Word Byte Word Byte Word 4 Byte Word Byte Word Byte 4 3 Cycles
Am29LV800B Command Definitions
Bus Cycles (Notes 2-5) First Second Addr Dat a Third Addr Dat a Fourth Addr Data Fifth Dat Addr a Sixth Addr Dat a Dat a RD F0 AA AA AA 2AA 555 2AA 555 2AA 555 2AA AA 55 555 AA AA A0 90 AA AA B0 30 2AA 555 2AA 555 PA XXX 2AA 555 2AA 555 55 55 PD 00 55 55 555 AAA 555 AAA 80 80 555 AAA 555 AAA AA AA 2AA 555 2AA 555 55 55 555 AAA SA 10 30 AAA 555 AAA 555 AAA A0 20 55 55 55 555 AAA 555 AAA 555 AAA 555 90 90 90 90 X00 X01 X02 X01 X02 (SA) X02 (SA) X04 PA 01 22DA DA 225B 5B XX00 XX01 00 01 PD
Addr RA XXX 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA XXX XXX 555 AAA 555 AAA XXX XXX
1 1 4 4 4
Program Unlock Bypass
Unlock Bypass Program (Note 10) 2 Unlock Bypass Reset (Note 11) Chip Erase Sector Erase Erase Suspend (Note 12) Erase Resume (Note 13) Word Byte Word Byte 2 6 6 1 1
Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18–A12 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operations. 4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles. 5. Address bits A18–A11 are don’t cares for unlock and command cycles, unless PA or SA required. 6. No unlock or command cycles required when reading array data. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 8. The fourth cycle of the autoselect command sequence is a read cycle. 9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information. 10. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. 12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 13. The Erase Resume command is valid only during the Erase Suspend mode.
Am29LV800B
21
WRITE OPERATION STATUS
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 2 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first.
START
Read DQ7–DQ0 Addr = VA
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to prog ra m m i n g d u r i n g E ra s e S u s p e n d . W h e n t h e Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading array data. During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to “1”; prior to this, the device outputs the “complement,” or “0.” The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7–DQ0 on the f ollowing r ead cycles. This is because DQ7 may change asynchronously with DQ0– DQ6 while Output Enable (OE#) is asserted low. Figure 19, Data# Polling Timings (During Embedded Algorithms), in the “AC Characteristics” section illustrates this. Table 2 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm. Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
DQ7 = Data?
Yes
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0 Addr = VA
DQ7 = Data?
Yes
No FAIL PASS
Figure 5. Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC.
22
Am29LV800B
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 2 shows the outputs for RY/BY#. Figures 13, 14, 17 and 18 shows RY/BY# for read, reset, program, and erase operations, respectively.
Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 2 to compare outputs for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the “DQ6: Toggle Bit I” subsection. Figure 20 shows the toggle bit timing diagram. Figure 21 shows the differences between DQ2 and DQ6 in graphical form.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on “DQ7: Data# Polling”). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 2 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm. Figure 20 in the “AC Characteristics” section shows the toggle bit timing diagrams. F igure 21 s hows the differences between DQ2 and DQ6 in graphical form. See also the subsection on “DQ2: Toggle Bit II”.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7– DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase cycle was not successfully completed.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended.
Am29LV800B
23
START
Read DQ7–DQ0
The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.” Under both these conditions, the system must issue the reset command to return the device to reading array data.
(Note
Read DQ7–DQ0
DQ3: Sector Erase Timer
Toggle Bit = Toggle? Yes No
No
DQ5 = 1?
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from “0” to “1.” The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 µs. See also the “Sector Erase Command Sequence” section. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is “1”, the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0”, the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 2 shows the outputs for DQ3.
Yes
Read DQ7–DQ0 Twice
(Notes 1, 2)
Toggle Bit = Toggle?
No
Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. See text.
Figure 6.
Toggle Bit Algorithm
24
Am29LV800B
Table 2. Write Operation Status
Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend-Program DQ7 (Note 2) DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5: Exceeded Timing Limits” for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
Am29LV800B
25
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . .–65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . .–65°C to +125°C Output Short Circuit Current (Note 3) . . . . . 200 mA Notes:
Voltage with Respect to Ground . . . . . . . . . . . . . . . . VCC (Note 1)–0.5 V to +4.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . –0.5 V to +12.5 V . . . . . . All other pins (Note 1)–0.5 V to VCC+0.5 V
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to – 2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8. 2. Minimum DC input voltage on pins A9, OE#, and RESET# is –0.5 V. During voltage transitions, A9, OE#, and RESET# may undershoot VSS to –2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA). . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA). . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA). . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for regulated voltage range . . +3.0 V to +3.6 V VCC for full voltage range . . . . . . +2.7 V to +3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
20 ns +0.8 V –0.5 V –2.0 V
20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns
20 ns
20 ns
Figure 7.
Maximum Negative Overshoot Waveform
Figure 8.
Maximum Positive Overshoot Waveform
26
Am29LV800B
DC CHARACTERISTICS CMOS Compatible
Parameter ILI ILIT ILO Description Input Load Current A9 Input Load Current Output Leakage Current Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC max CE# = VIL, OE# = VIH, Byte Mode CE# = VIL, OE# = VIH, Word Mode CE# = VIL, OE# = VIH CE#, RESET# = VCC±0.3 V RESET# = VSS ± 0.3 V VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V –0.5 0.7 x VCC VCC = 3.3 V IOL = 4.0 mA, VCC = VCC min IOH = –2.0 mA, VCC = VCC min IOH = –100 µA, VCC = VCC min 0.85 VCC VCC–0.4 2.3 2.5 V 11.5 5 MHz 1 MHz 5 MHz 1 MHz 7 2 7 2 15 0.2 0.2 0.2 Min Typ Max ±1.0 35 ±1.0 12 4 12 4 30 5 5 5 0.8 VCC + 0.3 12.5 0.45 mA µA µA µA V V V V V mA Unit µA µA µA
ICC1
VCC Active Read Current (Notes 1, 2)
ICC2 ICC3 ICC4 ICC5 VIL VIH VID VOL VOH1 VOH2 VLKO
VCC Active Write Current (Notes 2, 3, 5) VCC Standby Current (Note 2) VCC Reset Current (Note 2) Automatic Sleep Mode (Notes 2, 4) Input Low Voltage Input High Voltage Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage (Note 4)
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. 5. Not 100% tested.
Am29LV800B
27
DC CHARACTERISTICS (Continued) Zero Power Flash
20 Supply Current in mA
15
10
5
0 0 500 1000 1500 2000 Time in ns
Note: Addresses are switching at 1 MHz Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
2500
3000
3500
4000
10
8 Supply Current in mA 3.6 V 6 2.7 V 4
2
0 1 2 3 Frequency in MHz
Note: T = 25 °C Figure 10. Typical ICC1 vs. Frequency
4
5
28
Am29LV800B
TEST CONDITIONS
3.3
2.7 kΩ
Table 3.
Test Condition
Test Specifications
-70 -90, -120 1 TTL gate 30 5 0.0–3.0 1.5 1.5 100 pF ns V V V Unit
Device Under Test CL 6.2 kΩ
Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels
Note: Diodes are IN3064 or equivalent Figure 11. Test Setup
Output timing measurement reference levels
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS
3.0 V 0.0 V
Input
1.5 V
Measurement Level
1.5 V
Output
Figure 12. Input Waveforms and Measurement Levels
Am29LV800B
29
AC CHARACTERISTICS Read Operations
Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ Std tRC tACC tCE tOE tDF tDF tOEH Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Output Enable Hold Time (Note 1) Read Toggle and Data# Polling CE# = VIL OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Min Min Min Speed Options -70 70 70 70 30 25 25 -90 90 90 90 35 30 30 0 10 0 -120 120 120 120 50 30 30 Unit ns ns ns ns ns ns ns ns ns
tAXQX
tOH
Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1)
Notes:
1. Not 100% tested. 2. See Figure 11 and Table 3 for test specifications.
tRC Addresses CE# tO tOEH WE Outputs RESET# RY/BY# 0V
Figure 13. Read Operations Timings
Addresses Stable tACC
tD
OE#
tCE HIGH Z Output Valid
tO
HIGH Z
30
Am29LV800B
AC CHARACTERISTICS Hardware Reset (RESET#)
Parameter JEDEC Std tREADY tREADY tRP tRH tRPD tRB Description RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) RESET# Pulse Width RESET# High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Test Setup Max Max Min Min Min Min All Speed Options 20 500 500 50 20 0 Unit µs ns ns ns µs ns
Note: Not 100% tested.
RY/BY#
CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#, OE#
RESET# tRP
Figure 14. RESET# Timings
Am29LV800B
31
AC CHARACTERISTICS Word/Byte Configuration (BYTE#)
Parameter JEDEC Std tELFL/tELFH tFLQZ tFHQV Description CE# to BYTE# Switching Low or High BYTE# Switching Low to Output HIGH Z BYTE# Switching High to Output Active Max Max Min 25 70 -70 Speed Options -90 5 30 90 30 120 -120 Unit ns ns ns
CE#
OE#
BYTE# tELFL
BYTE# Switching from word to byte mode
DQ0–DQ14
Data Output (DQ0–DQ14)
Data Output
DQ15/A-1
DQ15 Output tFLQZ tELFH
Address Input
BYTE# BYTE# Switching from byte to word mode
DQ0–DQ14
Data Output Address Input tFHQ
V
Data Output (DQ0–DQ14) DQ15 Output
DQ15/A-1
Figure 15. BYTE# Timings for Read Operations
CE# The falling edge of the last WE# signal WE#
BYTE#
tSET (tAS)
tHOLD (tAH)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. Figure 16. BYTE# Timings for Write Operations
32
Am29LV800B
AC CHARACTERISTICS Erase/Program Operations
Parameter JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX Std tWC tAS tAH tDS tDH tOES tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 tVCS tRB tBUSY Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Programming Operation (Note 2) Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Byte Word Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Min Min Min 35 45 35 -70 70 Speed Options -90 90 0 45 45 0 0 0 0 0 35 30 9 11 0.7 50 0 90 50 50 50 -120 120 Unit ns ns ns ns ns ns ns ns ns ns ns µs sec µs ns ns
Notes:
1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information.
Am29LV800B
33
AC CHARACTERISTICS
Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE# OE# tW WE# tCS tD Data tD PD tBUSY RY/BY# Statu DOUT tRB tWPH tWHWH1 PA PA Read Status Data (last two cycles)
tC
A0h
VCC tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode.
Figure 17. Program Operation Timings
34
Am29LV800B
AC CHARACTERISTICS
Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA 555h for chip erase tA CE# VA VA Read Status Data
OE# tW WE# tCS tD
tC
tWP
tWHWH
tD Data 55h 30h 10 for Chip Erase tBUSY RY/BY# tVC VCC tRB In Progress Complete
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”). 2. Illustration shows device in word mode.
Figure 18.
Chip/Sector Erase Operation Timings
Am29LV800B
35
AC CHARACTERISTICS
tRC dresses VA tACC CE# tCH OE# tOEH WE# tOH DQ7 Complement Compleme Tru Valid Data High tDF tCE VA VA
tOE
Q0–DQ6 tBUS RY/BY#
Status
Status
Tru
Valid Data
High
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
ead cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
tRC Addresses VA tACC CE# tCH OE# tOEH WE# tOH DQ6/DQ2 tBUS RY/BY# High Valid (first read) Valid (second read) Valid (stops toggling) Valid Data tDF tCE VA VA VA
tOE
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
36
Am29LV800B
AC CHARACTERISTICS
Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 21.
DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter JEDEC Std tVIDR tRSP Description VID Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect Min Min All Speed Options 500 4 Unit ns µs
Note: Not 100% tested.
12 V
RESET#
0 or 3 V tVIDR Program or Erase Command Sequence tVIDR
0 or 3 V
CE#
WE# tRSP
RY/BY#
Figure 22.
Temporary Sector Unprotect Timing Diagram
Am29LV800B
37
AC CHARACTERISTICS
VID VIH RESET#
SA, A6, A1, A0
Valid* Sector Protect/Unprotect
Valid* Verify 40h
Valid*
Data
60h
60h
Status
1 μs CE#
Sector Protect: 150 μs Sector Unprotect: 15 ms
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 23.
Sector Protect/Unprotect Timing Diagram
38
Am29LV800B
AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations
Parameter JEDEC tAVAV tAVEL tELAX tDVEH tEHDX Std tWC tAS tAH tDS tDH tOES tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2 tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2 Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Programming Operation (Note 2) Sector Erase Operation (Note 2) Byte Word Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ 35 45 35 -70 70 Speed Options -90 90 0 45 45 0 0 0 0 0 35 30 9 11 0.7 50 50 50 -120 120 Unit ns ns ns ns ns ns ns ns ns ns ns µs sec
Notes:
1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information.
Am29LV800B
39
AC CHARACTERISTICS
P 555 for program A for program 2AA for erase SA for sector erase 555 for chip erase Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tD tD Data tR A0 for program PD for program 55 for erase 30 for sector erase 10 for chip erase DQ7
DOUT
Data# Polling PA
tAS
tAH
tWHWH1 or
tBUS
RESET#
RY/BY#
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device. 2. Figure indicates the last two bus cycles of command sequence. 3. Word mode address used as an example.
Figure 24. Alternate CE# Controlled Write Operation Timings
40
Am29LV800B
ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Chip Programming Time (Note 3) Byte Mode Word Mode Typ (Note 1) 0.7 14 9 11 9 5.8 300 360 27 17 Max (Note 2) 15 Unit s s µs µs s s Excludes system level overhead (Note 5) Comments Excludes 00h programming prior to erasure
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 1 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. Min –1.0 V –1.0 V –100 mA Max 12.5 V VCC + 1.0 V +100 mA
TSOP AND SO PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF
Notes:
1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Minimum Pattern Data Retention Time Test Conditions 150°C 125°C Min 10 20 Unit Years Years
Am29LV800B
41
PHYSICAL DIMENSIONS* TS 048—48-Pin Standard TSOP
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering.
42
Am29LV800B
PHYSICAL DIMENSIONS TSR048—48-Pin Reverse TSOP
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering.
Am29LV800B
43
PHYSICAL DIMENSIONS FBB 048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm
Dwg rev AF; 10/99
44
Am29LV800B
PHYSICAL DIMENSIONS SO 044—44-Pin Small Outline Package
Dwg rev AC; 10/99
45
Am29LV800B
REVISION SUMMARY Revision E (January 1998)
Distinctive Characteristics
Changed typical read and program/erase current specifications. Device now has a guaranteed minimum endurance of 1,000,000 write cycles.
In Note 2, the worst case endurance is now 1 million cycles.
Revision F (January 1999)
Global
Changed references for process technology to “0.32 µm.” Replaced the 70R ns regulated voltage speed option with 70 ns full voltage speed option.
In-System Sector Protect/Unprotect Algorithm Figure
Corrected A6 to 0, Changed wait specification to 150 µs on sector protect and 15 ms on sector unprotect.
Distinctive Characteristics
Added 20-year data retention bullet.
Connection Diagrams
Reverse TSOP: Modified markings. FBGA: Replaced Bump side (bottom) view with top view.
DC Characteristics
Changed typical read and program/erase current specifications.
AC Characteristics
Alternate CE# Controlled Erase/Program Operations: Changed t CP t o 35 ns for 70R, 80, and 90 speed options.
Ordering Information
Valid Combinations for FBGA Packages: New Table.
DC Characteristics—CMOS Compatible
ICC1, ICC2, ICC3, ICC4, ICC5: Added Note 2 “Maximum ICC specifications are tested with VCC = VCCmax”. ICC3, ICC4: Deleted VCC = VCCmax.
Erase and Programming Performance
Device now has a guaranteed minimum endurance of 1,000,000 write cycles.
Physical Dimensions
Corrected dimensions for package length and width in FBGA illustration (standalone data sheet version).
Physical Dimensions
Changed package drawing to FBB048.
Revision F+1 (February 1999)
Physical Dimensions
Corrected ball grid layout on FBB048 drawing. Added “048” to drawing title.
Revision E+1 (March 1998)
In-System Sector Protect/Unprotect Algorithms Figure
In the sector protect algorithm, added a “Reset PLSCNT=1” box in the path from “Protect another sector?” back to setting up the next sector address.
Revision F+2 (February 1999)
Distinctive Characteristics, Operating Ranges
Corrected to indicate that the VCC voltage range for all devices is 2.7–3.6 V.
DC Characteristics
Changed Note 1 to indicate that OE# is at VIH for the listed current.
AC Characteristics
Erase/Program Operations; Alternate CE# Controlled Erase/Program Operations: C orrected the notes reference for tWHWH1 and tWHWH2. These parameters are 100% tested. Corrected the note reference for tVCS. This parameter is not 100% tested.
Revision F+3 (July 2, 1999)
Global
Added references to availability of device in Known Good Die (KGD) form.
Revision F+4 (July 26, 1999)
Global
Added the 70R speed option, which is available in the extended temperature range.
Temporary Sector Unprotect Table
Added note reference for tVIDR. This parameter is not 100% tested.
Figure 23, Sector Protect/Unprotect Timing Diagram
A valid address is not required for the first write cycle; only the data 60h. Erase and Programming Performance
Ordering Information
Deleted the extended temperature range from the FBGA valid combinations.
Revision G (November 10, 1999)
Ordering Information
Deleted commercial and industrial temperature ranges from the 70R speed option.
Am29LV800B
46
AC Characteristics—Figure 17. Program Operations Timing and Figure 18. Chip/Sector Erase Operations
Deleted tGHWL and changed OE# waveform to start at high.
Revision G+3 (June 4, 2004)
Ordering Information
Added Lead-free (Pb-free) options to the Temperature range breakout of the OPN table and to the Valid Combinations table.
Physical Dimensions
Replaced figures with more detailed illustrations.
Revision G+4 (January 20, 2005)
Added migration statement to cover page and first page of data sheet. Added Colophon. Updated Trademark
Revision G+1 (July 7, 2000)
Ordering Information
Inserted dashes into ordering part numbers. Deleted burn-in option.
Revision G+2 (August 14, 2000)
Global
Deleted 70R and 80 ns speed options and burn-in option.
Revision G+5 (May 25, 2005)
Updated migration statement on cover page and first page of data sheet. Updated trademarks.
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.
Trademarks Copyright © 2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies
47
Am29LV800B
工商网监
湘ICP备2023018690号
