AM7992BDCB

FINAL Am7992B Serial Interface Adapter (SIA) DISTINCTIVE CHARACTERISTICS s Compatible with lEEE 802.3/Ethernet/Cheapernet specifications s Crystal/TTL oscillator-controlled Manchester encoder s Manchester decoder acquires clock and data within four bit times with an accuracy of ±3 ns s Guaranteed carrier and collision detection squelch threshold limits — Carrier/collision detected for inputs greater than –275 mV — No carrier/collision for inputs less than –175 mV s Input signal conditioning rejects transient noise — Transients |VIDC Max|) Receive ± Input Pulse Width to Turn-On (|Input| > |VIDC Max|) Decoder Acquisition Time RENA Hold Time (RCLK ↑ to RENAL) Receive ± Input Pulse Width to Not Turn-Off INTCARR Collision ± Input Pulse Width to Not Turn-On CLSN (|Input| > |VIDC Min|) Collision ± Input Pulse Width to Turn-On CLSN (|Input| > |VIDC Max|) Collision ± Input Pulse Width to Turn-Off CLSN (|Input| > |VIDC Max|) Collision ± Input Pulse Width to Not Turn-Off CLSN (|Input| < |VIDC Max|) CLSN Turn-On Delay (VIDC Max on Collision ± to CLSNH) CLSN Turn-Off Delay (VIDC Max on Collision ± to CLSNL) 26 (Note 4) 160 80 50 160 ns ns ns ns 40 (Note 4) 45 450 80 165 (Note 9) (Note 10) 120 20 5 25 80 300 (Note 8) Test Conditions Min 85 38 38 8 8 8 8 Max 118 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Receiver Specification Collision Specification 18 19 20 21 22 23 tCPWR tCPWO tCPWE tCPWN tCPH tCPO 10 ns ns 14 Am7992B AMD SWITCHING CHARACTERISTICS (continued) No. 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Parameters tTCL tTCH tTCR tTCF tTDS, tTES tTDH, tTEH tTOCE tOD tTOR tTOF tXTCH tXTCL tEJ1 tEJ51 Description TCLK LOW Time TCLK HIGH Time TCLK Rise Time TCLK Rise Time TX and TENA Setup Time to TCLK TX and TENA Hold Time to TCLK Transmit ± Output, (Bit Cell Center to Edge) TCLK HIGH to Transmit ± Output Transmit ± Output Rise Time Transmit ± Output Fall Time X1 to TCLK Propagation Delay for HIGH X1 to TCLK Propagation Delay for LOW Clock Acquisition Jitter Tolerance Jitter Tolerance After 50 Bit Times 20% – 80% (Notes 7 & 12) VCC = 5.0 V (Note 1) VCC = 5.0 V (Note 1) 5 5 16 19 (Note 1) 5 5 49.5 50.5 100 4 4 18 18 21.5 24.4 Test Conditions (Note 11) Min 45 45 8 8 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Transmitter Specification *Min = 4.5 V, Max = 5.5 V, TOSC = 50 ns; in production test, all differential input test conditions are done single-ended, non-VIRD levels are forces on DUT for waveform swing (levels chosen are due to tester limitations) and a distortion-free preamble is applied to Receive± inputs. Notes: 1. Tested but to values in excess of limits. Test accuracy not sufficient to allow screening guardbands. 2. Correlated to other tested parameter: IOD OFF = VOD OFF/RL. 3. Not tested. 4. Test done by monitoring output functionally. 5. Receive, Collision and Transmit functions are inactive: X1 driven by 20 MHz. 6. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second. 7. TCLK changes state on X1 rising edge, but initial state of TCLK is not defined. When TENA is High, TX data is Manchester encoded on the falling edge of X1 after the rising edge of TCLK. 8. Assumes 50 pF capacitance loading on RCLK and RX. 9. Test is done only for last BIT = 1, which is worst case. 10. Test done from 0.8 V of falling to 2.0 V of rising edge. 11. Test correlated to TTCH. 12. Measured from 50% point of X1 driving the input in production test. Am7992B 15 AMD KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don’t Care, Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance “Off” State KS000010 16 Am7992B AMD SWITCHING WAVEFORMS Bit Cell 1 1 (Note A) (Note E) BCC 1 INTCARR 10 RENA BCB BCC 0 BCB BCC 1 BCB BCC 0 BCB BCC 1 BCB Bit Cell 2 0 Bit Cell 3 1 Bit Cell 4 0 Bit Cell 5 1 Receive± (Measured Differentially) VCO Enable (Note D) VCO INTRCLK (Note B) RCK Enable RCLK 15 RX (Note C) (Note F) INTPLLCLK 03378I-12 Notes: A. Minimum Width > 45 ns. B. RCLK = INTRCLK when TEST LOW. C. RX undefined until bit time 5 (1st decoded bit). D. Oscillator Interrupt may occur at 2nd INTRCLK after Bit 2 Clock Transition. E. Timing Diagram does not include Internal Propagation Delays. F. First valid data at RX (Bit 5). Receive Timing – Start of Reception Clock Acquisition Am7992B 17 AMD SWITCHING WAVEFORMS 1 Bit (N – 1) Receive+ (Measured Differentially) 0 Bit N (Note B) BCC BCB BCC BCB (Note A) INTCARR 11 RENA 17 VCO Enable 12 VCO INTRCLK RCK Enable RCLK RX Bit (N – 1) Bit N PLL CLK 03378I-13 Notes: A. INTCARR deasserts 1.55 bit times after last Receive± Rising Edge. B. Start of Next Packet. Receive Timing – End of Reception (Last Bit = 0) 18 Am7992B AMD SWITCHING WAVEFORMS 0 Bit (N – 1) 1 Bit N Receive± (Measured Differentially) BCC INTCARR BCB BCC (Note A) 17 VCO Enable VCO INTRCLK RCK Enable RCLK RX Bit (N – 1) Bit N 16 RENA 11 PLL CLK Note: A. INTCARR deasserts 1.55 bit times after last Receive± Rising Edge. 03378I-14 Receive Timing – End of Reception (Last Bit = 1) Am7992B 19 AMD SWITCHING WAVEFORMS (Note A) X1 TCLK TENA TX TSEL (Note B) VH Transmit+ (Note C) VL VH Transmit– (Note C) Transmit± (Measured Differentially) VL (Note B) 31 1 0 1 03378I-15 Notes: A. X1 20 MHz Sine Wave from Crystal Oscillator or driven with X1 driven from External Source Waveform. B. TSEL connected as shown in Figure 2B. For Figure 2A, Transmit+ is HIGH when TENA is LOW. C. When Idle Transmit ± Zero Differential is 1/2 (VH + VL). Transmit Timing – Start of Packet 20 Am7992B AMD SWITCHING WAVEFORMS X1 TCLK TENA 29 TSEL CASE 1 TX (Last Bit = 0) Transmit+ Transmit– 0.5 VO at 2 µs 30 30 VO Bit (N – 2) BCC CASE 2 TX (Last Bit = 1) Bit (N – 1) BCC BCB Bit N BCC BCB Transmit± (Measured Differentially) VO BCB Transmit+ Transmit– 0.5 VO at 2 µs VO Transmit± (Measured Differentially) VO 03378I-16 Transmit Timing – End of Transmission* *TSEL Components (see Figure 2B). See Typical Performance Curve for Response at End of Transmission with Inductive Loads. Am7992B 21 AMD SWITCHING WAVEFORMS Collision Presence± 0V – 22 + VIDC Max VIDC Max 23 CLSN 2.0 V .8 V 03378I-17 Collision Timing X1 TCLK 2V 2V TENA 31 Transmit± (Measured Differentially) 80% 20% 33 80% 50% 20% 32 03378I-18 Transmit Timing (at start of packet) 22 Am7992B AMD SWITCHING WAVEFORMS Receive± (Measured Differentially) VIDC Min (–175 mV) VIDC Max (–275 mV) 14 13 17 VIRVD 0V 0V 0V VIRVD +1.5 V –1.5 V 10 RENA 2.0 V 03378I-19 Receive± Input Pulse Width Timing Collision± (Measured Differentially) VIDC Min (–175 mV) VIDC Max (–275 mV) 0V VIRVD 0V 0V VIRVD 19 18 22 20 21 +1.5 V –1.5 V CLSN 2.0 V 03378I-20 Collision± Input Pulse Width Timing 1 2 4 RCLK 9 8 5 2.0 V 0.2 V 0.8 V 3 RX 6 7 0.8 V 8 03378I-21 RCLK and RX Timing Am7992B 23 AMD SWITCHING WAVEFORMS 25 24 TCLK 0.8 V 26 28 29 2.0 V 0.8 V 27 0.8 V TX 2.0 0.8 28 2.0 0.8 TENA 2.0 V 0.8 V 03378I-22 TCLK and TX Timing TOSC X1 Driving Input 2.0 1.5 1.5 1.5 1.5 0.8 tHIGH* tLOW* tR* 2.0 TCLK 0.8 35 34 tF* ‘A’ Transmit+, Transmit– (Note A) 0V ‘B’ BCC (Bit Cell Center) BCB (Bit Cell Boundary) 03378I-23 Note: A. Encode Manchester clock transition (BCC) at Point ‘A’ and bit cell edge (BCB) at point ‘B’. *See Specification for External TTL Level in Functional Description section. X1 Driven from External Source 24 Am7992B AMD SWITCHING WAVEFORMS Bit Number INTRCLK BCC 1 BCB 2 3 4 5 55 6 56 BCC 7 57 BCC 8 58 BCC BCC BCC BCC 1/4 Bit Cell BCC PLL CLK 4.5 V Receive+ Receive– (Note A) 1.5 V 3V 0 +4.5 V 1.5 V 0 –1.5 V 0V 4.5 V Strobe RX Receive± A RX +3 V tEJI tEJ51 BCB Receive+ Receive– (Note B) 0 +4.5 V +1.5 V +1.5 V 0 –1.5 V –4.5 V Receive± tEJI tEJ51 B Strobe RX RX BCB Receive+ Receive– (Note C) +3 V 0 +4.5 V +1.5 V +1.5 V 0 –1.5 V Receive± tEJI tEJ51 C RX Strobe RX +4.5 V +1.5 V +3 V Receive+ Receive– (Note D) 0 +1.5 V 0 –1.5 V Receive± RX tEJI tEJ51 D 1/4 Bit Cell Strobe RX 03378I-24 Notes: A. Case 1, 5 Data Bit Pattern 0, 1 Rising clock edge moved toward 1/4 bit cell RCLK data strobe. Case 1 uses bit 5, Case 5 uses bit 55. B. Case 2, 6 Data Bit Pattern 1, 0 Falling clock edge moved toward 1/4 bit cell RCLK data strobe. Case 2 uses bit 6, Case 6 uses bit 56. C. Case 3, 7 Data Bit Pattern 1, 1 Falling bit cell edge moved toward 1/4 bit cell RCLK data strobe. Case 3 uses bit 6, Case 7 uses bit 56. D. Case 4, 8 Data Bit Pattern X, 0 Rising bit cell edge moved toward 1/4 bit cell RCLK data strobe. Case 4 uses bit 5, Case 8 uses bit 55. Input Jitter Timing Am7992B 25 AMD TYPICAL PERFORMANCE CURVE 600 500 400 Differential Output Voltage (VO) 300 (mV) 200 100 0 –100 1.0 R = 78 Ω* R = 78 Ω 3 L = 95 µH R = 78 Ω 2 L = 75 µH R = 78 Ω 1 L = 60 µH 2.0 3.0 Time (µs) 4.0 5.0 6.0 03378I-25 End of Transmission – Differential Output Voltage* *Equivalent Load: L R Notes: 60 µH 1. 802.3 Test Load: R Test L Test Am7992B 75 µH NOM. Am7996 75 µH NOM. 2. 802.3 10BASE5 Network Connection: AUI 80.4 VO Am7992B 95 µH 80.4 Am7996 3. 802.3 10BASE2 Network Connection: VO 03378I-26 26 Am7992B AMD SWITCHING TEST CIRCUITS Transmit+ DUT 50 pF Transmit– DUT RL = 78 Ω 03378I-27 03378I-28 A. Test Load for RX, RENA, RCLK, TCLK, CLSN B. Transmit± Output + DUT – DC Voltage 03378I-29 C. Receive± and Collision± Input Am7992B 27