AM7992BJC

FINAL Am7992B Serial Interface Adapter (SIA) DISTINCTIVE CHARACTERISTICS ■ Compatible with lEEE 802.3/Ethernet/Cheapernet specifications ■ Crystal/TTL oscillator-controlled Manchester encoder ■ Manchester decoder acquires clock and data within four bit times with an accuracy of ±3 ns ■ Guaranteed carrier and collision detection squelch threshold limits — Carrier/collision detected for inputs greater than –275 mV — No carrier/collision for inputs less than –175 mV ■ Input signal conditioning rejects transient noise — Transients |VIDC Max|) 14 tRPWO Receive ± Input Pulse Width to Turn-On (|Input| > |VIDC Max|) 15 tRLT 16 tREDH RENA Hold Time (RCLK ↑ to RENAL) 17 tRPWN 120 ns 20 (Note 4) 45 Decoder Acquisition Time ns ns 450 ns 80 ns Receive ± Input Pulse Width to Not Turn-Off INTCARR 165 ns 10 ns 40 Collision Specification 14 18 tCPWR Collision ± Input Pulse Width to Not Turn-On CLSN (|Input| > |VIDC Min|) 19 tCPWO Collision ± Input Pulse Width to Turn-On CLSN (|Input| > |VIDC Max|) 26 ns 160 ns (Note 4) 20 tCPWE Collision ± Input Pulse Width to Turn-Off CLSN (|Input| > |VIDC Max|) 21 tCPWN Collision ± Input Pulse Width to Not Turn-Off CLSN (|Input| < |VIDC Max|) 80 ns 22 tCPH CLSN Turn-On Delay (VIDC Max on Collision ± to CLSNH) 50 ns 23 tCPO CLSN Turn-Off Delay (VIDC Max on Collision ± to CLSNL) 160 ns Am7992B AMD SWITCHING CHARACTERISTICS (continued) No. Parameters Description Test Conditions Min Max Unit (Note 11) 45 ns 45 ns Transmitter Specification 24 tTCL TCLK LOW Time 25 tTCH TCLK HIGH Time 26 tTCR TCLK Rise Time 27 tTCF TCLK Rise Time 28 tTDS, tTES TX and TENA Setup Time to TCLK 29 tTDH, tTEH TX and TENA Hold Time to TCLK 30 tTOCE 31 tOD TCLK HIGH to Transmit ± Output 32 tTOR Transmit ± Output Rise Time 33 tTOF Transmit ± Output Fall Time 34 tXTCH X1 to TCLK Propagation Delay for HIGH 35 tXTCL X1 to TCLK Propagation Delay for LOW 36 tEJ1 Clock Acquisition Jitter Tolerance VCC = 5.0 V (Note 1) 37 tEJ51 Jitter Tolerance After 50 Bit Times VCC = 5.0 V (Note 1) 19 (Note 1) Transmit ± Output, (Bit Cell Center to Edge) 8 ns 8 ns 5 ns 5 ns 49.5 50.5 ns 100 ns 4 ns 4 ns 18 ns 5 18 ns 16 21.5 ns 24.4 ns 20% – 80% 5 (Notes 7 & 12) *Min = 4.5 V, Max = 5.5 V, TOSC = 50 ns; in production test, all differential input test conditions are done single-ended, non-VIRD levels are forces on DUT for waveform swing (levels chosen are due to tester limitations) and a distortion-free preamble is applied to Receive± inputs. Notes: 1. Tested but to values in excess of limits. Test accuracy not sufficient to allow screening guardbands. 2. Correlated to other tested parameter: IOD OFF = VOD OFF/RL. 3. Not tested. 4. Test done by monitoring output functionally. 5. Receive, Collision and Transmit functions are inactive: X1 driven by 20 MHz. 6. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second. 7. TCLK changes state on X1 rising edge, but initial state of TCLK is not defined. When TENA is High, TX data is Manchester encoded on the falling edge of X1 after the rising edge of TCLK. 8. Assumes 50 pF capacitance loading on RCLK and RX. 9. Test is done only for last BIT = 1, which is worst case. 10. Test done from 0.8 V of falling to 2.0 V of rising edge. 11. Test correlated to TTCH. 12. Measured from 50% point of X1 driving the input in production test. Am7992B 15 AMD KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010 16 Am7992B AMD SWITCHING WAVEFORMS Bit Cell 1 1 Receive± (Measured Differentially) Bit Cell 2 0 Bit Cell 3 1 Bit Cell 4 0 Bit Cell 5 1 (Note A) (Note E) BCC 1 BCB BCC 0 BCB BCC 1 BCB BCC 0 BCB BCC 1 BCB INTCARR 10 RENA (Note D) VCO Enable VCO (Note B) INTRCLK RCK Enable RCLK 15 (Note C) RX (Note F) INTPLLCLK 03378I-12 Notes: A. Minimum Width > 45 ns. B. RCLK = INTRCLK when TEST LOW. C. RX undefined until bit time 5 (1st decoded bit). D. Oscillator Interrupt may occur at 2nd INTRCLK after Bit 2 Clock Transition. E. Timing Diagram does not include Internal Propagation Delays. F. First valid data at RX (Bit 5). Receive Timing – Start of Reception Clock Acquisition Am7992B 17 AMD SWITCHING WAVEFORMS Receive+ (Measured Differentially) 1 0 Bit (N – 1) Bit N (Note B) BCC BCB BCC BCB (Note A) INTCARR 11 12 RENA 17 VCO Enable VCO INTRCLK RCK Enable RCLK RX Bit (N – 1) Bit N PLL CLK 03378I-13 Notes: A. INTCARR deasserts 1.55 bit times after last Receive± Rising Edge. B. Start of Next Packet. Receive Timing – End of Reception (Last Bit = 0) 18 Am7992B AMD SWITCHING WAVEFORMS Receive± (Measured Differentially) 0 Bit (N – 1) BCC 1 Bit N BCB BCC INTCARR (Note A) 17 VCO Enable VCO INTRCLK RCK Enable RCLK RX Bit (N – 1) Bit N 16 RENA 11 PLL CLK Note: A. INTCARR deasserts 1.55 bit times after last Receive± Rising Edge. 03378I-14 Receive Timing – End of Reception (Last Bit = 1) Am7992B 19 AMD SWITCHING WAVEFORMS (Note A) X1 TCLK TENA TX TSEL (Note B) VH Transmit+ (Note C) VL VH Transmit– (Note C) Transmit± (Measured Differentially) VL 1 (Note B) 0 1 31 03378I-15 Notes: A. X1 20 MHz Sine Wave from Crystal Oscillator or driven with X1 driven from External Source Waveform. B. TSEL connected as shown in Figure 2B. For Figure 2A, Transmit+ is HIGH when TENA is LOW. C. When Idle Transmit ± Zero Differential is 1/2 (VH + VL). Transmit Timing – Start of Packet 20 Am7992B AMD SWITCHING WAVEFORMS X1 TCLK TENA 29 TSEL CASE 1 TX (Last Bit = 0) Transmit+ Transmit– 0.5 VO at 2 µs VO 30 Transmit± (Measured Differentially) 30 VO Bit (N – 2) BCC Bit (N – 1) BCB BCC Bit N BCB BCC BCB CASE 2 TX (Last Bit = 1) Transmit+ Transmit– 0.5 VO at 2 µs VO Transmit± (Measured Differentially) VO 03378I-16 Transmit Timing – End of Transmission* *TSEL Components (see Figure 2B). See Typical Performance Curve for Response at End of Transmission with Inductive Loads. Am7992B 21 AMD SWITCHING WAVEFORMS Collision Presence± + 0V VIDC Max – VIDC Max 22 CLSN 23 2.0 V .8 V 03378I-17 Collision Timing X1 TCLK 2V 2V TENA 31 80% 80% Transmit± (Measured Differentially) 50% 20% 33 20% 32 03378I-18 Transmit Timing (at start of packet) 22 Am7992B AMD SWITCHING WAVEFORMS Receive± (Measured Differentially) +1.5 V VIRVD VIDC Min (–175 mV) 0V 0V 0V VIDC Max (–275 mV) VIRVD 14 –1.5 V 17 13 10 2.0 V RENA 03378I-19 Receive± Input Pulse Width Timing Collision± (Measured Differentially) +1.5 V VIRVD VIDC Min (–175 mV) VIDC Max (–275 mV) 0V 0V 0V VIRVD 19 –1.5 V 20 21 18 22 2.0 V CLSN 03378I-20 Collision± Input Pulse Width Timing 1 2 3 4 0.2 V RCLK 0.8 V 9 8 5 2.0 V RX 0.8 V 6 7 8 03378I-21 RCLK and RX Timing Am7992B 23 AMD SWITCHING WAVEFORMS 25 TCLK 24 2.0 V 0.8 V 0.8 V 26 27 28 29 2.0 0.8 TX 0.8 V 2.0 0.8 28 2.0 V 0.8 V TENA 03378I-22 TCLK and TX Timing TOSC X1 Driving Input 2.0 1.5 1.5 1.5 1.5 0.8 tHIGH* tLOW* tR* tF* 2.0 TCLK 0.8 35 34 ‘A’ Transmit+, Transmit– (Note A) ‘B’ 0V BCC (Bit Cell Center) BCB (Bit Cell Boundary) Note: A. Encode Manchester clock transition (BCC) at Point ‘A’ and bit cell edge (BCB) at point ‘B’. *See Specification for External TTL Level in Functional Description section. X1 Driven from External Source 24 Am7992B 03378I-23 AMD SWITCHING WAVEFORMS 1 Bit Number 2 3 4 BCB INTRCLK BCC BCC BCC BCC 5 6 7 8 55 56 57 58 BCC BCC BCC BCC PLL CLK 1/4 Bit Cell 4.5 V Receive+ Receive– (Note A) Receive± 1.5 V 3V 0V 0 +4.5 V 1.5 V 0 –1.5 V 4.5 V Strobe RX tEJI tEJ51 A RX BCB +3 V Receive+ 0 +4.5 V Receive– (Note B) Receive± +1.5 V +1.5 V 0 –1.5 V –4.5 V tEJI tEJ51 B RX Strobe RX BCB Receive+ Receive– (Note C) Receive± +3 V 0 +4.5 V +1.5 V +1.5 V 0 –1.5 V tEJI tEJ51 C RX Strobe RX Receive+ +4.5 V +1.5 V +3 V Receive– 0 Receive± +1.5 V 0 –1.5 V (Note D) tEJI tEJ51 D RX 1/4 Bit Cell Strobe RX Notes: A. Case 1, 5 Data Bit Pattern 0, 1 Rising clock edge moved toward 1/4 bit cell RCLK data strobe. Case 1 uses bit 5, Case 5 uses bit 55. 03378I-24 B. Case 2, 6 Data Bit Pattern 1, 0 Falling clock edge moved toward 1/4 bit cell RCLK data strobe. Case 2 uses bit 6, Case 6 uses bit 56. C. Case 3, 7 Data Bit Pattern 1, 1 Falling bit cell edge moved toward 1/4 bit cell RCLK data strobe. Case 3 uses bit 6, Case 7 uses bit 56. D. Case 4, 8 Data Bit Pattern X, 0 Rising bit cell edge moved toward 1/4 bit cell RCLK data strobe. Case 4 uses bit 5, Case 8 uses bit 55. Input Jitter Timing Am7992B 25 AMD TYPICAL PERFORMANCE CURVE 600 R = 78 Ω* 500 R = 78 Ω 3 L = 95 µH 400 Differential Output Voltage (VO) 300 (mV) R = 78 Ω 2 L = 75 µH 200 R = 78 Ω 1 L = 60 µH 100 0 –100 1.0 2.0 3.0 4.0 5.0 Time (µs) 6.0 03378I-25 End of Transmission – Differential Output Voltage* *Equivalent Load: L R Notes: 60 µH 1. 802.3 Test Load: L Test R Test Am7992B 75 µH NOM. 2. 802.3 10BASE5 Network Connection: Am7996 75 µH NOM. AUI Am7992B 80.4 VO Am7996 95 µH 3. 802.3 10BASE2 Network Connection: 80.4 VO 03378I-26 26 Am7992B AMD SWITCHING TEST CIRCUITS Transmit+ DUT RL = 78 Ω DUT 50 pF Transmit– 03378I-27 03378I-28 A. Test Load for RX, RENA, RCLK, TCLK, CLSN B. Transmit± Output + DUT – DC Voltage 03378I-29 C. Receive± and Collision± Input Am7992B 27