AM79C98

FINAL Am79C98 Twisted-Pair Ethernet Transceiver (TPEX) DISTINCTIVE CHARACTERISTICS s CMOS device provides compliant operation and low operating current from a single +5 V supply s Power Down mode provides reduced power consumption for battery-powered applications. Reset capability allows use in remote MAU applications. s Pin-selectable twisted-pair receive polarity detection and automatic inversion of the receive signal. Polarity indication output pin can directly drive an LED. s Pin-selectable twisted-pair Link Integrity Test capability conforming to the IEEE 802.3 standard for 10BASE-T. Link status pin can directly drive an LED. s Internal twisted-pair transmitter digital predistortion circuit reduces medium-induced jitter and ensures compliance with the 10BASE-T transmit and receive waveform requirements s Pin-selectable SQE Test (heartbeat) enable s Transmit and receive status indications are available on separate, dedicated pins s AUI loopback, Jabber Control, and SQE Test functions comply with the 10BASE-T standard IEEE Std 802.3i-1990 GENERAL DESCRIPTION T he Am79C98 Twisted-Pair Ethernet Transceiver (TPEX) is an integrated circuit that implements the medium attachment unit (MAU) functions for the twisted-pair medium, as specified by the IEEE 802.3 standard (Type 10BASE-T). This device provides the necessary electrical and functional interface between the IEEE 802.3 standard attachment unit interface (AUI) and the twisted-pair cable. A network based on the 10BASE-T standard can use unshielded twisted-pair cables, providing an economical solution to networking by allowing the use of existing telephone wiring. The Am79C98 provides a minimal component count and cost-effective solution to the design and implementation of 10BASE-T standard networks. TPEX provides twisted-pair driver and receiver circuits, including on-board transmit digital predistortion, receiver squelch, and an AUI port with pin-selectable SQE Test enable. The device also provides a number of additional features, including pin-selectable TwistedPair Receive Polarity Detection and Automatic Polarity Reversal, Link Status indication, Link Test disable function, and transmit and receive status. The Twisted-Pair Polarity and Link Status pins can be used to drive LEDs directly. The Am79C98 is fabricated in CMOS technology and requires a single +5 V supply. The device is available in 24-pin SKINNYDIP® plastic dual in-line and 28-pin plastic leaded chip carrier (PLCC) packaging. Publication# 14395 Rev: D Amendment/0 Issue Date: May 1994 1 2 Line Receiver and Squelch Circuit Jabber Control Line Driver and Predistortion TXD+ TXD– TXP+ TXP– Link Test LNKST Line Driver Collision and Loopback RCV RXD+ Line Receiver and Smart Squelch RXD– Line Driver Polarity Detect and Auto Reversal Voltage Controlled Oscillator RXPOL Twisted-Pair Interface BLOCK DIAGRAM DO+ DO– XMT CI+ CI– SQE TEST Am79C98 DI+ DI– REXT PRDN/RST TEST Attachment Unit Interface (AUI) 14395D-1 AMD RELATED AMD PRODUCTS Part No. Am7996 Am79C100 Am79C90 Am79C900 Am79C940 Am79C960 Am79C961 Am79C965 Am79C970 Am79C974 Am79C981 Am79C987 Description IEEE-802.3/Ethernet/Cheapernet Tap Transceiver Twisted-Pair Ethernet Transceiver Plus (TPEX+) CMOS Local Area Network Controller for Ethernet (C-LANCE) Integrated Local Area Communications ControllerTM (ILACCTM) Media Access Controller for Ethernet (MACETM) PCnet-ISA Single-Chip Ethernet Controller (for ISA bus) PCnet-ISA+ Single-Chip Ethernet Controller (with Microsoft® Plug n’ Play support) PCnet-32 Single-Chip Ethernet Controller (for 386DX, 486 and VL buses) PCnet-PCI Single-Chip Ethernet Controller (for PCI bus) PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems Integrated Multiport Repeater PlusTM (IMR+TM) Hardware Implemented Management Information BaseTM (HIMIBTM) CONNECTION DIAGRAM Top View DIP DI+ DI– CI+ CI– DI+ DI– DVSS XMT LNKST AVSS DO+ DO– PRDN/RST REXT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 TXD+ TXD– TXP+ TXP– DVDD TEST SQE^TEST AVDD RXD+ RXD– RXPOL DVSS DVSS XMT LNKST AVSS AVSS DO+ 5 6 7 8 9 10 11 PLCC TXD+ TXD– CI+ TXP+ 25 24 23 22 21 20 19 12 13 14 15 16 17 18 RCV PRDN/RST RXPOL REXT RXD– RXD+ DO– CI– 2 4 3 1 28 27 26 TXP– DVDD DVDD TEST SQE^TEST AVDD AVDD RCV 14395D-2 Note: Pin 1 is marked for orientation 14395D-3 Am79C98 3 AMD LOGIC SYMBOL DVDD DO+ DO– Attachment Unit Interface (AUI) DI+ DI– CI+ CI– AVDD TXD+ TXP+ TXD– TXP– Twisted Pair Interface Am79C98 RXD+ RXD– LNKST RXPOL XMT RCV SQE TEST TEST REXT PRDN/RST DVSS AVSS 14395D-4 4 Am79C98 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below. AM79C98 OPTIONAL PROCESSING Blank = Standard Processing TECHNOLOGY C = CMOS Electrically Erasable PACKAGE TYPE P = 24-Pin Plastic DIP (PD 3024) J = 28-Pin Plastic Leaded Chip Carrier (PL 028) SPEED Not Applicable DEVICE NUMBER/DESCRIPTION Am79C98 Twisted-Pair Ethernet Transceiver (TPEX) Valid Combinations AM79C98 PC, JC Valid Combinations Valid combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am79C98 5 PIN DESCRIPTION AVDD Analog Power This pin supplies +5 V to analog portions of the TPEX circuitry. PRDN/RST Power Down/Reset Input, Active LOW Driving this input LOW resets the internal logic of TPEX and places the device in a special Power Down mode. In the Power Down/Reset mode, all output drivers are placed in their inactive state. AVSS Analog Ground This pin is the ground reference for analog portions of the TPEX circuitry. RCV Receive Output This pin is driven HIGH while TPEX is receiving data on the RXD pins and is transferring the received signal onto the AUI DI pair. The RCV and XMT pins are simultaneously driven HIGH during collision. CI+, CI– Control In Output AUI port differential driver. DI+, DI– Data In Output AUI port differential driver. REXT External Resistor Input An external precision resistor is connected between this pin and AVDD in order to provide a voltage reference for the internal voltage-controlled oscillator (VCO). DO+, DO– Data Out Input AUI port differential receiver. RXD+, RXD– Receive Data Input 10BASE-T port differential receivers. DVDD Digital Power This pin supplies +5 V to digital portions of the TPEX circuitry. RXPOL Receive Polarity Open Drain, Input/Output The twisted-pair receiver is capable of detecting a receive signal with reversed polarity (wiring error). The RXPOL pin is normally in the LOW state, indicating correct polarity of the received signal. If the receiver detects reversed polarity, then this pin is not driven (goes HIGH) and the polarity of subsequent packets is inverted. In the LOW output state, this pin can sink up to a maximum of 16 mA and is therefore capable of driving an LED. This feature can be disabled by strapping this pin LOW. In this case, the Receive Polarity correction circuit is disabled and the internal receive signal remains noninverted, irrespective of the received signal. This pin is internally pulled HIGH when inactive. DVSS Digital Ground This pin is the ground reference for digital portions of TPEX circuitry. LNKST Link Status Open Drain, Input/Output When this pin is tied LOW, the internal Link Test Receive function is disabled and the Transmit and Receive functions will remain active irrespective of arriving idle Link Test pulses and data. TPEX continues to generate idle Link Test pulses irrespective of the status of this pin. As an output, this pin is driven LOW if the link is identified as functional. However, if the link is determined to be nonfunctional, due to missing idle Link Test pulses or data packets, then this pin is not driven. In the LOW output state, the pin is capable of sinking a maximum of 16 mA and can be used to drive an LED. This pin is internally pulled HIGH when inactive. SQE TEST Signal Quality Test (Heartbeat) Enable Input, Active LOW The SQE Test function is enabled by tying this input LOW. This input is internally pulled HIGH when inactive. 6 Am79C98 TEST Test Input, Active HIGH This pin should be tied HIGH for normal operation. If this pin is driven LOW, TPEX will enter Loopback Test mode. The type of loopback is determined by the state of the SQE TEST pin. If this pin is in the LOW state (Station MAU), TPEX transfers data independently from DO to the TXD/TXP circuit and from RXD to the DI circuit. If the SQE TEST is in the HIGH state (Repeater MAU), then data on the RXD circuit is transmitted back onto the TXD/TXP circuit and data on the DO circuit is transmitted onto the DI pair. TXP+, TXP– Transmit Predistortion Output Transmit waveform predistortion control. XMT Transmit Output This pin is driven HIGH while TPEX is receiving data on the AUI DO pair and is transmitting data on the TXD/ TXP pins. The XMT and RCV pins are simultaneously driven HIGH during collision. TXD+, TXD– Transmit Data Output 10BASE-T port differential drivers. Am79C98 7 FUNCTIONAL DESCRIPTION The Twisted-Pair Ethernet Transceiver (TPEX) complies with the requirements specified by the IEEE 802.3 standard for the attachment unit interface (AUI) and the standard for 10BASE-T medium attachment unit (MAU). TPEX also implements a number of features in addition to the IEEE 802.3 standard. An outline of functions implemented by the Am79C98 is given below. Attachment Unit Interface (DO+/–, DI+/–, CI+/–) The AUI electrical and functional characteristics comply with those specified by the IEEE 802.3, Sections 7 and 14 (drafted). The AUI pins can be wired directly to the isolation transformer, for a remote MAU application, or to another device (e.g., Am7992 serial interface adapter). The end-of-packet SQE Test function (heartbeat) can be disabled to allow the device to be employed in a repeater application. data reception, and the collision detection functions are disabled, and remain disabled until valid data or >2 consecutive Link Test pulses appear on the RXD+/– pair. During Link Fail, the LNKST pin is internally pulled HIGH. When the link is identified as functional, the LNKST pin is driven LOW and is capable of directly driving a “link OK” LED. In order to interoperate with systems that do not implement Link Test, this function can be disabled by grounding the LNKST pin. When disabled, the driver and receiver functions remain enabled irrespective of the presence or absence of data or Link Test pulses on the RXD+/– pair. The transmitter continues to generate Link Test pulses in the absence of transmit data even if the Link Test function is disabled. Polarity Detection and Reversal The TPEX receive function includes the ability to invert the polarity of the signals appearing at the RXD± pair if the polarity of the received signal is reversed (such as in the case of a wiring error). This feature allows data packets received from a reverse-wired RXD± input pair to be corrected in the TPEX prior to transfer to the DTE via the AUI interface (DI±). The polarity detection function is activated following reset or Link Fail, and will reverse the receive polarity based on both the polarity of any previous Link Test pulses and the polarity of subsequent packets with a valid end transmit delimiter (ETD). When in the Link Fail state, TPEX will recognize Link Test pulses of either positive or negative polarity. Exit from the Link Fail state is caused by the reception of five to six consecutive Link Test pulses of identical polarity. On entry to the Link Pass state, the polarity of the last five Link Test pulses is used to determine the initial receive polarity configuration and the receiver is reconfigured to subsequently recognize only Link Test pulses of the previously established polarity. This link pulse algorithm is employed only until ETD polarity determination is made, as described later in this section. Positive Link Test pulses are defined as received signals with a positive amplitude greater than 520 mV and a pulse width of 60 ns to 200 ns. This positive excursion may be followed by a negative excursion. This definition is consistent with the expected received signal at a correctly wired receiver when a Link Test pulse that fits the template of Figure 14-12 in the 10BASE-T standard is generated at a transmitter and passed through 100 m of twisted-pair cable. Negative Link Test pulses are defined as received signals with a negative amplitude greater than 520 mV and a pulse width of 60 ns to 200 ns. This negative excursion may be followed by a positive excursion. This definition is consistent with the expected received signal at a reverse wired receiver when a Link Test pulse that fits the template of Figure 14-12 in the 10BASE-T Twisted-Pair Transmit Function Data transmission to the 10BASE-T medium occurs when valid AUI signals appear on the DO+/–differential pair. This data stream is routed to the differential driver circuitry in the TXD+/– pins. The driver circuitry provides necessary electrical driving capability and predistortion control for transmitting signals over maximum-length twisted-pair cable, as specified by the IEEE 802.3 10BASE-T standard. The transmit function meets the propagation delays and jitter specified by the standard. During transmission, the XMT pin is driven HIGH and can be used for status information. Twisted-Pair Receive Function The receiver complies with the receiver specifications of the IEEE 802.3 10BASE-T standard, including noise immunity and received signal rejection criteria (“Smart Squelch”). Signals meeting these criteria appearing at the RXD+/– differential input pair are routed to the DI+/– outputs. The receiver function meets the propagation delays and jitter requirements specified by the standard. Receiver squelch level drops to approximately half its threshold value after unsquelch to allow reception of minimum amplitude signals and to offset carrier fade in the event of worst-case signal attenuation and crosstalk noise conditions. During receive, the RCV pin is driven HIGH and can be used for status information. Link Test Function The Link Test function is implemented as specified by the IEEE 802.3 10BASE-T standard. During periods of transmit pair inactivity, Link Test pulses will be periodically sent over the twisted-pair medium to allow constant monitoring of medium integrity. When the Link Test function is enabled, the absence of Link Test pulses on the RXD+/– pair will cause the TPEX to go into a Link Fail state. In Link Fail state, data transmission, 8 Am79C98 standard is generated at a transmitter and passed through 100 m of twisted-pair cable. The polarity detection/correction algorithm will remain “armed” until two consecutive packets with valid ETD of identical polarity are detected. When “armed,” the receiver is capable of changing the initial or previous polarity configuration based on the most recent ETD polarity. On receipt of the first packet with valid ETD following reset or Link Fail, TPEX will utilize the inferred polarity information to configure its RXD± input, regardless of its previous state. On receipt of a second packet with a valid ETD with correct polarity, the detection/correction algorithm will “lock in” the initial polarity. If the second (or subsequent) packet is not detected as confirming the previous polarity decision, the most recently detected ETD polarity will be used as the new default. Note that packets with invalid ETD have no effect on updating the previous polarity decision. Once two consecutive packets with valid ETD have been received, TPEX will disable the detection/correction algorithm until either a Link Fail condition occurs or PRDN/RST is asserted. During polarity reversal, the RXPOL pin is internally pulled HIGH. During normal polarity conditions, the RXPOL pin is driven LOW and is capable of directly driving a “Polarity OK” LED using an integrated 16 mA driver. If desired, the polarity reversal function can be disabled by grounding the RXPOL pin. mission. This signal is a self-test indication to the DTE that the MAU collision circuitry is functional. An SQE message consists of a 10 MHz signal on the CI+/– pair with a duration of 8 bit times (800 ns). When enabled, an SQE Test will occur at the end of every transmission, starting eight bit times (800 ns) after the last transition of the transmitted signal. For repeater applications, the SQE Test function can be disabled by tying the SQE TEST pin HIGH or by leaving it disconnected. Jabber Function The Jabber function inhibits the twisted-pair transmit function of TPEX if the DO+/– circuit is active longer than the time permitted to transmit the maximumlength 802.3/Ethernet data packet (50 ms nominal). This prevents any one node from disrupting the network due to a “stuck on” or faulty transmitter. If this maximum transmit time is exceeded, TPEX transmitter circuitry is disabled and a 10 MHz signal is driven onto the CI+/– pair. Once the transmit data stream is removed from the DO+/– pair of inputs, an “unjab” time of 250 ms to 750 ms will elapse before TPEX removes the 10 MHz signal from the CI+/– pair and re-enables the transmit path. Power Down In addition to on-board power-on-reset circuitry, the PRDN/RST pin is used as the master reset for TPEX. PRDN/RST must be driven LOW for a minimum of two microseconds for reset to occur. The PRDN/RST pin can also be used to put the TPEX into an inactive state, causing the device to consume less power. This feature is useful in battery-powered or low-duty-cycle systems. Driving PRDN/RST LOW resets the internal logic of TPEX and places the device into idle mode. In this mode, the twisted-pair driver pins (TXD+/–,TXP+/–) are driven LOW, the AUI pins (CI+/–, DI+/–) are driven HIGH, the LNKST and RXPOL pins are in the inactive state, and XMT and RCV are LOW. TPEX will remain in idle as long as PRDN/RST is asserted. Following the rising edge of the signal on PRDN/RST, TPEX will remain in the reset state for 10 µs. Twisted-Pair Interface Status Two outputs (XMT and RCV) indicate whether TPEX is transmitting (AUI to twisted-pair) or receiving (twistedpair to AUI). Both signals are asserted during a collision. In Link Fail mode, RCV is disabled. In Jabber Detect mode, XMT is disabled. Both signals are active HIGH. Collision Detect Function Simultaneous carrier sense (presence of valid data signals) by both the AUI DO+/– pair and the RXD+/– pair constitutes a collision, thereby causing a 10 MHz signal to be asserted on the CI+/– output pair. The CI+/– output meets the drive requirements for the AUI. This 10 MHz signal will remain on the CI+/– pair until one of the two colliding states changes from active to idle. The CI+/– output pair stays HIGH for two bit times at the end of a collision, decreasing to the idle level within eighty bit times after the last LOW-to-HIGH transition. Both the XMT and RCV pins are driven HIGH during collision. Test Modes TPEX implements two types of loopback test modes suitable for Station (DTE) or Repeater applications. The Test mode is entered by driving the TEST pin HIGH. The two types of test modes available are: 1. Station (DTE): SQE TEST pin LOW. Data on DO+/– pair is transmitted onto the TXD+/– and TXP+/– pairs and data on the RXD+/– input pair is transmitted onto the DI+/– output pair. The jabber function and collision detection functions are disabled. 2. Repeater: SQE TEST pin HIGH. Data on DO+/– pair is looped back onto the DI+/– pair and data on the RXD+/– pair is retransmitted on the twisted-pair drivers (TXD+/– and TXP+/– pairs). Signal Quality Error (SQE) Test (Heartbeat) Function When the SQE TEST pin is driven LOW, TPEX will routinely exercise the collision detection circuitry by generating an SQE message at the end of every trans- Am79C98 9 In both modes, the jabber circuitry, collision detection, and collision oscillator functions are disabled and the AUI and RXD+/– squelch circuits are active. TPEX External Components F igure 1 shows a typical twisted-pair port external components schematic. The resistors used should have a ±1% tolerance to ensure interoperability with 10BASE-T-compliant networks. Filters and pulse transformers are necessary devices that have a major influence on the performance and compliance of a TPEX- based MAU. Specifically, the transmitted waveforms are heavily influenced by filter characteristics and the twisted-pair receivers employ several criteria to continuously monitor the incoming signal’s amplitude and timing characteristics to determine when and if to assert the internal carrier sense. For these reasons, it is crucial that the values and tolerances of the external components be as specified. Several manufacturers produce a module that combines the functions of the transmit and receive filters and the pulse transformers into one package. TXD+ TXP+ TXD– TXP– 57.6 324.0 768.0 57.6 324.0 1:1 XMIT Filter TD+ TD– Twisted-Pair Cable Am79C100 TPEX 1:1 RXD+ RXD– 100 Ω RECV Filter RD+ RD– Module 14395D-5 Note: The filter/transformer module shown is available from the following manufacturers: Belfuse, TDK, Pulse Engineering, PCA, Valor Electronics, and Nano Pulse. Figure 1. Typical Twisted-Pair Port External Components 10 Am79C98 12 ANLG +5 V Optional 0.1µF 40.2 Ω AUI Connector AVDD DO+ DONote 3 DI+ DINote 2 100 Ω CI+ CIAm79C98 Optional Enable Heartbeat DGTL +5 V DGTL GND ANLG +5 V REXT 24.3 kΩ 1% TEST PWDN/RST DVDD DGTL +5 V DVSS 47 pF 47 pF 100 K COL 0.1µF Optional 4.7µF DGTL GND 14395D-7 AMD 0.01µF 40.2 Ω ANLG GND 57.6 Ω 324.0 Ω 57.6 Ω 768.0 Ω 324.0 Ω XMT Filter Note 1 RD+ 3 RCV Filter RD– 6 ANLG GND 0.1 µF Pulse Transformer AVSS TXD+ TXP+ TXDTXPRXD+ RXDFilter and Transformer Module RJ45 Connector TD+ TD– 1 2 SQE^TEST Am79C98 LNKST RXPOL XMT RCV Figure 3. Typical TPEX System Application LINK OK RX POL OK XMT RCV 330 Ω Notes: 0.01µF 74HC132 DGTL GND 1. Compatible filter modules, with a brief description of package type and features are included in Table 1 of this section. 2. The resistor values are recommended for general purpose use, and should allow compliance to the 10BASE-T specification for template fit and jitter performance. However, the overall performance of the transmitter is also affected by the transmit filter configuration. 3. Compatible AUI transformer modules, with a brief description of package type and features are included in Table 2 of this section. AMD Table 1. TPEX Compatible Media Interface Modules Manufacturer Bel Fuse Bel Fuse Bel Fuse Valor Electronics Valor Electronics Valor Electronics Nano pulse Nano pulse Nano pulse TDK TDK Pulse Engineering Pulse Engineering Bel Fuse Part # A556-2006-DE 0556-2006-00 0556-2006-01 PT3877 PT3983 FL1012 NP6612 NP6581 NP6696 TLA 470 HIM3000 PE65421 SUPRA 1.1 0556-6392-00 Package 16-pin 0.3” DIL 14-pin SIP 14-pin SIP 16-pin 0.3” DIL 8-pin 0.3” DIL 16-pin 0.3” DIL 16-pin 0.3” DIL 8-pin 0.3” DIL 24-pin 0.6” DIL 14-pin SIP 24-pin 0.6” DIL 16-pin 0.3” DIL 16-pin 0.5” DIL 16-pin 0.5” DIL Description Transmit and receive filters and transformers Transmit and receive filters and transformers Transmit and receive filters, transformers and common mode chokes Transmit and receive filters and transformers Transmit and receive common mode chokes Transmit and receive filters and transformers, transmit common mode choke Transmit and receive filters, transformers and common mode chokes Transmit and receive common mode chokes Transmit and receive filters, transformers and common mode chokes Transmit and receive filters and transformers Transmit and receive filters, transformers and common mode chokes Transmit and receive filters and transformers Transmit and receive filters and transformers, transmit common mode choke Transmit and receive filters, transformers, and common mode chokes Table 2. Am79C98 TPEX Compatible AUI Transformers Manufacturer Bel Fuse Valor Electronics TDK Pulse Engineering Part # A553-0506-AB LT6031 TLA 100-3E PE64106 Package 16-pin 0.3” DIL 16-pin 0.3” DIL 16-pin 0.3” DIL 16-pin 0.3” DIL Description 50 µH 50 µH 100 µH 50 µH Am79C98 13 AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature: . . . . . . . . . . . -65°C to +150°C Ambient Temperature Under Bias: . . . . 0°C to +70°C Supply Voltage to AVSS or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Temperature (TA): . . . . . . . . . . . . . . . . 0°C to +70°C Supply Voltages (AVDD, DVDD): . . . . . . . . . +5 V ± 5% Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating range unless otherwise specified Parameter Symbol VIL VIH VOL VOH IILL IILD Parameter Description Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage Input Leakage Current Input Leakage Current (Open drain pins, output inactive) Input Current at DO+, DODO+/- Open Circuit Input Common Mode Voltage (Bias) Differential Mode Input Voltage Range (DO+/-) DO+/- Squelch Threshold DO+ Switching Threshold Differential Output Voltage |(DI+) - (DI-)| OR |(CI+) - (CI-)| DI+/- & CI+/Differential Output Voltage Imbalance DI+/- & CI+/Differential Idle Output Voltage DI+/- & CI+/Differential Idle Output Current DI+/- & CI+/- Common Mode Output Voltage (Note 1) RL = 78 Ω RL = 78 Ω (Note 1) RL = 78 Ω RL = 78 Ω (Note 1) RL = 78 Ω IOL1 = 16 mA (Open drain) IOL2 = 4.0 mA IOH = -0.4 mA 0 < VIN < DVDD + 0.5 V 0 < VIN < DVDD + 0.5 V 2.4 10 500 Test Conditions Min DVSS-0.5 2.0 Max 0.8 0.5 + DVDD 0.4 Unit V V V V µA µA Digital Input Voltage Digital Output Voltage Digital Input Leakage Current AUI IIAXD VAICM VAIDV VASQ VATH VAOD VAODI -1 < Vin < AVDD + 0.5 V IIN = 0 V AVDD = 5 V -500 AVDD - 3.0 -2.5 160 -35 620 -25 500 AVDD - 1.0 +2.5 -275 +35 1100 +25 µA V V mV mV mV mV VAODOFF IAODOFF VAOCM -40 -1 2.5 +40 1 AVDD mV mA V 14 Am79C98 AMD DC CHARACTERISTICS (continued) Parameter Symbol IIRXD RRXD VTIVB VTIDV VTSQ+ VTSQ– VTHS+ VTHS– VRXDTH VTXH VTXL VTXI Parameter Description Input Current at RXD+/– RXD+/– Differential Input Resistance RXD+, RXD– Open Circuit Input Voltage (Bias) Differential Mode Input Voltage Range (RXD+/–) RXD Positive Squelch Threshold (Peak) RXD Negative Squelch Threshold (Peak) RXD Post-Squelch Positive Threshold (Peak) RXD Post-Squelch Negative Threshold (Peak) RXD Switching Threshold TXD+/– and TXP+/– Output HIGH Voltage TXD+/– and TXP+/– Output LOW Voltage TXD+/– and TXP+/– Differential Output Voltage Imbalance TXD+/– and TXP+/– Differential Idle Output Voltage TXD+/– and TXP+/– Differential Driver Output Impedance Input Current at REXT Pin DVDD = +5 V (Note 1) Test Conditions AVSS < VIN < AVDD (Note 1) IIN = 0 mA AVDD = +5 V Sinusoid 5 MHz < f< 10 MHz Sinusoid 5 MHz < f< 10 MHz Sinusoid 5 MHz < f< 10 MHz Sinusoid 5 MHz < f< 10 MHz (Note 1) (Note 2) DVSS = 0 V (Note 2) DVDD = +5 V Min –500 10 AVDD - 3.0 –3.1 300 –520 150 –293 –60 DVDD - 0.6 DVSS –40 AVDD - 1.5 3.1 520 –300 293 –150 60 DVDD DVSS + 0.6 +40 Max 500 Unit µA KΩ V V mV mV mV mV mV V V mV Twisted Pair Interface VTXOFF RTX –40 +40 40 mV Ω IIREXT REXT = 24.3K Ω ± 1% AVDD = +5 V PRDN/RST = HIGH 120 µA Power Supply Current IDD Power Supply Current (Transmitting 10 MHz Data) (Typical TP load) Power Supply Current (Transmitting 10 MHz Data) (No TP load) IDDPRDN Power Supply Current in Power Down Mode 115 mA PRDN/RST = HIGH 90 mA PRDN/RST = LOW 4 mA Am79C98 15 AMD SWITCHING CHARACTERISTICS over COMMERCIAL Parameter Symbol Parameter Description Transmit Timing tPWODO tPWKDO tTON tTSD tDODION tDODISD tTETD tTR tTF tTM tTHD tTLD tTHDP tTLDP tXMTON tXMTOFF tPERLP tPWLP tPWPLP tJA tJR tJREC DO Pulse Width Accept/Reject Threshold DO Pulse Width Maintain/Turn-Off Threshold Transmit Start Up Delay Transmit Static Propagation Delay (DO to TXD) DO to DI Startup Delay DO to DI Static Propagation Delay Transmit End of Transmission Transmitter Rise Time (10% to 90%) Transmitter Fall Time (90% to 10%) Transmitter Rise and Fall Time Mismatch DO L–>H to TXD+ L–>H and TXD- H->L Delay DO H–>L to TXD+ H–>L and TXD– L–>H Delay DO L–>H to TXP+ H–>L and TXP- L->H Delay DO H–>L to TXP+ L–>H and TXP– H->L Delay XMT Asserted Delay XMT De-asserted Delay Idle Signal Period Idle Link Test Pulse Width Predistortion Idle Link Test Pulse Width Transmit Jabber Activation Time Transmit Jabber Reset Time Transmit Jabber Recovery Time (Minimum time gap between transmitted packets to prevent jabber activation) (Note 1) (Note 1) 8 75 40 20 250 1.0 Steady State (Note 1) Steady State (Note 1) Steady State (Note 1) Steady State (Note 1) tTSD – 1.0 tTSD – 1.0 tTSD + 40 tTSD + 40 250 |VIN| > |VASQ| (Note 3) |VIN| > |VASQ| (Note 4) Min 15 105 Max 35 200 300 120 300 100 450 10 10 4 tTSD + 1.0 tTSD + 1.0 tTSD + 60 tTSD + 60 100 300 24 120 60 150 750 – Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ms ms µs 16 Am79C98 AMD SWITCHING CHARACTERISTICS (continued) Parameter Symbol Parameter Description Receive Timing tPWKRD tRON tRVB tRSD tRETD tRHD tRLD tRR tRF tRM tRCVON tRCVOFF tCON tCOFF tPER tCPW tSQED tSQEL RXD Pulse Width Maintain/Turn-Off Threshold Receiver Start Up Delay (RXD to DI+/–) First Validly Timed Bit on DI+/– (RXD to DI) Receiver Static Propagation Delay (RXD to DI) DI End of Transmission RXD L–>H to DI+ L–>H and DI– H–>L Delay RXD H–>L to DI+ H–>L and DI- L->H Delay DI+, DI–, CI+, CI– Rise Time (10% to 90%) DI+, DI–, CI+, CI– Fall Time (10% to 90%) DI+/– & CI+/– Rise and Fall Time Mismatch (|tRR – tRF|) RCV Asserted Delay RCV De-asserted Delay Collision Turn-On Delay (CI+/–) Collision Turn-Off Delay (CI+/–) Collision Period (CI+/–) Collision Output Pulse Width (CI+/-) SQE Test Delay Time SQE Test Length 87 40 600 500 tRON – 50 (Note 1) (Note 1) 200 tRSD – 2.5 tRSD – 2.5 tRSD + 2.5 tRSD + 2.5 5.0 5.0 2.0 tRON + 100 tRSD + 250 500 500 117 60 1600 1500 |VIN| >|VTHS| (Note 5) 5 MHz Sinusoid Min 136 200 Max 200 400 tRON + 100 70 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Collision Detection and SQE Test Notes: 1. Parameter not tested. 2. Uses switching test load. 3. DO pulses narrower than tPWODO (min) will be rejected; pulses wider than tPWODO (max) will turn internal DO carrier sense on. 4. DO pulses narrower than tPWKDO (min) will maintain internal DO carrier sense on; pulses wider than tPWKDO (max) will turn internal DO carrier sense off. 5. RXD pulses narrower than tPWKRD (min) will maintain internal RXD carrier sense on; pulses wider than tPWKRD (max) will turn internal RXD carrier sense off. Am79C98 17 AMD SWITCHING WAVEFORMS tPWPLP TXD+ TXP+ tPWPLP TXD– TXP– tPWLP tPERLP 14395D-9 TP Idle Link Test Pulse SWITCHING TEST CIRCUITS DVDD 294 Ω TXD+ TXD– 100 pF Includes test jig capacitance 294 Ω Test Point DVSS 14395D-10 TXD Switching Test Circuit DVDD 715 Ω TXP+ TXP– 100 pF Includes test jig capacitance 715 Ω Test Point DVSS 14395D-11 TXP Switching Test Circuit Am79C98 19 AMD RECEIVE TEST CIRCUIT DVDD DI+ DI– CI+ CI– 52.3 Ω Test Point 100 pF 154 Ω DVSS 14395D-13 AUI DI, CI Switching Test Circuit DO + / – RXD + / – tCON CI + CI – tCOFF tCPW tPER 14395D-14 Collision Timing DO + / – tSQED CI + CI – tSQEL 14395D-15 SQE Test Timing (SQE^Test Pin Connected to VSS) Am79C98 21 Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am186, Am386, Am486, Am29000, bIMR, eIMR, eIMR+, GigaPHY, HIMIB, ILACC, IMR, IMR+, IMR2, ISA-HUB, MACE, Magic Packet, PCnet, PCnet-FAST, PCnet-FAST+, PCnet-Mobile, QFEX, QFEXr, QuASI, QuEST, QuIET, TAXIchip, TPEX, and TPEX Plus are trademarks of Advanced Micro Devices, Inc. Microsoft is a registered trademark of Microsoft Corporation. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.