AM85C30-8JC

FINAL Am85C30 Enhanced Serial Communications Controller DISTINCTIVE CHARACTERISTICS s Fastest data rate of any Am8530 — 8.192 MHz / 2.048 Mb/s — 10 MHz / 2.5 Mb/s — 16.384 MHz / 4.096 Mb/s s Low-power CMOS technology s Pin and function compatible with other NMOS and CMOS 8530s s Easily interfaced with most CPUs — Compatible with non-multiplexed bus s Many enhancements over NMOS Am8530H — Allows Am85C30 to be used more effectively in high-speed applications — Improves interface capabilities s Two independent full-duplex serial channels s Asynchronous mode features — Programmable stop bits, clock factor, character length and parity — Break detection/generation — Error detection for framing, overrun, and parity s Synchronous mode features — Supports IBM® BISYNC, SDLC, SDLC Loop, HDLC, and ADCCP Protocols Advanced Micro Devices — Programmable CRC generators and checkers — SDLC/HDLC support includes frame control, zero insertion and deletion, abort, and residue handling s Enhanced SCC functions support high-speed frame reception using DMA 14-bit byte counter 10 × 19 SDLC/HDLC Frame Status FIFO Independent Control on both channels Enhanced operation does not allow special receive conditions to lock the 3-byte DATA FIFO when the 10 × 19 FIFO is enabled s Local Loopback and Auto Echo modes s Internal or external character synchronization s 2-Mb/s FM encoding transmit and receive capability using internal DPLL for 16.384-MHz product s Internal synchronization between RxC to PCLK and TxC to PCLK — This allows the user to eliminate external synchronization hardware required by the NMOS device when transmitting or receiving data at the maximum rate of 1/4 PCLK frequency — — — — GENERAL DESCRIPTION AMD’s Am85C30 is an enhanced pin-compatible version of the popular Am8530H Serial Communications Controller. The Enhanced Serial Communications Controller (ESCC) is a high-speed, low-power, multiprotocol communications peripheral designed for use with 8- and 16-bit microprocessors. It has two independent,full-duplex channels and functions as a serial-toparallel, parallel-to-serial converter/controller. AMD’s proprietary enhancements make the Am85C30 easier to interface and more effective in high-speed applications due to a reduction in software burden and the elimination of the need for some external glue logic. The Am85C30 is easy to use due to a variety of sophisticated internal functions, including on-chip baud rate generators, digital phase-locked loops, and crystal oscillators, which dramatically reduce the need for external logic. The device can generate and check CRC codes in any SYNC mode, and can be programmed to check data integrity in various modes. The ESCC also has facilities for modem controls in both channels. In applications where these controls are not needed, the modem controls can be used for general-purpose I/O. This versatile device supports virtually any serial data transfer application such as networks, modems, cassettes, and tape drivers. The ESCC is designed for nonmultiplexed buses and is easily interfaced with most CPUs, such as 80188, 80186, 80286, 8080, Z80, 6800, 68000 and MULTIBUS™. Publication# 10216 Rev. F Issue Date: June 1993 Amendment /0 AMD Enhancements that allow the Am85C30 to be used more effectively in high-speed applications include: s A 10 × 19 bit SDLC/HDLC frame status FIFO array s A 14-bit SDLC/HDLC frame byte counter s Automatic SDLC/HDLC opening frame flag transmission s TxD pin forced High in SDLC NRZI mode after closing flag s Automatic SDLC/HDLC Tx underrun/EOM flag reset s Automatic SDLC/HDLC Tx CRC generator reset/ preset s RTS synchronization to closing SDLC/HDLC flag DTR/REQ deactivation delay significantly reduced s External PCLK to RxC or TxC synchronization requirement eliminated for PCLK divide-by-four operation Other enhancements to improve the Am85C30 interface capabilities include: s Write data valid setup time to falling edge of WR requirement eliminated s Reduced INT response time s Reduced access recovery time (tRC) to 3 PCLK best case (3 1/2 PCLK worst case) s Improved Wait timing s Write Registers WR3, WR4, WR5, and WR10 made readable s Lower priority interrupt masking without INTACK s Complete SDLC/HDLC CRC character reception BLOCK DIAGRAM TxDA Transmitter Receiver RxDA RTxCA TRxCA DTR/REQA SYNCA W/REQA RTSA CTSA DCDA TxDB RxDB RTxCB TRxCB Channel B +5 V GND PCLK DTR/REQB SYNCB W/REQB RTSB CTSB DCDB 10216F-1 Baud Rate Generator Internal Control Logic 10×19 Bit Frame Status FIFO Channel A Registers Data Control 8 5 CPU Bus VO Control Logic Internal Bus Channel A Interrupt Control Lines Interrupt Control Logic Channel B Registers RELATED AMD PRODUCTS Part No. Am7960 80186 80286, 80C286 Description Coded Data Transceiver Highly Integrated 16-Bit Microprocessor High-Performance 16-Bit Microprocessor Part No. Am9517A 5380, 53C80 80188 Am386® Description DMA Controller SCSI Bus Controller Highly Integrated 8-Bit Microprocessor High-Performance 32-Bit Microprocessor 2 Am85C30 AMD CONNECTION DIAGRAMS Top View DIP D1 D3 D5 D7 INT IEO IEI INTACK +5 V W/REQA SYNCA RTxCA RxDA TRxCA TxDA DTR/REQA RTSA CTSA DCDA PCLK 1• 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Am85C30 INT 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 D0 D2 D4 D6 RD WR A/B CE D/C GND W/REQB SYNCB RTxCB RxDB TRxCB TxDB DTR/REQB RTSB CTSB DCDB 10216F-2 PLCC, LCC D7 D5 RD D4 D6 D3 D1 WR D0 D2 6 IEO IEI INTACK +5 V W/REQA SYNCA RTxCA RxDA TRxCA TxDA NC 7 8 9 10 11 12 13 14 15 16 17 54 32 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 A/B CE D/C NC GND W/REQB SYNCB RTxCB RxDB TRxCB TxDB 18 19 20 21 22 23 24 25 26 27 28 PCLK DCDB CTSB CTSA DCDA RTSB DTR/REQA DTR/REQB RTSA NC NC Note: Pin 1 is marked for orientation. 10216F-3 LOGIC SYMBOL Data Bus Bus Timing and Reset 8 D7–D0 RD WR A/B Control CE D/C TxDA RxDA TRxCA RTxCA SYNCA W/REQA DTR/REQA RTSA CTSA DCDA TxDB RxDB TRxCB RTxCB SYNCB W/REQB DTR/REQB RTSB CTSB DCDB Serial Data Channel Clocks Channel Controls for Modem, DMA, or Other Interrupt INT INTACK IEI IE0 Serial Data Channel Clocks Channel Controls for Modem, DMA, or Other 10216F-4 +5 V GND PCLK Am85C30 3 AMD ORDERING INFORMATION Commodity Products AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM85C30 -10 P C OPTIONAL PROCESSING Blank = Standard Processing TEMPERATURE RANGE C = Commercial (0 to +70°C) PACKAGE TYPE P = 40-Pin Plastic DIP (PD 040) J = 44-Pin Plastic Leaded Chip Carrier (PL 044) SPEED OPTION -8 = 8.192 MHz -10 = 10 MHz -16 = 16.384 MHz DEVICE NUMBER/DESCRIPTION Am85C30 Enhanced Serial Communications Controller Valid Combinations AM85C30-8 AM85C30-10 AM85C30-16 PC, JC Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and check on newly released combinations. 4 Am85C30 AMD ORDERING INFORMATION Industrial Products AMD industrial products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM85C30 -10 J I OPTIONAL PROCESSING Blank = Standard Processing TEMPERATURE RANGE I = Industrial (-40 to +85°C) PACKAGE TYPE J = 44-Pin Leadless Chip Carrier (PL 044) SPEED OPTION -10 = 10 MHz -16 = 16.384 MHz DEVICE NUMBER/DESCRIPTION Am85C30 Enhanced Serial Communications Controller Valid Combinations AM85C30-10 AM85C30-16 JI Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and check on newly released combinations. Am85C30 5 AMD MILITARY ORDERING INFORMATION APL Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883 requirements. The order number (Valid Combination) is formed by a combination of: AM85C30 -10 B U A LEAD FINISH A = Hot Solder Dip PACKAGE TYPE U = 44-Pin Leadless Chip Carrier (CL 044) Q = 40-Pin Ceramic DIP (CD 040) DEVICE CLASS /B = Class B SPEED OPTION -8 = 8.192 MHz -10 = 10 MHz -16 = 16.384 MHz DEVICE NUMBER/DESCRIPTION Am85C30 Enhanced Serial Communications Controller Valid Combinations AM85C30-8 AM85C30-10 AM85C30-16 BQA, BUA Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and check on newly released combinations. 6 Am85C30 AMD PIN DESCRIPTION Bus Timing and Reset RD Read (Input; Active Low) This signal indicates a Read operation and, when the SCC is selected, enables the SCC’s bus drivers. During the Interrupt Acknowledge cycle, this signal gates the interrupt vector onto the bus if the SCC is the highest priority device requesting an interrupt. used as general-purpose input pins. Both are Schmitttrigger buffered to accommodate slow rise-time signals. The SCC detects pulses on these pins and may interrupt the CPU on both logic level transitions. DTR/REQA, DTR/REQB Data Terminal Ready/Request (Outputs; Active Low) These outputs follow the inverted state programmed into the DTR bit in WR5. They can also be used as general-purpose outputs or as Request Lines for a DMA controller. WR Write (Input; Active Low) When the SCC is selected, this signal indicates a Write operation. The coincidence of RD and WR is interpreted as a reset. RTSA, RTSB Request to Send (Outputs; Active Low) When the Request to Send (RTS) bit in Write Register 5 is set, the RTS signal goes Low. When the RTS bit is reset in the asynchronous mode and Auto Enable is on, the signal goes High after the transmitter is empty. In SYNC mode, or in asynchronous mode with Auto Enable off, the RTS pins strictly follow the inverted state of the RTS bit. Both pins can be used as general-purpose outputs. In SDLC mode, the AUTO RTS RESET enhancement described later in this document brings RTS High after the last 0 of the closing flag leaves the TxD pin. Channel Clocks RTxCA, RTxCB Receive/Transmit Clocks (Inputs; Active Low) These pins can be programmed in several different modes of operation. In each channel, RTxC may supply the receive clock, the transmit clock, the clock for the baud rate generator, or the clock of the digital phaselocked loop. These pins can also be programmed for use with the respective SYNC pins as a crystal oscillator. The receive clock may be 1, 16, 32, or 64 times the data rate in asynchronous modes. TRxCA, TRxCB Transmit/Receive Clocks (Inputs/Outputs; Active Low) These pins can be programmed in several different modes of operation. TRxC may supply the receive clock or the transmit clock in the input mode or supply the output of the digital phase-locked loop, the crystal oscillator, the baud rate generator, or the transmit clock in the output mode. SYNCA, SYNCB Synchronization (Inputs/Outputs; Active Low) These pins can act either as inputs, outputs, or part of the crystal oscillator circuit. In the Asynchronous Receive mode (crystal oscillator option not selected), these pins are inputs similar to CTS and DCD. In this mode, transitions on these lines affect the state of the Sync/ Hunt status bits in Read Register 0 but have no other function. In External Synchronization mode with the crystal oscillator not selected, these lines also act as inputs. In this mode, SYNC must be driven Low two receive clock cycles after the last bit in the SYNC character is received. Character assembly begins on the rising edge of the receive clock immediately preceding the activation of SYNC. In the Internal Synchronization mode (Monosync and Bisync) with the crystal oscillator not selected, these pins act as outputs and are active only during the part of the receive clock cycle in which SYNC characters are recognized. The SYNC condition is not latched, so these outputs are active each time a SYNC pattern is recognized (regardless of character boundaries). In SDLC mode, these pins act as outputs and are valid on receipt of a flag. Channel Controls for Modem, DMA, or Other CTSA, CTSB Clear to Send (Inputs; Active Low) If these pins are programmed as Auto Enables, a Low on these inputs enables their respective transmitters. If not programmed as Auto Enables, they may be used as general-purpose inputs. Both inputs are Schmitt-trigger buffered to accommodate slow rise-time inputs. The SCC detects pulses on these inputs and may interrupt the CPU on both logic level transitions. DCDA, DCDB Data Carrier Detect (Inputs; Active Low) These pins function as receiver enables if they are programmed as Auto Enables; otherwise, they may be Am85C30 7 AMD W/ REQA, W/ REQB Wait/Request (Outputs; Open drain when programmed for a Wait function, driven High or Low when programmed for a Request function) These dual-purpose outputs may be programmed as Request lines for a DMA controller or as Wait lines to synchronize the CPU to the SCC data rate. The reset state is Wait. interrupt (interrupt acknowledge cycle only). IEO is connected to the next lower priority device’s IEI input and thus inhibits interrupts from lower priority devices. INT Interrupt Request (Output; Active Low, Open Drain) This signal is activated when the SCC requests an interrupt. Control A/ B Channel A/Channel B Select (Input) This signal selects the channel in which the Read or Write operation occurs. INTACK Interrupt Acknowledge (Input; Active Low) This signal indicates an active interrupt acknowledge cycle. During this cycle, the SCC interrupt daisy chain settles. When RD becomes active, the SCC places an interrupt vector on the data bus (if IEI is High). INTACK is latched by the rising edge of PCLK. CE Chip Enable (Input; Active Low) This signal selects the SCC for a Read or Write operation. Serial Data RxDA, RxDB Receive Data (Inputs; Active High) These input signals receive serial data at standard TTL levels. D/ C Data/Control Select (Input) This signal defines the type of information transferred to or from the SCC. A High means data is transferred; a Low indicates a command is transferred. TxDA, TxDB Transmit Data (Outputs; Active High) These output signals transmit serial data at standard TTL levels. Data Bus D7 –D0 Data Bus (Input/Output; Three State) These lines carry data and commands to and from the SCC. Miscellaneous GND Ground Interrupt IEI Interrupt Enable In (Input; Active High) IEI is used with IEO to form an interrupt daisy chain when there is more than one interrupt-driven device. A High IEI indicates that no other higher priority device has an interrupt under service or is requesting an interrupt. PCLK Clock (Input) This is the master SCC clock used to synchronize internal signals. PCLK is not required to have any phase relationship with the master system clock. PCLK is a TTL- level signal. Maximum transmit rate is 1/4 PCLK. VCC + 5 V Power Supply IEO Interrupt Enable Out (Output; Active High) IEO is High only if IEI is High and the CPU is not servicing an SCC interrupt or the SCC is not requesting an 8 Am85C30 AMD ARCHITECTURE The ESCC internal structure includes two full-duplex channels, two 10 × 19 bit SDLC/HDLC frame status FIFOs, two baud rate generators, internal control and interrupt logic, and a bus interface to a non-multiplexed bus. Associated with each channel are a number of Read and Write registers for mode control and status information, as well as logic necessary to interface with modems or other external devices (see Logic Symbol). The logic for both channels provides formats, synchronization, and validation for data transferred to and from the channel interface. The modem control inputs are monitored by the control logic under program control. All of the modem control signals are general-purpose in nature and can optionally be used for functions other than modem control. The register set for each channel includes ten control (Write) registers, two SYNC character (Write) registers, and four status (Read) registers. In addition, each baud rate generator has two (Read/Write) registers for holding the time constant that determines the baud rate. Finally, associated with the interrupt logic is a Write register for the interrupt vector accessible through either channel, a Write-only Master Interrupt Control register, and three Read registers: one containing the vector with status information (Channel B only), one containing the vector without status (A only), and one containing the interrupt pending bits (A only). The registers for each channel are designated as follows: WR0–WR15—Write Registers 0 through 15. An additional Write register, WR7 Prime (WR7′), is available for enabling or disabling additional SDLC/HDLC enhancements if bit D0 of WR15 is set. RR0–RR3, RR10, RR12, RR13, RR15—Read Registers 0 through 3, 10, 12, 13, and 15. If bit D2 of WR15 is set, then two additional Read registers, RR6 and RR7, are available. These registers are used with the 10 × 19 bit Frame Status FIFO. Table 1 lists the functions assigned to each Read and Write register. The ESCC contains only one WR2 and WR9, but they can be accessed by either channel. All other registers are paired (one for each channel). Baud Rate Generator Internal Control Logic Data Control 8 5 Interrupt Control Lines Interrupt Control Logic Channel B Registers Channel A Registers 10×19 Bit Frame Status FIFO Channel A TxDA Transmitter Receiver RxDA RTxCA TRxCA SYNCA Control Logic RTSA CTSA DCDA CPU Bus VO Internal Bus TxDB RxDB RTxCB TRxCB Channel B SYNCB RTSB CTSB DCDB +5 V GND PCLK 10216F-5 Figure 1. Block Diagram of ESCC Architecture Am85C30 9 AMD Data Path The transmit and receive data path illustrated in Figure 2 is identical for both channels. The receiver has three 8-bit buffer registers in a FIFO arrangement, in addition to the 8-bit receive shift register. This scheme creates additional time for the CPU to service an interrupt at the beginning of a block of high-speed data. Incoming data are routed through one of several paths (data or CRC) depending on the selected mode (the character length in asynchronous modes also determines the data path). The transmitter has an 8-bit transmit data buffer register loaded from the internal data bus and a 20-bit transmit shift register that can be loaded either from the synccharacter registers or from the transmit data register. Depending on the operational mode, outgoing data are routed through one of four main paths before they are transmitted from the Transmit Data output (TxD). Table 1. Read and Write Register Functions Read Register Functions Write Register Functions RR0 Transmit/Receive buffer status and External status RR1 Special Receive Condition status (also 10 × 19 bit FIFO Frame Reception Status if WR15 bit D2 is set) RR2 Modified interrupt vector (Channel B only) Unmodified interrupt vector (Channel A only) RR3 Interrupt Pending bits (Channel A only) RR6 LSB Byte Count (14-bit counter) (if WR15 bit D2 set) RR7 MSB Byte Count (14-bit counter) and 10 × 19 bit FIFO Status (if WR15 bit D2 is set) RR8 Receive buffer RR10 Miscellaneous XMTR, RCVR status RR12 Lower byte of baud rate generator time constant RR13 Upper byte of baud rate generator time constant RR15 External/Status interrupt information Write Register Functions WR0 Command Register, Register Pointers CRC initialize, initialization commands for the various modes, shift right/shift left command Interrupt conditions and data transfer mode definition Interrupt vector (accessed through either channel) Receive parameters and control Transmit/Receive miscellaneous parameters and modes Transmit parameters and controls Sync character or SDLC address field Sync character or SDLC flag SDLC/HDLC enhancements (if bit D0 of WR15 is set) Transmit buffer Master interrupt control and reset (accessed through either channel) Miscellaneous transmitter/receiver control bits, data encoding Clock mode control, Rx and Tx clock source Lower byte of baud rate generator time constant Upper byte of baud rate generator time constant Miscellaneous control bits, DPLL control External/Status interrupt control WR1 WR2 WR3 WR4 WR5 WR6 WR7 WR7′ WR8 WR9 WR10 WR11 WR12 WR13 WR14 WR15 10 Am85C30 AMD Am85C30 11 AMD DETAILED DESCRIPTION The functional capabilities of the ESCC can be described from two different points of view: as a data communications device, it transmits and receives data in a wide variety of data communications protocols; as a microprocessor peripheral, it interacts with the CPU and provides vectored interrupts and handshaking signals. The ESCC does not require symmetric transmit and receive clock signals—a feature allowing use of the wide variety of clock sources. The transmitter and receiver can handle data at a rate of 1, 1/16, 1/32, or 1/64 of the clock rate supplied to the receive and transmit clock inputs. In asynchronous modes, the SYNC pin may be programmed as an input used for functions, such as monitoring a ring indicator. Data Communications Capabilities The ESCC provides two independent full-duplex channels programmable for use in any common asynchronous or SYNC data-communication protocol. Figure 3 and the following description briefly detail these protocols. Synchronous Modes The ESCC supports both byte-oriented and bit-oriented synchronous communication. SYNC byte-oriented protocols can be handled in several modes, allowing character synchronization with a 6-bit or 8-bit SYNC character (Monosync), any 12-bit or 16-bit SYNC pattern (Bisync), or with an external SYNC signal. Leading SYNC characters can be removed without interrupting the CPU. 5- or 7-bit SYNC characters are detected with 8- or 16-bit patterns in the ESCC by overlapping the larger pattern across multiple incoming SYNC characters as shown in Figure 4. CRC checking for Synchronous byte-oriented modes is delayed by one character time so that the CPU may disable CRC checking on specific characters. This permits the implementation of protocols, such as IBM BISYNC. Both CRC-16 (X16 + X15 + X2 + 1) and CCITT (X16 + X12 + X5 + 1) error-checking polynomials are supported. Either polynomial may be selected in BISYNC and MONO-SYNC modes. Users may preset the CRC generator and checker to all 1s or all 0s. The ESCC also provides a feature that automatically transmits CRC data when no other data are available for transmission. This allows for high-speed transmissions under DMA control Asynchronous Modes Transmission and reception can be accomplished independently on each channel with 5 to 8 bits per character, plus optional even or odd parity. The transmitters can supply 1, 1 1/2, or 2 stop bits per character and can provide a break output at any time. The receiver breakdetection logic interrupts the CPU both at the start and at the end of a received break. Reception is protected from spikes by a transient spike-rejection mechanism that checks the signal one-half a bit time after a Low level is detected on the receive data input. If the Low does not persist (as in the case of a transient), the character assembly process does not start. Framing errors and overrun errors are detected and buffered together with the partial character on which they occur. Vectored interrupts allow fast servicing of error conditions using dedicated routines. Furthermore, a built-in checking process avoids the interpretation of framing error as a new start bit; a framing error results in the addition of one-half a bit time to the point at which the search for the next start bit begins. Start Marking Line Parity Stop Data Data Asynchronous Sync Data Monosync Sync Sync Data Signal Data External Sync Flag Address Information SDLC/HDLC × 25 Bisync Data Marking Line Data CRC1 CRC2 Data CRC1 CRC2 Data CRC1 CRC2 CRC1 CRC2 Flag 10216F-7 Figure 3. SCC Protocols 12 Am85C30 AMD 5 Bits Sync Sync Sync 8 Bits 16 Bits 10216F-8 Data Data Data Data Figure 4. Detecting 5- or 7-Bit Synchronous Characters with no need for CPU intervention at the end of a message. When there are no data or CRC to send in SYNC modes, the transmitter inserts 6-, 8-, or 16-bit SYNC characters, regardless of the programmed character length. The ESCC supports SYNC bit-oriented protocols, such as SDLC and HDLC, by performing automatic flag sending, zero-bit insertion, and CRC generation. A special command can be used to abort a frame in transmission. At the end of a message, the ESCC automatically transmits the CRC and trailing flag when the transmitter underruns. The transmitter may also be programmed to send an idle line consisting of continuous flag characters or a steady marking condition. If a transmit underrun occurs in the middle of a message, an external/status interrupt warns the CPU of this status change so that an abort may be issued. The ESCC may also be programmed to send an abort itself in case of an underrun, relieving the CPU of this task. One to 8 bits per character can be sent allowing reception of a message with no prior information about the character structure in the information field of a frame. The receiver automatically acquires synchronization on the leading flag of a frame in SDLC or HDLC and provides a synchronization signal on the SYNC pin (an interrupt can also be programmed). The receiver can be programmed to search for frames addressed by a single byte (or 4 bits within a byte) of a user-selected address or to a global broadcast address. In this mode, frames not matching either the user-selected or broadcast address are ignored. The number of address bytes can be extended under software control. For receiving data, an interrupt on the first received character, or an interrupt on every character, or on special condition only (end-offrame) can be selected. The receiver automatically deletes all 0s inserted by the transmitter during character assembly. CRC is also calculated and is automatically checked to validate frame transmission. At the end of transmission, the status of a received frame is available in the status registers. In SDLC mode, the ESCC must be programmed to use the SDLC CRC polynomial, but the generator and checker may be preset to all 1s or all 0s. The CRC is inverted before transmission and the receiver checks against the bit pattern 0001110100001111. NRZ, NRZI or FM coding may be used in any 1X mode. The parity options available in asynchronous modes are available in synchronous modes. The ESCC can be conveniently used under DMA control to provide high-speed reception or transmission. In reception, for example, the ESCC can interrupt the CPU when the first character of a message is received. The CPU then enables the DMA to transfer the message to memory. The ESCC then issues an end-of-frame interrupt and the CPU can check the status of the received message. Thus, the CPU is freed for other service while the message is being received. The CPU may also enable the DMA first and have the ESCC interrupt only on end-of-frame. This procedure allows all data to be transferred via the DMA. SDLC Loop Mode The ESCC supports SDLC Loop mode in addition to normal SDLC. In a SDLC Loop, there is a primary controller station that manages the message traffic flow and any number of secondary stations. In SDLC Loop mode, the ESCC performs the functions of a secondary station while an ESCC operating in regular SDLC mode can act as a controller (Figure 5). Controller Secondary #1 Secondary #2 Secondary #3 Secondary #4 10216F-9 Figure 5. A SDLC Loop A secondary station in a SDLC Loop is always listening to the messages being sent around the loop and, in fact, must pass these messages to the rest of the loop by retransmitting them with a 1-bit time delay. The secondary station can place its own message on the loop only at specific times. The controller signals that secondary stations may transmit messages by sending a special character, called an EOP (End of Poll), around the loop. The EOP character is the bit pattern 11111110. Because of zero insertion during messages, this bit pattern is unique and easily recognized. Am85C30 13 AMD When a secondary station has a message to transmit and recognizes an EOP on the line, it changes the last binary 1 of the EOP to a 0 before transmission. This has the effect of turning the EOP into a flag sequence. The secondary station now places its message on the loop and terminates the message with an EOP. Any secondary stations farther down the loop with messages to transmit can then append their messages to the message of the first secondary station by the same process. Any secondary stations without messages to send merely echo the incoming messages and are prohibited from placing messages on the loop (except upon recognizing an EOP). SDLC Loop mode is a programmable option in the ESCC. NRZ, NRZI, and FM coding may all be used in SDLC Loop mode. Time Constant Values for Standard Baud Rates at BR Clock = 3.9936 MHz Rate (Baud) 19200 9600 7200 4800 3600 2400 2000 1800 1200 600 300 150 134.5 110 75 50 Time Constant (decimal/Hex notation) 102 206 275 414 553 830 996 1107 1662 3326 6654 13310 14844 18151 26622 39934 (0066) (00CE) (0113) (019E) (0229) (033E) (03E4) (0453) (067E) (0CFE) (19FE) (33FE) (39FC) (46E7) (67FE) (98FE) Error 0 0 0.12% 0 0.06% 0 0.04% 0.03% 0 0 0 0 0.0007% 0.0015% 0 0 Baud Rate Generator Each channel in the ESCC contains a programmable baud rate generator. Each generator consists of two 8-bit time constant registers that form a 16-bit time constant, a 16-bit down counter, and a flip-flop on the output producing a square wave. On start-up, the flip-flop on the output is set in a High state, the value in the time constant register is loaded into the counter, and the counter starts counting down. The output of the baud rate generator toggles upon reaching zero; the value in the time constant register is loaded into the counter, and the process is repeated. The time constant may be changed at any time, but the new value does not take effect until the next load of the counter. The output of the baud rate generator may be used as either the transmit clock, the receive clock, or both. It can also drive the digital phase-locked loop (see next section). If the receive clock or transmit clock is not programmed to come from the TRxC pin, the output of the baud rate generator may be echoed out via the TRxC pin. The following formula relates the time constant to the baud rate where PCLK or RTxC is the baud rate generator input frequency in Hz. The clock mode is X1, X16, X32, or X64 as selected in Write Register 4, bits D6 and D7. Synchronous operation modes should select X1 and asynchronous should select X16, X32, or X64. PCLK or RTxC Frequency Time Constant = 2 (Baud Rate)(Clock Mode) The following formula relates the time constant to the baud rate. The baud rate is in bits/second. Baud Rate = PCLK or RTxC Frequency 2 × (Clock Mode) × (Time Constant + 2) –2 Digital Phase-Locked Loop The ESCC contains a digital phase-locked loop (DPLL) to recover clock information from a data stream with NRZI or FM encoding. The DPLL is driven by a clock that is nominally 32 (NRZI) or 16 (FM) times the data rate. The DPLL uses this clock, along with the data stream, to construct a clock for the data. This clock may then be used as the SCC receive clock, the transmit clock, or both. For NRZI encoding, the DPLL counts the 32X clock to create nominal bit times. As the 32X clock is counted, the DPLL is searching the incoming data stream for edges (either 1/0 or 0/1). As long as no transitions are detected, the DPLL output will be free running and its input clock source will be divided by 32, producing an output clock without any phase jitter. Upon detecting a transition the DPLL will adjust its clock output (during the next counting cycle) by adding or subtracting a count of 1, thus producing a terminal count closer to the center of the bit cell. The adding or subtracting of a count of 1 will produce a phase jitter of ±5.63° on the output of the DPLL. Because the SCC’s DPLL uses both edges of the incoming signal to compare with its clock source, the mark-space ratio (50%) of the incoming signal should not deviate by more than ±1.5% if proper locking is to occur. For FM encoding, the DPLL still counts from 0 to 31, but with a cycle corresponding to two bit times. When the DPLL is locked, the clock edges in the data stream should occur between counts 15 and 16 and between 14 Am85C30 AMD counts 31 and 0. The DPLL looks for edges only during a time centered on the 15/16 counting transition. The 32X clock for the DPLL can be programmed to come from either the RTxC input or the output of the baud rate generator. The DPLL output may be programmed to be echoed out of the SCC via the TRxC pin (if this pin is not being used as an input). additional transition at the center of the bit cell. In FM0 (biphase space), a transition occurs at the beginning of every bit cell. A 0 is represented by an additional transition at the center of the bit cell, and a 1 is represented by no additional transition at the center of the bit cell. In addition to these four methods, the ESCC can be used to decode Manchester (biphase level) data by using the DPLL in the FM mode and programming the receiver for NRZ data. Manchester encoding always produces a transition at the center of the bit cell. If the transition is 0/1, the bit is a 0. If the transition is 1/0, the bit is a 1. Auto Echo and Local Loopback The ESCC is capable of automatically echoing everything it receives. This feature is useful mainly in asynchronous modes but works in SYNC and SDLC modes as well. In Auto Echo mode, TxD is RxD. Auto Echo mode can be used with NRZI or FM encoding with no additional delay, because the data stream is not decoded before retransmission. In Auto Echo mode, the CTS input is ignored as a transmitter enable (although transitions on this input can still cause interrupts if programmed to do so). In this mode, the transmitter is actually bypassed, and the programmer is responsible for disabling transmitter interrupts and WAIT/ REQUEST on transmit. The ESCC is also capable of Local Loopback. In this mode, TxD is RxD just as in Auto Echo mode. However, in Local Loopback mode, the internal transmit data is tied to the internal receive data, and RxD is ignored (except to be echoed out via TxD). The CTS and DCD inputs are also ignored as transmit and receive enables. However, transitions on these inputs can still cause interrupts. Local Loopback works in asynchronous, SYNC, and SDLC modes with NRZ, NRZI, or FM coding of the data stream. 0 1 0 Crystal Oscillator When using a crystal oscillator to supply the receive or transmit clocks to a channel of the SCC, the user should: 1. Select a crystal oscillator that satisfies the following specifications: 30 ppm @ 25°C 50 ppm over temperatures of –20° to 70°C 5 ppm/yr aging 5-MW drive level 2. Place crystal across RTxC and SYNC pins. 3. Place 30-pF capacitors to ground from both RTxC and SYNC pins. 4. Set bit D7 of WR11 to 1. Data Encoding The ESCC may be programmed to encode and decode the serial data in four different ways (Figure 6). In NRZ encoding, a 1 is represented by a High level, and a 0 is represented by a Low level. In NRZI encoding, a 1 is represented by no change in level, and a 0 is represented by a change in level. In FM1 (more properly, biphase mark), a transition occurs at the beginning of every bit cell. A 1 is represented by an additional transition at the center of the bit cell, and a 0 is represented by no Data NRZ 1 1 0 Bit Cell Level High = 1 Low = 0 No Change = 1 Change = 0 Bit Center Transition Transition = 1 No Transition = 0 No Transition = 1 Transition = 0 NRZI FM1 (Biphase Mark) (Biphase Mark) FM0 Manchester High Low = 1 Low High = 0 10216F-10 Figure 6. Data Encoding Methods Am85C30 15 AMD I/O Interface Capabilities The ESCC offers the choice of Polling, Interrupt (vectored or nonvectored), and Block Transfer modes to transfer data, status, and control information to and from the CPU. The Block Transfer mode can be implemented under CPU or DMA control. The other 2 bits are related to the Z-Bus interrupt priority chain (Figure 7). As a Z-Bus peripheral, the ESCC may request an interrupt only when no higher priority device is requesting one, for example, when IEI is High. If the device in question requests an interrupt, it pulls down INT. The CPU then responds with INTACK, and the interrupting device places the vector on the A/D bus. In the SCC, the IP bit signals a need for interrupt servicing. When an IP bit is set to 1 and the IEI input is High, the INT output is pulled Low, requesting an interrupt. In the ESCC, if the IE bit is set for an interrupt, then the IP for that source can never be set. The IP bits are readable in RR3A. The IUS bits signal that an interrupt request is being serviced. If an IUS is set, all interrupt sources of lower priority in the ESCC and external to the ESCC are prevented from requesting interrupts. The internal interrupt sources are inhibited by the state of the internal daisy chain, while lower priority devices are inhibited by the IEO output of the ESCC being pulled Low and propagated to subsequent peripherals. An IUS bit is set during an Interrupt Acknowledge cycle if there are no higher priority devices requesting interrupts. There are three types of interrupts: Transmit, Receive, and External/Status. Each interrupt type is enabled under program control with Channel A having higher priority than Channel B, and with Receive, Transmit, and External/Status interrupts prioritized in that order within each channel. When the Transmit interrupt is enabled, the CPU is interrupted when the transmit buffer becomes empty. (This implies that the transmitter must have had a data character written into it so that it can become empty.) When enabled, the Receive can interrupt the CPU in one of three ways: Interrupt on First Receive Character or Special Receive condition Interrupt on all Receive Characters or Special Receive condition Interrupt on Special Receive condition only Polling All interrupts are disabled. Three status registers in the ESCC are automatically updated whenever any function is performed. For example, end-of-frame in SDLC mode sets a bit in one of these status registers. The idea behind polling is for the CPU to periodically read a status register until the register contents indicate the need for data to be transferred. Only one register needs to be read; depending on its contents, the CPU either writes data, reads data, or continues. Two bits in the register indicate the need for data transfer. An alternative is a poll of the Interrupt Pending register to determine the source of an interrupt. The status for both channels resides in one register. Interrupts When an ESCC responds to an Interrupt Acknowledge signal (INTACK) from the CPU, an interrupt vector may be placed on the data bus. This vector is written in WR2 and may be read in RR2A or RR2B (Figures 8 and 9). To speed interrupt response time, the ESCC can modify 3 bits in this vector to indicate status. If the vector is read in Channel A, status is never included; if it is read in Channel B, status is always included. Each of the six sources of interrupts in the ESCC (Transmit, Receive, and External/Status interrupts in both channels) has 3 bits associated with the interrupt source: Interrupt Pending (IP), Interrupt Under Service (IUS), and Interrupt Enable (IE). Operation of the IE bit is straightforward. If the IE bit is set for a given interrupt source, then that source can request interrupts. The exception is when the MIE (Master Interrupt Enable) bit in WR9 is reset and no interrupts may be requested. The IE bits are write-only. Peripheral +5 V IEI AD7–AD0 INT INTACK IEO D7–D0 AD7–AD0 INT INTACK Peripheral IEI AD7–AD0 INT INTACK IEO Peripheral IEI AD7–AD0 INT INTACK +5 V 10216F-11 Figure 7. Z-Bus Interrupt Schedule 16 Am85C30 AMD Interrupt on First Character or Special Condition and Interrupt on Special Condition Only are typically used with the Block Transfer mode. A Special Receive Condition is one of the following: receiver overrun, framing error in asynchronous mode, end-of-frame in SDLC mode, and optionally, a parity error. The Special Receive Condition interrupt is different from an ordinary Receive Character Available interrupt only in the status placed in the vector during the Interrupt Acknowledge cycle. In Interrupt on First Receive Character, an interrupt can occur from Special Receive Conditions any time after the first Receive Character Interrupt. The main function of the External/Status interrupt is to monitor the signal transitions of the CTS, DCD, and SYNC pins; however, an External/Status interrupt is also caused by a Transmit Underrun condition, a zero count in the baud rate generator, the detection of a Break (asynchronous mode), Abort (SDLC mode), or EOP (SDLC Loop mode) sequence in the data stream. The interrupt caused by the Abort or EOP has a special feature allowing the ESCC to interrupt when the Abort or EOP sequence is detected or terminated. This feature facilitates the proper termination of the current message, correct initialization of the next message, and the accurate timing of the Abort condition in external logic in SDLC mode. In SDLC Loop mode, this feature allows secondary stations to recognize the wishes of the primary station to regain control of the loop during a poll sequence. CPU/DMA Block Transfer The SCC provides a Block Transfer mode to accommodate CPU block transfer functions and DMA controllers. The Block Transfer mode uses the WAIT/REQUEST output in conjunction with the Wait/Request bits in WR1. The WAIT/REQUEST output can be defined under software control as a WAIT line in the CPU Block Transfer mode or as a REQUEST line in the DMA Block Transfer mode. To a DMA controller, the ESCC REQUEST output indicates that the ESCC is ready to transfer data to or from memory. To the CPU, the WAIT line indicates that the SCC is not ready to transfer data, thereby requesting that the CPU extend the I/O cycle. The DTR/REQUEST can be used as the transmit request line, thus allowing full-duplex operation under DMA control. PROGRAMMING INFORMATION Each channel has fifteen Write registers that are individually programmed from the system bus to configure the functional personality of each channel. Each channel also has eight Read registers from which the system can read Status, Baud rate, or Interrupt information. On the Am85C30, only four data registers (Read and Write for Channels A and B) are directly selected by a High on the D/C input and the appropriate levels on the RD, WR, and A/B pins. All other registers are addressed indirectly by the content of Write Register 0 in conjunction with a Low on the D/C input and the appropriate levels on the RD, WR, and A/B pins. If bit D3 in WR0 is 1 and bits 5 and 6 are 0, then bits 0, 1, and 2 address the higher registers 8 through 15. If bits 4, 5, and 6 contain a different code, bits 0, 1, and 2 address the lower registers 0 through 7 as shown in Table 2. Writing to or reading from any register except RR0, WR0, and the data registers thus involves two operations: First, write the appropriate code into WR0, then follow this by a Write or Read operation on the register thus specified. Bits 0 through 4 in WR0 are automatically cleared after this operation, so that WR0 then points to WR0 or RR0 again. Channel A/Channel B selection is made by the A/B input (High = A, Low = B). The system program first issues a series of commands to initialize the basic mode of operation. This is followed by other commands to qualify conditions within the selected mode. For example, the asynchronous mode, character length, clock rate, number of stop bits, even or odd parity might be set first. Then the interrupt mode would be set and, finally, receiver or transmitter enable. Am85C30 17 AMD Table 2. Register Addressing D/C High Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low “Point High” Code In WR0: Either Way Not True Not True Not True Not True Not True Not True Not True Not True True True True True True True True True X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D2, D1, D0 In WR0: X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Write Register Data 0 1 2 3 4 5 6 7 Data 9 10 11 12 13 14 15 Read Register Data 0 1 2 3 (0) (1) (2) (3) Data – 10 (15) 12 13 (10) 15 Read Registers The ESCC contains eight Read registers [actually nine, counting the receive buffer (RR8) in each channel]. Four of these may be read to obtain status information (RR0, RR1, RR10, and RR15). Two registers (RR12 and RR13) may be read to learn the baud rate generator time constant. RR2 contains either the unmodified interrupt vector (Channel A) or the vector modified by status information (Channel B). RR3 contains the Interrupt Pending (IP) bits (Channel A). In addition, if bit D2 of WR15 is set, RR6 and RR7 are available for providing frame status from the 10 × 19 bit Frame Status FIFO. Figure 8 shows the formats for each Read register. The status bits of RR0 and RR1 are carefully grouped to simplify status monitoring, for example, when the interrupt vector indicates a Special Receive Condition interrupt, all the appropriate error bits can be read from a single register (RR1). Please refer to Am85C30 Technical Manual for detailed descriptions of the read registers. Write Registers The ESCC contains 15 Write registers (16 counting WR8, the transmit buffer) in each channel. These Write registers are programmed separately to configure the functional “personality” of the channels. Two registers (WR2 and WR9) are shared by the two channels that can be accessed through either of them. WR2 contains the interrupt vector for both channels, while WR9 contains the interrupt control bits. In addition, if bit D0 of WR15 is set, Write Register 7 prime (WR7′) is available for programming additional SDLC/HDLC enhancements. When bit D0 of WR15 is set, executing a write to WR7 actually writes to WR7′ to further enhance the functional “personality” of each channel. Figure 8 shows the format of each Write register. 18 Am85C30 AMD Read Register 0 D7 D6 D5 D4 D3 D2 D1 D0 Rx Character Available Zero Count Tx Buffer Empty DCD SYNC Hunt CTS Tx Underrun/EOM Break Abort Read Register 3 D7 D6 D5 D4 D3 D2 D1 D0 Channel B EXT STAT IP* Channel B Tx IP* Channel B Rx IP* Channel A EXT STAT IP* Channel A Tx IP* Channel A Rx IP* 0 0 *Always 0 in B Channel Read Register 1 D7 D6 D5 D4 D3 D2 D1 D0 All Sent Residue Code 2 Residue Code 1 Residue Code 0 Parity Error Rx Overrun Error CRC Framing Error End-of-Frame (SDLC) Read Register 6 D7 D6 D5 D4 D3 D2 D1 D0 BC0 BC1 BC2 BC3 BC4 BC5 BC6 BC7 14-Bit LSB Byte Count Read Register 2 D7 D6 D5 D4 D3 D2 D1 D0 V0 V1 V2 V3 V4 V5 V6 V7 Read Register 7 D7 D6 D5 D4 D3 D2 D1 D0 BC8 BC9 BC10 BC11 BC12 BC13 FDA* FOY** *FIFO Data Available Status **FIFO Overflow Status 10216F-12 Interrupt Vector* 14-Bit MSB Byte Count 10 × 19 bit FIFO Status *Modified in B Channel Figure 8. Read Register Bit Functions Am85C30 19 AMD Read Register 10 D7 D6 D5 D4 D3 D2 D1 D0 0 On Loop 0 0 Loop Sending 0 Two Clocks Missing One Clock Missing Read Register 13 D7 D6 D5 D4 D3 D2 D1 D0 TC8 TC9 TC10 TC11 TC12 TC13 TC14 TC15 Upper Byte of Time Constant Read Register 12 D7 D6 D5 D4 D3 D2 D1 D0 TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 Read Register 15 D7 D6 D5 D4 D3 D2 D1 D0 SDLC/HDLC Enhancement Status* Zero Count IE 10 × 19 bit FIFO Enable/Disable* DCD IE SYNC Hunt IE CTS IE Tx Underrun/EOM IE Break/Abort IE 10216F-12 (concluded) Lower Byte of Time Constant *Added Enhancement Figure 8. Read Register Bit Functions (continued) Write Register 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Null Code Reset Rx CRC Checker Reset Tx CRC Generator Reset Tx Underrun/EOM Latch 0 0 1 1 0 1 0 1 10216F-13 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Null Code Point High Register Group Reset Ext/Status Interrupts Send Abort Enable Int on Next Rx Character Reset Tx Int Pending Error Reset Reset Highest IUS Figure 9. Write Register Bit Functions 20 Am85C30 AMD Write Register 4 D7 D6 D5 D4 D3 D2 D1 D0 Parity Enable Parity Even/Odd 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Write Register 1 D7 D6 D5 D4 D3 D2 D1 D0 Ext Int Enable Tx Int Enable Parity is Special Condition Rx Int Disable Rx Int on First Character or Special Condition Int on All Rx Characters or Special Condition Rx Int on Special Condition only Wait/DMA Request on Receive/Transmit Wait/DMA Request Function Wait/DMA Request Enable 0 0 1 1 0 1 0 1 Sync Modes Enable 1 Stop Bit/Character 1 1/2 Stop Bits/Character 2 Stop Bits/Character 8-Bit Sync Character 16-Bit Sync Character SDLC Mode (01111110 Flag) External Sync Mode Write Register 2 D7 D6 D5 D4 D3 D2 D1 D0 V0 V1 V2 V3 V4 V5 V6 V7 X1 Clock Mode X16 Clock Mode X32 Clock Mode X64 Clock Mode Interrupt Vector* Write Register 5 D7 D6 D5 D4 D3 D2 D1 D0 Tx CRC Enable RTS SDLC/CRC-16 Tx Enable Send Break 0 0 1 1 0 1 0 1 Write Register 3 D7 D6 D5 D4 D3 D2 D1 D0 Rx Enable Sync Character Load Inhibit Address Search Mode (SDLC) Rx CRC Enable Enter Hunt Mode Auto Enable 0 0 1 1 0 1 0 1 Tx 5 Bits (or less)/Character Tx 7 Bits/Character Tx 6 Bits/Character Tx 8 Bits/Character DTR Rx 5 Bits/Character Rx 7 Bits/Character Rx 6 Bits/Character Rx 8 Bits/Character Write Register 6 D7 D6 D5 D4 D3 D2 D1 D0 SYNC7 SYNC1 SYNC7 SYNC3 ADR7 ADR7 SYNC6 SYNC0 SYNC6 SYNC2 ADR6 ADR6 SYNC5 SYNC5 SYNC5 SYNC1 ADR5 ADR5 SYNC4 SYNC4 SYNC4 SYNC0 ADR4 ADR4 SYNC3 SYNC3 SYNC3 1 ADR3 1 SYNC2 SYNC2 SYNC2 1 ADR2 1 SYNC1 SYNC1 SYNC1 1 ADR1 1 SYNC0 SYNC0 SYNC0 1 ADR0 1 Monosync 8 Bits Monosync 8 Bits Bisync 16 Bits Bisync 12 Bits SDLC SDLC (Address 0) 10216F-13 Figure 9. Write Register Bit Functions (continued) Am85C30 21 AMD Write Register 7 D7 D6 D5 D4 D3 D2 D1 D0 SYNC7 SYNC5 SYNC5 SYNC11 0 SYNC6 SYNC4 SYNC14 SYNC10 1 SYNC5 SYNC3 SYNC13 SYNC9 1 SYNC4 SYNC2 SYNC12 SYNC8 1 SYNC3 SYNC1 SYNC11 SYNC7 1 SYNC2 SYNC1 SYNC0 1 SYNC10 SYNC9 SYNC6 SYNC5 1 1 SYNC0 1 SYNC8 SYNC4 0 Monosync 8 Bits Monosync 8 Bits Bisync 16 Bits Bisync 12 Bits SDLC Write Register 7 ′ D7 D6 D5 D4 D3 D2 D1 D0 Auto Tx Flag Auto EOM Latch Reset Auto RTS TxD Pulled High in SDLC NRZI Mode Fast DTR/REQ Mode CRC Check Bytes Completely Received Extended Read Enable Must Be Set to 0 Write Register 9 D7 D6 D5 D4 D3 D2 D1 D0 VIS NV DLC MIE Status High/Status Low Interrupt Masking without INTACK* Write Register 11 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 1 0 1 TRxC Out TRxC Out TRxC Out TRxC Out TRxC O/I = = = = XTAL Output Transmit Clock BR Generator Output DPLL Output 0 0 1 1 0 1 0 1 No Reset Channel Reset B Channel Reset A Force Hardware Reset 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 *Added Enhancement Transmit Clock Transmit Clock Transmit Clock Transmit Clock = = = = = = = = RTxC Pin TRxC Pin BR Generator Output DPLL Output Receive Clock Receive Clock Receive Clock Receive Clock RTxC Pin TRxC Pin BR Generator Output DPLL Output RTxC XTAL/No XTAL 10216F-13 Figure 9. Write Register Bit Functions (continued) 22 Am85C30 AMD Write Register 10 D7 D6 D5 D4 D3 D2 D1 D0 6-Bit/8-Bit Sync Loop Mode Abort/Flag on Underrun Mark/Flag Idle Go Active on Roll 0 0 1 1 0 1 0 1 Write Register 12 D7 D6 D5 D4 D3 D2 D1 D0 TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 Lower Byte of Time Constant NRZ NRZI FM1 (Transition = 1) FM0 (Transition = 0) CRC Preset ‘1’ or ‘0’ Write Register 13 D7 D6 D5 D4 D3 D2 D1 D0 TC8 TC9 TC10 TC11 TC12 TC13 TC14 TC15 Upper Byte of Time Constant Write Register 14 D7 D6 D5 D4 D3 D2 D1 D0 BR Generator Enable BR Generator Source DTR/Request Function Auto Echo Local Loopback 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Write Register 15 D7 D6 D5 D4 D3 D2 D1 D0 SDLC/HDLC Enhancements Enable* Zero Count IE 10 × 19 Bit FIFO Enable* DCD IE Sync/Hunt IE CTS IE Tx Underrun/EOM IE Break/Abort IE * Added Enhancement 10216F-13 (concluded) Null Command Enter Search Mode Reset Missing Clock Disable DPLL Set Source = BR Generator Set Source = RTxC Set FM Mode Set NRZI Mode Figure 9. Write Register Bit Functions (continued) Am85C30 Timing The ESCC generates internal control signals from WR and RD that are related to PCLK. Since PCLK has no phase relationship with WR and RD, the circuitry generating these internal control signals must provide time for metastable conditions to disappear. This gives rise to a recovery time related to PCLK. The recovery time applies only between bus transactions involving the ESCC. The recovery time required for proper operation is specified from the falling edge of WR or RD in the first transaction involving the ESCC, to the falling edge of WR or RD in the second transaction involving the ESCC. This time must be at least 3 1/2 PCLK regardless of which register or channel is being accessed. Read Cycle Timing Figure 10 illustrates Read cycle timing. Addresses on A/B and D/C and the status on INTACK must remain stable throughout the cycle. If CE falls after RD falls or if it rises before RD rises, the effective RD is shortened. Write Cycle Timing Figure 11 illustrates Write cycle timing. Addresses on A/B and D/C and the status on INTACK must remain stable throughout the cycle. If CE falls after WR falls or if it rises before WR rises, the effective WR is shortened. Data must be valid before the rising edge of WR. Am85C30 23 AMD Interrupt Acknowledge Cycle Timing NO TAG illustrates Interrupt Acknowledge cycle timing. Between the time INTACK goes Low and the falling edge of RD, the internal and external IEI/IEO daisy chains settle. If there is an interrupt pending in the ESCC and IEI is High when RD falls, the Acknowledge cycle is intended for the SCC. In this case, the ESCC may be programmed to respond to RD Low by placing its interrupt vector on D7–D0 ; it then sets the appropriate Interrupt-Under-Service latch internally. A/B, D/C INTACK CE WR D7 –D0 Address Valid Data Valid 10216F-14 Figure 10. Read Cycle Timing A/B, D/C INTACK CE WR D7 –D0 Address Valid Data Valid Figure 11. Write Cycle Timing 10216F-15 INTACK RD D7 –D0 Vector 10216F-16 Figure 12. Interrupt Acknowledge Cycle Timing 24 Am85C30 AMD FIFO FIFO Enhancements When used with a DMA controller, the Am85C30 Frame Status FIFO enhancement maximizes the ESCC’s ability to receive high-speed back-to-back SDLC messages while minimizing frame overruns due to CPU latencies in responding to interrupts. Additional logic was added to the industry-standard NMOS SCC consisting of a 10-deep by 19-bit status FIFO, a 14-bit receive byte counter, and control logic as shown in Figure 13. The 10 × 19 bit status FIFO is separate from the existing 3-byte receive data and error FIFOs. When the enhancement is enabled, the status in Read Register 1 (RR1) and byte count for the SDLC frame will be stored in the 10 × 19 bit status FIFO. This allows the DMA controller to transfer the next frame into memory while the CPU verifies that the message was properly received. Summarizing the operation, data is received, assembled, and loaded into the 3-byte receive FIFO before being transferred to memory by the DMA controller. When a flag is received at the end of an SDLC frame, the frame byte count from the 14-bit counter and 5 status bits are loaded into the status FIFO for verification by the CPU. The CRC checker is automatically reset in preparation for the next frame, which can begin immediately. Since the byte count and status are saved for each frame, the message integrity can be verified at a later time. Status information for up to 10 frames can be stored before a status FIFO overrun could occur. If receive interrupts are enabled while the 10 × 19 FIFO is enabled, an SDLC end-of-frame special condition will SCC Status Reg (Existing) RR1 6 Bits 14-Bit Byte Counter 14 Bits Reset on Flag Detect Increment on Byte DET Enable Count in SDLC End-of-Frame Signal Status Read Comp Residue Bits(3) Overrun CRC Error 10 × 19 Bit FIFO Array Tail Pointer 4-Bit Counter Head Pointer 4-Bit Counter 4-Bit Comparator Over Equal 5 Bits EOF = 1 2 Bits 6-Bit MUX 6 Bits RR1 Interface to SCC 6 Bits Bit 7 Bit 6 Bits 0–5 RR7 EN 8 Bits FIFO Enable RR6 WR(15) Bit 2 Set Enables Status FIFO Byte Counter Contains 14 Bits for a 16-kb Maximum Count FIFO Data Available Status Bit Status Bit Set to 1 When Reading From FIFO FIFO Overflow Status Bit MSB of RR(7) is Set on Status FIFO Overflow In SDLC mode, the following definitions apply: • All Sent bypasses MUX and equals contents of SCC Status Register. • Parity bits bypass MUX and do the same. • EOF is set to 1 whenever reading from the FIFO. 10216F-17 Figure 13. SCC Status Register Modifications Am85C30 25 AMD not lock the 3-byte receive data FIFO. An SDLC end-of-frame still locks the 3-byte receive data FIFO in “Interrupt on first Receive Character or Special Condition” and “Interrupt on Special Condition Only” modes when the 10 × 19 FIFO is disabled. This feature allows the 10 × 19 SDLC FIFO to accept multiple SDLC frames without CPU intervention at the end of each frame. from the status register, and reads from RR7 and RR6 will contain bits that are undefined. Bit 6 of RR7 (FIFO Data Available) can be used to determine if status data is coming from the FIFO or directly from the status register, since it is set to 1 whenever the FIFO is not empty. Because not all status bits are stored in the FIFO, the All Sent, Parity, and EOF bits will bypass the FIFO. The status bits sent through the FIFO will be Residue Bits (3), Overrun, and CRC Error. The sequence for proper operation of the byte count and FIFO logic is to read the registers in the following order, RR7, RR6, and RR1 (reading RR6 is optional). Additional logic prevents the FIFO from being emptied by multiple reads from RR1. The read from RR7 latches the FIFO empty/full status bit (bit 6) and steers the status multiplexer to read from the SCC megacell instead of the status FIFO (since the status FIFO is empty). The read from RR1 allows an entry to be read from the FIFO (if the FIFO was empty, logic is added to prevent a FIFO underflow condition). FIFO Detail For a better understanding of details of the FIFO operation, refer to the block diagram contained in Figure 13. Enable/Disable This FIFO is implemented so that it is enabled when WR15 bit 2 is set and the ESCC is in the SDLC/HDLC mode, otherwise the status register contents bypass the FIFO and go directly to the bus interface (the FIFO pointer logic is reset either when disabled or via a channel or power-on reset). When the FIFO mode is disabled, the ESCC is completely downward-compatible with the NMOS Am8530. The FIFO mode is disabled on power-up (WR15 bit 2 is set to 0 on reset). The effects of backward compatibility on the register set are that RR4 is an image of RR0, RR5 is an image of RR1, RR6 is an image of RR2, and RR7 is an image of RR3. For the details of the added registers, refer to Figure 15. The status of the FIFO Enable signal can be obtained by reading RR15 bit 2. If the FIFO is enabled, the bit will be set to 1; otherwise, it will be reset. Write Operation When the end of an SDLC frame (EOF) has been received and the FIFO is enabled, the contents of the status and byte-count registers are loaded into the FIFO. The EOF signal is used to increment the FIFO. If the FIFO overflows, the MSB of RR7 (FIFO Overflow) is set to indicate the overflow. This bit and the FIFO control logic are reset by disabling and reenabling the FIFO control bit (WR15 bit 2). For details of FIFO control timing during an SDLC frame, refer to Figure 14. Read Operation When WR15 bit 2 is set and the FIFO is not empty, the next read to status register RR1 or the additional registers RR7 and RR6 will actually be from the FIFO. Reading status register RR1 causes one location of the FIFO to be emptied, so status should be read after reading the byte count, otherwise the count will be incorrect. Before the FIFO underflows, it is disabled. In this case, the multiplexer is switched to allow status to be read directly Byte Count Data Stream Byte Counter Detail The 14-bit byte counter allows for packets up to 16K bytes to be received. For a better understanding of its operation, refer to Figures 13 and 14. 0 F 1 2 3 4 5 6 7 0 F 1 2 3 4 5 6 7 ADDDDCCF ADDDDCCF Key F : Flag A : Address Field D : Data C : Control Field Internal Byte Strobe Increments Counter Don’t Load Reset Counter On Byte Counter 1st Flag Load Counter Reset Byte Into FIFO and Counter Here Increment PTR Internal Byte Strobe Increments Counter Reset Byte Counter Reset Byte Counter Load Counter Into FIFO and Increment PTR 10216F-18 Figure 14. SDLC Byte Counting Detail 26 Am85C30 AMD 7 RR7 6 5 BC 13 4 BC 12 3 BC 11 2 BC 10 1 BC 9 0 BC 8 FOY FDA FIFO Data Available Status 1 = Status Reads Will Come From FIFO 0 = Status Reads Will Come From SCC FIFO Overflow Status 1 = FIFO Overflowed During Operation 0 = Normal 7 RR6 BC 7 7 RR15 • 6 BC 6 6 • 5 BC 5 5 • 4 BC 4 4 • 3 BC 3 3 • 2 BC 2 2 FEN 1 BC 1 1 • 0 BC 0 0 ENH ENH: SDLC/HDLC Enhancement Status 1 = Enhancements Enabled 0 = Enhancements Disabled Read From FIFO LSB Byte Count Status FIFO Enable Control Bit 1 = Status and Byte Count Will be Held in the Status FIFO Until Read 0 = Status Will Not be Held (SCC Emulation Mode) • = No Change From NMOS SCC DFN 10216F-19 Figure 15. SCC Additional Registers Enable The byte counter is enabled when the SCC is in the SDLC/HDLC mode and WR15 bit 2 is set to 1. WR7′. Table 3 shows what functions on the Am85C30 are enabled when these bits are set. When bit D2 of WR15 is set to 1, two additional registers (RR6 and RR7) per channel specific to the 10 × 19 bit Frame Status FIFO are made available. The Am85C30 register map when this function is enabled is shown in Table 4. Bit D0 of WR15 determines whether or not other enhancements pertinent only to SDLC/HDLC mode operation are available for programming via WR7′ as shown below. Write Register 7 prime (WR7′) can be written to when bit D0 of WR15 is set to 1. When this bit is set, writing to WR7 (flag register) actually writes to WR7′. If bit D6 of this register is set to 1, previously unreadable registers WR3, WR4, WR5, and WR10 are readable by the pro-cessor. In addition, WR7′ is also readable by having this bit set. WR3 is read when a bogus RR9 register is accessed during a read cycle. WR10 is read by accessing RR11, and WR7′ is accessed by executing a read to RR14. The Am85C30 register map with bit D0 of WR15 and bit D6 of WR7′ set is shown in Table 5. If both bits D0 and D2 of WR15 are set to 1 and D6 of WR7′ is set to 1, then the Am85C30 register map is as shown in Table 6. Reset The byte counter is reset whenever an SDLC flag character is received. The reset is timed so that the contents of the byte counter are successfully written into the FIFO. Increment The byte counter is incremented by writes to the data FIFO. The counter represents the number of bytes received by the SCC, rather than the number of bytes transferred from the SCC. (These counts may differ by up to the number of bytes in the receive data FIFO contained in the SCC.) Am85C30 SDLC/HDLC Enhancement Register Access SDLC/HDLC enhancements on the Am85C30 are enabled or disabled via bits D2 or D0 in WR15. Bit D2 determines whether or not the 10 × 19 bit SDLC/HDLC frame status FIFO is enabled while bit D0 determines whether or not other enhancements are enabled via Am85C30 27 AMD Table 3. Enhancement Options WR15 Bit D2 10 × 19 Bit FIFO Enabled 1 0 WR15 Bit D0 SDLC/HDLC Enhancement Enabled 0 1 WR7′ Bit D6 Extended Read Enabled x 0 Functions Enabled 10 × 19 bit FIFO enhancement enabled only SDLC/HDLC enhancements enabled only SDLC/HDLC enhancements enabled with extended read enabled 10 × 19 bit FIFO and SDLC/HDLC enhancements enabled 10 × 19 bit FIFO and SDLC/HDLC enhancements with extended read enabled 0 1 1 1 1 0 1 1 1 Table 4. 10 × 19 Bit FIFO Enabled A/ B 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PNT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PNT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PNT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Write WR0B WR1B WR2 WR3B WR4B WR5B WR6B WR7B WR0A WR1A WR2 WR3A WR4A WR5A WR6A WR7A Read RR0B RR1B RR2B RR3B (RR0B) (RR1B) RR6B RR7B RR0A RR1A RR2A RR3A (RR0A) (RR1A) RR6A RR7A With the Point High command: A/ B 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PNT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PNT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PNT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Write WR8B WR9 WR10B WR11B WR12B WR13B WR14B WR15B WR8A WR9 WR10A WR11A WR12A WR13A WR14A WR15A Read RR8B RR13B RR10B (RR15B) RR12B RR13B (RR10B) RR15B RR8A (RR13A) RR10A (RR15A) RR12A RR13A (RR10A) RR15A 28 Am85C30 AMD D7 D6 D5 D4 DTR/REQ Fast Mode D3 D2 SDLC/HDLC Auto RTS Turnoff D1 SDLC/HDLC Auto EOM Reset D0 SDLC/HDLC Auto Tx Flag Must Be Set to 0 Ext. Read Enable Rx comp. CRC Force TxD High *Note: Options 3, 4, 5, and 6 may be used regardless of whether SDLC/HDLC mode is selected. WR7′—SDLC/HDLC Programmable Enhancements* Table 5. SDLC/HDLC Enhancements Enabled A/ B 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PNT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PNT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PNT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Write WR0B WR1B WR2 WR3B WR4B WR5B WR6B WR7B WR0A WR1A WR2 WR3A WR4A WR5A WR6A WR7A Read RR0B RR1B RR2B RR3B RR4B (WR4B) RR5B (WR5B) (RR2B) (RR3B) RR0A RR1A RR2A RR3A RR4A (WR4A) RR5A (WR5A) (RR2A) (RR3A) With the Point High command: A/ B 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PNT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PNT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PNT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Write WR8B WR9 WR10B WR11B WR12B WR13B WR14B WR15B WR8A WR9 WR10A WR11A WR12A WR13A WR14A WR15A Read RR8B RR9 (WR3B) RR10B RR11B (WR10B) RR12B RR13B RR14B (WR7′B) RR15B RR8A RR9A (WR3A) RR10A RR11A (WR10A) RR12A RR13A RR14A (WR7A) RR15A Am85C30 29 AMD Table 6. SDLC/HDLC Enhancements and 10 × 19 Bit FIFO Enabled A/ B 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PNT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PNT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PNT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Write WR0B WR1B WR2 WR3B WR4B WR5B WR6B WR7B WR0A WR1A WR2 WR3A WR4A WR5A WR6A WR7A Read RR0B RR1B RR2B RR3B RR4B RR5B RR6B RR7B RR0A RR1A RR2A RR3A RR4A RR5A RR6A RR7A (WR4B) (WR5B) (WR4A) (WR5A) With the Point High command: A/ B 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PNT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PNT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PNT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Write WR8B WR9 WR10B WR11B WR12B WR13B WR14B WR15B WR8A WR9 WR10A WR11A WR12A WR13A WR14A WR15A Read RR8B RR9 (WR3B) RR10B RR11B (WR10B) RR12B RR13B RR14B (WR7′B) RR15B RR8A RR9A (WR3A) RR10A RR11A (WR10A) RR12A RR13A RR14A (WR7′A) RR15A 30 Am85C30 AMD Auto RTS Reset On the CMOS ESCC, if bit D0 of WR15 and bit D2 of WR7′ are set to 1 and the channel is in SDLC mode, the RTS pin may be reset early in the Tx Underrun routine and the RTS pin will remain active until the last 0 bit of the closing flag leaves the TxD pin as shown in Figure 16. Note that in order for this to function properly, bits D3 and D2 of WR10 must be set to 1 and 0, respectively. Register, the last 2 bits of the CRC check character received are never transferred to the Receive Data FIFO. Thus, the received CRC characters are unavailable for use. CMOS Am85C30 On the Am85C30, the option of being able to receive the complete CRC characters generated by the transmitter is provided when both bit D0 of WR15 and bit D5 of WR7′ are set to 1. When these 2 bits are set and an end-offrame flag is detected, the last 2 bits of the CRC will be clocked into the Receive Shift Register before its contents are transferred to the Receive Data FIFO. The data-CRC boundary and CRC character bit formats for each Residue Code provided are shown in Figures 17A through 17D for each character length selected. CRC Character Reception NMOS Am8530H On the NMOS Am8530H, when the end-of-frame flag is detected, the contents of the Receive Shift Register are transferred to the Receive Data FIFO regardless of the number of bits accumulated. Because of the 3-bit delay between the Receive SYNC Register and Receive Shift Data Being Sent Data CRC CRC Flag Tx Underrun/EOM RTS Bit D1 WR5 RTS Pin (Active Low) 10216F-20 Figure 16. Auto RTS Reset Mode Am85C30 31 AMD Residue Code 012 001 D C0 C5 C8 D C1 C6 C9 D C2 C7 C10 D C3 C8 C11 D C4 C9 C12 C0 C5 C10 C13 C1 C6 C11 C14 C2 C7 C12 C15 D D C4 C8 D C0 C5 C9 Residue Code 012 101 D C1 C6 C10 D C2 C7 C11 D C3 C8 C12 D C4 C9 C13 C0 C5 C10 C14 C1 C6 C11 C15 Residue Code 012 100 D D C3 C8 D D C4 C9 D C0 C5 C10 D C1 C6 C11 D C2 C7 C12 D C3 C8 C13 D C4 C9 C14 C0 C5 C10 C15 D D C2 C7 C8 D D C3 C8 C9 Residue Code 012 010 D D C4 C9 C10 D C0 C5 C10 C11 D C1 C6 C11 C12 D C2 C7 C12 C13 D C3 C8 C13 C14 D C4 C9 C14 C15 Residue Code 012 110 D D C1 C6 C8 D D C2 C7 C9 D D C3 C8 C10 D D C4 C9 C11 D C0 C5 C10 C12 D C1 C6 C11 C13 D C2 C7 C12 C14 D C3 C8 C13 C15 10216F-21 Figure 17A. 5 Bits/Character 32 Am85C30 AMD Residue Code 012 010 D C0 C6 C8 D C1 C7 C9 D C2 C8 C10 D C3 C9 C11 D C4 C10 C12 D C5 C11 C13 C0 C6 C12 C14 C1 C7 C13 C15 D D C5 C8 D C0 C6 C9 Residue Code 012 110 D C1 C7 C10 D C2 C8 C11 D C3 C9 C12 D C4 C10 C13 D C5 C11 C14 C0 C6 C12 C15 Residue Code 012 001 D D C4 C8 D D C5 C9 D C0 C6 C10 D C1 C7 C11 D C2 C8 C12 D C3 C9 C13 D C4 C10 C14 D C5 C11 C15 D D C3 C8 D D C4 C9 Residue Code 012 101 D D C5 C10 D C0 C6 C11 D C1 C7 C12 D C2 C8 C13 D C3 C9 C14 D C4 C10 C15 Residue Code 012 011 D D C2 C8 D D C3 C9 D D C4 C10 D D C5 C11 D C0 C6 C12 D C1 C7 C13 D C2 C8 C14 D C3 C9 C15 D D C1 C7 C8 D D C2 C8 C9 Residue Code 012 100 D D C3 C9 C10 D D C4 C10 C11 D D C5 C11 C12 D C0 C6 C12 C13 D C1 C7 C13 C14 D C2 C8 C14 C15 10216F-21 Figure 17B. 6 Bits/Character Am85C30 33 AMD Residue Code 012 111 D C0 C7 C8 D C1 C8 C9 D C2 C9 C10 D C3 C10 C11 D C4 C11 C12 D C5 C12 C13 D C6 C13 C14 C0 C7 C14 C15 D D C6 C8 D C0 C7 C9 Residue Code 012 100 D C1 C8 C10 D C2 C9 C11 D C3 C10 C12 D C4 C11 C13 D C5 C12 C14 D C6 C13 C15 Residue Code 012 010 D D C5 C8 D D C6 C9 D C0 C7 C10 D C1 C8 C11 D C2 C9 C12 D C3 C10 C13 D C4 C11 C14 D C5 C12 C15 D D C4 C8 D D C5 C9 Residue Code 012 110 D D C6 C10 D C0 C7 C11 D C1 C8 C12 D C2 C9 C13 D C3 C10 C14 D C4 C11 C15 Residue Code 012 001 D D C3 C8 D D C4 C9 D D C5 C10 D D C6 C11 D C0 C7 C12 D C1 C8 C13 D C2 C9 C14 D C3 C10 C15 D D C2 C8 D D C3 C9 Residue Code 012 101 D D C4 C10 D D C5 C11 D D C6 C12 D C0 C7 C13 D C1 C8 C14 D C2 C9 C15 Residue Code 012 011 D D C1 C8 D D C2 C9 D D C3 C10 D D C4 C11 D D C5 C12 D D C6 C13 D C0 C7 C14 D C1 C8 C15 10216F-21 Figure 17C. 7 Bits/Character 34 Am85C30 AMD Residue Code 012 011 (No Residue) DDDDDDDD C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 D D C7 C8 D C0 C8 C9 Residue Code 012 111 (1 Residue Bit) D C1 C9 C10 D C2 C10 C11 D C3 C11 C12 D C4 C12 C13 D C5 C13 C14 D C6 C14 C15 Residue Code 012 000 (2 Residue Bits) D D C6 C8 D D C7 C9 D C0 C8 C10 D C1 C9 C11 D C2 C10 C12 D C3 C11 C13 D C4 C12 C14 D C5 C13 C15 D D C5 C8 D D C6 C9 Residue Code 012 100 (3 Residue Bits) D D C7 C10 D C0 C8 C11 D C1 C9 C12 D C2 C10 C13 D C3 C11 C14 D C4 C12 C15 Residue Code 012 010 (4 Residue Bits) D D C4 C8 D D C5 C9 D D C6 C10 D D C7 C11 D C0 C8 C12 D C1 C9 C13 D C2 C10 C14 D C3 C11 C15 D D C3 C8 D D C4 C9 Residue Code 012 110 (5 Residue Bits) D D C5 C10 D D C6 C11 D D C7 C12 D C0 C8 C13 D C1 C9 C14 D C2 C10 C15 Residue Code 012 001 (6 Residue Bits) D D C2 C8 D D C3 C9 D D C4 C10 D D C5 C11 D D C6 C12 D D C7 C13 D C0 C8 C14 D C1 C9 C15 D D C1 C8 D D C2 C9 Residue Code 012 101 (7 Residue Bits) D D C3 C10 D D C4 C11 D D C5 C12 D D C6 C13 D D C7 C14 D C0 C8 C15 10216F-21 (concluded) Figure 17D. 8 Bits/Character Am85C30 35 AMD Auto Flag Mode On the NMOS Am8530H, if the transmitter is actively mark idling and a frame of data is ready to be transmitted, the Mark/Flag Idle bit must be set to 0 before data is written to WR8, otherwise the opening flag will not be sent properly. However, care must be exercised in doing this because the mark idle pattern (eight 1 bits) is transmitted 8 bits at a time, and all 8 bits must have transferred out of the Transmit Shift Register before a flag may be loaded and sent. If data is written into the Transmit Buffer (WR8) before the flag is loaded into the Transmit Shift Register, the data character written to WR8 will supersede flag transmission and the opening flag will not be transmitted. On the CMOS Am85C30, if bit D0 of WR15 is set to 1 and the ESCC is programmed for SDLC operation, an option is provided via bit D0 of WR7′ that eliminates this requirement. If bit D0 of WR7′ is set to 1 and a character is written to the Transmit Buffer while the transmitter is mark idling, the Mark/Flag Idle bit in WR10 need not be reset to 0 in order to have the opening flag sent because the transmitter will automatically send it before commencing to send data. In addition, as long as bit D0 of WR15 and bit D1 of WR7′ are set to 1, the CRC transmit generator will be automatically preset to the initial state programmed by bit D7 of WR10 (so the Reset Tx CRC Generator command is also not necessary), and the Tx Underrun/EOM latch will be reset automatically on every new frame sent. This ensures that an opening flag and proper CRC generation and transmission will always be sent without processor intervention under varying bus latency conditions. WR5 (D0) and the Tx Underrun/EOM bit in RR0 (D6). However, if the Transmit Enable bit is set to 0 when a transmit underrun (i.e., both the Transmit Buffer and Transmit Shift Register become empty) occurs, the CRC check characters will not be sent regardless of the state of the Tx Underrun/EOM bit. If the Transmit Enable bit is set to 1 when an underrun occurs, then the state of the Tx Underrun/EOM bit and the Abort/Flag on Underrun bit in WR10 (D2) determine the action taken by the transmitter. The Abort/Flag on Underrun bit may be set or reset by the processor, whereas the Tx Underrun/EOM bit is set by the transmitter and can only be reset by the processor via the Reset Tx Underrun/EOM Command in WR0. If the Tx Underrun/EOM bit is set to 1 when an underrun occurs, the transmitter will close the frame by sending a flag; however, if this bit is set to 0, the frame data will be appended with either the accumulated CRC characters followed by a flag or an abort pattern followed by a flag, depending on the state of the Abort/Flag on Underrun bit in the WR10 (D2). In either case, after the closing flag is sent, the transmitter will idle the transmission line as specified by the Mark/Flag Idle bit D3 in WR10. Hence, if the CRC check characters are to be properly appended to a frame, the Abort/Flag on Underrun bit must be set to 0, and the Reset Tx Underrun/EOM Command must be issued after the first but before the last character is written to the Transmit Buffer. This will ensure that either an abort or the CRC will be transmitted if an underrun occurs. Normally, the Abort/Flag on Underrun bit in WR10 should be set to 1 around the same time that the Tx Underrun/EOM bit is reset so that an abort will be sent if the transmitter accidentally underruns, and then set to 0 near the end of the frame to allow the correct transmission of CRC. On the Am85C30, if bit D0 of WR15 is set to 1, the option of having the Tx Underrun/EOM bit reset automatically at the start of every frame is provided via bit D1 of WR7′. This helps alleviate the software burden of having to respond within one character time when high-speed data are being sent. Auto Transmit CRC Generator Preset The NMOS Am8530H does not automatically preset the CRC generator prior to frame transmission. This must be done in software, usually during the initialization routine. This is accomplished by issuing the Reset Tx CRC Generator Command via WR0. For proper results, this command must be issued while the transmitter is enabled and idling and before any data are written to the Transmit Buffer. In addition, if CRC is to be used, the transmit CRC generator must be enabled by setting bit D0 of WR5 to 1. CRC is normally calculated on all characters between opening and closing flags, so this bit should be set to 1 at initialization and never changed. On the CMOS Am85C30, setting bit D0 of WR15 to 1 will cause the transmit CRC generator to be preset automatically every time an opening flag is sent, so the Reset Tx CRC Generator Command is not necessary. SDLC/HDLC NRZI Transmitter Disabling On the NMOS Am8530H, if NRZI encoding is being used and the transmitter is disabled, the state of the TxD pin will depend on the last bit sent. That is, the TxD pin may either idle in a Low or High state as shown in Figure 18. On the CMOS Am85C30, an option is provided that allows setting the TxD pin High when operating in SDLC mode with NRZI encoding enabled. If bit D0 of WR15 is set to 1, then bit D3 of WR7′ can be used to set the TxD pin High. Note that the operation of this bit is independent of the Tx Enable bit in WR5. The Tx Enable bit in WR5 is used to disable and enable the transmitter, Auto Tx Underrun/EOM Latch Reset On the ESCC, the transmission of the CRC check characters is controlled by the Transmit CRC Enable bit in 36 Am85C30 AMD 1 1 0 0 1 1 1 1 1 1 0 0 Transmitter Disabled Here TxD Pin Output (NRZI Encoded) Hi Lo 10216F-22 Figure 18. Transmitter Disabling with NRZI Encoding whereas bit D3 of WR7′ acts as a pseudo transmitter disable and enable by just forcing the TxD pin High when set even though the transmitter may actually be mark or flag idling. Care must be used when setting this bit because any character being transmitted at the time this bit is set will be “chopped off,” and data written to the Transmit Buffer while this bit is set will be lost. When the transmit underrun occurs and the CRC and closing flag have been sent, bit D3 can be set to pull TxD High. When ready to start sending data again this bit must be reset to 0 before the first character is written to the Transmit Buffer. Note that resetting this bit causes the TxD pin to take whatever state the NRZI encoder is in at the time, so synchronization at the receiver may take longer because the first transition seen on the TxD pin may not coincide with a bit boundary. Note that in order for this to function properly, bits D3 and D2 of WR10 must be set to 1 and 0, respectively. interrupt occurs, a read to RR2 emulates a hardware Interrupt Acknowledge cycle as it functions in Vectored mode. In this case the CPU must first read RR2 to determine the internal interrupt source and then jump to the appropriate interrupt routine. Reading RR2 sets the IUS bit for the highest priority IP. After the interrupting condition is cleared, the routine can then read RR3 to determine if any other IPs are set and clear them. At the end of the interrupt routine, a Reset IUS command must be issued to unlock the internal daisy chain. Since the CPU can acknowledge the ESCC of highest priority with a read of its RR2 interrupt vector, there is no need for an external daisy chain. IEI for all ESCC devices should be tied active High. When acknowledging an ESCC interrupt request, the CPU must issue one read to RR2 per interrupt request. The modified interrupt vector can be read from Channel B, or the original vector stored in WR2 can be read from Channel A. Either action will produce the same internal actions on the IUS logic. Note that the No Vector and Vector Includes Status bits in WR9 are ignored when bit D5 in WR9 is set to 1. Interrupt Masking Without INTACK The NMOS Am8530H’s ability to mask lower priority interrupts is done via the IUS bit. This bit is internal to the SCC and is not observable by the processor. Being able to automatically mask lower priority interrupts allows a modular approach to coding interrupt routines. However, using the masking capabilities of the NMOS SCC requires that the INTACK cycle be generated. In standalone applications, having to generate INTACK through external hardware in order to use this capability is an unnecessary expense. On the CMOS Am85C30, if bit D5 in WR9 is set to 1, the INTACK cycle does not need to be generated in order to have the IUS bit set. This allows the user to respond to ESCC interrupt requests with a software acknowledgment through RR2. When bit D5 in WR9 is set and an 2-Mb/s FM Data Transmission and Reception The 16-MHz version of the CMOS Am85C30 (Am85C30-16) is capable of transmitting and receiving FM-encoded data at the rate of 2 Mb/s. This is accomplished by applying a 32-MHz clock to the RTxC pin and assigning this waveform to drive the Internal Digital Phase-Locked Loop (DPLL) clock. This feature allows the user to send both clock and data information over the same line at 2 Mb/s and can eliminate external DPLLs required for high-speed NRZ data clock generation. Am85C30 37 AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . –65°C to +150°C Voltage at any Pin Relative to VSS . . . . . . . . . . . . . . . . . –0.5 to +7.0 V Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) . . . . . . . 0°C to +70°C Supply Voltage (VCC) . . . . . . . . . . . . . +5 V ± 10% Industrial (I) Devices Ambient Temperature (TA) . . . . . –40°C to +85°C Supply Voltage (VCC) . . . . . . . . . . . . . . 5 V ±10% Military (M) Devices Case Temperature (TC) . . . . . . . –55°C to 125°C Supply Voltage (VCC) . . . . . . . . . . . . . . 5 V ±10% Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating range Parameter Symbol VIH VIL VOH1 VOH2 VOL IIL IOL ICC1 Parameter Description Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Input Leakage Output Leakage VCC Supply Current IOH = –1.6 mA IOH = –250 µA IOL = +2.0 mA 0.4 V ≤ VIN ≤ 2.4 V 0.4 V ≤ VOUT ≤ 2.4 V 8.192 MHz 10 MHz 12 MHz 16.384 MHz Inputs at voltage rails, output unloaded Test Conditions Commercial Min 2.2 –0.3* 2.4 VCC –0.8 0.4 ±10.0 ±10.0 18 18 22 22 10 Unmeasured pins returned to ground = 1 MHz over specified temperature range 15 20 Max VCC +0.3* 0.8 Unit V V V V V µA µA mA mA mA mA pF pF pF CIN COUT CMO Input Capacitance Output Capacitance Bidirectional Capacitance *VIH Max and VIL Min not tested. Guaranteed by design. Standard Test Conditions The characteristics below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND. Positive current flows into the referenced pin. Standard conditions are as follows: +4.5 V ≤ VCC ≤ +5.5 V GND = 0 V 0°C ≤ TA ≤ 70°C SWITCHING TEST CIRCUITS Standard Test Dynamic Load Circuit IO L = 2 mA Threshold Voltage VT = 1.4 V 2.2 K From Output Under Test 75 pF IOH = 250 µA 10216F-23 10216F-24 Open-Drain Test Load +5 V From Output Under Test 75 pF 38 Am85C30 AMD SWITCHING CHARACTERISTICS over COMMERCIAL operating range General Timing (see Figure 19) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14a 14b 15a 15b 16a 16b 17 18 19 20 21 22 Parameter Symbol TdPC(REQ) TdPC(W) TsRXC(PC) TsRXD(RXCr) ThRXD(RXCr) TsRXD(RXCf) ThRXD(RXCf) TsSY(RXC) ThSY(RXC) TsTXC(PC) TdTXCf(TXD) TdTXCr(TXD) TdTXD(TRX) TwRTXh TwRTxh(E) TwRTXI TwRTXl(E) TcRTX TcRTx(E) TcRTXX TwTRXh TwTRXI TcTRX TwEXT TwSY Parameter Description PCLK ↓ to W/REQ Valid Delay PCLK ↓ to Wait Inactive Delay RxC ↑ to PCLK ↑ Setup Time (Notes 1, 4 & 8) RxD to RxC ↑ Setup Time (Xl Mode) (Note 1) RxD to RxC ↑ Hold Time (Xl Mode) (Note 1) RxD to RxC ↓ Setup Time (Xl Mode) (Notes 1, 5) RxD to RxC ↓ Hold Time (Xl Mode) (Notes 1, 5) SYNC to RxC ↑ Setup Time (Note 1) SYNC to RxC ↑ Hold Time (Note 1) TxC ↓ to PCLK ↑ Setup Time (Notes 2, 4 & 8) TxC ↓ to TxD Delay (Xl Mode) (Note 2) TxC ↑ to TxD Delay (Xl Mode) (Notes 2, 5) TxD to TRxC Delay (Send Clock Echo) RTxC High Width (Note 6) RTxC High Width (Note 9) RTxC Low Width (Note 6) RTxC Low Width (Note 9) RTxC Cycle Time (Notes 6, 7) RTxC Cycle Time (Note 9) Crystal Oscillator Period (Note 3) TRxC High Width (Note 6) TRxC Low Width (Note 6) TRxC Cycle Time (Notes 6, 7) DCD or CTS Pulse Width SYNC Pulse Width 150 50 150 50 488 125 125 150 150 488 200 200 1000 NA 0 150 0 150 –200 5TcPC NA 200 200 200 120 40 120 40 400 100 100 120 120 400 120 120 1000 8.192 MHz Min Max 250 350 NA NA 0 125 0 125 –150 5TcPC NA 150 150 140 80 15.6 80 15.6 244 31.25 62 80 80 244 70 70 1000 10 MHz Min Max 150 250 NA NA 0 50 0 50 –100 5TcPc NA 80 80 80 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 16.384 MHz Min Max 80 180 NA ns ns ns ns ns ns Unit ns ns Notes: 1. RxC is RTxC or TRxC, whichever is supplying the receive clock. 2. TxC is TRxC or RTxC, whichever is supplying the transmit clock. 3. Both RTxC and SYNC have 30-pF capacitors to ground connected to them. 4. Parameter applies only if the data rate is one-fourth the PCLK rate. In all other cases, no phase relationship between RxC and PCLK or TxC and PCLK is required. 5. Parameter applies only to FM encoding/decoding. 6. Parameter applies only for transmitter and receiver; DPLL and baud rate generator timing requirements are identical to chip PCLK requirements. 7. The maximum receive or transmit data is 1/4 PCLK. 8. External PCLK to RxC or TxC synchronization requirement eliminated for PCLK divide-by-four operation. TRxC and RTxC rise and fall times are identical to PCLK. Reference timing specs Tfpc and Trpc. Tx and Rx input clock slow rates should be kept to a maximum of 30 ns. All parameters related to input CLK edges should be referenced at the point at which the transition begins or ends, whichever is the worst case. 9. ENHANCED FEATURE—RTxC used as input to internal DPLL only. Am85C30 39 AMD SWITCHING TEST INPUT/OUTPUT WAVEFORM 2.4 V 0.4 V 2.0 V 0.8 V Test Points 2.0 V 0.8 V 10216F-25 AC testing: Inputs are driven at 2.4 V for a logic 1 and 0.4 V for a logic 0. Timing measurements are made at 2.0 V for a logic 1 and 0.8 V for logic 0. PCLK 1 W/REQ Request 2 W/REQ Wait 3 RTxC, TRxC Receive 4 5 6 7 RxD 8 9 SYNC External 10 TRxC RTxC Transmit 11 12 TxD 13 TRxC Output 14 15 RTxC 16 17 TRxC 18 20 19 CTS, DCD, R1 21 21 SYNC Input 22 22 10216F-26 Figure 19. General Timing 40 Am85C30 AMD SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) System Timing (see Figure 20) No. 1 2 3 4 5 6 7a 7b 8 9 10 Parameter Symbol TdRXC(REQ) TdRXC(W) TdRXC(SY) TdRXC(INT) TdTXC(REQ) TdTXC(W) TdTXC(DRQ) TdTXC(EDRQ) TdTXC(INT) TdSY(INT) TdEXT(INT) Parameter Description RXC ↑ W/REQ Valid Delay (Note 2) RXC ↑ to Wait Inactive Delay (Notes 1, 2) RxC ↑ to SYNC Valid Delay (Note 2) RxC ↑ to INT Valid Delay (Notes 1, 2) TxC ↓ to W/REQ Valid Delay (Note 3) TxC ↓ to Wait Inactive Delay (Notes 1, 3) TxC ↓ to DTR/REQ Valid Delay (Note 3) TxC ↓ to DTR/REQ Valid Delay (Notes 3, 4) TxC ↓ to INT Valid Delay (Notes 1, 3) SYNC Transition to INT Valid Delay (Note 1) DCD or CTS Transition to INT Valid Delay (Note 1) Parameter Description RXC ↑ W/REQ Valid Delay (Note 2) RXC ↑ to Wait Inactive Delay (Notes 1, 2) RxC ↑ to SYNC Valid Delay (Note 2) RxC ↑ to INT Valid Delay (Notes 1, 2) TxC ↓ to W/REQ Valid Delay (Note 3) TxC ↓ to Wait Inactive Delay (Notes 1, 3) TxC ↓ to DTR/REQ Valid Delay (Note 3) TxC ↓ to DTR/REQ Valid Delay (Notes 3, 4) TxC ↓ to INT Valid Delay (Notes 1, 3) SYNC Transition to INT Valid Delay (Note 1) DCD or CTS Transition to INT Valid Delay (Note 1) 8.192 MHz Min 8 8 4 10 5 5 4 5 6 2 2 Max 12 14 7 16 8 11 7 8 10 6 6 10 MHz Min 8 8 4 10 5 5 4 5 6 2 2 16.384 MHz Min 8 8 4 10 5 5 4 5 6 2 2 Max 12 14 7 16 8 11 7 8 10 6 6 Unit TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc Max 12 14 7 16 8 11 7 8 10 6 6 Unit TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc No. 1 2 3 4 5 6 7a 7b 8 9 10 Parameter Symbol TdRXC(REQ) TdRXC(W) TdRXC(SY) TdRXC(INT) TdTXC(REQ) TdTXC(W) TdTXC(DRQ) TdTXC(EDRQ) TdTXC(INT) TdSY(INT) TdEXT(INT) Notes: 1. Open-drain output, measured with open-drain test load. 2. RxC is RTxC or TRxC, whichever is supplying the receive clock. 3. TxC is TRxC or RTxC, whichever is supplying the transmit clock. 4. Parameter applies to Enhanced Request mode only. Am85C30 41 AMD SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) Read and Write Timing (see Figure 21) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Parameter Symbol TwPCI TwPCh TfPC TrPC TcPC TsA(WR) ThA(WR) TsA(RD) ThA(RD) TsIA(PC) TsIA(WR) ThIA(WR) TsIA(RD) ThIAi(RD) ThIA(PC) TsCEI(WR) ThCE(WR) TsCEh(WR) TsCEI(RD) ThCE(RD) TsCEh(RD) TwRDI TdRD(DRA) TdRDr(DR) TdRDf(DR) TdRD(DRz) Parameter Description PCLK Low Width PCLK High Width PCLK Fall Time PCLK Rise Time PCLK Cycle Time Address to WR ↓ Setup Time Address to WR ↑ Hold Time Address to RD ↓ Setup Time Address to RD ↑ Hold Time INTACK to PCLK ↑ Setup Time INTACK to WR ↓ Setup Time (Note 1) INTACK to WR ↑ Hold Time INTACK to RD ↓ Setup Time (Note 1) INTACK to RD ↑ Hold Time INTACK to PCLK ↑ Hold Time CE Low to WR ↓ Setup Time CE to WR ↑ Hold Time CE High to WR ↓ Setup Time CE Low to RD ↓ Setup Time (Note 1) CE to RD ↑ Hold Time (Note1) CE High to RD ↓ Setup Time (Note 1) RD Low Width (Note 1) RD ↓ to Read Data Active Delay RD ↑ to Read Data Not Valid Delay RD ↓ to Read Data Valid Delay RD ↑ to Read Data Float Delay (Note 2) 122 70 0 70 0 20 145 0 145 0 40 0 0 60 0 0 60 150 0 0 140 40 8.192 MHz Min 50 50 Max 2000 2000 15 15 4000 100 50 0 50 0 20 120 0 120 0 30 0 0 50 0 0 50 125 0 0 120 35 10 MHz Min 40 40 Max 2000 2000 12 12 4000 61 35 0 35 0 15 70 0 70 0 15 0 0 30 0 0 30 75 0 0 70 20 16.384 MHz Min 26 26 Max 2000 2000 8 8 4000 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Parameter does not apply to Interrupt Acknowledge transactions. 2. Float delay is defined as the time at which the data bus is released from its drive state with a maximum DC load and minimum AC load. 42 Am85C30 AMD RTxC TRxC Receive W/REQ Request W/REQ Wait SYNC Output 3 INT 1 2 4 RTxC TRxC Transmit W/REQ Request 5 W/REQ Wait DTR REQ Request 7 INT 8 CTS, DCD, RI 6 SYNC Input 9 INT 10 10216F-27 Figure 20. System Timing Am85C30 43 AMD PCLK 6 1 2 5 3 4 A/B, D/C 7 8 9 10 INTACK 11 10 13 14 12 15 CE 16 18 RD 19 22 20 21 D7 –D0 Read 23 25 27 Valid 17 24 26 WR 28 D7 –D0 Write 31 29 Valid 30 W/REQ Wait 32 W/REQ Request 33 35 DTR/REQ Request 34 36 INT 37 10216F-28 Figure 21. Read and Write Timing 44 Am85C30 AMD SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) Interrupt Acknowledge Timing, Reset Timing, Cycle Timing (see Figures 22–24) No. 27 28 29 30 31 32 33 34 35a 35b 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Parameter Symbol TdA(DR) TwWRI TdWRf(DW) ThDW(WR) TdWR(W) TdRD(W) TdWRf(REQ) TdRDf(REQ) TdWRr(REQ) TdWRr(EREQ) TdRDr(REQ) TdPC(INT) TdIAi(RD) TwRDA TdRDA(DR) TsIEI(RDA) ThIEI(RDA) TdIEI(IEO) TdPC(IEO) TdRDA(INT) TdRD(WRQ) TdWRQ(RD) TwRES Trc Parameter Description Address Required Valid to Read Data Valid Delay WR Low Width WR ↓ to Write Data Valid Write Data to WR ↑ Hold Time WR ↓ to Wait Valid Delay (Note 2) RD ↓ to Wait Valid Delay (Note 2) WR ↓ to W/REQ Not Valid Delay RD ↓ to W/REQ Not Valid Delay WR ↓ to DTR/REQ Not Valid Delay WR ↓ to DTR/REQ Not Valid Delay RD ↑ to DTR/REQ Not Valid Delay PCLK ↓ to INT Valid Delay (Note 2) INTACK to RD ↓ (Acknowledge) Delay (Note 3) RD (Acknowledge) Width RD ↓ (Acknowledge) to Read Data Valid Delay IEI to RD ↓ (Acknowledge) Setup Time IEI to RD ↑ (Acknowledge) Hold Time IEI to IEO Delay Time PCLK ↑ to IEO Delay RD ↓ to INT Inactive Delay (Note 2) RD ↑ to WR ↓ Delay for No Reset WR ↑ to RD ↓ Delay for No Reset WR and RD Coincident Low for Reset Valid Access Recovery Time (Note 1) 15 15 150 3.5 95 0 95 200 450 15 15 100 3.5 150 150 140 80 0 80 175 320 10 10 75 3.5 0 170 170 170 170 4.0TcPc 120 NA 500 125 125 120 50 0 45 80 200 150 35 0 100 100 120 120 4.0TcPc 120 NA 400 50 75 70 8.192 MHz Min Max 220 125 35 0 50 50 70 70 70 NA 175 10 MHz Min Max 160 75 20 16.384 MHz Min Max 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TcPc 4.0TcPc ns Notes: 1. Parameter applies only between transactions involving the ESCC, if WR/RD falling edge is synchronized to PCLK falling edge, then TrC = 3TcPc. 2. Open-drain output, measured with open-drain test load. 3. Parameter is system dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of DdPC(IEO) for the highest priority device in the daisy chain, TsIEI(RDA) for the SCC, and TdIEI(IEO) for each device separating them in the daisy chain. 4. Parameter applies to Enhanced Request mode only. Am85C30 45 AMD WR 46 RD 47 48 10216F-29 Figure 22. Reset Timing CE 49 RD or WR 10216F-30 Figure 23. Cycle Timing PCLK 10 15 INTACK 14 10 38 RD 39 23 24 D7 –D0 40 41 Valid 26 42 IEI 43 44 IEO 45 INT 10216F-31 Figure 24. Interrupt Acknowledge Timing 46 Am85C30 AMD SWITCHING CHARACTERISTICS over MILITARY/INDUSTRIAL operating range General Timing (see Figure 19) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14a 14b 15a 15b 16a 16b 17 18 19 20 21 Parameter Symbol TdPC(REQ) TdPC(W) TsRXC(PC) TsRXD(RXCr) ThRXD(RXCr) TsRXD(RXCf) ThRXD(RXCf) TsSY(RXC) ThSY(RXC) TsTXC(PC) TdTXCf(TXD) TdTXCr(TXD) TdTXD(TRX) TwRTXh TwRTxh(E) TwRTXI TwRTXl(E) TcRTX TcRTx(E) TcRTXX TwTRXh TwTRXI TcTRX TwEXT Parameter Description PCLK ↓ to W/REQ Valid Delay PCLK ↓ to Wait Inactive Delay RxC ↑ to PCLK ↑ Setup Time (Notes 1, 4 & 8) RxD to RxC ↑ Setup Time (Xl Mode) (Note 1) RxD to RxC ↑ Hold Time (Xl Mode) (Note 1) RxD to RxC ↓ Setup Time (Xl Mode) (Notes 1, 5) RxD to RxC ↓ Hold Time (Xl Mode) (Notes 1, 5) SYNC to RxC ↑ Setup Time (Note 1) SYNC to RxC ↑ Hold Time (Note 1) TxC ↓ to PCLK ↑ Setup Time (Notes 2, 4 & 8) TxC ↓ to TxD Delay (Xl Mode) (Note 2) TxC ↑ to TxD Delay (Xl Mode) (Notes 2, 5) TxD to TRxC Delay (Send Clock Echo) RTxC High Width (Note 6) RTxC High Width (Note 9) RTxC Low Width (Note 6) RTxC Low Width (Note 9) RTxC Cycle Time (Notes 6, 7) RTxC Cycle Time (Note 9) Crystal Oscillator Period (Note 3) TRxC High Width (Note 6) TRxC Low Width (Note 6) TRxC Cycle Time (Notes 6, 7) DCD or CTS Pulse Width 150 50 150 50 488 125 125 150 150 488 200 1000 NA 0 150 0 150 –200 5TcPC NA 200 200 200 120 40 120 40 400 100 100 120 120 400 120 1000 8.192 MHz Min Max 250 350 NA NA 0 125 0 125 –150 5TcPC NA 150 150 140 80 15.6 80 15.6 244 31.25 62 80 80 244 70 1000 10 MHz Min Max 150 250 NA NA 0 50 0 50 –100 5TcPc NA 80 80 80 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 16.384 MHz Min Max 80 180 NA ns ns ns ns ns ns Unit ns ns 22 TwSY SYNC Pulse Width 200 120 70 ns Notes: 1. RxC is RTxC or TRxC, whichever is supplying the receive clock. 2. TxC is TRxC or RTxC, whichever is supplying the transmit clock. 3. Both RTxC and SYNC have 30-pF capacitors to ground connected to them. 4. Parameter applies only if the data rate is one-fourth the PCLK rate. In all other cases, no phase relationship between RxC and PCLK or TxC and PCLK is required. 5. Parameter applies only to FM encoding/decoding. 6. Parameter applies only for transmitter and receiver; DPLL and baud rate generator timing requirements are identical to chip PCLK requirements. 7. The maximum receive or transmit data is 1/4 PCLK. 8. External PCLK to RxC or TxC synchronization requirement eliminated for PCLK divide-by-four operation. TRxC and RTxC rise and fall times are identical to PCLK. Reference timing specs Tfpc and Trpc. Tx and Rx input clock slow rates should be kept to a maximum of 30 ns. All parameters related to input CLK edges should be referenced at the point at which the transition begins or ends, whichever is the worst case. 9. ENHANCED FEATURE—RTxC used as input to internal DPLL only. Am85C30 47 AMD SWITCHING CHARACTERISTICS over MILITARY/INDUSTRIAL operating range (continued) System Timing (see Figure 20) No. 1 2 3 4 5 6 7a 7b 8 9 10 Parameter Symbol TdRXC(REQ) TdRXC(W) TdRXC(SY) TdRXC(INT) TdTXC(REQ) TdTXC(W) TdTXC(DRQ) TdTXC(EDRQ) TdTXC(INT) TdSY(INT) TdEXT(INT) Parameter Description RXC ↑ W/REQ Valid Delay (Note 2) RXC ↑ to Wait Inactive Delay (Notes 1, 2) RxC ↑ to SYNC Valid Delay (Note 2) RxC ↑ to INT Valid Delay (Notes 1, 2) TxC ↓ to W/REQ Valid Delay (Note 3) TxC ↓ to Wait Inactive Delay (Notes 1, 3) TxC ↓ to DTR/REQ Valid Delay (Note 3) TxC ↓ to DTR/REQ Valid Delay (Notes 3, 4) TxC ↓ to INT Valid Delay (Notes 1, 3) SYNC Transition to INT Valid Delay (Note 1) DCD or CTS Transition to INT Valid Delay (Note 1) Parameter Description RXC ↑ W/REQ Valid Delay (Note 2) RXC ↑ to Wait Inactive Delay (Notes 1, 2) RxC ↑ to SYNC Valid Delay (Note 2) RxC ↑ to INT Valid Delay (Notes 1, 2) TxC ↓ to W/REQ Valid Delay (Note 3) TxC ↓ to Wait Inactive Delay (Notes 1, 3) TxC ↓ to DTR/REQ Valid Delay (Note 3) TxC ↓ to DTR/REQ Valid Delay (Notes 3, 4) TxC ↓ to INT Valid Delay (Notes 1, 3) SYNC Transition to INT Valid Delay (Note 1) DCD or CTS Transition to INT Valid Delay (Note 1) 8.192 MHz Min 8 8 4 10 5 5 4 5 6 2 2 Max 12 14 7 16 8 11 7 8 10 6 6 Min 8 8 4 10 5 5 4 5 6 2 2 16.384 MHz Min 8 8 4 10 5 5 4 5 6 2 2 Max 12 14 7 16 8 11 7 8 10 6 6 Unit TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc 10 MHz Max 12 14 7 16 8 11 7 8 10 6 6 Unit TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc No. 1 2 3 4 5 6 7a 7b 8 9 10 Parameter Symbol TdRXC(REQ) TdRXC(W) TdRXC(SY) TdRXC(INT) TdTXC(REQ) TdTXC(W) TdTXC(DRQ) TdTXC(EDRQ) TdTXC(INT) TdSY(INT) TdEXT(INT) Notes: 1. Open-drain output, measured with open-drain test load. 2. RxC is RTxC or TRxC, whichever is supplying the receive clock. 3. TxC is TRxC or RTxC, whichever is supplying the transmit clock. 4. Parameter applies to Enhanced Request mode only. 48 Am85C30 AMD SWITCHING CHARACTERISTICS over MILITARY/INDUSTRIAL operating range (continued) Read and Write Timing (see Figure 21) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Parameter Symbol TwPCI TwPCh TfPC TrPC TcPC TsA(WR) ThA(WR) TsA(RD) ThA(RD) TsIA(PC) TsIA(WR) ThIA(WR) TsIA(RD) ThIAi(RD) ThIA(PC) TsCEI(WR) ThCE(WR) TsCEh(WR) TsCEI(RD) ThCE(RD) TsCEh(RD) TwRDI TdRD(DRA) TdRDr(DR) TdRDf(DR) TdRD(DRz) Parameter Description PCLK Low Width PCLK High Width PCLK Fall Time PCLK Rise Time PCLK Cycle Time Address to WR ↓ Setup Time Address to WR ↑ Hold Time Address to RD ↓ Setup Time Address to RD ↑ Hold Time INTACK to PCLK ↑ Setup Time INTACK to WR ↓ Setup Time (Note 1) INTACK to WR ↑ Hold Time INTACK to RD ↓ Setup Time (Note 1) INTACK to RD ↑ Hold Time INTACK to PCLK ↑ Hold Time CE Low to WR ↓ Setup Time CE to WR ↑ Hold Time CE High to WR ↓ Setup Time CE Low to RD ↓ Setup Time (Note 1) CE to RD ↑ Hold Time (Note1) CE High to RD ↓ Setup Time (Note 1) RD Low Width (Note 1) RD ↓ to Read Data Active Delay RD ↑ to Read Data Not Valid Delay RD ↓ to Read Data Valid Delay RD ↑ to Read Data Float Delay (Note 2) 122 70 0 70 0 20 145 0 145 0 40 0 0 60 0 0 60 150 0 0 140 40 8.192 MHz Min 50 50 Max 1000 1000 15 15 2000 100 50 0 50 0 20 120 0 120 0 30 0 0 50 0 0 50 125 0 0 125 35 10 MHz Min 40 40 Max 1000 1000 12 12 2000 61 35 0 35 0 15 70 0 70 0 15 0 0 30 0 0 30 75 0 0 70 20 16.384 MHz Min 26 26 Max 1000 1000 8 8 2000 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Parameter does not apply to Interrupt Acknowledge transactions. 2. Float delay is defined as the time at which the data bus is released from its drive state with a maximum DC load and minimum AC load. Am85C30 49 AMD SWITCHING CHARACTERISTICS over MILITARY/INDUSTRIAL operating range (continued) Interrupt Acknowledge Timing, Reset Timing, Cycle Timing (see Figures 22–24) No. 27 28 29 30 31 32 33 34 35a 35b 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Parameter Symbol TdA(DR) TwWRI TdWRf(DW) ThDW(WR) TdWR(W) TdRD(W) TdWRf(REQ) TdRDf(REQ) TdWRr(REQ) TdWRr(EREQ) TdRDr(REQ) TdPC(INT) TdIAi(RD) TwRDA TdRDA(DR) TsIEI(RDA) ThIEI(RDA) TdIEI(IEO) TdPC(IEO) TdRDA(INT) TdRD(WRQ) TdWRQ(RD) TwRES Trc Parameter Description Address Required Valid to Read Data Valid Delay WR Low Width WR ↓ to Write Data Valid Write Data to WR ↑ Hold Time WR ↓ to Wait Valid Delay (Note 2) RD ↓ to Wait Valid Delay (Note 2) WR ↓ to W/REQ Not Valid Delay RD ↓ to W/REQ Not Valid Delay WR ↓ to DTR/REQ Not Valid Delay WR ↓ to DTR/REQ Not Valid Delay RD ↑ to DTR/REQ Not Valid Delay PCLK ↓ to INT Valid Delay (Note 2) INTACK to RD ↓ (Acknowledge) Delay (Note 3) RD (Acknowledge) Width RD ↓ (Acknowledge) to Read Data Valid Delay IEI to RD ↓ (Acknowledge) Setup Time IEI to RD ↑ (Acknowledge) Hold Time IEI to IEO Delay Time PCLK ↑ to IEO Delay RD ↓ to INT Inactive Delay (Note 2) RD ↑ to WR ↓ Delay for No Reset WR ↑ to RD ↓ Delay for No Reset WR and RD Coincident Low for Reset Valid Access Recovery Time (Note 1) 15 15 150 3.5 95 0 95 200 450 15 15 100 3.5 150 150 140 80 0 80 175 320 10 10 75 3.5 0 170 170 170 170 4.0TcPc 120 NA 500 125 125 120 50 0 45 80 200 150 35 0 100 100 120 120 4.0TcPc 120 NA 400 50 75 70 8.192 MHz Min Max 220 125 35 0 50 50 70 70 70 NA 175 10 MHz Min Max 160 75 20 16.384 MHz Min Max 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TcPc 4.0TcPc ns Notes: 1 Parameter applies only between transactions involving the ESCC, if WR/RD falling edge is synchronized to PCLK falling edge, then TrC = 3TcPc. 2. Open-drain output, measured with open-drain test load. 3. Parameter is system dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of DdPC(IEO) for the highest priority device in the daisy chain, TsIEI(RDA) for the SCC, and TdIEI(IEO) for each device separating them in the daisy chain. 4. Parameter applies to Enhanced Request mode only. 50 Am85C30 AMD PHYSICAL DIMENSIONS* CD 040 2.035 2.080 .098 MAX .565 .605 1 .050 .065 .100 BSC TOP VIEW .005 MIN .590 .615 .008 .012 .015 .060 0° 15° .015 .022 .700 MAX END VIEW .150 MIN 06824D BZ13 CD 040 5/20/92 c dc .160 .220 .125 .160 SIDE VIEW *For reference only. BSC is an ANSI standard for Basic Space Centering. Am85C30 51 AMD PHYSICAL DIMENSIONS CL 044 .500 BSC .250 BSC .050 BSC .250 BSC .045 .055 .500 BSC .022 .028 .015 MIN .003 .015 .640 .660 .040 X 45° REF. (3x) (OPTIONAL) .625 BSC .054 .088 .064 .100 .006 .022 .640 .660 .625 BSC INDEX CORNER .020 X 45° REF. (OPTIONAL) PLANE 2 PLANE 1 06825E AW 29 8/15/91 c dc 52 Am85C30 AMD PHYSICAL DIMENSIONS PD 040 2.040 2.080 .530 .580 1 .045 .065 .090 .110 TOP VIEW .005 MIN .600 .625 .008 .015 .140 .225 .120 .160 .014 .022 SIDE VIEW .015 .060 0° 7° .630 .700 END VIEW 06823E CJ76 PD 040 1/21/93 c dc PL 044 .042 .048 .050 REF .020 MIN .042 .056 .026 .032 .025 R .045 .013 .021 .500 .590 REF .630 .685 .650 .695 .656 .650 .656 .685 .695 TOP VIEW .009 .015 .165 .180 .090 .120 06752F CJ48 PL 044 1/21/93 c dc SIDE VIEW Trademarks Copyright © 1993 Advanced Micro Devices, Inc. All rights reserved. AMD is a registered trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Am85C30 53 AMENDMENT Am85C30 Enhanced Serial Communications Controller SUMMARY This amendment adds information to the Final Data Sheet on the Commercial and Industrial 20 MHz speed grades. This latest offering complements the 8, 10, and 16 MHz speed grades currently offered by AMD. Advanced Micro Devices A few minor inaccuracies are also corrected and a clarification section on Hardware Reset in Software that had been previously available as a separate page is now reprinted here for ease of reference. Pages 39 and 47: SWITCHING CHARACTERISTICS s In note 8 change from “clock slow rates” to “clock slew rates”. Pages 39–50: SWITCHING CHARACTERISTICS s Add minimum and maximum limits, where appropriate, for the 20 MHz speed grade now being offered. DETAILS Page 1: DISTINCTIVE CHARACTERISTICS s Add 20 MHz/5.0 Mbyte/s under “Fastest data rate of any Am85C30” bullet. Page 4: Ordering Information, Commodity Products s Change word from “Commodity” to “Standard” s Add Am85C30-20 to valid combinations and -20 = 20 MHz to SPEED OPTION Page 5: Ordering Information, Industrial Products s Add Am85C30-20 to valid combinations and -20 = 20 MHz to SPEED OPTION s Change package description from “J = 44-Pin Leadless Chip Carrier (PL 044) ” to “J = 44-Pin Plastic Leaded Chip Carrier (PL 044) ”. Page 38: DC CHARACTERISTICS s Delete ICC1 for the 12 MHz speed grade since this speed is not offered. s Add ICC1 for the 20 MHz speed grade now being offered. s Change symbol from “CMO” to “CI/O” and add note on Capacitance. Note: Minor corrections should be made on the existing data sheets. However, for ease of use, pages 38–50 as well as the page on Hardware Reset in Software are printed with this amendment. Publication# 10216 Rev. F Amendment /1 Issue Date: December 1993 AMD AMENDMENT ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . –65°C to +150°C Voltage at any Pin Relative to VSS . . OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . 0°C to +70°C Supply Voltage (VCC) . . . . . . . . . . . . . . . . +5 V ± 10% Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . –40°C to +85°C Supply Voltage (VCC) . . . . . . . . . . . . . . . . . 5 V ± 10% Military (M) Devices Case Temperature (TC) . . . . . . . . . –55°C to +125°C Supply Voltage (VCC) . . . . . . . . . . . . . . . . . 5 V ± 10% Operating ranges define those limits between which the functionality of the device is guaranteed. . . . . . . . . . . . . . –0.5 to +7.0 V Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. DC CHARACTERISTICS over operating range unless otherwise specified Parameter Symbol VIH VIL VOH1 VOH2 VOL IIL IOL ICC1 Parameter Description Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Input Leakage Output Leakage VCC Supply Current IOH = –1.6 mA IOH = –250 µA IOL = +2.0 mA 0.4 V ≤ VIN ≤ 2.4 V 0.4 V ≤ VOUT ≤ 2.4 V 8.192 MHz 10 MHz 16.384 MHz 20 MHz Inputs at voltage rails, output unloaded Test Conditions Min 2.2 –0.3* 2.4 VCC –0.8 0.4 ±10.0 ±10.0 18 18 22 22 10 15 20 Max VCC +0.3* 0.8 Unit V V V V V µA µA mA mA mA mA pF pF pF CIN** COUT** CI/O** Input Capacitance Output Capacitance Bidirectional Capacitance Unmeasured pins returned to ground = 1 MHz over specified temperature range *VIH Max and VIL Min not tested. Guaranteed by design. **These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. Standard Test Conditions The characteristics below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND. Positive current flows into the referenced pin. Standard conditions are as follows: +4.5 V ≤ VCC ≤ +5.5 V GND = 0 V 0°C ≤ TA ≤ 70°C SWITCHING TEST CIRCUITS Standard Test Dynamic Load Circuit IO L = 2 mA Threshold Voltage VT = 1.4 V 2.2K From Output Under Test 75 pF IOH = 250 µA 10216F/1-1 10216F/1-2 Open-Drain Test Load +5 V From Output Under Test 75 pF 2 Am85C30 AMENDMENT AMD SWITCHING CHARACTERISTICS over COMMERCIAL operating range unless otherwise specified—General Timing (see Figure 19) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14a 14b 15a 15b 16a 16b 17 18 19 20 21 Parameter Symbol TdPC(REQ) TdPC(W) TsRXC(PC) TsRXD(RXCr) ThRXD(RXCr) TsRXD(RXCf) ThRXD(RXCf) TsSY(RXC) ThSY(RXC) TsTXC(PC) TdTXCf(TXD) TdTXCr(TXD) TdTXD(TRX) TwRTXh TwRTxh(E) TwRTXI TwRTXl(E) TcRTX TcRTx(E) TcRTXX TwTRXh TwTRXI TcTRX TwEXT Parameter Description PCLK ↓ to W/REQ Valid Delay PCLK ↓ to Wait Inactive Delay RxC ↑ to PCLK ↑ Setup Time (Notes 1, 4 & 8) RxD to RxC ↑ Setup Time (Xl Mode) (Note 1) RxD to RxC ↑ Hold Time (Xl Mode) (Note 1) RxD to RxC ↓ Setup Time (Xl Mode) (Notes 1, 5) RxD to RxC ↓ Hold Time (Xl Mode) (Notes 1, 5) SYNC to RxC ↑ Setup Time (Note 1) SYNC to RxC ↑ Hold Time (Note 1) TxC ↓ to PCLK ↑ Setup Time (Notes 2, 4 & 8) TxC ↓ to TxD Delay (Xl Mode) (Note 2) TxC ↑ to TxD Delay (Xl Mode) (Notes 2, 5) TxD to TRxC Delay (Send Clock Echo) RTxC High Width (Note 6) RTxC High Width (Note 9) RTxC Low Width (Note 6) RTxC Low Width (Note 9) RTxC Cycle Time (Notes 6, 7) RTxC Cycle Time (Note 9) Crystal Oscillator Period (Note 3) TRxC High Width (Note 6) TRxC Low Width (Note 6) TRxC Cycle Time (Notes 6, 7) DCD or CTS Pulse Width 150 50 150 50 488 125 125 150 150 488 200 1000 NA 0 150 0 150 –200 5TcPc NA 200 200 200 120 40 120 40 400 100 100 120 120 400 120 1000 8.192 MHz Min Max 250 350 NA NA 0 125 0 125 –150 5TcPc NA 150 150 140 80 15.6 80 15.6 244 31.25 62 80 80 244 70 1000 10 MHz Min Max 150 250 NA NA 0 50 0 50 –100 5TcPc NA 80 80 80 70 15.6 70 15.6 200 31.25 61 70 70 200 60 1000 16.384 MHz Min Max 80 180 NA NA 0 45 0 45 –90 5TcPc NA 70 70 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 MHz Min Max Unit 70 170 NA ns ns ns ns ns ns ns ns ns 22 TwSY SYNC Pulse Width 200 120 70 60 ns Notes: 1. RxC is RTxC or TRxC, whichever is supplying the receive clock. 2. TxC is TRxC or RTxC, whichever is supplying the transmit clock. 3. Both RTxC and SYNC have 30-pF capacitors to ground connected to them. 4. Parameter applies only if the data rate is one-fourth the PCLK rate. In all other cases, no phase relationship between RxC and PCLK or TxC and PCLK is required. 5. Parameter applies only to FM encoding/decoding. 6. Parameter applies only for transmitter and receiver; DPLL and baud rate generator timing requirements are identical to chip PCLK requirements. 7. The maximum receive or transmit data is 1/4 PCLK. 8. External PCLK to RxC or TxC synchronization requirement eliminated for PCLK divide-by-four operation. TRxC and RTxC rise and fall times are identical to PCLK. Reference timing specs Tfpc and Trpc. Tx and Rx input clock slew rates should be kept to a maximum of 30 ns. All parameters related to input CLK edges should be referenced at the point at which the transition begins or ends, whichever is the worst case. 9. ENHANCED FEATURE—RTxC used as input to internal DPLL only. Am85C30 3 AMD AMENDMENT SWITCHING TEST INPUT/OUTPUT WAVEFORM 2.4 V 0.4 V 2.0 V 0.8 V Test Points 2.0 V 0.8 V 10216F/1-3 AC testing: Inputs are driven at 2.4 V for a logic 1 and 0.4 V for a logic 0. Timing measurements are made at 2.0 V for a logic 1 and 0.8 V for logic 0. PCLK 1 W/REQ Request 2 W/REQ Wait 3 RTxC, TRxC Receive 4 5 6 7 RxD 8 9 SYNC External 10 TRxC RTxC Transmit 11 12 TxD 13 TRxC Output 14 15 RTxC 16 17 TRxC 18 20 19 CTS, DCD, R1 21 21 SYNC Input 22 22 10216F/1-4 Figure 19. General Timing 4 Am85C30 AMENDMENT AMD SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) System Timing (see Figure 20) No. 1 2 3 4 5 6 7a 7b 8 9 10 Parameter Symbol TdRXC(REQ) TdRXC(W) TdRXC(SY) TdRXC(INT) TdTXC(REQ) TdTXC(W) TdTXC(DRQ) TdTXC(EDRQ) TdTXC(INT) TdSY(INT) TdEXT(INT) Parameter Symbol TdRXC(REQ) TdRXC(W) TdRXC(SY) TdRXC(INT) TdTXC(REQ) TdTXC(W) TdTXC(DRQ) TdTXC(EDRQ) TdTXC(INT) TdSY(INT) TdEXT(INT) Parameter Description RXC ↑ W/REQ Valid Delay (Note 2) RXC ↑ to Wait Inactive Delay (Notes 1, 2) RxC ↑ to SYNC Valid Delay (Note 2) RxC ↑ to INT Valid Delay (Notes 1, 2) TxC ↑ to W/REQ Valid Delay (Note 3) TxC ↓ to Wait Inactive Delay (Notes 1, 3) TxC ↓ to DTR/REQ Valid Delay (Note 3) TxC ↓ to DTR/REQ Valid Delay (Notes 3, 4) TxC ↓ to INT Valid Delay (Notes 1, 3) SYNC Transition to INT Valid Delay (Note 1) DCD or CTS Transition to INT Valid Delay (Note 1) Parameter Description RXC ↑ W/REQ Valid Delay (Note 2) RXC ↑ to Wait Inactive Delay (Notes 1, 2) RxC ↑ to SYNC Valid Delay (Note 2) RxC ↑ to INT Valid Delay (Notes 1, 2) TxC ↓ to W/REQ Valid Delay (Note 3) TxC ↓ to Wait Inactive Delay (Notes 1, 3) TxC ↓ to DTR/REQ Valid Delay (Note 3) TxC ↓ to DTR/REQ Valid Delay (Notes 3, 4) TxC ↓ to INT Valid Delay (Notes 1, 3) SYNC Transition to INT Valid Delay (Note 1) DCD or CTS Transition to INT Valid Delay (Note 1) 8.192 MHz Min 8 8 4 10 5 5 4 5 6 2 2 Max 12 14 7 16 8 11 7 8 10 6 6 Min 8 8 4 10 5 5 4 5 6 2 2 20 MHz Min 8 8 4 10 5 5 4 5 6 2 2 Max 12 14 7 16 8 11 7 8 10 6 6 Unit TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc 10 MHz Max 12 14 7 16 8 11 7 8 10 6 6 Unit TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc 16.384 MHz Min 8 8 4 10 5 5 4 5 6 2 2 Max 12 14 7 16 8 11 7 8 10 6 6 No. 1 2 3 4 5 6 7a 7b 8 9 10 Notes: 1. Open-drain output, measured with open-drain test load. 2. RxC is RTxC or TRxC, whichever is supplying the receive clock. 3. TxC is TRxC or RTxC, whichever is supplying the transmit clock. 4. Parameter applies to Enhanced Request mode only. Am85C30 5 AMD AMENDMENT SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) Read and Write Timing (see Figure 21) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Parameter Symbol TwPCI TwPCh TfPC TrPC TcPC TsA(WR) ThA(WR) TsA(RD) ThA(RD) TsIA(PC) TsIA(WR) ThIA(WR) TsIA(RD) ThIAi(RD) ThIA(PC) TsCEI(WR) ThCE(WR) TsCEh(WR) TsCEI(RD) ThCE(RD) TsCEh(RD) TwRDI TdRD(DRA) TdRDr(DR) TdRDf(DR) TdRD(DRz) Parameter Description PCLK Low Width PCLK High Width PCLK Fall Time PCLK Rise Time PCLK Cycle Time Address to WR ↓ Setup Time Address to WR ↑ Hold Time Address to RD ↓ Setup Time Address to RD ↑ Hold Time INTACK to PCLK ↑ Setup Time INTACK to WR ↓ Setup Time (Note 1) INTACK to WR ↑ Hold Time INTACK to RD ↓ Setup Time (Note 1) INTACK to RD ↑ Hold Time INTACK to PCLK ↑ Hold Time CE Low to WR ↓ Setup Time CE to WR ↑ Hold Time CE High to WR ↓ Setup Time CE Low to RD ↓ Setup Time (Note 1) CE to RD ↑ Hold Time (Note1) CE High to RD ↓ Setup Time (Note 1) RD Low Width (Note 1) RD ↓ to Read Data Active Delay RD ↑ to Read Data Not Valid Delay RD ↓ to Read Data Valid Delay RD ↑ to Read Data Float Delay (Note 2) 122 70 0 70 0 20 145 0 145 0 40 0 0 60 0 0 60 150 0 0 140 40 8.192 MHz Min 50 50 Max 2000 2000 15 15 4000 100 50 0 50 0 20 120 0 120 0 30 0 0 50 0 0 50 125 0 0 120 35 10 MHz Min 40 40 Max 2000 2000 12 12 4000 61 35 0 35 0 15 70 0 70 0 15 0 0 30 0 0 30 75 0 0 70 20 16.384 MHz Min 26 26 Max 2000 2000 8 8 4000 50 30 0 30 0 15 65 0 65 0 15 0 0 25 0 0 25 65 0 0 65 20 20 MHz Min 22 22 Max Unit 2000 2000 5 5 2000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Parameter does not apply to Interrupt Acknowledge transactions. 2. Float delay is defined as the time at which the data bus is released from its drive state with a maximum DC load and minimum AC load. 6 Am85C30 AMENDMENT AMD RTxC TRxC Receive W/REQ Request W/REQ Wait SYNC Output 3 INT 1 2 4 RTxC TRxC Transmit W/REQ Request 5 W/REQ Wait DTR REQ Request 7 INT 8 CTS, DCD, RI 6 SYNC Input 9 INT 10 10216F/1-5 Figure 20. System Timing Am85C30 7 AMD PCLK 6 AMENDMENT 1 2 5 3 4 A/B, D/C 7 8 9 10 INTACK 11 10 13 14 12 15 CE 16 18 RD 19 22 20 21 D0–D7 Read 23 25 27 Valid 17 24 26 WR 28 D0–D7 Write 31 29 Valid 30 W/REQ Wait 32 W/REQ Request 33 35 DTR/REQ Request 34 36 INT 37 10216F/1-6 Figure 21. Read and Write Timing 8 Am85C30 AMENDMENT AMD SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) Interrupt Acknowledge Timing, Reset Timing, Cycle Timing (see Figures 22–24) No. 27 28 29 30 31 32 33 34 35a 35b 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Parameter Symbol TdA(DR) TwWRI TdWRf(DW) ThDW(WR) TdWR(W) TdRD(W) TdWRf(REQ) TdRDf(REQ) TdWRr(REQ) TdWRr(EREQ) TdRDr(REQ) TdPC(INT) TdIAi(RD) TwRDA TdRDA(DR) TsIEI(RDA) ThIEI(RDA) TdIEI(IEO) TdPC(IEO) TdRDA(INT) TdRD(WRQ) TdWRQ(RD) TwRES Trc Parameter Description Address Required Valid to Read Data Valid Delay WR Low Width WR ↓ to Write Data Valid Write Data to WR ↑ Hold Time WR ↓ to Wait Valid Delay (Note 2) RD ↓ to Wait Valid Delay (Note 2) WR ↓ to W/REQ Not Valid Delay RD ↓ to W/REQ Not Valid Delay WR ↓ to DTR/REQ Not Valid Delay WR ↓ to DTR/REQ Not Valid Delay RD ↑ to DTR/REQ Not Valid Delay PCLK ↓ to INT Valid Delay (Note 2) INTACK to RD ↓ (Acknowledge) Delay (Note 3) RD (Acknowledge) Width RD ↓ (Acknowledge) to Read Data Valid Delay IEI to RD ↓ (Acknowledge) Setup Time IEI to RD ↑ (Acknowledge) Hold Time IEI to IEO Delay Time PCLK ↑ to IEO Delay RD ↓ to INT Inactive Delay (Note 2) RD ↑ to WR ↓ Delay for No Reset WR ↑ to RD ↓ Delay for No Reset WR and RD Coincident Low for Reset Valid Access Recovery Time (Note 1) 15 15 150 3.5 95 0 95 200 450 15 15 100 3.5 150 150 140 80 0 80 175 320 10 10 75 3.5 0 170 170 170 170 4TcPc 120 NA 500 125 125 120 50 0 45 80 200 10 10 65 3.5 150 35 0 100 100 120 120 4TcPc 120 NA 400 50 75 70 45 0 40 70 180 8.192 MHz Min Max 220 125 35 0 50 50 70 70 4TcPc 70 NA 175 45 65 60 10 MHz Min Max 160 75 20 0 50 50 65 65 65 NA 160 16.384 MHz Min Max 100 65 20 20 MHz Min Max Unit 90 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TcPc 4TcPc ns Notes: 1 Parameter applies only between transactions involving the ESCC, if WR/RD falling edge is synchronized to PCLK falling edge, then TrC = 3TcPc. 2. Open-drain output, measured with open-drain test load. 3. Parameter is system dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of DdPC(IEO) for the highest priority device in the daisy chain, TsIEI(RDA) for the SCC, and TdIEI(IEO) for each device separating them in the daisy chain. 4. Parameter applies to Enhanced Request mode only. Am85C30 9 AMD WR AMENDMENT 46 RD 47 48 10216F/1-7 Figure 22. Reset Timing CE 49 RD or WR 10216F/1-8 Figure 23. Cycle Timing PCLK 10 15 INTACK 14 10 38 RD 39 23 24 D0–D7 40 41 Valid 26 42 IEI 43 44 IEO 45 INT 10216F/1-9 Figure 24. Interrupt Acknowledge Timing 10 Am85C30 AMENDMENT AMD SWITCHING CHARACTERISTICS over MILITARY/INDUSTRIAL operating range unless otherwise specified—General Timing (see Figure 19) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14a 14b 15a 15b 16a 16b 17 18 19 20 21 Parameter Symbol TdPC(REQ) TdPC(W) TsRXC(PC) TsRXD(RXCr) ThRXD(RXCr) TsRXD(RXCf) ThRXD(RXCf) TsSY(RXC) ThSY(RXC) TsTXC(PC) TdTXCf(TXD) TdTXCr(TXD) TdTXD(TRX) TwRTXh TwRTxh(E) TwRTXI TwRTXl(E) TcRTX TcRTx(E) TcRTXX TwTRXh TwTRXI TcTRX TwEXT Parameter Description PCLK ↓ to W/REQ Valid Delay PCLK ↓ to Wait Inactive Delay RxC ↑ to PCLK ↑ Setup Time (Notes 1, 4 & 8) RxD to RxC ↑ Setup Time (Xl Mode) (Note 1) RxD to RxC ↑ Hold Time (Xl Mode) (Note 1) RxD to RxC ↓ Setup Time (Xl Mode) (Notes 1, 5) RxD to RxC ↓ Hold Time (Xl Mode) (Notes 1, 5) SYNC to RxC ↑ Setup Time (Note 1) SYNC to RxC ↑ Hold Time (Note 1) TxC ↓ to PCLK ↑ Setup Time (Notes 2, 4 & 8) TxC ↓ to TxD Delay (Xl Mode) (Note 2) TxC ↑ to TxD Delay (Xl Mode) (Notes 2, 5) TxD to TRxC Delay (Send Clock Echo) RTxC High Width (Note 6) RTxC High Width (Note 9) RTxC Low Width (Note 6) RTxC Low Width (Note 9) RTxC Cycle Time (Notes 6, 7) RTxC Cycle Time (Note 9) Crystal Oscillator Period (Note 3) TRxC High Width (Note 6) TRxC Low Width (Note 6) TRxC Cycle Time (Notes 6, 7) DCD or CTS Pulse Width 150 50 150 50 488 125 125 150 150 488 200 1000 NA 0 150 0 150 –200 5TcPc NA 200 200 200 120 40 120 40 400 100 100 120 120 400 120 1000 8.192 MHz Min Max 250 350 NA NA 0 125 0 125 –150 5TcPc NA 150 150 140 80 15.6 80 15.6 244 31.25 62 80 80 244 70 1000 10 MHz Min Max 150 250 NA NA 0 50 0 50 –100 5TcPc NA 80 80 80 70 15.6 70 15.6 200 31.25 61 70 70 200 60 1000 16.384 MHz Min Max 80 180 NA NA 0 45 0 45 –90 5TcPc NA 70 70 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 MHz Industrial Only Min Max Unit 70 170 NA ns ns ns ns ns ns ns ns ns 22 TwSY SYNC Pulse Width 200 120 70 60 ns Notes: 1. RxC is RTxC or TRxC, whichever is supplying the receive clock. 2. TxC is TRxC or RTxC, whichever is supplying the transmit clock. 3. Both RTxC and SYNC have 30-pF capacitors to ground connected to them. 4. Parameter applies only if the data rate is one-fourth the PCLK rate. In all other cases, no phase relationship between RxC and PCLK or TxC and PCLK is required. 5. Parameter applies only to FM encoding/decoding. 6. Parameter applies only for transmitter and receiver; DPLL and baud rate generator timing requirements are identical to chip PCLK requirements. 7. The maximum receive or transmit data is 1/4 PCLK. 8. External PCLK to RxC or TxC synchronization requirement eliminated for PCLK divide-by-four operation. TRxC and RTxC rise and fall times are identical to PCLK. Reference timing specs Tfpc and Trpc. Tx and Rx input clock slew rates should be kept to a maximum of 30 ns. All parameters related to input CLK edges should be referenced at the point at which the transition begins or ends, whichever is the worst case. 9. ENHANCED FEATURE—RTxC used as input to internal DPLL only. Am85C30 11 AMD AMENDMENT SWITCHING CHARACTERISTICS over MILITARY/INDUSTRIAL operating range (continued)—System Timing (see Figure 20) No. 1 2 3 4 5 6 7a 7b 8 9 10 Parameter Symbol TdRXC(REQ) TdRXC(W) TdRXC(SY) TdRXC(INT) TdTXC(REQ) TdTXC(W) TdTXC(DRQ) TdTXC(EDRQ) TdTXC(INT) TdSY(INT) TdEXT(INT) Parameter Symbol TdRXC(REQ) TdRXC(W) TdRXC(SY) TdRXC(INT) TdTXC(REQ) TdTXC(W) TdTXC(DRQ) TdTXC(EDRQ) TdTXC(INT) TdSY(INT) TdEXT(INT) Parameter Description RXC ↑ W/REQ Valid Delay (Note 2) RXC ↑ to Wait Inactive Delay (Notes 1, 2) RxC ↑ to SYNC Valid Delay (Note 2) RxC ↑ to INT Valid Delay (Notes 1, 2) TxC ↑ to W/REQ Valid Delay (Note 3) TxC ↓ to Wait Inactive Delay (Notes 1, 3) TxC ↓ to DTR/REQ Valid Delay (Note 3) TxC ↓ to DTR/REQ Valid Delay (Notes 3, 4) TxC ↓ to INT Valid Delay (Notes 1, 3) SYNC Transition to INT Valid Delay (Note 1) DCD or CTS Transition to INT Valid Delay (Note 1) Parameter Description RXC ↑ W/REQ Valid Delay (Note 2) RXC ↑ to Wait Inactive Delay (Notes 1, 2) RxC ↑ to SYNC Valid Delay (Note 2) RxC ↑ to INT Valid Delay (Notes 1, 2) TxC ↓ to W/REQ Valid Delay (Note 3) TxC ↓ to Wait Inactive Delay (Notes 1, 3) TxC ↓ to DTR/REQ Valid Delay (Note 3) TxC ↓ to DTR/REQ Valid Delay (Notes 3, 4) TxC ↓ to INT Valid Delay (Notes 1, 3) SYNC Transition to INT Valid Delay (Note 1) DCD or CTS Transition to INT Valid Delay (Note 1) 8.192 MHz Min 8 8 4 10 5 5 4 5 6 2 2 Max 12 14 7 16 8 11 7 8 10 6 6 Min 8 8 4 10 5 5 4 5 6 2 2 10 MHz Max 12 14 7 16 8 11 7 8 10 6 6 Unit TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc 16.384 MHz Min 8 8 4 10 5 5 4 5 6 2 2 Max 12 14 7 16 8 11 7 8 10 6 6 No. 1 2 3 4 5 6 7a 7b 8 9 10 20 MHz Industrial Only Min Max 8 8 4 10 5 5 4 5 6 2 2 12 14 7 16 8 11 7 8 10 6 6 Unit TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc TcPc Notes: 1. Open-drain output, measured with open-drain test load. 2. RxC is RTxC or TRxC, whichever is supplying the receive clock. 3. TxC is TRxC or RTxC, whichever is supplying the transmit clock. 4. Parameter applies to Enhanced Request mode only. 12 Am85C30 AMENDMENT AMD SWITCHING CHARACTERISTICS over MILITARY/INDUSTRIAL operating range (continued) Read and Write Timing (see Figure 21) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Parameter Symbol TwPCI TwPCh TfPC TrPC TcPC TsA(WR) ThA(WR) TsA(RD) ThA(RD) TsIA(PC) TsIA(WR) ThIA(WR) TsIA(RD) ThIAi(RD) ThIA(PC) TsCEI(WR) ThCE(WR) TsCEh(WR) TsCEI(RD) ThCE(RD) TsCEh(RD) TwRDI TdRD(DRA) TdRDr(DR) TdRDf(DR) TdRD(DRz) Parameter Description PCLK Low Width PCLK High Width PCLK Fall Time PCLK Rise Time PCLK Cycle Time Address to WR ↓ Setup Time Address to WR ↑ Hold Time Address to RD ↓ Setup Time Address to RD ↑ Hold Time INTACK to PCLK ↑ Setup Time INTACK to WR ↓ Setup Time (Note 1) INTACK to WR ↑ Hold Time INTACK to RD ↓ Setup Time (Note 1) INTACK to RD ↑ Hold Time INTACK to PCLK ↑ Hold Time CE Low to WR ↓ Setup Time CE to WR ↑ Hold Time CE High to WR ↓ Setup Time CE Low to RD ↓ Setup Time (Note 1) CE to RD ↑ Hold Time (Note1) CE High to RD ↓ Setup Time (Note 1) RD Low Width (Note 1) RD ↓ to Read Data Active Delay RD ↑ to Read Data Not Valid Delay RD ↓ to Read Data Valid Delay RD ↑ to Read Data Float Delay (Note 2) 122 70 0 70 0 20 145 0 145 0 40 0 0 60 0 0 60 150 0 0 140 40 20 MHz 8.192 MHz Min Max 50 50 1000 1000 15 15 2000 100 50 0 50 0 20 120 0 120 0 30 0 0 50 0 0 50 125 0 0 125 35 10 MHz Min Max 40 40 1000 1000 12 12 2000 61 35 0 35 0 15 70 0 70 0 15 0 0 30 0 0 30 75 0 0 70 20 16.384 MHz Min Max 26 26 1000 1000 8 8 2000 50 30 0 30 0 15 65 0 65 0 15 0 0 25 0 0 25 65 0 0 65 20 Industrial Only Min 22 22 Max Unit 1000 1000 5 5 2000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Parameter does not apply to Interrupt Acknowledge transactions. 2. Float delay is defined as the time at which the data bus is released from its drive state with a maximum DC load and minimum AC load. Am85C30 13 AMD AMENDMENT SWITCHING CHARACTERISTICS over MILITARY/INDUSTRIAL operating range (continued) Interrupt Acknowledge Timing, Reset Timing, Cycle Timing (see Figures 22–24) No. 27 28 29 30 31 32 33 34 35a 35b 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Parameter Symbol TdA(DR) TwWRI TdWRf(DW) ThDW(WR) TdWR(W) TdRD(W) TdWRf(REQ) TdRDf(REQ) TdWRr(REQ) TdWRr(EREQ) TdRDr(REQ) TdPC(INT) TdIAi(RD) TwRDA TdRDA(DR) TsIEI(RDA) ThIEI(RDA) TdIEI(IEO) TdPC(IEO) TdRDA(INT) TdRD(WRQ) TdWRQ(RD) TwRES Trc Parameter Description Address Required Valid to Read Data Valid Delay WR Low Width WR ↓ to Write Data Valid Write Data to WR ↑ Hold Time WR ↓ to Wait Valid Delay (Note 2) RD ↓ to Wait Valid Delay (Note 2) WR ↓ to W/REQ Not Valid Delay RD ↓ to W/REQ Not Valid Delay WR ↓ to DTR/REQ Not Valid Delay WR ↓ to DTR/REQ Not Valid Delay RD ↑ to DTR/REQ Not Valid Delay PCLK ↓ to INT Valid Delay (Note 2) INTACK to RD ↓ (Acknowledge) Delay (Note 3) RD (Acknowledge) Width RD ↓ (Acknowledge) to Read Data Valid Delay IEI to RD ↓ (Acknowledge) Setup Time IEI to RD ↑ (Acknowledge) Hold Time IEI to IEO Delay Time PCLK ↑ to IEO Delay RD ↓ to INT Inactive Delay (Note 2) RD ↑ to WR ↓ Delay for No Reset WR ↑ to RD ↓ Delay for No Reset WR and RD Coincident Low for Reset Valid Access Recovery Time (Note 1) 15 15 150 3.5 95 0 95 200 450 15 15 100 3.5 150 150 140 80 0 80 175 320 10 10 75 3.5 0 170 170 170 170 4TcPc 120 NA 500 125 125 120 50 0 45 80 200 10 10 65 3.5 150 35 0 100 100 120 120 4TcPc 120 NA 400 50 75 70 45 0 40 70 180 8.192 MHz Min Max 220 125 35 0 50 50 70 70 4TcPc 70 NA 175 45 65 60 10 MHz Min Max 160 75 20 0 50 50 65 65 65 NA 160 16.384 MHz Min Max 100 65 20 20 MHz Industrial Only Min Max Unit 90 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TcPc 4TcPc ns Notes: 1 Parameter applies only between transactions involving the ESCC, if WR/RD falling edge is synchronized to PCLK falling edge, then TrC = 3TcPc. 2. Open-drain output, measured with open-drain test load. 3. Parameter is system dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of DdPC(IEO) for the highest priority device in the daisy chain, TsIEI(RDA) for the SCC, and TdIEI(IEO) for each device separating them in the daisy chain. 4. Parameter applies to Enhanced Request mode only. 14 Am85C30 AMENDMENT AMD Am85C30 HARDWARE RESET IN SOFTWARE In the absence of a hardware logic or a Power-On-Reset mechanism, the following procedure should be used to ensure that the ESCC is properly reset. 1. Power Up 2. Read RR0 3. Read RR1 4. Write a C0h to WR9 5. Read RR0 (Dummy Read) (Dummy Read) (Hardware Reset) (Should expect binary 01XXX100 = typically ‘44h’) (Should expect binary 0X000110 = typically ‘06h’) (Should get ‘a value’) Note: For hardware reset only steps 1 through 4 are needed; steps 5 through 8 are mentioned simply for confirmation. Also, this procedure is applicable to only the first time hardware reset. Any subsequent chip reset can be achieved by simply writing a ‘C0’ to WR9. For further information refer to the Technical Manual PID # 07513D. 6. Read RR1 7. Write ‘a value’ to Write Register 2 8. Read RR2 If RR2 = WR2, in steps 7 and 8, then the ESCC is properly reset. Am85C30 15