AMC010CFLKA

FINAL AmC0XXCFLKA 1, 2, 4, or 10 Megabyte 5.0 V-only Flash Memory PC Card DISTINCTIVE CHARACTERISTICS s High performance — 150 ns maximum access time s Single supply operation — Write and erase voltage, 5.0 V ±5% — Read voltage, 5.0 V ±5% s CMOS low power consumption — 45 mA maximum active read current (x8 mode) — 65 mA maximum active erase/write current (x8 mode) s High write endurance — Minimum 100,000 erase/write cycles s PCMCIA/JEIDA 68-pin standard — Selectable byte- or word-wide configuration s Write protect switch — Prevents accidental data loss s Zero data retention power — Batteries not required for data storage s Separate attribute memory — 512 byte EEPROM s Automated write and erase operations increase system write performance — 64K byte memory sectors for faster automated erase speed — Typically 1.5 seconds per single memory sector erase — Random address writes to previously erased bytes (16 µs typical per byte) s Total system integration solution — Support from independent software and hardware vendors s Low insertion and removal force — State-of-the-art connector allows for minimum card insertion and removal effort s Sector erase suspend/resume — Suspend the erase operation to allow a read operation in another sector within the same device GENERAL DESCRIPTION AMD’s 5.0 V-only Flash Memory PC Card provides the highest system level performance for data and file storage solutions to the portable PC market segment. Manufactured with AMD’s Negative Gate Erase, 5.0 V-only technology, the AMD 5.0 V-only Flash Memory Cards are the most cost-effective and reliable approach to single-supply Flash memory cards. Data files and application programs can be stored on the “C” series cards. This allows OEM manufacturers of portable systems to eliminate the weight, high power consumption and reliability issues associated with electromechanical disk-based systems. The “C” series cards also allow today’s bulky and heavy battery packs to be reduced in weight and size. Typically only two “AA” alkaline batteries are required for total system operation. AMD’s Flash Memory PC Cards provide the most efficient method to transfer useful work between different hardware platforms. The enabling technology of the “C” series cards enhances the productivity of mobile workers. Widespread acceptance of the “C” series cards is assured due to their compatibility with the 68-pin PCMCIA/JEIDA international standard. AMD’s Flash Memory Cards can be read in either a byte-wide or word-wide mode which allows for flexible integration into various system platforms. Compatibility is assured at the hardware interface and software interchange specification. The Card Information Structure (CIS) or Metaformat, can be written by the OEM at the memory card’s attribute memory address space beginning at address 00000H by using a format utility. The CIS appears at the beginning of the Card’s attribute memory space and defines the low-level organization of data on the PC Card. The “C” series cards contains a separate 512 byte EEPROM memory for the cards’ attribute memory space. This allows all of the Flash memory to be used for the common memory space. Third party software solutions such as Microsoft’s Flash File System (FFS), M-System’s True FFS, and SCM’s SCM-FFS, enable AMD’s Flash Memory PC Card to replicate the function of traditional disk-based memory systems. Publication# 18723 Rev: C Amendment/+1 Issue Date: May 1998 BLOCK DIAGRAM VCC R R D0–D15 WE OE WP I/O Transceivers and Buffers WP (Note 1) D8–D15 D0–D7 WE OE VCC Write Protect Switch A0 A1–A23* CE2 VCC R R R CE1 A1–A9 Decoder A0–A8 D0–D7 Am29F040 A0–A18 D0–D7 CE WE S0* OE VSS VCC Am29F040 A0–A18 D8–D15 CE WE S1* OE VSS VCC Address Buffers and Decoders A0–A18 CEH0– CEH9 CEL0– CEL9 A0 CE2 CE1 REG Attribute Memory CE CD1 CD2 A0–A18 D0–D7 CE WE S2* OE VSS VCC A0–A18 D8–D15 CE WE S3* OE VSS VCC Card Detect BVD1 BVD2 10K VCC Battery Voltage Detect A0–A18 D0–D7 CE WE S18* OE VSS VCC A0–A18 D8–D15 CE WE S19* OE VSS VCC GND VCC 18723C-1 Notes: R = 20 K(min)/140 KΩ (max) *1 Mbyte card = S0 + S1, *2 Mbyte card = S0…S3, *4 Mbyte card = S0…S7, *10 Mbyte card = S0…S19 2 AmC0XXCFLKA 5/4/98 PC CARD PIN ASSIGNMENTS Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 3 GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE NC VCC1 NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND I I I I I I I I I I I I/O I/O I/O O I/O I/O I/O I/O I/O I I I I I I I I I 3 Ground Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Card Enable 1 (Note 3) Address Bit 10 Output Enable Address Bit 11 Address Bit 9 Address Bit 8 Address Bit 13 Address Bit 14 Write Enable No Connect Power Supply No Connect (Note 1) Address Bit 16 Address Bit 15 Address Bit 12 Address Bit 7 Address Bit 6 Address Bit 5 Address Bit 4 Address Bit 3 Address Bit 2 Address Bit 1 Address Bit 0 Data Bit 0 Data Bit 1 Data Bit 2 Write Protect (Note 3) Ground Function Pin# 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Signal GND CD1 D11 D12 D13 D14 D15 CE2 NC NC NC A17 A18 A19 A20 A21 VCC2 NC A22 A23 NC NC NC NC NC NC REG BVD2 BVD1 D8 D9 D10 CD2 GND I O O I/O I/O I/O O I I I I I I I O I/O I/O I/O I/O I/O I I/O Ground Card Detect 1 (Note 3) Data Bit 11 Data Bit 12 Data Bit 13 Data Bit 14 Data Bit 15 Card Enable 2 (Note 3) No Connect No Connect No Connect Address Bit 17 Address Bit 18 Address Bit 19 (Note 4) Address Bit 20 (Note 5) Address Bit 21 (Note 6) Power Supply No Connect (Note 1) Address Bit 22 Address Bit 23 (Note 7) No Connect No Connect No Connect No Connect No Connect No Connect Register Select Battery Voltage Detect 2 (Note 2) Battery Voltage Detect 1 (Note 2) Data Bit 8 Data Bit 9 Data Bit 10 Card Detect 2 (Note 3) Ground Function Notes: I = Input to card, O = Output from card I/O = Bidirectional NC = No connect In systems which switch VCC individually to cards, no signal should be directly connected between cards other than ground. 1. VPP not required for Programming or Reading operations. 2. BVD = Internally pulled-up. 3. Signal must not be connected between cards. 4. Highest address bit for 1 Mbyte card. 5. Highest address bit for 2 Mbyte card. 6. Highest address bit for 4 Mbyte card. 7. Highest address bit for 10 Mbyte card. 5/4/98 AmC0XXCFLKA 3 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM C 0XX C FL K A xxx SPEED OPTION -150 ns REVISION LEVEL OUTPUT CONFIGURATION: (x16/x8) FLASH TECHNOLOGY SERIES MEMORY CARD DENSITY 001 = One Megabyte 002 = Two Megabyte 004 = Four Megabyte 010 = Ten Megabyte PC MEMORY CARD AMD 4 AmC0XXCFLKA 5/4/98 PIN DESCRIPTION A0–A23 Address Inputs These inputs are internally latched during write cycles. target address is latched on the falling edge of the WE pulse and the appropriate data is latched on the rising edge of the pulse. WP Write Protect This output is active high and disables all card write operations. BVD1, BVD2 Battery Voltage Detect Internally pulled-up. MEMORY CARD OPERATIONS The “C” series Flash Memory Card is organized as an array of individual devices. Each device is 512K bytes in size with eight 64K byte sectors. Although the address space is continuous each physical device defines a logical address segment size. Byte-wide erase operations could be performed in four ways: s In increments of the segment size s In increments of the sectors in individual segments s All eight sectors in parallel within individual segments s Selected sectors of the eight sectors in parallel within individual segments Multiple segments may be erased concurrently when additional ICC current is supplied to the device. Once a memory sector or memory segment is erased any address location may be programmed. Flash technology allows any logical “1” data bit to be programmed to a logical “0”. The only way to reset bits to a logical “1” is to erase the entire memory sector of 64K bytes or memory segment of 512K bytes. Erase operations are the only operations that work on entire memory sectors or memory segments. All other operations such as word-wide programming are not affected by the physical memory segments. The common memory space data contents are altered in a similar manner as writing to individual Flash memory devices. On-card address and data buffers activate the appropriate Flash device in the memory array. Each device internally latches address and data during write cycles. Refer to Table 1. Attribute memory is a separately accessed card memory space. The register memory space is active when the REG pin is driven low. The Card Information Structure (CIS) describes the capabilities and specification of a card. The CIS is stored in the attribute memory space beginning at address 00000H. The “C” series cards contain a separate 512 byte EEPROM memory for the Card Information Structure. D0–D7 are active during attribute memory accesses. D8–D15 should be ignored. Odd order bytes present invalid data. Refer to Table 2. CD1, CD2 Card Detect When card detect 1 and 2 = ground the system detects the card. CE1, CE2 Card Enable This input is active low. The memory card is deselected and power consumption is reduced to standby levels when CE is high. CE activates the internal memory card circuitry that controls the high and low byte control logic of the card, input buffers segment decoders, and associated memory devices. D0–D15 Data Input/Output Data inputs are internally latched on write cycles. Data outputs during read cycles. Data pins are active high. When the memory card is deselected or the outputs are disabled the outputs float to tristate. GND Ground NC No Connect Corresponding pin is not connected internally to the die. OE Output Enable This input is active low and enables the data buffers through the card outputs during read cycles. REG Attribute Memory Select This input is active low and enables reading the CIS from the EEPROM. VCC PC Card Power Supply For device operation (5.0 V ± 5%). WE Write Enable This input is active low and controls the write function of the command register to the memory array. The 5/4/98 AmC0XXCFLKA 5 Word-Wide Operations The “C” series cards provide the flexibility to operate on data in a byte-wide or word-wide format. In word-wide operations the Low-bytes are controlled with CE1 when A0 = 0. The High-bytes are controlled with CE2 with A0 = don’t care. Table 1. Common Memory Bus Operations Pins/Operation READ-ONLY Read (x8) (Note 6) Read (x8) (Note 7) Read (x8) (Note 8) Read (x16) (Note 9) Output Disable Standby (Note 3) READ/WRITE Read (x8) (Notes 2, 6) Read (x8) (Notes 2, 7) Read (x8) (Notes 2, 8) Read (x16) (Notes 2, 9) Write (x8) (Notes 4, 6) Write (x8) (Notes 4, 7) Write (x8) (Notes 4, 8) Write (x16) (Notes 5, 9) Output Disable Standby (Note 3) VIH VIH VIH VIH VIH VIH VIH VIH VIH X VIH VIH VIL VIL VIH VIH VIL VIL X VIH VIL VIL VIH VIL VIL VIL VIH VIL X VIH VIL VIL VIL VIL VIH VIH VIH VIH VIH X VIH VIH VIH VIH VIL VIL VIL VIL VIL X VIL VIH X X VIL VIH X X X X High-Z High-Z Data Out-Odd Data Out-Odd High-Z High-Z Data In-Odd Data In-Odd High-Z High-Z Data Out-Even Data Out-Odd High-Z Data Out-Even Data In-Even Data In-Odd High-Z Data In-Even High-Z High-Z VIH VIH VIH VIH VIH X VIH VIH VIL VIL X VIH VIL VIL VIH VIL X VIH VIL VIL VIL VIL VIH X VIH VIH VIH VIH VIH X VIL VIH X X X X High-Z High-Z Data Out-Odd Data Out-Odd High-Z High-Z Data Out-Even Data Out-Odd High-Z Data Out-Even High-Z High-Z REG CE2 CE1 OE WE A0 D8–D15 D0–D7 Legend: X = Don’t Care, where Don’t Care is either at VIL or VIH level. See DC Characteristics for voltage levels of normal TTL or CMOS input levels. Volt-only? Notes: 1. VPP pins are not connected in the 5.0 V-Only Flash Memory Card. 2. Manufacturer and device codes may be accessed via a command register write sequence. (Refer to Autoselect Command in Tables 3 and 4.) 3. Standby current is ICCS. 4. Refer to Tables 3 and 4 for valid DIN during a byte write operation. 5. Refer to Table 5 for valid DIN during a word write operation. 6. Byte access—Even. In this x8 mode, A0 = VIL outputs or inputs the “even” byte (low byte) of the x16 word on D0–D7. 7. Byte access—Odd. In this x8 mode, A0 = VIH outputs or inputs the “odd” byte (high byte) of the x16 word on D0–D7. This is accomplished internal to the card by transposing D8–D15 to D0–D7. 8. Odd byte only access. In this x8 mode, A0 = X outputs or inputs the “odd” byte (high byte) of the x16 word on D8–D15. 9. x16 word accesses present both “even” (low) and “odd” (high) bytes. A0 = X. 6 AmC0XXCFLKA 5/4/98 Table 2. Pins/Operation READ-ONLY Read (x8) (Notes 2, 4) Read (x8) (Notes 3, 4) Read (x8) (Note 3) Read (x16) (Notes 3, 4, 5) Output Disable Standby (Note 6) READ/WRITE Read (x8) (Notes 2, 4) Read (x8) (Notes 3, 4) Read (x8) (Note 4) Read (x16) (Note 4) Write (x8) (Notes 2, 5) Write (x8) (Note 5) Write (x8) (Notes 4, 5) Write (x16) (Note 5) Output Disable Standby (Note 6) VIL VIL VIL VIL VIL VIL VIL VIL VIL X VIL VIL VIL VIL VIL X REG Attribute Memory Bus Operations CE2 CE1 OE WE A0 D8–D15 D0–D7 VIH VIH VIL VIL X VIH VIL VIL VIH VIL X VIH VIL VIL VIL VIL VIH X VIH VIH VIH VIH VIH X VIL VIH X X X X High-Z High-Z Not Valid Not Valid High-Z High-Z Data Out-Even Not Valid High-Z Data Out-Even High-Z High-Z VIH VIH VIL VIL VIH VIH VIL VIL X VIH VIL VIL VIH VIL VIL VIL VIH VIL X VIH VIL VIL VIL VIL VIH VIH VIH VIH VIH X VIH VIH VIH VIH VIL VIL VIL VIL VIL X VIL VIH X X VIL VIH X X X X High-Z High-Z Not Valid Not Valid High-Z High-Z High-Z High-Z High-Z High-Z Data Out-Even Not Valid High-Z Data Out-Even Data In-Even High-Z High-Z Data In-Even High-Z High-Z Legend: X = Don’t Care, where Don’t Care is either VIL or VIH levels. See DC Characteristics for voltage levels of normal TTL or CMOS input levels. Volt-only? Notes: 1. VPP pins are not connected in the 5.0 V-Only Flash Memory Card. 2. In this x8 mode, A0 = VIL outputs or inputs the “even” byte (low byte) of the x16 word on D0–D7. 3. Only even-byte data is valid during Attribute Memory Read function. 4. During Attribute Memory Read function, REG and OE must be active for the entire cycle. 5. During Attribute Memory Write function, REG and WE must be active for the entire cycle, OE must be inactive for the entire cycle. 6. Standby current is ICCS. 5/4/98 AmC0XXCFLKA 7 Byte-Wide Operations Byte-wide data is available on D0–D7 for read and write operations (CE 1 = low, CE 2 = high). Even and odd bytes are stored in separate memory segments (i.e., S0 and S1) and are accessed when A0 is low and high respectively. The even byte is the low order byte and the odd byte is the high order byte of a 16-bit word. Erase operations in the byte-wide mode must account for data multiplexing on D0–D7 by changing the state of A0. Each memory sector or memory segment pair must be addressed separately for erase operations. Read Characteristics and Waveforms for the specific timing parameters. Output Disable Data outputs from the card are disabled when OE is at a logic-high level. Under this condition, outputs are in the high-impedance state. Standby Operations Byte-wide read accesses only require half of the read/ write output buffer (x16) to be active. In addition, only one memory segment is active within either the high order or low order bank. Activation of the appropriate half of the output buffer is controlled by the combination of both CE pins. The CE pins also control power to the high and low-order banks of memory. Outputs of the memory bank not selected are placed in the high impedance state. The individual memory segment is activated by the address decoders. The other memory segments operate in standby. An active memory segment continues to draw power until completion of a write or erase operation if the card is deselected in the process of one of these operations. Card Detection Each CD (output) pin should be read by the host system to determine if the memory card is adequately seated in the socket. CD1 and CD2 are internally tied to ground. If both bits are not detected, the system should indicate that the card must be reinserted. Write Protection The AMD Flash memory card has three types of write protection. The PCMCIA/JEIDA socket itself provides the first type of write protection. Power supply and control pins have specific pin lengths in order to protect the card with proper power supply sequencing in the case of hot insertion and removal. A mechanical write protect switch provides a second type of write protection. When this switch is activated, WE is internally forced high. The Flash memory command register is disabled from accepting any write commands. The third type of write protection is achieved with VCC1 and VCC2 below VLKO. Each Flash memory device that comprises a Flash memory segment will reset the command register to the read-only mode when V CC i s below VLKO. VLKO is the voltage below which write operations to individual command registers are disabled. Auto Select Operation A host system or external card reader/writer can determine the on-card manufacturer and device I.D. codes. Codes are available after writing the 90H command to the command register of a memory segment per Tables 3 and 4. Reading from address location 00000H in any segment provides the manufacturer I.D. while address location 00002H provides the device I.D. To terminate the Auto Select operation, it is necessary to write the Read/Reset command sequence into the register. Write Operations Write and erase operations are valid only when VCC1 and VCC2 are above 4.75 V. This activates the state machine of an addressed memory segment. The command register is a latch which saves address, commands, and data information used by the state machine and memory array. When Write Enable (WE) and appropriate CE(s) are at a logic-level low, and Output Enable (OE ) is at a logic-high, the command register is enabled for write operations. The falling edge of WE latches address information and the rising edge latches data/command information. Write or erase operations are performed by writing appropriate data patterns to the command register of accessed Flash memory sectors or memory segments. The byte-wide and word-wide commands are defined in Tables 3, 4, and 5, respectively. MEMORY CARD BUS OPERATIONS Read Enable Two Card Enable (CE) pins are available on the memor y card. Both CE p ins must be active low for word-wide read accesses. Only one CE is required for byte-wide accesses. The CE pins control the selection and gates power to the high and low memory segments. The Output Enable (OE ) controls gating accessed data from the memory segment outputs. The device will automatically power-up in the read/ reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC 8 AmC0XXCFLKA 5/4/98 Table 3. Even Byte Command Definitions (Note 5) Embedded Command Sequence Reset/Read Autoselect Byte Write Segment Erase Sector Erase Bus Write Cycles Req’d 4 4 4 6 6 First Bus Write Cycle Addr* Second Bus Write Cycle Third Bus Write Cycle Addr* Data Fourth Bus Read/Write Cycle Addr* RA Data RD Fifth Bus Write Cycle Addr* Data Sixth Bus Write Cycle Addr* Data Data Addr* Data AAAAH AAH 5554H 55H AAAAH F0H AAAAH AAH 5554H 55H AAAAH 90H 00H/02H 01H/A4H AAAAH AAH 5554H 55H AAAAH A0H AAAAH AAH 5554H 55H AAAAH 80H AAAAH AAH 5554H 55H AAAAH 80H PA AAAAH AAAAH PD AAH AAH 5554H 55H AAAAH 10H 5554H 55H SA 30H Sector Erase Suspend Sector Erase Resume Erase can be suspended during sector erase with Addr (don’t care), Data (B0H) Erase can be resumed after suspend with Addr (don’t care), Data (30H) * Address for Memory Segment 0 (S0) only. Address for the higher even memory segments (S2–S18) = (Addr) + (N/2)* 100000H where N = Memory Segment number (0) for 1 Mbyte, N = (0, 2) for 2 Mbyte, N = (0, 2, 4, 6) for 4 Mbyte, N = (0…18) for 10 Mbyte. Notes: 1. Address bit A16 = X = Don’t Care for all address commands except for Program Address (PA), Read Address (RA) and Sector Address (SA). 2. Bus operations are defined in Table 1. 3. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A17, A18, A19 will uniquely select any sector of a segment. To select the memory segment:1 and 2 Mbyte: Use CE1 and A20 4 Mbyte: Use CE1 and A20, A21 10 Mbyte: Use CE1 and A20–A23. 4. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE pulse. 5. A0 = 0 and CE1 = 0 5/4/98 AmC0XXCFLKA 9 Table 4. Embedded Command Sequence Reset/Read Autoselect Byte Write Segment Erase Sector Erase Bus Write Cycles Req’d 4 4 4 6 6 First Bus Write Cycle Addr* Odd Byte Command Definitions (Note 5) Second Bus Write Cycle Third Bus Write Cycle Addr* Data Fourth Bus Read/Write Cycle Addr* RA Data RD Fifth Bus Write Cycle Addr* Data Sixth Bus Write Cycle Addr* Data Data Addr* Data AAABH AAH 5555H 55H AAABH F0H AAABH AAH 5555H 55H AAABH 90H 00H/02H 01H/A4H AAABH AAH 5555H 55H AAABH A0H AAABH AAH 5555H 55H AAABH 80H AAABH AAH 5555H 55H AAABH 80H PA AAABH AAABH PD AAH AAH 5555H 55H AAABH 10H 5555H 55H SA 30H Sector Erase Suspend Sector Erase Resume Erase can be suspended during sector erase with Addr (don’t care), Data (B0H) Erase can be resumed after suspend with Addr (don’t care), Data (30H) *Address for Memory Segment 1 (S1) only. Address for the higher odd memory segments (S3–S19) = (Addr) + ((N–1)/2)* 100000H + 80000H where N = Memory Segment number (1) for 1 Mbyte, N = (1, 3) for 2 Mbyte, N = (1, 3, 5, 7) for 4 Mbyte, N = (1…19) for 10 Mbyte. Notes: 1. Address bit A16 = X = Don’t Care for all address commands except for Program Address (PA), Read Address (RA) and Sector Address (SA). 2. Bus operations are defined in Table 1. 3. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A17, A18, A19 will uniquely select any sector of a segment. To select the memory segment:1 and 2 Mbyte: Use CE2 and A20 4 Mbyte: Use CE2 and A20, A21 10 Mbyte: Use CE2 and A20–A23. 4. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE pulse. 5. A0 = 1 and CE1 = 0 or A0 = X and CE2 = 0. 10 AmC0XXCFLKA 5/4/98 Table 5. Word Command Definitions (Note 7) Embedded Command Sequence Reset/Read Autoselect Byte Write Segment Erase Sector Erase Bus Write Cycles Req’d 4 4 4 6 6 First Bus Write Cycle Addr* Data Second Bus Write Cycle Addr* Data Third Bus Write Cycle Addr* Data Fourth Bus Read/Write Cycle Addr* RA Data RW 0101/ A4A4 PW AAAA AAAA 5554H 5555 AAAAH 1010 5554H 5555 SA 3030 Fifth Bus Write Cycle Addr* Data Sixth Bus Write Cycle Addr* Data AAAAH AAAA 5554H 5555 AAAAH F0F0 AAAAH AAAA 5554H 5555 AAAAH 9090 00H/02H AAAAH AAAA 5554H 5555 AAAAH A0A0 AAAAH AAAA 5554H 5555 AAAAH 8080 AAAAH AAAA 5554H 5555 AAAAH 8080 PA AAAAH AAAAH Sector Erase Suspend Sector Erase Resume Erase can be suspended during sector erase with Addr (don’t care), Data (B0H) Erase can be resumed after suspend with Addr (don’t care), Data (30H) Notes: 1. Address bit A16 = X = Don’t Care for all address commands except for Program Address (PA) and Sector Address (SA). 2. Bus operations are defined in Table 1. 3. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A17, A18, A19 will uniquely select any sector of a segment. To select the memory segment:1 and 2 Mbyte: Use CE1, CE2, A20 4 Mbyte: Use CE1, CE2, A20, A21 0 Mbyte: Use CE1, CE2, A20–A23. 4. RW = Data read from location RA during read operation. (Word Mode). PW = Data to be programmed at location PA. Data is latched on the rising edge of WE. (Word Mode). 5. Address for Memory Segment Pair 0 (S0 and S1) only. Address for the higher Memory Segment Pairs (S2, S3 = Pair 1, S4, S5 = Pair 2, S6, S7 = Pair 3…) is equal to (Addr) + M* (80000H) where M = Memory Segment Pair number. 6. Word = 2 bytes = odd byte and even byte. 7. CE1 = 0 and CE2 = 0. Table 6. Memory Sector Address Table for Memory Segment S0 Sector 0 1 2 3 4 5 6 7 A19 0 0 0 0 1 1 1 1 A18 0 0 1 1 0 0 1 1 A17 0 1 0 1 0 1 0 1 Address Range 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh FLASH MEMORY WRITE/ERASE OPERATIONS Details of AMD’s Embedded Write and Erase Operations Embedded Erase™ Algorithm The automatic memory sector or memory segment erase does not require the device to be entirely preprogramming prior to executing the Embedded Erase command. Upon executing the Embedded Erase command sequence, the addressed memory sector or memory segment will automatically write and verify the entire memory segment or memory sector for an all “zero” data pattern. The system is not required to provide any controls or timing during these operations. When the memory sector or memory segment is automatically verified to contain an all “zero” pattern, a self-timed chip erase-and-verify begins. The erase and verify operations are complete when the data on D7 of the memory sector or memory segment is “1” (see “Write Operation Status” section) at which time the Note: A0 is not mapped internally. 5/4/98 AmC0XXCFLKA 11 device returns to the Read mode (D15 on the odd byte). The system is not required to provide any control or timing during these operations. A Reset command after the device has begun execution will stop the device but the data in the operated segment will be undefined. In that case, restart the erase on that sector and allow it to complete. When using the Embedded Erase algorithm, the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verify command is required). The margin voltages are internally generated in the same manner as when the standard erase verify command is used. The Embedded Erase command sequence is a command only operation that stages the memory sector or memory segment for automatic electrical erasure of all bytes in the array. The automatic erase begins on the rising edge of the WE and terminates when the data on D7 of the memory sector or memory segment is “1” (see “Write Operation Status” section) at which time the device returns to the Read mode. Please note that for the memory segment or memory sector erase operation, Data Polling may be performed at any address in that segment or sector. Figure 1 and Table 7 illustrate the Embedded Erase Algorithm, a typical command string and bus operations. Table 7. Embedded Erase Algorithm Bus Operation Standby Write Read Embedded Erase command sequence Command Comments Wait for VCC ramp 6 bus cycle operation Data Polling to verify erasure As described earlier, once the memory sector in a device or memory segment completes the Embedded Erase operation it returns to the Read mode and addresses are no longer latched. Therefore, the device requires that a valid address input to the device is supplied by the system at this particular instant of time. Otherwise, the system will never read a “1” on D7. A system designer has two choices to implement the Embedded Erase algorithm: 1. The system (CPU) keeps the sector address (within any of the sectors being erased) valid during the entire Embedded Erase operation, or 2. Once the system executes the Embedded Erase command sequence, the CPU takes away the address from the device and becomes free to do other tasks. In this case, the CPU is required to keep track of the valid sector address by loading it into a temporary register. When the CPU comes back for performing Data Polling, it should reassert the same address. Since the Embedded Erase operation takes a significant amount of time (1.5–30 s), option 2 makes more sense. However, the choice of these two options has been left to the system designer. Sector Erase Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the sector erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE , while the command (data) is latched on the rising edge of WE . A time-out of 100 µs from the rising edge of the last sector erase command will initiate the sector erase command(s). Multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. This sequence is followed with writes of the sector erase command 30H to addresses in other sectors desired to be concurrently erased. A time-out of 100 µs from the rising edge of the WE pulse for the last sector erase command will initiate the sector erase. If another sector erase command is written within the 100 µs time-out window the timer is reset. Any command other than sector erase within the time-out window will reset the device to the read mode, ignoring the previous command string (refer to “Write Operation Status” section for Sector Erase Timer operation). Loading the sector erase buffer may be done in any sequence and with anysector number. Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector Start Write Embedded Erase Command Sequence (Table 3 and 4) Data Poll from Device (Figure 3) Erasure Complete 18723C-2 Figure 1. Embedded Erase Algorithm 12 AmC0XXCFLKA 5/4/98 or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. A Reset command after the device has begun execution will stop the device but the data in the operated segment will be undefined. In that case, restart the erase on that sector and allow it to complete. The automatic sector erase begins after the 100 µs time out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on D7 is “1” (see “Write Operation Status” section) at which time the device returns to read mode. Data Polling must be performed at an address within any of the sectors being erased. Figure 1 illustrates the Embedded Erase Algorithm using typical command strings and bus operations. temporary register. When the CPU comes back for performing Data Polling, it should reassert the same address. However, since the Embedded Programming operation takes only 16 µs typically, it may be easier for the CPU to keep the address stable during the entire Embedded Programming operation instead of reasserting the valid address during Data Polling. Anyway, this has been left to the system designer’s choice to go for either operation. Any commands written to the segment during this period will be ignored. Figure 2 and Table 8 illustrate the Embedded Program Algorithm, a typical command string, and bus operation. Table 8. Embedded Program Algorithm Bus Operation Standby Write Write Read Embedded Program command sequence Program Address/Data Command Comments Wait for VCC ramp 3 bus cycle operation 1 bus cycle operation Data Polling to verify program Embedded Program™ Algorithm The Embedded Program Setup is a four bus cycle operation that stages the addressed memory sector or memory segment for automatic programming. Once the Embedded Program Setup operation is performed, the next WE pulse causes a transition to an active programming operation. Addresses are internally latched on the falling edge of the WE pulse. Data is internally latched on the rising edge of the WE pulse. The rising edge of WE also begins the programming operation. The system is not required to provide further control or timing. The device will automatically provide an adequate internally generated write pulse and verify margin. The automatic programming operation is completed when the data on D7 of the addressed memory sector or memory segment is equivalent to data written to this bit (see Write Operation Status section) at which time the device returns to the Read mode (no write verify command is required). Addresses are latched on the falling edge of WE during the Embedded Program command execution and hence the system is not required to keep the addresses stable during the entire Programming operation. However, once the device completes the Embedded Program operation, it returns to the Read mode and addresses are no longer latched. Therefore, the device requires that a valid address input to the device is supplied by the system at this particular instant of time. Otherwise, the system will never read a valid data on D7. A system designer has two choices to implement the Embedded Programming algorithm: 1. The system (CPU) keeps the address valid during the entire Embedded Programming operation, or 2. Once the system executes the Embedded Programming command sequence, the CPU takes away the address from the device and becomes free to do other tasks. In this case, the CPU is required to keep track of the valid address by loading it into a Reset Command The Reset command initializes the sector or segment to the read mode. Please refer to Tables 3 and 4, “Byte Command Definitions,” and Table 5, “Word Command Definitions” for the Reset command operation. The sector or segment remains enabled for reads until the command register contents are altered. There is a 6 µs Write Recovery Time before Read for the first read after a write. The Reset command will safely reset the segment memory to the Read mode. Memory contents are not altered. Following any other command, write the Reset command once to the segment. This will safely abort any operation and reset the device to the Read mode. The Reset is needed to terminate the auto select operation. It can be used to terminate an Erase or Sector Erase operation, but the data in the sector or segment being erased would then be undefined. Write Operation Status Data Polling—D7 (D15 on Odd Byte) The Flash Memory PC Card features Data Polling as a method to indicate to the host system that the Embedded algorithms are either in progress or completed. While the Embedded Programming algorithm is in operation, an attempt to read the device will produce the complement of expected valid data on D7 of the addressed memory sector or memory segment. Upon 5/4/98 AmC0XXCFLKA 13 Start Write Embedded Write Command Sequence per Table 3 or 4 Data Poll Device Verify Byte Yes No Last Address Yes Completed No Increment Address 18723C-3 Figure 2. Embedded Programming Algorithm in Byte-Wide Mode Toggle Bit—D6 (D14 on Odd Byte) The Flash Memory PC Card also features a “Toggle Bit” as a method to indicate to the host system that the Embedded algorithms are either in progress or have been completed. While the Embedded Program or Erase algorithm is in progress, successive attempts to read data from the device will result in D6 toggling between one and zero. Once the Embedded Program or Erase algorithm is completed, D6 will stop toggling and valid data on D0–D7 will be read on the next successive read attempt. The Toggle bit is also used for entering Erase Suspend mode. Please refer to the section entitled “Sector Erase Suspend.” Please note that even if the device completes the Embedded algorithm operation and D6 stops toggling, data bits D0–D7 (including D6) may not be valid during the current bus cycle. This may happen since the internal circuitry may be switching from status mode to the Read mode. There is a time delay associated with this mode switching. Since this time delay is always less than tOE (OE access time), the next successive read attempt (OE going low) will provide the valid data on D0D7. Also note that once the D6 bit has stopped toggling and the output enable OE is held low thereafter (without toggling) the data bits (D0–D7) will be valid after tOEtime delay. See Figures 4 and 6 for the Data Polling diagram and timing specifications. completion of the Embedded Program algorithm an attempt to read the device will produce valid data on D7. The Data Polling feature is valid after the rising edge of the fourth WE pulse of the four write pulse sequence. While the Embedded Erase algorithm is in operation, D7 will read “0” until the erase operation is completed. Upon completion of the erase operation, the data on D7 will read “1”. The Data Polling feature is only active during the Embedded Programming or Erase algorithms. Please note that the AmC0XXCFLKA data pin (D7) may change asynchronously while Output Enable (OE) is asserted low. This means that the device is driving status information on D7 at one instant of time and then the byte’s valid data at the next instant of time. Depending on when the system samples the D7 output, it may read either the status or valid data. Even if the device has completed the Embedded operation and D7 has a valid data, the data outputs on D0–D6 may be still invalid since the switching time for data bits (D0–D7) will not be the same. This happens since the internal delay paths for data bits (D0–D7) within the device are different. The valid data will be provided only after a certain time delay (