BS640HD8V

Am29BDS128H/Am29BDS640H Data Sheet ( RETIRED PRODUCT (AM29BDS40H ONLY) The Am29BDS640H has been retired and is not recommended for designs. For new designs, S29WS064K supersedes Am29BDS640H. Please refer to the S29WS-K family data sheet for specifications and ordering information. The Am29BDS128H is available and is not affected by this revision. The following document contains information on Spansion memory products. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support the Am29BDS640H part numbers. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Publication Number 27024 Revision B Amendment 3 Issue Date May 10, 2006 THIS PAGE LEFT INTENTIONALLY BLANK. DATA SHEET Am29BDS128H/Am29BDS640H 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory The Am29BDS640H has been retired and is not recommended for designs. For new designs, S29WS064K supersedes Am29BDS640H. Please refer to the S29WS-K family data sheet for specifications and ordering information. The Am29BDS128H is available and is not affected by this revision. DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES ■ ■ ■ Single 1.8 volt read, program and erase (1.65 to 1.95 volt) Manufactured on 0.13 µm process technology VersatileIO™ (VIO) Feature — Device generates data output voltages and tolerates data input voltages as determined by the voltage on the VIO pin — 1.8V compatible I/O signals Simultaneous Read/Write operation — Data can be continuously read from one bank while executing erase/program functions in other bank — Zero latency between read and write operations — Four bank architecture: 128 Mb has 16/48/48/16 Mbit banks 64 Mb has 8/24/24/8 Mbit banks Programable Burst Interface — 2 Modes of Burst Read Operation — Linear Burst: 8, 16, and 32 words with wrap-around — Continuous Sequential Burst SecSiTM (Secured Silicon) Sector region — Up to 128 words accessible through a command sequence — Up to 64 factory-locked words — Up to 64 customer-lockable words Sector Architecture — Banks A and D each contain both 4 Kword sectors and 32 Kword sectors; Banks B and C contain ninety-six 32 Kword sectors — Sixteen 4 Kword boot sectors Half of the boot sectors are at the top of the address range; half are at the bottom of address range Minimum 1 million erase cycle guarantee per sector 20-year data retention at 125°C — Reliable operation for the life of the system 80-ball FBGA package (128 Mb) or 64-ball FBGA (64 Mb) package ■ HARDWARE FEATURES ■ Handshaking feature — Provides host system with minimum possible latency by monitoring RDY — Reduced Wait-state handshaking option further reduces initial access cycles required for burst accesses beginning on even addresses ■ ■ Hardware reset input (RESET#) — Hardware method to reset the device for reading array data WP# input — Write protect (WP#) function allows protection of the four highest and four lowest 4 kWord boot sectors, regardless of sector protect status Persistent Sector Protection — A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector — Sectors can be locked and unlocked in-system at VCC level Password Sector Protection — A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password ACC input: Acceleration function reduces programming time; all sectors locked when ACC = VIL CMOS compatible inputs, CMOS compatible outputs Low VCC write inhibit ■ ■ ■ ■ ■ ■ ■ ■ SOFTWARE FEATURES ■ ■ Supports Common Flash Memory Interface (CFI) Software command set compatible with JEDEC 42.4 standards — Backwards compatible with Am29F and Am29LV families Data# Polling and toggle bits — Provides a software method of detecting program and erase operation completion Erase Suspend/Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences Burst Suspend/Resume — Suspends a burst operation to allow system use of the address and data bus, than resumes the burst at the previous state Publication# 27024 Rev: B Amendment: 3 Issue Date: May 10, 2006 ■ ■ ■ ■ PERFORMANCE CHARCTERISTICS ■ Read access times at 75/66/54 MHz (CL=30 pF) — Burst access times of 9.3/11/13.5 ns at industrial temperature range — Synchronous latency of 49/56/69 ns — Asynchronous random access times of 45/50/55 ns Power dissipation (typical values, CL = 30 pF) — Burst Mode Read: 10 mA — Simultaneous Operation: 25 mA — Program/Erase: 15 mA — Standby mode: 0.2 µA ■ ■ ■ ■ DATA SHEET GENERAL DESCRIPTION The Am29BDS128H/Am29BDS640H is a 128 or 64 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory device, organized as 8,388,608 or 4,194,304 words of 16 bits each. This device uses a single VCC of 1.65 to 1.95 V to read, program, and erase the memory array. A 12.0-volt VHH on ACC may be used for faster program performance if desired. The device can also be programmed in standard EPROM programmers. At 75 MHz, the device provides a burst access of 9.3 ns at 30 pF with a latency of 49 ns at 30 pF. At 66 MHz, the device provides a burst access of 11 ns at 30 pF with a latency of 56 ns at 30 pF. At 54 MHz, the device provides a burst access of 13.5 ns at 30 pF with a latency of 69ns at 30 pF. The device operates within the industrial temperature range of -40°C to +85°C. The device is offered in FBGA packages. The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The device is divided as shown in the following table: Quantity Bank A 31 B C D 8 8 4 Kwords 96 96 31 15 48 48 15 32 Kwords 32 Kwords 32 Kwords 32 Kwords 128 Mb 8 64 Mb 8 Size 4 Kwords The clock polarity feature provides system designers a choice of active clock edges, either rising or falling. The active clock edge initiates burst accesses and determines when data will be output. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The h ardware RESET# pin t erminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory device. The host system can detect whether a program or erase operation is complete by using the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The device also offers two types of data protection at the sector level. When at VIL, WP# locks the four highest and four lowest boot sectors. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. AMD Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection. The VersatileIO™ (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VIO pin. The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to control asynchronous read and write operations. For burst operations, the device additionally requires Ready (RDY), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/microcontrollers for high performance read operations. The burst read mode feature gives system designers flexibility in the interface to the device. The user can preset the burst length and wrap through the same memory space, or read the flash array in continuous mode. 2 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram of Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7 Special Handling Instructions for FBGA Package .................... 8 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 9 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 11 Table 1. Device Bus Operations ....................................................11 Low VCC Write Inhibit .............................................................. 24 Write Pulse “Glitch” Protection ................................................ 24 Logical Inhibit .......................................................................... 24 Power-Up Write Inhibit ............................................................ 24 Table 8. CFI Query Identification String ......................................... 24 Table 9. System Interface String .................................................... 25 Table 10. Device Geometry Definition ........................................... 25 Table 11. Primary Vendor-Specific Extended Query ..................... 26 Table 12. Am29BDS128H Sector Address Table .......................... 27 Table 13. Am29BDS640H Sector Address Table .......................... 31 Requirements for Asynchronous Read Operation (Non-Burst) ............................................................ 11 Requirements for Synchronous (Burst) Read Operation ........ 11 8-, 16-, and 32-Word Linear Burst with Wrap Around ............ 12 Table 2. Burst Address Groups .......................................................12 Command Definitions . . . . . . . . . . . . . . . . . . . . . 33 Reading Array Data ................................................................ 33 Set Configuration Register Command Sequence ................... 33 Figure 3. Synchronous/Asynchronous State Diagram ................... 33 Read Mode Setting ................................................................. 33 Programmable Wait State Configuration ................................ 33 Table 14. Programmable Wait State Settings ................................ 34 Burst Suspend/Resume .......................................................... 12 Configuration Register ............................................................ 13 Reduced Wait-state Handshaking Option .............................. 13 Simultaneous Read/Write Operations with Zero Latency ....... 13 Writing Commands/Command Sequences ............................ 13 Accelerated Program Operation ............................................. 14 Autoselect Mode ..................................................................... 14 Table 3. Autoselect Codes (High Voltage Method) ........................15 Table 4. Am29BDS128H Boot Sector/Sector Block Addresses for Protection/Unprotection ........................................................................16 Table 5. Am29BDS640H Boot Sector/Sector Block Addresses for Protection/Unprotection ........................................................................17 Reduced Wait-state Handshaking Option ............................... 34 Table 15. Wait States for Reduced Wait-state Handshaking ........ 34 Standard Handshaking Option ................................................ 35 Table 16. Wait States for Standard Handshaking .......................... 35 Read Mode Configuration ....................................................... 35 Table 17. Read Mode Settings ....................................................... 35 Burst Active Clock Edge Configuration ................................... 35 RDY Configuration .................................................................. 35 Table 18. Configuration Register ................................................... 36 Reset Command ..................................................................... 36 Autoselect Command Sequence ............................................ 36 Table 19. Autoselect Data .............................................................. 37 Sector/Sector Block Protection and Unprotection .................. 17 Sector Protection .................................................................... 17 Selecting a Sector Protection Mode ....................................... 17 Persistent Sector Protection ................................................... 18 Persistent Protection Bit (PPB) ............................................... 18 Persistent Protection Bit Lock (PPB Lock) ............................. 18 Dynamic Protection Bit (DYB) ................................................ 18 Table 6. Sector Protection Schemes ...............................................19 Enter SecSi™ Sector/Exit SecSi Sector Command Sequence .............................................................. 37 Program Command Sequence ............................................... 37 Unlock Bypass Command Sequence ..................................... 37 Figure 4. Program Operation ......................................................... 38 Persistent Sector Protection Mode Locking Bit ...................... 19 Password Protection Mode ..................................................... 19 Password and Password Mode Locking Bit ........................... 20 64-bit Password ...................................................................... 20 Persistent Protection Bit Lock ................................................. 20 High Voltage Sector Protection .............................................. 20 Standby Mode ........................................................................ 20 Automatic Sleep Mode ........................................................... 21 RESET#: Hardware Reset Input ............................................. 21 Output Disable Mode .............................................................. 21 Figure 1. Temporary Sector Unprotect Operation........................... 21 Figure 2. In-System Sector Protection/ Sector Unprotection Algorithms ...................................................... 22 Chip Erase Command Sequence ........................................... 38 Sector Erase Command Sequence ........................................ 38 Erase Suspend/Erase Resume Commands ........................... 39 Figure 5. Erase Operation.............................................................. 40 Password Program Command ................................................ 40 Password Verify Command .................................................... 40 Password Protection Mode Locking Bit Program Command .. 40 Persistent Sector Protection Mode Locking Bit Program Command ....................................................................................... 40 SecSi Sector Protection Bit Program Command .................... 41 PPB Lock Bit Set Command ................................................... 41 DYB Write Command ............................................................. 41 Password Unlock Command .................................................. 41 Figure 6. PPB Program Algorithm.................................................. 42 SecSi™ (Secured Silicon) Sector Flash Memory Region ............................................................ 23 Factory-Locked Area (64 words) ............................................ 23 Table 7. SecSiTM Sector Addresses ...............................................23 PPB Program Command ........................................................ 43 All PPB Erase Command ........................................................ 43 Figure 7. PPB Erase Algorithm ...................................................... 44 Customer-Lockable Area (64 words) ...................................... 23 SecSi Sector Protection Bits ................................................... 23 Hardware Data Protection ...................................................... 23 Write Protect (WP#) ................................................................ 24 DYB Write Command ............................................................. 45 PPB Status Command ............................................................ 45 PPB Lock Bit Status Command .............................................. 45 DYB Status Command ............................................................ 45 Command Definitions ............................................................. 46 Table 20. Memory Array Command Definitions ............................ 46 Table 21. Sector Protection Command Definitions ....................... 47 May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 3 DATA Write Operation Status . . . . . . . . . . . . . . . . . . . . . 48 DQ7: Data# Polling ................................................................. 48 Figure 8. Data# Polling Algorithm ................................................... 48 SHEET cess................................................................................................ 63 Figure 27. Standard Handshake Burst Suspend at Address 3Fh (Starting Address 3Dh or Earlier)............................................................ 64 Figure 28. Standard Handshake Burst Suspend at Address 3Eh/3Fh (Without a Valid Initial Access)....................................................... 64 Figure 29. Standard Handshake Burst Suspend at Address 3Eh/3Fh (with 1 Access CLK)....................................................................... 65 Figure 30. Read Cycle for Continuous Suspend............................ 65 DQ6: Toggle Bit I .................................................................... 49 Figure 9. Toggle Bit Algorithm......................................................... 50 DQ2: Toggle Bit II ................................................................... 50 Table 22. DQ6 and DQ2 Indications ...............................................51 Reading Toggle Bits DQ6/DQ2 .............................................. 51 DQ5: Exceeded Timing Limits ................................................ 51 DQ3: Sector Erase Timer ....................................................... 51 Table 23. Write Operation Status ....................................................52 Asynchronous Mode Read .................................................... 66 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 31. Asynchronous Mode Read with Latched Addresses .... 67 Figure 32. Asynchronous Mode Read............................................ 67 Figure 33. Reset Timings ............................................................... 68 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 53 Figure 10. Maximum Negative Overshoot Waveform ..................... 53 Figure 11. Maximum Positive Overshoot Waveform....................... 53 Erase/Program Operations ..................................................... 69 Figure 34. Asynchronous Program Operation Timings: AVD# Latched Addresses ...................................................................................... 70 Figure 35. Asynchronous Program Operation Timings: WE# Latched Addresses ...................................................................................... 71 Figure 36. Synchronous Program Operation Timings: WE# Latched Addresses ...................................................................................... 72 Figure 37. Synchronous Program Operation Timings: CLK Latched Addresses ...................................................................................... 73 Figure 38. Chip/Sector Erase Command Sequence ...................... 74 Figure 39. Accelerated Programming Timing................................. 75 Figure 40. Data# Polling Timings (During Embedded Algorithm) .. 76 Figure 41. Toggle Bit Timings (During Embedded Algorithm)........ 76 Figure 42. Synchronous Data Polling Timings/Toggle Bit Timings 77 Figure 43. DQ2 vs. DQ6................................................................. 77 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 53 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 54 CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . 54 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 12. Test Setup...................................................................... 55 Table 24. Test Specifications ..........................................................55 Key to Switching Waveforms . . . . . . . . . . . . . . . 55 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 55 Figure 13. Input Waveforms and Measurement Levels .................. 55 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 56 VCC Power-up ......................................................................... 56 Figure 14. VCC Power-up Diagram ................................................. 56 CLK Characterization ............................................................. 56 Figure 15. CLK Characterization..................................................... 56 Temporary Sector Unprotect .................................................. 78 Figure 44. Temporary Sector Unprotect Timing Diagram .............. Figure 45. Sector/Sector Block Protect and Unprotect Timing Diagram ............................................................. Figure 46. Latency with Boundary Crossing .................................. Figure 47. Latency with Boundary Crossing into Program/Erase Bank ............................................................... Figure 48. Example of Wait States Insertion.................................. Figure 49. Back-to-Back Read/Write Cycle Timings ...................... 78 79 80 81 82 83 Synchronous/Burst Read ....................................................... 57 Figure 16. CLK Synchronous Burst Mode Read (rising active CLK) ... .........................................................................................................58 Figure 17. CLK Synchronous Burst Mode Read (Falling Active Clock) .........................................................................................................58 Figure 18. Synchronous Burst Mode Read..................................... 59 Figure 19. 8-word Linear Burst with Wrap Around .......................... 59 Figure 20. Linear Burst with RDY Set One Cycle Before Data ....... 60 Figure 21. Reduced Wait-state Handshake Burst Suspend/Resume at an Even Address............................................................................. 61 Figure 22. Reduced Wait-state Handshake Burst Suspend/Resume at an Odd Address .............................................................................. 61 Figure 23. Reduced Wait-state Handshake Burst Suspend/Resume at Address 3Eh (or Offset from 3Eh)................................................... 62 Figure 24. Reduced Wait-state Handshake Burst Suspend/Resume at Address 3Fh (or Offset from 3Fh by a Multiple of 64) ..................... 62 Figure 25. Standard Handshake Burst Suspend Prior to Initial Access .........................................................................................................63 Figure 26. Standard Handshake Burst Suspend at or after Initial Ac- Erase and Programming Performance . . . . . . . 84 BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 84 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 85 VBB080—80-ball Fine-Pitch Ball Grid Array (BGA) 11.5 x 9 mm Package ........................................................................ 85 VBD064—64-ball Fine-Pitch Ball Grid Array (BGA) 9 x 8 mm Package ........................................................................ 86 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 87 4 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET PRODUCT SELECTOR GUIDE Part Number Burst Frequency Speed Option Max Initial Synchronous Access Time, ns (TIACC) Reduced Wait-state Handshaking; Even Address Max Initial Synchronous Access Time, ns (TIACC) Reduced Wait-state Handshaking; Odd Address; or Standard Handshaking Max Burst Access Time, ns (TBACC) Max Asynchronous Access Time, ns (TACC) Max CE# Access Time, ns (TCE) Max OE# Access Time, ns (TOE) 11 13.5 VCC, VIO = 1.65 – 1.95 V Am29BDS128H/Am29BDS640H 66 MHz E8, E9 56 54 MHz D8, D9 69 71 11 50 87.5 13.5 55 Note: Speed Options ending in “8” indicate the “reduced wait-state handshaking” option, which speeds initial synchronous accesses for even addresses. Speed Options ending in “9” indicate the “standard handshaking” option. See the AC Characteristics section of this data sheet for full specifications. BLOCK DIAGRAM VCC VSS VIO RDY Buffer RDY Erase Voltage Generator WE# RESET# WP# ACC State Control Command Register Input/Output Buffers DQ15–DQ0 PGM Voltage Generator Chip Enable Output Enable Logic Data Latch CE# OE# Y-Decoder Timer Address Latch VCC Detector Y-Gating X-Decoder Cell Matrix AVD# CLK Burst State Control Burst Address Counter Amax–A0 Note: Amax = A22 (128 Mb) or A21 (64 Mb) May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 5 DATA SHEET BLOCK DIAGRAM OF SIMULTANEOUS OPERATION CIRCUIT VCC VSS VIO Bank A Address Latches and Control Logic Y-Decoder DQ15–DQ0 Bank A Amax–A0 X-Decoder OE# Bank B Address Latches and Control Logic Y-Decoder DQ15–DQ0 Bank B WP# ACC RESET# WE# CE# AVD# RDY DQ15–DQ0 Amax–A0 X-Decoder DQ15–DQ0 Status STATE CONTROL & COMMAND REGISTER Amax–A0 Control X-Decoder Latches and Control Logic Y-Decoder Bank C Address Bank C DQ15–DQ0 Amax –A0 Amax –A0 X-Decoder Bank D Address Latches and Control Logic Y-Decoder Bank D DQ15–DQ0 6 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET CONNECTION DIAGRAM 80-ball Fine-Pitch Ball Grid Array Top View, Balls Facing Down (Am29BDS128H only) A8 NC A7 NC B8 NC B7 NC C8 NC C7 A13 C6 A9 C5 WE# C4 RDY C3 A7 D8 A22 D7 A12 D6 A8 D5 RESET# D4 ACC D3 A17 D2 A4 D1 VCC E8 NC E7 A14 E6 A10 E5 A21 E4 A18 E3 A6 E2 A2 E1 CLK F8 VIO F7 A15 F6 A11 F5 A19 F4 A20 F3 A5 F2 A1 F1 WP# G8 VSS G7 A16 G6 DQ7 G5 DQ5 G4 DQ2 G3 DQ0 G2 A0 G1 AVD# H8 NC H7 NC H6 DQ14 H5 DQ12 H4 DQ10 H3 DQ8 H2 CE# H1 VIO J8 NC J7 DQ15 J6 DQ13 J5 VCC J4 DQ11 J3 DQ9 J2 OE# J1 VSS K8 NC K7 VSS K6 DQ6 K5 DQ4 K4 DQ3 K3 DQ1 K2 VSS K1 NC L8 NC L7 NC M8 NC M7 NC A2 NC A1 NC B2 NC B1 NC C2 A3 C1 NC L2 NC L1 NC M2 NC M1 NC May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 7 DATA SHEET 64-ball Fine-Pitch Ball Grid Array Top View, Balls Facing Down (Am29BDS640H only) A8 NC A7 A13 A6 A9 A5 WE# A4 RDY A3 A7 A2 A3 A1 NC B8 NC B7 A12 B6 A8 B5 RESET# B4 ACC B3 A17 B2 A4 B1 VCC C8 NC C7 A14 C6 A10 C5 A21 C4 A18 C3 A6 C2 A2 C1 CLK D8 VIO D7 A15 D6 A11 D5 A19 D4 A20 D3 A5 D2 A1 D1 WP# E8 VSS E7 A16 E6 DQ7 E5 DQ5 E4 DQ2 E3 DQ0 E2 A0 E1 AVD# F8 NC F7 NC F6 DQ14 F5 DQ12 F4 DQ10 F3 DQ8 F2 CE# F1 VIO G8 NC G7 DQ15 G6 DQ13 G5 VCC G4 DQ11 G3 DQ9 G2 OE# G1 VSS H8 NC H7 VSS H6 DQ6 H5 DQ4 H4 DQ3 H3 DQ1 H2 VSS H1 NC Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. 8 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET INPUT/OUTPUT DESCRIPTIONS Amax–A0 = Address inputs Amax = A22 (128 Mb) or A21 (64 Mb) Data input/output Chip Enable input. Asynchronous relative to CLK for the Burst mode. Output Enable input. Asynchronous relative to CLK for the Burst mode. Write Enable input. Device Power Supply (1.65 – 1.95 V). Input & Output Buffer Power Supply (1.65 – 1.95 V). Ground No Connect; not connected internally Ready output; In Synchronous Mode, indicates the status of the Burst read. Low = data invalid. High = data valid. In Asynchronous Mode, indicates the status of the internal program and erase function. Low = program/erase in progress. High Impedance = program/erase completed. CLK = CLK is not required in asynchronous mode. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. 23 or 22 Amax–A0 CLK WP# ACC CE# OE# WE# RESET# AVD# RDY DQ15–DQ0 16 AVD# = DQ15–DQ0 = CE# OE# WE# VCC VIO VSS NC RDY = = = = = = = = Address Valid input. Indicates to device that the valid address is present on the address inputs (Amax–A0). Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. High = device ignores address inputs RESET# = Hardware reset input. Low = device resets and returns to reading array data Hardware write protect input. At VIL, disables program and erase functions in the four highest and four lowest sectors. At VIH, does not protect any sectors. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, locks all sectors. Should be at VIH for all other conditions. WP# = ACC = LOGIC SYMBOL May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 9 DATA SHEET ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am29BDS 128 H E 8 VK I TEMPERATURE RANGE I = Industrial (–40°C to +85°C) 80-Ball Fine-Pitch Ball Grid Array (BGA) 0.80 mm pitch, 11.5 x 9 mm package (VBB080) 80-Ball Fine-Pitch Ball Grid Array (BGA) 0.80 mm pitch, 11.5 x 9mm, Pb-free Package (VBB080) 64-Ball Fine-Pitch Ball Grid Array (BGA) 0.80 mm pitch, 8 X 9 mm package (VBD064) VIO = 1.8 V, reduced wait-state handshaking enabled VIO = 1.8 V, standard handshaking 66 MHz 54 MHz 0.13 µm PACKAGE TYPE VK = VF = VM = VIO AND HANDSHAKING OPTIONS 8 9 E D H = = = = = SPEED PROCESS TECHNOLOGY DENSITY 128 = 64 = DEVICE FAMILY 128 Mbit (8 M x 16-bit) 64 Mbit (4 M x 16-bit) Am29BDS CMOS Flash Memory, Simultaneous Read/Write, Burst Mode Flash Memory, 1.8 Volt-only Read, Program, and Erase Valid Combinations Order Number Am29BDS128HE8 Am29BDS128HE9 VKI Am29BDS128HD8 Am29BDS128HD9 Am29BDS128HE8 Am29BDS128HE9 VFI Am29BDS128HD8 Am29BDS128HD9 Am29BDS640HE8 Am29BDS640HE9 VMI Am29BDS640HD8 Am29BDS640HD9 BS640HD8V BS128HD8VF BS128HD8V Package Marking BS128HE8V Burst Frequency (MHz) 66 Density BS128HE9V 54 BS128HD9V BS128HE8VF 66 BS128HE9VF 54 BS128HD9VF BS640HE8V 66 BS640HE9V 64 Mbit 54 BS640HD9V 128 Mbit Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. 10 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Device Bus Operations CLK (See Note) X X X L L Operation Asynchronous Read - Addresses Latched Asynchronous Read - Addresses Steady State Asynchronous Write Synchronous Write Standby (CE#) Hardware Reset Burst Read Operations Load Starting Burst Address Advance Burst to next address with appropriate Data presented on the Data Bus Terminate current Burst read cycle Terminate current Burst read cycle via RESET# Terminate current Burst read cycle and start new Burst read cycle CE# L L L L H X OE# L L H H X X WE# H H L L X X Amax–0 Addr In Addr In Addr In Addr In HIGH Z HIGH Z DQ15–0 I/O I/O I/O I/O HIGH Z HIGH Z RESET# H H H H H L AVD# X X X X L L H X L X L X X X H H H H H Addr In HIGH Z HIGH Z HIGH Z HIGH Z X Burst Data Out HIGH Z HIGH Z I/O H H H L H X H X X Legend: L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions. Note: Default active edge of CLK is the rising edge. Requirements for Asynchronous Read Operation (Non-Burst) To read data from the memory array, the system must first assert a valid address on Amax–A0, while driving AVD# and CE# to VIL. WE# should remain at VIH. The rising edge of AVD# latches the address. The data will appear on DQ15–DQ0. Since the memory array is divided into four banks, each bank remains enabled for read access until the command register contents are altered. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (t C E ) is the delay from the stable addresses and stable CE# to valid data at the outputs. The output enable access time (tOE) is the delay from the falling edge of OE# to valid data at the output. May 10, 2006 27024B3 The internal state machine is set for reading array data in asynchronous mode upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. Requirements for Synchronous (Burst) Read Operation The device is capable of continuous sequential burst operation and linear burst operation of a preset length. When the device first powers up, it is enabled for asynchronous read operation. Prior to entering burst mode, the system should determine how many wait states are desired for the initial word (tIACC) of each burst access, what mode of burst operation is desired, which edge of the clock will be the 11 Am29BDS128H/Am29BDS640H DATA active clock edge, and how the RDY signal will transition with valid data. The system would then write the configuration register command sequence. See “Set Configuration Register Command Sequence” section on page 33 and “Command Definitions” section on page 33 for further details. Once the system has written the “Set Configuration Register” command sequence, the device is enabled for synchronous reads only. The initial word is output tIACC after the active edge of the first CLK cycle. Subsequent words are output tBACC after the active edge of each successive clock cycle, which automatically increments the internal address counter. Note that the device has a fixed internal address boundary that occurs every 64 words, starting at address 00003Fh. During the time the device is outputting data at this fixed internal address boundary (address 00003Fh, 00007Fh, 0000BFh, etc.), a two cycle latency occurs before data appears for the next address (address 000040h, 000080h, 0000C0h, etc.). The RDY output indicates this condition to the system by pulsing low. For standard handshaking devices, there is no two cycle latency between 3Fh and 40h (or offset from these values by a multiple of 64) if the latched address was 3Eh or 3Fh or offset from these values by a multiple of 64). See Figure 46, “Latency with Boundary Crossing,” on page 80. For reduced wait-state handshaking devices, if the address latched is 3Eh or 3Fh (or offset from these values by a multiple of 64) two additional cycle latency occurs prior to the initial access and the two cycle latency between 3Fh and 40h (or offset from these values by a multiple of 64) will not occur. The device will continue to output sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location, until the system drives CE# high, RESET# low, or AVD# low in conjunction with a new address. See Table 1, “Device Bus Operations,” on page 11. If the host system crosses the bank boundary while reading in burst mode, and the device is not programming or erasing, a two-cycle latency will occur as described above in the subsequent bank. If the host system crosses the bank boundary while the device is programming or erasing, the device will provide read status information. The clock will be ignored. After the host has completed status reads, or the device has completed the program or erase operation, the host can restart a burst operation using a new address and AVD# pulse. If the clock frequency is less than 6 MHz during a burst mode operation, additional latencies will occur. RDY indicates the length of the latency by pulsing low. SHEET 8-, 16-, and 32-Word Linear Burst with Wrap Around The remaining three modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. In each of these modes, the burst addresses read are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode (see Table 2.) Table 2. Mode 8-word 16-word 32-word Burst Address Groups Group Size Group Address Ranges 8 words 16 words 32 words 0-7h, 8-Fh, 10-17h,... 0-Fh, 10-1Fh, 20-2Fh,... 00-1Fh, 20-3Fh, 40-5Fh,... As an example: if the starting address in the 8-word mode is 39h, the address range to be read would be 38-3Fh, and the burst sequence would be 39-3A-3B-3C-3D-3E-3F-38h-etc. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. Note that in these three burst read modes the address pointer does not cross the boundary that occurs every 64 words; thus, no wait states are inserted (except during the initial access). The RDY pin indicates when data is valid on the bus. The devices can wrap through a maximum of 128 words of data (8 words up to 16 times, 16 words up to 8 times, or 32 words up to 4 times) before requiring a new synchronous access (latching of a new address). Burst Suspend/Resume The Burst Suspend/Resume feature allows the system to temporarily suspend a synchronous burst operation during the initial access (before data is available) or after the device is outputting data. When the burst operation is suspended, any previously latched internal data and the current state are retained. Burst Suspend requires CE# to be asserted, WE# de-asserted, and the initial address latched by AVD# or the CLK edge. Burst Suspend occurs when OE# is de-asserted. See Figure 21, “Reduced Wait-state Handshake Burst Suspend/Resume at an Even Address,” on page 61, Figure 22, “Reduced Wait-state Handshake Burst Suspend/Resume at an Odd Address,” on page 61, Figure 23, “Reduced Wait-state Handshake Burst Suspend/Resume at Address 3Eh (or Offset from 3Eh),” on page 62, Figure 24, “Reduced Wait-state Handshake Burst Suspend/Resume at 27024B3 May 10, 2006 12 Am29BDS128H/Am29BDS640H DATA Address 3Fh (or Offset from 3Fh by a Multiple of 64),” on page 62, Figure 25, “Standard Handshake Burst Suspend Prior to Initial Access,” on page 63, Figure 26, “Standard Handshake Burst Suspend at or after Initial Access,” on page 63, Figure 27, “Standard Handshake Burst Suspend at Address 3Fh (Starting Address 3Dh or Earlier),” on page 64, Figure 28, “Standard Handshake Burst Suspend at Address 3Eh/3Fh (Without a Valid Initial Access),” on page 64, and Figure 29, “Standard Handshake Burst Suspend at Address 3Eh/3Fh (with 1 Access CLK),” on page 65. Burst plus Burst Suspend should not last longer than tRCC without re-latching an address or crossing an address boundary. To resume the burst access, OE# must be re-asserted. The next active CLK edge will resume the burst sequence where it had been suspended. See Figure 30, “Read Cycle for Continuous Suspend,” on page 65. The RDY pin is only controlled by CE#. RDY will remain active and is not placed into a high-impedance state when OE# is de-asserted. SHEET Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in another bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 49, “Back-to-Back Read/Write Cycle Timings,” on page 83 shows how read and write cycles may be initiated for simultaneous operation with zero latency. R e fe r t o t h e D C C h a r a c t e r i s t i c s t a b l e fo r read-while-program and read-while-erase current specifications. Writing Commands/Command Sequences The device has the capability of performing an asynchronous or synchronous write operation. While the device is configured in Asynchronous read it is able to perform Asynchronous write operations only. CLK is ignored in the Asynchronous programming mode. When in the Synchronous read mode configuration, the device is able to perform both Asynchronous and Synchronous write operations. CLK and WE# address latch is supported in the Synchronous programming mode. During a synchronous write operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE# to V IH w hen providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or data. During an asynchronous write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. The asynchronous and synchronous programing operation is independent of the Set Device Read Mode bit in the Configuration Register (see Table 18, “Configuration Register,” on page 36). The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. An erase operation can erase one sector, multiple sectors, or the entire device. Table 12, “Am29BDS128H Sector Address Table,” on page 27 indicates the address space that each sector occupies. The device address space is divided into four banks: Banks B and C contain only 32 Kword sectors, while Banks A and D contain both 4 Kword boot sectors in addition to 32 Kword sectors. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. Configuration Register The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, RDY configuration, and synchronous mode active. Reduced Wait-state Handshaking Option The device can be equipped with a reduced wait-state handshaking feature that allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready to be read. The host system should use the programmable wait state configuration to set the number of wait states for optimal burst mode operation. The initial word of burst data is indicated by the rising edge of RDY after OE# goes low. The presence of the reduced wait-state handshaking feature may be verified by writing the autoselect command sequence to the device. See “Autoselect Command Sequence” for details. For optimal burst mode performance on devices without the reduced wait-state handshaking option, the host system must set the appropriate number of wait states in the flash device depending on clock frequency and the presence of a boundary crossing. See “Set Configuration Register Command Sequence” section on page 33 section for more information. The device will automatically delay RDY and data by one additional clock cycle when the starting address is odd. The autoselect function allows the host system to determine whether the flash device is enabled for reduced wait-state handshaking. See the “Autoselect Command Sequence” section for more information. May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 13 DATA ICC2 in the “DC Characteristics” section on page 54 represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. SHEET ming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins must be as shown in Table 3, “Autoselect Codes (High Voltage Method),” on page 15. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 4, “Am29BDS128H Boot Sector/Sector Block Addresses for Protection/Unprotection,” on page 16). Table 3 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0. However, the autoselect codes can also be accessed in-system through the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 20, “Memory Array Command Definitions,” on page 46. Note that if a Bank Address (BA) is asserted during the third write cycle of the autoselect command, the host system can read autoselect data that bank and then immediately read array data from the other bank, without exiting the autoselect mode. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 20, “Memory Array Command Definitions,” on page 46. This method does not require VID. Autoselect mode may only be entered and used when in the asynchronous read mode. Refer to the “Autoselect Command Sequence” section on page 36 for more information. Accelerated Program Operation The device offers accelerated program operations through the ACC function. ACC is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this input, the device automatically enters the aforementioned Unlock Bypass mode and uses the higher voltage on the input to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the ACC input returns the device to normal operation. Note that sectors must be unlocked prior to raising ACC to VHH. Note that the ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. In addition, the ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. When at VIL, ACC locks all sectors. ACC should be at VIH for all other conditions. Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output from the internal register (which is separate from the memory array) on DQ15–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding program- 14 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET Table 3. Autoselect Codes (High Voltage Method) Amax A11 to to CE# OE# WE# RESET# A12 A10 L L H H X X A5 to A4 A3 A2 A1 A0 X L L L L H H X X VID X L L L H H L L H H SA X VID X L L L L L L H H L L L H H H L H L H L DQ15 to DQ0 0001h 227Eh 2218h (128 Mb) 221Eh (64 Mb) 2200h (128 Mb) 2201h (64 Mb) 0001h (protected), 0000h (unprotected) DQ15 - DQ8 = 0 DQ7 - Factory Lock Bit 1 = Locked, 0 = Not Locked DQ6 -Customer Lock Bit 1 = Locked, 0 = Not Locked DQ5 = Handshake Bit 1 = Reduced wait-state Handshake, 0 = Standard Handshake DQ4 - DQ0 = 0 0001h (protected), 0000h (unprotected) Description Manufacturer ID: AMD Read Cycle 1 Device ID Read Cycle 2 Read Cycle 3 Sector Protection Verification A9 VID A8 A7 X X A6 L Indicator Bits L L H H X X VID X X L X L L H H Hardware Sector Group Protection L L H H SA X VID X X X L L L H L Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care. Notes: 1. The autoselect codes may also be accessed in-system via command sequences. 2. PPB Protection Status is shown on the data bus May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 15 DATA Table 4. Am29BDS128H Boot Sector/Sector Block Addresses for Protection/Unprotection Sector/ Sector Block Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords SHEET Sector/ Sector Block Size 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords Sector SA131-SA134 SA135-SA138 SA139-SA142 SA143-SA146 SA147-SA150 SA151–SA154 SA155–SA158 SA159–SA162 SA163–SA166 SA167–SA170 SA171–SA174 SA175–SA178 SA179–SA182 SA183–SA186 SA187–SA190 SA191–SA194 SA195–SA198 SA199–SA202 SA203–SA206 SA207–SA210 SA211–SA214 SA215–SA218 SA219–SA222 SA223–SA226 SA227–SA230 SA231–SA234 SA235–SA238 SA239–SA242 SA243–SA246 SA247–SA250 SA251–SA254 SA255–SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269 A22–A12 011111XXXXX 100000XXXXX 100001XXXXX 100010XXXXX 100011XXXXX 100100XXXXX 100101XXXXX 100110XXXXX 100111XXXXX 101000XXXXX 101001XXXXX 101010XXXXX 101011XXXXX 101100XXXXX 101101XXXXX 101110XXXXX 101111XXXXX 110000XXXXX 110001XXXXX 110010XXXXX 110011XXXXX 110100XXXXX 110101XXXXX 110110XXXXX 110111XXXXX 111000XXXXX 111001XXXXX 111010XXXXX 111011XXXXX 111100XXXXX 111101XXXXX 111110XXXXX 11111100XXX 11111101XXX 11111110XXX 11111111000 11111111001 11111111010 11111111011 11111111100 11111111101 11111111110 11111111111 Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11–SA14 SA15–SA18 SA19–SA22 SA23-SA26 SA27-SA30 SA31-SA34 SA35-SA38 SA39-SA42 SA43-SA46 SA47-SA50 SA51–SA54 SA55–SA58 SA59–SA62 SA63–SA66 SA67–SA70 SA71–SA74 SA75–SA78 SA79–SA82 SA83–SA86 SA87–SA90 SA91–SA94 SA95–SA98 SA99–SA102 SA103–SA106 SA107–SA110 SA111–SA114 SA115–SA118 SA119–SA122 SA123–SA126 SA127–SA130 A22–A12 00000000000 00000000001 00000000010 00000000011 00000000100 00000000101 00000000110 00000000111 00000001XXX 00000010XXX 00000011XXX 000001XXXXX 000010XXXXX 000011XXXXX 000100XXXXX 000101XXXXX 000110XXXXX 000111XXXXX 001000XXXXX 001001XXXXX 001010XXXXX 001011XXXXX 001100XXXXX 001101XXXXX 001110XXXXX 001111XXXXX 010000XXXXX 010001XXXXX 010010XXXXX 010011XXXXX 010100XXXXX 010101XXXXX 010110XXXXX 010111XXXXX 011000XXXXX 011001XXXXX 011010XXXXX 011011XXXXX 011100XXXXX 011101XXXXX 011110XXXXX 16 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA Table 5. Am29BDS640H Boot Sector/Sector Block Addresses for Protection/Unprotection Sector/ Sector Block Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords SHEET Sector/ Sector Block Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords Sector SA135 SA136 SA137 SA138 SA139 SA140 SA141 A21–A12 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111 Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11–SA14 SA15–SA18 SA19–SA22 SA23-SA26 SA27-SA30 SA31-SA34 SA35-SA38 SA39-SA42 SA43-SA46 SA47-SA50 SA51–SA54 SA55–SA58 SA59–SA62 SA63–SA66 SA67–SA70 SA71–SA74 SA75–SA78 SA79–SA82 SA83–SA86 SA87–SA90 SA91–SA94 SA95–SA98 SA99–SA102 SA103–SA106 SA107–SA110 SA111–SA114 SA115–SA118 SA119–SA122 SA123–SA126 SA127–SA130 SA131 SA132 SA133 SA134 A21–A12 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX 0000010XXX 0000011XXX 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX 10111XXXXX 11000XXXXX 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX 11101XXXXX 11110XXXXX 1111100XXX 1111101XXX 1111110XXX 1111111000 Sector/Sector Block Protection and Unprotection The hardware sector protection feature disables both programming and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented via two methods. (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table 4, “Am29BDS128H Boot Sector/Sector Block Addresses for Protection/Unprotection,” on page 16 Sector Protection The Am29BDSxxxH family features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: Persistent Sector Protection A command sector protection method that replaces the old 12 V controlled protection method. Password Sector Protection A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted WP# Hardware Protection A write protect pin that can prevent program or erase operations in the outermost sectors. The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen. Selecting a Sector Protection Mode All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method will be used. If the customer decides to continue using the Persistent Sector Protection method, they must set the Persistent Sector Protection Mode May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 17 DATA Locking Bit. This will permanently set the part to operate only using Persistent Sector Protection. If the customer decides to use the password method, they must set the Password Mode Locking Bit. This will permanently set the part to operate only using password sector protection. It is important to remember that setting either the Persistent Sector Protection Mode Locking Bit or the Password Mode Locking Bit permanently selects the protection mode. It is not possible to switch between the two methods once a locking bit has been set. It is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. This is so that it is not possible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at the factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See “Autoselect Command Sequence” section on page 36 for details. SHEET dividual PPBs are programmable. It is the responsibility of the user to perfor m the preprogramming operation. Otherwise, an already erased sector PPBs has the potential of being over-erased. There is no h ar d wa r e m e c h a ni s m t o p r even t s ec to r P P B s over-erasure. Persistent Protection Bit Lock (PPB Lock) A global volatile bit. When set to “1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through the DYB Write Command. When the par ts are first shipped, the PPBs are cleared. The DYBs and PPB Lock are defaulted to power up in the cleared state – meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are Non-Volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PBB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to “1”. Setting the PPB Lock disables all program and erase commands to the Non-Volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. Persistent Sector Protection The Persistent Sector Protection method replaces the old 12 V controlled protection method while at the same time enhancing flexibility by providing three different sector protection states: ■ Persistently Locked—A sector is protected and cannot be changed. ■ Dynamically Locked—The sector is protected and can be changed by a simple command ■ Unlocked—The sector is unprotected and can be changed by a simple command In order to achieve these states, three types of “bits” are going to be used: Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (“Am29BDS128H Boot Sector/Sector Block Addresses for Protection/Unprotection” section on page 16). All 4 Kbyte boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Program Command. Note: If a PPB requires erasure, all of the sector PPBs must first be preprogrammed prior to PPB erasing. All PPBs erase in parallel, unlike programming where in- 18 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA System boot code can determine if any changes to the PPB are needed e.g. to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PPBs during system operation. The WP# write protect pin adds a final level of hardware protection to the four highest and four lowest 4 Kbyte sectors. When this pin is low it is not possible to change the contents of these four sectors. These sectors generally hold system boot code. So, the WP# pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again. Note: to achieve the best protection, it’s recommended to execute the PPB lock bit set command early in the boot code, and protect the boot code by holding WP# = VIL. Table 6. Sector Protection Schemes PPB Lock 0 1 0 0 0 1 1 1 Protected—PPB not changeable, DYB is changeable Protected—PPB and DYB are changeable SHEET In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately tPSP before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately tSEA after which the device returns to read mode without having erased the protected sector. The programming of the DYB, PPB, and PPB lock for a given sector can be ver ified by wr iting a DYB/PPB/PPB lock verify command to the device. Persistent Sector Protection Mode Locking Bit Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode. Password Protection Mode The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differences between the Persistent Sector Protection and the Password Sector Protection Mode: ■ When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit is set to the locked state, rather than cleared to the unlocked state. ■ The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. The password is stored in a one-time programmable (OTP) region of the flash memory. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-pro- DYB 0 0 0 1 1 0 1 1 PPB 0 0 1 0 1 1 0 1 Sector State Unprotected—PPB and DYB are changeable Unprotected—PPB not changeable, DYB is changeable Table 6 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the sector. May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 19 DATA grammed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for each “password check.” This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. SHEET Password Verify command from reading the contents of the password on the pins of the device. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Lock Bit is also set, after a hardware reset (RESET# asserted) or a power-up reset the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a “1”. If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit can be set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode. Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the password. It is recommended that the password be somehow correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: 1. It permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. 2. It also disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. High Voltage Sector Protection Sector protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage (V ID ) to be placed on the RESET# pin. Refer to Figure 2, “In-System Sector Protection/ Sector Unprotection Algorithms,” on page 22 for details on this procedure. Note that for sector unprotect, all unprotected sectors must be first protected prior to the first sector write cycle. Once the Password Mode Locking bit or Persistent Protection Locking bit are set, the high voltage sector protect/unprotect capability is disabled. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC ± 0.2 V. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the “DC Characteristics” section on page 54 represents the standby current specification. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see “Password Program Command” section on page 40 and “Password Verify Command” section on page 40). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the 20 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET Embedded Algorithms) before the device is ready to read data again. If RESET# is asser ted when a program or erase operation is not executing, the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after RESET# returns to VIH. Refer to the “AC Characteristics” section on page 68 for RESET# parameters and to Figure 33, “Reset Timings,” on page 68 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state. Figure 1. Temporary Sector Unprotect Operation START Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous mode, the device automatically enables this mode when addresses remain stable for tACC + 60 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. While in synchronous mode, the device automatically enables this mode when either the first active CLK level is greater than tACC or the CLK runs slower than 5 MHz. Note that a new burst operation is required to provide new data. ICC6 in the “DC Characteristics” section on page 54 represents the automatic sleep mode current specification. RESET#: Hardware Reset Input The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS ± 0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS ± 0.2 V, the standby current will be greater. RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the device requires a time of t READY ( during RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected (If WP# = VIL, outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again. May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 21 DATA SHEET START PLSCNT = 1 RESET# = VID Wait 1 ms Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address START PLSCNT = 1 RESET# = VID Wait 1 ms Temporary Sector Unprotect Mode No First Write Cycle = 60h? Yes Set up sector address No First Write No Cycle = 60h? Yes All sectors protected? Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A7:A0 = 01000010 Temporary Sector Unprotect Mode Sector Protect: Write 60h to sector address with A7–A0 = 00000010 Wait 150 µs Verify Sector Protect: Write 40h to sector address with A7–A0 = 00000010 Read from sector address with A7–A0 = 00000010 No No PLSCNT = 25? Yes Data = 01h? Increment PLSCNT Reset PLSCNT = 1 Wait 1.5 ms Verify Sector Unprotect: Write 40h to sector address with A7–A0 = 00000010 Read from sector address with A7–A0 = 00000010 Set up next sector address Increment PLSCNT Yes No Yes No Device failed Protect another sector? No Remove VID from RESET# PLSCNT = 1000? Yes Data = 00h? Yes Device failed Write reset command Last sector verified? Yes No Sector Protect Algorithm Sector Protect complete Sector Unprotect Algorithm Remove VID from RESET# Write reset command Sector Unprotect complete Figure 2. In-System Sector Protection/ Sector Unprotection Algorithms 22 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The Customer-lockable SecSi Sector area can be protected using one of the following procedures: ■ Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, except that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector Region without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. ■ Write the three-cycle Enter SecSi Sector Secure Region command sequence, and then use the alternate method of sector protection described in the High Voltage Sector Protection section. Once the SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. SecSi Sector Protection Bits The SecSi Sector Protection Bits prevent programming of the SecSi Sector memory area. Once set, the SecSi Sector memory area contents are non-modifiable. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 20, “Memory Array Command Definitions,” on page 46 for command definitions). The device offers two types of data protection at the sector level: ■ The PPB and DYB associated command sequences disables or re-enables both program and erase operations in any sector or sector group. ■ When WP# is at VIL, the four outermost sectors are locked. ■ When ACC is at VIL, all sectors are locked. The following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. SecSi™ (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN) The 128-word SecSi sector is divided into 64 factory-lockable words that can be programmed and locked by the customer. The SecSi sector is located at addresses 000000h-00007Fh in both Persistent Protection mode and Password Protection mode. It uses in dicato r b its (DQ 6, DQ7) to indicate t he factory-locked and customer-locked status of the part. The system accesses the SecSi Sector through a command sequence (see “Enter SecSi™ Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Factory-Locked Area (64 words) T h e fa c t o r y - l o cke d a r e a o f t h e S e c S i S e c t o r (000000h-00003Fh) is locked when the par t is shipped, whether or not the area was programmed at the factory. The SecSi Sector Factory-locked Indicator Bit (DQ7) is permanently set to a “1”. AMD offers the ExpressFlash service to program the factory-locked area with a random ESN, a customer-defined code, or any combination of the two. Because only AMD can program and protect the factory-locked area, this method ensures the security of the ESN once the product is shipped to the field. Contact an AMD representative for details on using the AMD ExpressFlash service. Table 7. SecSiTM Sector Addresses Sector Size Am29BDS128H/ Am29BDS640H Factory-Locked Area Customer-Lockable Area 128 words 64 words 64 words Address Range 000000h–00007Fh 000000h–00003Fh 000040h–00007Fh Customer-Lockable Area (64 words) The customer-lockable area of the SecSi Sector (000040h-00007Fh) is shipped unprotected, which allows the customer to program and optionally lock the area as appropriate for the application. The SecSi Sector Customer-locked Indicator Bit (DQ6) is shipped as “0” and can be permanently locked to “1” by issuing the SecSi Protection Bit Program Command. The SecSi Sector can be read any number of times, but May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 23 DATA SHEET CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. Write Protect (WP#) The Write Protect feature provides a hardware method of protecting the four outermost sectors. This function is provided by the WP# pin and overrides the previously discussed Sector Protection/Unprotection method. If the system asserts VIL on the WP# pin, the device disables program and erase functions in the eight “outermost” 4 Kword boot sectors. If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in “PPB Program Command” section on page 43. Note that the WP# pin must not be left floating or unconnected; inconsistent behavior of the device may result. Low VCC Write Inhibit When V CC i s less than V LKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 8-11. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 8-11. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100, available via the AMD site at the following URL: http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies Table 8. Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h CFI Query Identification String Description Query Unique ASCII string “QRY” Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) 24 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA Table 9. Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0017h 0019h 0000h 0000h 0004h 0000h 0009h 0000h 0004h 0000h 0004h 0000h SHEET System Interface String Description VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N µs Typical timeout for Min. size buffer write 2N µs (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) Table 10. Addresses 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 001xh 0001h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 00xDh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h Device Geometry Definition Description Device Size = 2N byte BDS128H = 0018h; BDS640H = 0017h Flash Device Interface description (refer to CFI publication 100) Max. number of bytes in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 2 Information Address 31h: BDS128H = 00FDh; BDS640H = 007Dh Erase Block Region 3 Information Erase Block Region 4 Information May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 25 DATA Table 11. Addresses 40h 41h 42h 43h 44h 45h Data 0050h 0052h 0049h 0031h 0033h 000Ch SHEET Primary Vendor-Specific Extended Query Description Query-unique ASCII string “PRI” Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Technology (Bits 5-2) 0011 = 0.13 µm 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 0002h 0001h 0000h 0007h 00x7h 0001h 0000h 00B5h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 07 = Advanced Sector Protection Simultaneous Operation: number of Sectors in all banks except boot block BDS128H = 00E7h; BDS640H = 0077h Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Boot Sector Flag Program Suspend. 00h = not supported Bank Organization: X = Number of banks Bank A – Bank D Region Information. X = Number of sectors in bank. Address: 58h = Bank A; 59h = Bank B; 5Ah = Bank C; 5Bh = Bank D Data: BDS128H / BDS640H 4Eh 4Fh 50h 57h 58h 59h 5Ah 5Bh 00C5h 0001h 0000h 0004h 0027h / 0017h 0060h / 0030h 0060h / 0030h 0027h / 0017h 26 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET Table 12. Am29BDS128H Sector Address Table Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 Bank D SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Sector Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords (x16) Address Range 000000h–000FFFh 001000h–001FFFh 002000h–002FFFh 003000h–003FFFh 004000h–004FFFh 005000h–005FFFh 006000h–006FFFh 007000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 090000h–097FFFh 098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh Bank C Bank Sector SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords (x16) Address Range 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h–17FFFFh 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h–1FFFFFh May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 27 DATA Table 12. Bank Sector SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 Bank C SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords SHEET Am29BDS128H Sector Address Table (Continued) (x16) Address Range 200000h–207FFFh 208000h–20FFFFh 210000h–217FFFh 218000h–21FFFFh 220000h–227FFFh 228000h–22FFFFh 230000h–237FFFh 238000h–23FFFFh 240000h–247FFFh 248000h–24FFFFh 250000h–257FFFh 258000h–25FFFFh 260000h–267FFFh 268000h–26FFFFh 270000h–277FFFh 278000h–27FFFFh 280000h–287FFFh 288000h–28FFFFh 290000h–297FFFh 298000h–29FFFFh 2A0000h–2A7FFFh 2A8000h–2AFFFFh 2B0000h–2B7FFFh 2B8000h–2BFFFFh 2C0000h–2C7FFFh 2C8000h–2CFFFFh 2D0000h–2D7FFFh 2D8000h–2DFFFFh 2E0000h–2E7FFFh 2E8000h–2EFFFFh 2F0000h–2F7FFFh 2F8000h–2FFFFFh Bank C Bank Sector SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords (x16) Address Range 300000h–307FFFh 308000h–30FFFFh 310000h–317FFFh 318000h–31FFFFh 320000h–327FFFh 328000h–32FFFFh 330000h–337FFFh 338000h–33FFFFh 340000h–347FFFh 348000h–34FFFFh 350000h–357FFFh 358000h–35FFFFh 360000h–367FFFh 368000h–36FFFFh 370000h–377FFFh 378000h–37FFFFh 380000h–387FFFh 388000h–38FFFFh 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h–3C7FFFh 3C8000h–3CFFFFh 3D0000h–3D7FFFh 3D8000h–3DFFFFh 3E0000h–3E7FFFh 3E8000h–3EFFFFh 3F0000h–3F7FFFh 3F8000h–3FFFFFh 28 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA Table 12. Bank Sector SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 SA148 SA149 Bank B SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords SHEET Am29BDS128H Sector Address Table (Continued) (x16) Address Range 400000h–407FFFh 408000h–40FFFFh 410000h–417FFFh 418000h–41FFFFh 420000h–427FFFh 428000h–42FFFFh 430000h–437FFFh 438000h–43FFFFh 440000h–447FFFh 448000h–44FFFFh 450000h–457FFFh 458000h–45FFFFh 460000h–467FFFh 468000h–46FFFFh 470000h–477FFFh 478000h–47FFFFh 480000h–487FFFh 488000h–48FFFFh 490000h–497FFFh 498000h–49FFFFh 4A0000h–4A7FFFh 4A8000h–4AFFFFh 4B0000h–4B7FFFh 4B8000h–4BFFFFh 4C0000h–4C7FFFh 4C8000h–4CFFFFh 4D0000h–4D7FFFh 4D8000h–4DFFFFh 4E0000h–4E7FFFh 4E8000h–4EFFFFh 4F0000h–4F7FFFh 4F8000h–4FFFFFh Bank B Bank Sector SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198 Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords (x16) Address Range 500000h–507FFFh 508000h–50FFFFh 510000h–517FFFh 518000h–51FFFFh 520000h–527FFFh 528000h–52FFFFh 530000h–537FFFh 538000h–53FFFFh 540000h–547FFFh 548000h–54FFFFh 550000h–557FFFh 558000h–55FFFFh 560000h–567FFFh 568000h–56FFFFh 570000h–577FFFh 578000h–57FFFFh 580000h–587FFFh 588000h–58FFFFh 590000h–597FFFh 598000h–59FFFFh 5A0000h–5A7FFFh 5A8000h–5AFFFFh 5B0000h–5B7FFFh 5B8000h–5BFFFFh 5C0000h–5C7FFFh 5C8000h–5CFFFFh 5D0000h–5D7FFFh 5D8000h–5DFFFFh 5E0000h–5E7FFFh 5E8000h–5EFFFFh 5F0000h–5F7FFFh 5F8000h–5FFFFFh May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 29 DATA Table 12. Bank Sector SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 Bank B SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230 Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords SHEET Am29BDS128H Sector Address Table (Continued) (x16) Address Range 600000h–607FFFh 608000h–60FFFFh 610000h–617FFFh 618000h–61FFFFh 620000h–627FFFh 628000h–62FFFFh 630000h–637FFFh 638000h–63FFFFh 640000h–647FFFh 648000h–64FFFFh 650000h–657FFFh 658000h–65FFFFh 660000h–667FFFh 668000h–66FFFFh 670000h–677FFFh 678000h–67FFFFh 680000h–687FFFh 688000h–68FFFFh 698000h–69FFFFh 6A0000h–6A7FFFh 6A8000h–6AFFFFh 6B0000h–6B7FFFh 6B8000h–6BFFFFh 6C0000h–6C7FFFh 6C8000h–6CFFFFh 6D0000h–6D7FFFh 6D8000h–6DFFFFh 6E0000h–6E7FFFh 6E8000h–6EFFFFh 6F0000h–6F7FFFh 6F8000h–6FFFFFh Bank A 690000h–697FFFh Bank Sector SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269 Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords (x16) Address Range 700000h–707FFFh 708000h–70FFFFh 710000h–717FFFh 718000h–71FFFFh 720000h–727FFFh 728000h–72FFFFh 730000h–737FFFh 738000h–73FFFFh 740000h–747FFFh 748000h–74FFFFh 750000h–757FFFh 758000h–75FFFFh 760000h–767FFFh 768000h–76FFFFh 770000h–777FFFh 778000h–77FFFFh 780000h–787FFFh 788000h–78FFFFh 790000h–797FFFh 798000h–79FFFFh 7A0000h–7A7FFFh 7A8000h–7AFFFFh 7B0000h–7B7FFFh 7B8000h–7BFFFFh 7C0000h–7C7FFFh 7C8000h–7CFFFFh 7D0000h–7D7FFFh 7D8000h–7DFFFFh 7E0000h–7E7FFFh 7E8000h–7EFFFFh 7F0000h–7F7FFFh 7F8000h–7F8FFFh 7F9000h–7F9FFFh 7FA000h–7FAFFFh 7FB000h–7FBFFFh 7FC000h–7FCFFFh 7FD000h–7FDFFFh 7FE000h–7FEFFFh 7FF000h–7FFFFFh 30 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA Table 13. Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 Bank D SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 Bank C SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 Sector Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords SHEET Am29BDS640H Sector Address Table Bank Sector SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 Bank C SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Address Range 0E8000h–0EFFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h–17FFFFh 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h–1FFFFFh Address Range 000000h–000FFFh 001000h–001FFFh 002000h–002FFFh 003000h–003FFFh 004000h–004FFFh 005000h–005FFFh 006000h–006FFFh 007000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 090000h–097FFFh 098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 31 DATA Table 13. Bank Sector SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 Bank B SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords SHEET Am29BDS640H Sector Address Table Bank Sector SA107 SA108 SA109 SA110 SA111 Bank B SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 Bank A SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords Address Range 320000h–327FFFh 328000h–32FFFFh 330000h–337FFFh 338000h–33FFFFh 340000h–347FFFh 348000h–34FFFFh 350000h–357FFFh 358000h–35FFFFh 360000h–367FFFh 368000h–36FFFFh 370000h–377FFFh 378000h–37FFFFh 380000h–387FFFh 388000h–38FFFFh 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h–3C7FFFh 3C8000h–3CFFFFh 3D0000h–3D7FFFh 3D8000h–3DFFFFh 3E0000h–3E7FFFh 3E8000h–3EFFFFh 3F0000h–3F7FFFh 3F8000h–3F8FFFh 3F9000h–3F9FFFh 3FA000h–3FAFFFh 3FB000h–3FBFFFh 3FC000h–3FCFFFh 3FD000h–3FDFFFh 3FE000h–3FEFFFh 3FF000h–3FFFFFh Address Range 200000h–207FFFh 208000h–20FFFFh 210000h–217FFFh 218000h–21FFFFh 220000h–227FFFh 228000h–22FFFFh 230000h–237FFFh 238000h–23FFFFh 240000h–247FFFh 248000h–24FFFFh 250000h–257FFFh 258000h–25FFFFh 260000h–267FFFh 268000h–26FFFFh 270000h–277FFFh 278000h–27FFFFh 280000h–287FFFh 288000h–28FFFFh 290000h–297FFFh 298000h–29FFFFh 2A0000h–2A7FFFh 2A8000h–2AFFFFh 2B0000h–2B7FFFh 2B8000h–2BFFFFh 2C0000h–2C7FFFh 2C8000h–2CFFFFh 2D0000h–2D7FFFh 2D8000h–2DFFFFh 2E0000h–2E7FFFh 2E8000h–2EFFFFh 2F0000h–2F7FFFh 2F8000h–2FFFFFh 300000h–307FFFh 308000h–30FFFFh 310000h–317FFFh 318000h–31FFFFh 32 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 20, “Memory Array Command Definitions,” on page 46 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. Refer to the AC Characteristics section for timing diagrams. be C0h, address bits A11–A0 should be 555h, and address bits A19–A12 set the code to be latched. The device will power up or after a hardware reset with the default setting, which is in asynchronous mode. The register must be set before the device can enter synchronous mode. The configuration register can not be changed during device operations (program, erase, or sector lock). Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data in asynchronous mode. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data from any non-erase-suspended sector within the same bank. See the “Erase Suspend/Erase Resume Commands” section on page 39 for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the “Reset Command” section on page 36 for more information. See also “Requirements for Asynchronous Read Operation (Non-Burst)” section on page 11 and “Requirements for Synchronous (Burst) Read Operation” section on page 11 for more information. The Asynchronous Read and Synchronous/Burst Read tables provide the read parameters, and Figure 16, “CLK Synchronous Burst Mode Read (rising active CLK),” on page 58, Figure 18, “Synchronous Burst Mode Read,” on page 59, and Figure 31, “Asynchronous Mode Read with Latched Addresses,” on page 67 show the timings. Power-up/ Hardware Reset Asynchronous Read Mode Only Set Burst Mode Configuration Register Command for Synchronous Mode (D15 = 0) Set Burst Mode Configuration Register Command for Asynchronous Mode (D15 = 1) Synchronous Read Mode Only Figure 3. Synchronous/Asynchronous State Diagram Read Mode Setting On power-up or hardware reset, the device is set to be in asynchronous read mode. This setting allows the system to enable or disable burst mode during system operations. Address A19 determines this setting: “1” for asynchronous mode, “0” for synchronous mode. Programmable Wait State Configuration The programmable wait state feature informs the device of the number of clock cycles that must elapse after AVD# is driven active before data will be available. This value is determined by the input frequency of the device. Address bits A14–A12 determine the setting (see Table 14, “Programmable Wait State Settings,” on page 34). The wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. The number of wait states that should be programmed into the device is directly related to the clock frequency. Set Configuration Register Command Sequence The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, RDY configuration, and synchronous mode active. The configuration register must be set before the device will enter burst mode. The configuration register is loaded with a three-cycle command sequence. The first two cycles are standard unlock sequences. On the third cycle, the data should May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 33 DATA Table 14. A14 0 0 0 0 1 1 1 1 SHEET address bits A14–A12 to 010 for the system/device to execute at maximum speed. Table 15 describes the typical number of clock cycles (wait states) for various conditions. Table 15. System Frequency Range 6–22 MHz 22–28 MHz 28–43 MHz 43–54 MHz Programmable Wait State Settings A13 0 0 1 1 0 0 1 1 A12 0 1 0 1 0 1 0 1 Total Initial Access Cycles 2 3 4 5 6 7 (default) Reserved Reserved Wait States for Reduced Wait-state Handshaking Even Initial Address 2 2 3 4 2 2 3 4 Odd Initial Address 2 3 4 5 2 3 4 5 E (66 MHz) D (54 MHz) Device Speed Rating Notes: 1. Upon power-up or hardware reset, the default setting is seven wait states. 2. RDY will default to being active with data when the Wait State Setting is set to a total initial access cycle of 2. 6–28 MHz 28–35 MHz 35–53 MHz 53–66 MHz It is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. A hardware reset will set the wait state to the default setting. Reduced Wait-state Handshaking Option If the device is equipped with the reduced wait-state handshaking option, the host system should set Notes: 1. If the latched address is 3Eh or 3Fh (or an address offset from either address by a multiple of 64), add two access cycles to the values listed. 2. In the 8-, 16-, and 32-word burst modes, the address pointer does not cross 64-word boundaries (3Fh, or addresses offset from 3Fh by a multiple of 64). 3. Typical initial access cycles may vary depending on system margin requirements. 34 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA Standard Handshaking Option For optimal burst mode performance on devices with the standard handshaking option, the host system must set the appropriate number of wait states in the flash device depending on the clock frequency. Table 16 describes the typical number of clock cycles (wait states) for various conditions with A14-A12 set to 101. Table 16. Wait States for Standard Handshaking Conditions at Address Initial address Initial address is 3E or 3Fh (or offset from these addresses by a multiple of 64) and is at boundary crossing* Typical No. of Clock Cycles after AVD# Low 7 SHEET the starting location. The sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eight-word mode. Table 17 shows the address bits and settings for the four read modes. Table 17. Read Mode Settings Address Bits Burst Modes Continuous 8-word linear wrap around 16-word linear wrap around 32-word linear wrap around A16 0 0 1 1 A15 0 1 0 1 7 Note: Upon power-up or hardware reset the default setting is continuous. * In the 8-, 16- and 32-word burst read modes, the address pointer does not cross 64-word boundaries (addresses which are multiples of 3Fh). Burst Active Clock Edge Configuration By default, the device will deliver data on the rising edge of the clock after the initial synchronous access time. Subsequent outputs will also be on the following rising edges, barring any delays. The device can be set so that the falling clock edge is active for all synchronous accesses. Address bit A17 determines this setting; “1” for rising active, “0” for falling active. RDY Configuration By default, the device is set so that the RDY pin will output VOH whenever there is valid data on the outputs. The device can be set so that RDY goes active one data cycle before active data. Address bit A18 determines this setting; “1” for RDY active with data, “0” for RDY active one clock cycle before valid data. In asynchronous mode, RDY is an open-drain output. The autoselect function allows the host system to determine whether the flash device is enabled for h an d s h ak i n g . S e e th e “ Au t os e l e c t C om m a n d Sequence” section on page 36 for more information. Read Mode Configuration The device supports four different read modes: continuous mode, and 8, 16, and 32 word linear wrap around modes. A continuous sequence begins at the starting address and advances the address pointer until the burst operation is complete. If the highest address in the device is reached during the continuous burst read mode, the address pointer wraps around to the lowest address. For example, an eight-word linear read with wrap around begins on the starting address written to the device and then advances to the next 8 word boundary. The address pointer then returns to the 1st word after the previous eight word boundary, wrapping through Configuration Register Table 18 shows the address bits that determine the configuration register settings for various device functions. May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 35 DATA Table 18. Address BIt A19 A18 A17 Function Set Device Read Mode RDY Clock Settings (Binary) SHEET Configuration Register 0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Mode (default) 0 = RDY active one clock cycle before data 1 = RDY active with data (default) 0 = Burst starts and data is output on the falling edge of CLK 1 = Burst starts and data is output on the rising edge of CLK (default) Synchronous Mode A16 A15 Read Mode 00 = Continuous (default) 01 = 8-word linear with wrap around 10 = 16-word linear with wrap around 11 = 32-word linear with wrap around A14 A13 A12 000 = Data is valid on the 2th active CLK edge after AVD# transition to VIH 001 = Data is valid on the 3th active CLK edge after AVD# transition to VIH 010 = Data is valid on the 4th active CLK edge after AVD# transition to VIH Programmable 011 = Data is valid on the 5th active CLK edge after AVD# transition to VIH 100 = Data is valid on the 6th active CLK edge after AVD# transition to VIH Wait State 101 = Data is valid on the 7th active CLK edge after AVD# transition to VIH (default) 110 = Reserved 111 = Reserved Note:Device will be in the default state upon power-up or hardware reset. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins (prior to the third cycle). This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 20, “Memory Array Command Definitions,” on page 46 shows the address and data requirements. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. No subsequent data will be made available if the autoselect data is read in synchronous mode. The system may read at any address within the same bank any number of times without initiating another autoselect command sequence. Read commands to other banks will return data from the array. The following table describes the address requirements for the various autoselect functions, and the resulting data. BA represents the bank address, and 36 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SA represents the sector address. The device ID is read in three cycles. Table 19. Description Manufacturer ID Device ID, Word 1 Device ID, Word 2 Device ID, Word 3 Sector Protection Verification Address (BA) + 00h (BA) + 01h (BA) + 0Eh (BA) + 0Fh SHEET next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 20, “Memory Array Command Definitions,” on page 46 shows the address and data requirements for the program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by monitoring DQ7 or DQ6/DQ2. Refer to the “Write Operation Status” section on page 48 for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bit to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to primarily program to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. The host system may also initiate the chip erase and sector erase sequences in the unlock bypass mode. The erase command sequences are four cycles in length instead of six cycles. Table 20, “Memory Array Command Definitions,” on page 46 shows the requirements for the unlock bypass command sequences. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. During the unlock bypass mode, only the Read, Unlock Bypass Program, Unlock Bypass Sector Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset com- Autoselect Data Read Data 0001h 227Eh (BDS128H) 221Eh (BDS640H) 2218h (BDS128H) 2201h (BDS640H) 2200h 0001h (locked), 0000h (unlocked) DQ15 - DQ8 = 0 DQ7: Factory Lock Bit 1 = Locked, 0 = Not Locked DQ6: Customer Lock Bit 1 = Locked, 0 = Not Locked DQ5: Handshake Bit 1 = Reduced Wait-state Handshake, 0 = Standard Handshake (SA) + 02h Indicator Bits (BA) + 03h The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight word electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 20, “Memory Array Command Definitions,” on page 46 shows the address and data requirements for both command sequences. Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 37 DATA mands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode. The device offers accelerated program operations through the ACC input. When the system asserts VHH on this input, the device automatically enters the Unlock Bypass mode. The system may then write the t wo - c y c l e U n l o ck B y p a s s p r o g ra m c o m m a n d sequence. The device uses the higher voltage on the ACC input to accelerate the operation. Figure 4, “Program Operation,” on page 38 illustrates the algorithm for the program operation. Refer to the Erase/Program Operations table in the AC Characteristics section for parameters, and Figure 34, “Asynchronous Program Operation Timings: AVD# Latched Addresses,” on page 70 and Figure 36, “Synchronous Program Operation Timings: WE# Latched Addresses,” on page 72 for timing diagrams. SHEET command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 20, “Memory Array Command Definitions,” on page 46 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to the “Write Operation Status” section on page 48 for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a h ardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The host system may also initiate the chip erase command sequence while the device is in the unlock bypass mode. The command sequence is two cycles cycles in length instead of six cycles. See Table 20, “Memory Array Command Definitions,” on page 46 for details on the unlock bypass command sequences. Figure 5, “Erase Operation,” on page 40 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations table in the AC Characteristics section for parameters and timing diagrams. START Write Program Command Sequence Embedded Program algorithm in progress Data Poll from System Verify Data? No Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 20, “Memory Array Command Definitions,” on page 46 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of no less than t SEA o ccurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the Yes No Increment Address Last Address? Yes Programming Completed Note: See Table 20 for program command sequence. Figure 4. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase 38 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than t SEA , otherwise erasure may begin. Any sector erase address and command following the exceeded time-out, tSEA, may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See “DQ3: Sector Erase Timer” section on page 51.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to the “Write Operation Status” section on page 48 for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The host system may also initiate the sector erase command sequence while the device is in the unlock bypass mode. The command sequence is four cycles cycles in length instead of six cycles. The Unlock Bypass Reset Command is required to return to reading array data when the bank is in the unlock bypass mode. Figure 5, “Erase Operation,” on page 40 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations table in the Figure , “AC Characteristics,” on page 69 for parameters and timing diagrams. SHEET Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the minimum tSEA time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of tESL to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Figure , “Write Operation Status,” on page 48 for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. Refer to the “Write Operation Status” section on page 48 for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the “Autoselect Mode” section on page 14 and “Autoselect Command Sequence” section on page 36 for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 39 DATA are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. START SHEET ing as a “0”. The password is all Fs when shipped from the factory. All 64-bit password combinations are valid as a password. Password Verify Command The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device will always drive all Fs onto the DQ data bus. Embedded Erase algorithm in progress Write Erase Command Sequence Data Poll from System No Data = FFh? Also, the device will not operate in Simultaneous Operation when the Password Verify command is executed. Only the password is returned regardless of the bank address. The lower two address bits (A1–A0) are valid during the Password Verify. Writing the SecSi Sector Exit command returns the device back to normal operation. Yes Erasure Completed Password Protection Mode Locking Bit Program Command The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the password. Once programmed, the Password Protection Mode Locking Bit cannot be erased and the Persistent Protection Mode Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection Mode. After issuing “PL/68h” at the fourth bus cycle, the device requires a time out period of approximately 150 µs for programming the Password Protection Mode Locking Bit. Then by writing “PL/48h” at the fifth bus cycle, the device outputs verify data at DQ0. If DQ0 = 1, then the Password Protection Mode Locking Bit is programmed. If not, the system must repeat this program sequence from the fourth cycle of “PL/68h”. Exiting the Password Protection Mode Locking Bit Program command is accomplished by writing the SecSi Sector Exit command or Read/Reset command. Notes: 1. See Table 20 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 5. Erase Operation Password Program Command The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. 4 Password Program commands are required to program the password. The user must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. There are no provisions for entering the 2-cycle unlock cycle, the password program command, and all the password data. There is no special addressing order required for programming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read operations to any memory location will return the programming status. Once programming is complete, the user must issue a Read/Reset command to return the device to normal operation. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-out by the Embedded Program Algorithm™ with the cell remain- Persistent Sector Protection Mode Locking Bit Program Command The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. After issuing “SMPL/68h” at the fourth bus cycle, the device requires a time out period of approximately 150 µs for programming the Persistent Prote ction Mo de L ockin g Bit. Then by wr itin g “SMPL/48h” at the fifth bus cycle, the device outputs verify data at DQ0. If DQ0 = 1, then the Persistent Pro- 40 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA tection Mode Locking Bit is programmed. If not, the system must repeat this program sequence from the fourth cycle of “PL/68h”. Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the SecSi Sector Exit command or Reset command. SHEET command is accomplished by writing the Read/Reset command. Password Unlock Command The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become accessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 µs at a time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 µs execution window for each portion of the unlock, the command will be ignored. The Password Unlock function is accomplished by writing Password Unlock command and data to the device to perform the clearing of the PPB Lock Bit. The password is 64 bits long, so the user must write the Password Unlock command 4 times. A1 and A0 are used for matching. Writing the Password Unlock command is not address order specific. The lower address A1–A0= 00, the next Password Unlock command is to A1–A0= 01, then to A1–A0= 10, and finally to A1–A0= 11. Once the Password Unlock command is entered for all four words, the RDY pin goes LOW indicating that the device is busy. Approximately 1 µs is required for each portion of the unlock. Once the first portion of the password unlock completes (RDY is not driven and DQ6 does not toggle when read), the Password Unlock command is issued again, only this time with the next part of the password. Four Password Unlock commands are required to successfully clear the PPB Lock Bit. As with the first Password Unlock command, the RDY signal goes LOW and reading the device results in the DQ6 pin toggling on successive read operations until complete. It is the responsibility of the microprocessor to keep track of the number of Password Unlock commands, the order, and when to read the PPB Lock bit to confirm successful password unlock. In order to relock the device into the Password Mode, the PPB Lock Bit Set command can be re-issued. Exiting the Password Unlock Command is accomplished by writing SecSi Sector Exit command. SecSi Sector Protection Bit Program Command To protect the SecSi Sector, write the SecSi Sector Protect command sequence while in the SecSi Sector mode. After issuing “OPBP/48h” at the fourth bus cycle, the device requires a time out period of approximately 150 µs to protect the SecSi Sector. Then, by writing “OPBP/48” at the fifth bus cycle, the device outputs verify data at DQ0. If DQ0 = 1, then the SecSi Sector is protected. If not, then the system must repeat this program sequence from the fourth cycle of “OPBP/48h”. PPB Lock Bit Set Command The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear or the Password Unlock command is executed. Upon setting the PPB Lock Bit, the PPBs are latched into the DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the SecSi Sector Exit command, only while in the Persistent Sector Protection Mode. DYB Write Command The DYB Write command is used to set or clear a DYB for a given sector. The high order address bits (Amax–A11) are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware reset. Exiting the DYB Write May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 41 DATA SHEET Figure 6. PPB Program Algorithm 42 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET ing a specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase command is written (60h), all Sector PPBs are erased in parallel. If the PPB Lock Bit is set, the ALL PPB Erase command will not execute and the command will time-out without erasing the PPBs. After issuing “WP/60h” at the fourth bus cycle, the device requires a time out period of approximately 1.5 ms to erase the PPB. Writing “SBA+WP/40h” at the fifth bus cycle produces verify data at DQ0. If DQ0 = 0, the PPB is erased. If not, the system must repeat this program sequence from the fourth cycle of “WP/60h”. It is the responsibility of the system to preprogram all PPBs prior to issuing the All PPB Erase command. If the system attempts to erase a cleared PPB, over-erasure may occur, making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. Writing the SecSi Sector Exit command or Read/Reset command return the device to normal operation. PPB Program Command The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs). The specific sector address (Amax–A12) are written at the same time as the program command 60h. If the PPB Lock Bit is set and the correspondingly PPB is set for the sector, the PPB Program command will not execute and the command will time out without programming the PPB. After issuing “SBA+WP/68h” at the fourth bus cycle, the device requires a time out period of approximately 150 µs to program the PPB. Writing “SBA+WP/48” at the fifth bus cycle produces verify data at DQ0. If DQ0 = 1, the PPB is programmed. If not, the system must repeat this program sequence from the fourth cycle of “SBA+WP/68h”. The PPB Program command does not follow the Embedded Program algorithm. Writing the SecSi Sector Exit command or Read/Reset command return the device back to normal operation. All PPB Erase Command The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually eras- May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 43 DATA SHEET Figure 7. PPB Erase Algorithm 44 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET tor Exit command return the device to normal operation. DYB Write Command The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at hardware reset. There is one DYB per sector. If the PPB is set, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. Writing Read/Reset command returns the device to normal operations. PPB Lock Bit Status Command The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status verify command to the device. Read/Reset and SecSi Sector Exit return the device to normal operation. DYB Status Command The programming of the DYB for a given sector can be verified by writing a DYB Status command to the device. Writing SecSi Sector Exit command returns the device to normal operation. PPB Status Command The programming of the PPB for a given sector can be verified by writing a PPB status verify command to the device. Writing Read/Reset command and SecSi Sec- May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 45 DATA SHEET Command Definitions Table 20. Cycles First Addr 1 1 4 6 4 4 4 6 6 3 2 2 2 1 2 1 1 3 1 RA XXX 555 555 555 555 555 555 555 555 XX XX XX XX XX BA BA 555 55 Data RD F0 AA AA AA AA AA AA AA AA A0 80 80 98 90 B0 30 AA 98 2AA 55 (CR)555 C0 XXX 00 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA PA SA XXX 55 55 55 55 55 55 55 55 PD 30 10 BA+555 BA+555 SA+555 BA+555 555 555 555 555 90 90 90 90 A0 80 80 20 BA+X00 BA+X01 SA+X02 BA+X03 PA 555 555 0001 227E (12)* (13)* Data AA AA 2AA 2AA 55 55 555 SA 10 30 BA+X0E (10)* BA+X0F (11)* Memory Array Command Definitions Bus Cycles (Notes 1–6) Second Addr Data Third Addr Data Fourth Addr Data Addr Fifth Data Sixth Addr Data Command Sequence (Notes) Asynchronous Read (7) Reset (8) Autoselect (9) Unlock Bypass Mode Manufacturer ID Device ID (9, 10)* Sector Lock Verify (12)* Indicator Bits (13)* Program Chip Erase Sector Erase Entry Program (14, 15) Sector Erase (14, 15) Erase (14, 15) CFI (14, 15) Reset (20) Erase Suspend (16) Erase Resume (17) Set Configuration Register (18) CFI Query (19) * For actual hexadecimal data values, refer to the note number indicated. Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK which ever comes first. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells indicate read cycles. All others are write cycles. 4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD. 5. Unless otherwise noted, address bits Amax–A12 are don’t cares. 6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 7. No unlock or command cycles required when bank is reading array data. 8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock. 9. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address. See the Autoselect Command Sequence section for more information. 10. BDS128H: 2218h; BDS640H: 221Eh. 11. BDS128H: 2200h; BDS640H: 2201h 12. The data is 0000h for an unlocked sector and 0001h for a locked sector SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax–A12 uniquely select any sector. BA = Address of the bank (BDS128H: A22–A20; BDS640H: A21–A19) for which command is being written. SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked. CR = Configuration Register address bits A19–A12. 13. DQ15–DQ8 = 0, DQ7: Factory Lock Bit (1 = Locked, 0 = Not Locked), DQ6: Customer Lock Bit (1 = Locked, 0 = Not Locked), DQ5: Handshake Bit (1 = Reduced wait-state Handshake, 0 = Standard Handshake), DQ4–DQ0 = 0 14. The Unlock Bypass command sequence is required prior to this command sequence. 15. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 16. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 17. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 18. See “Set Configuration Register Command Sequence” for details. This command is unavailable in Unlock Bypass mode. 19. Command is valid when device is ready to read array data or when device is in autoselect mode. 20. The Unlock Bypass Reset command is required to exit this mode before sending any other commands to the device. The only commands that are allowed in the Unlock Bypass mode are the Entry and exit (Reset), Program, Erase, Sector Erase and CFI. 46 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA Table 21. Cycles Command Sequence (Notes) SecSi Sector Entry Exit Protection Bit Program (8, 9) Program (11) Verify (11) Unlock (11) Program (8, 9) All Erase (8, 10, 12) Status (13) PPB Lock Bit Set Status (8) Write DYB Erase Status Persistent Password Protection Protection Locking Bit Program (8, 9) Locking Bit Program (8, 9) PPB First Addr 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 Data AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA SHEET Sector Protection Command Definitions Bus Cycles (Notes 1–6) Second Third Addr 555 555 555 555 555 555 555 555 BA+555 555 BA+555 555 555 BA+555 555 Data 88 90 60 38 C8 28 60 60 90 78 58 48 48 58 60 SA SA SA SA PL RD(1) X1 X0 RD(0) 68 PL 48 PL RD(0) XX SA+OW XX[0–3] XX[0–3] XX0 SBA+WP WPE SBA+WP 00 68 PD[0–3] PD[0–3] PD0 68 60 RD(0) XX1 SBA+WP SBA+ WPE PD1 48 40 XX2 XX XX PD2 RD(0) RD(0) XX3 PD3 SA+OW 48 OW RD(0) Addr Fourth Data Fifth Addr Data Sixth Addr Data Seventh Addr Data Addr 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA Data 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 3 4 6 4 4 7 6 6 4 3 4 4 4 4 6 Password 6 555 AA 2AA 55 555 60 SL 68 SL 48 SL RD(0) Legend: X = Don’t care PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK which ever comes first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax–A12 uniquely select any sector. BA = Address of the bank (BDS128H: A22–A20; BDS640H: A21–A19) for which command is being written. SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked. OW = Address (A7–A0) is (00011010). PD3–PD0 = Password Data. PD3–PD0 present four 16 bit combinations that represent the 64-bit password. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells indicate read cycles. All others are write cycles. 4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, WD, PWD, and PD3–PD0. 5. Unless otherwise noted, address bits Amax–A12 are don’t cares. 6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 7. No unlock or command cycles required when bank is reading array data. 8. Not supported in Synchronous Read Mode, command mode verify are always asynchronous read operations. PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity. PL = Address (A7–A0) is (00001010) RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 1. If unprotected, DQ0 = 0. RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 1. If unprotected, DQ1 = 0. SBA = Sector address block to be protected. SL = Address (A7–A0) is (00010010) WD= Write Data. See “Configuration Register” definition for specific write data WP = Address (A7–A0) is (00000010) WPE = Address (A7–A0) is (01000010) 9. The fourth cycle programs the addressed locking bit. The fifth and sixth cycles are used to validate whether the bit has been fully programmed. If DQ0 (in the sixth cycle) reads 0, the program command must be issued and verified again. 10. The fourth cycle erases all PPBs. The fifth and sixth cycles are used to validate whether the bits have been fully erased. If DQ0 (in the sixth cycle) reads 1, the erase command must be issued and verified again. 11. The entire four bus-cycle sequence must be entered for each portion of the password. 12. Before issuing the erase command, all PPBs should be programmed in order to prevent over-erasure of PPBs. 13. In the fourth cycle, 01h indicates PPB set; 00h indicates PPB not set. May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 47 DATA SHEET WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 23, “Write Operation Status,” on page 52 and the following subsections describe the function of these bits. DQ7 and DQ6 each offers a method for determining whether a program or erase operation is complete or in progress. invalid. Valid data on DQ7-DQ0 will appear on successive read cycles. Table 23, “Write Operation Status,” on page 52 shows the outputs for Data# Polling on DQ7. Figure 8, “Data# Polling Algorithm,” on page 48 shows the Data# Polling a l g o r it h m . F ig u r e 4 0 , “ D a t a # Po l l i n g T i m i n g s (During Embedded Algorithm),” on page 76 in the AC Characteristics section shows the Data# Polling timing diagram. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately tPSP, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately tASP, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6–DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 8. Data# Polling Algorithm 48 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately tASP, all sectors protected toggle time, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately tPSP after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. See the following for additional information: Figure 9, “Toggle Bit Algorithm,” on page 50, “DQ6: Toggle Bit I” o n p a g e 4 9 , F i g u r e 4 1 , “ To g g l e B i t T i m i n g s (During Embedded Algorithm),” on page 76 (toggle bit timing diagram), and Table 22, “DQ6 and DQ2 Indications,” on page 51. Toggle Bit I on DQ6 requires either OE# or CE# to be deasserted and reasserted to show the change in state. RDY: Ready The RDY is a dedicated output that, when the device is configured in the Synchronous mode, indicates (when at logic low) the system should wait 1 clock cycle before expecting the next word of data. The RDY pin is only controlled by CE#. Using the RDY Configuration Command Sequence, RDY can be set so that a logic low indicates the system should wait 2 clock cycles before expecting valid data. The following conditions cause the RDY output to be low: during the initial access (in burst mode), and after the boundary that occurs every 64 words beginning with the 64th address, 3Fh. When the device is configured in Asynchronous Mode, the RDY is an open-drain output pin which indicates whether an Embedded Algorithm is in progress or completed. The RDY status is valid after the rising edge of the final WE# pulse in the command sequence. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is in high impedance (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 23, “Write Operation Status,” on page 52 shows the outputs for RDY. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 49 DATA SHEET DQ2: Toggle Bit II START Read Byte (DQ7-DQ0) Address = VA Read Byte (DQ7-DQ0) Address = VA The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 22, “DQ6 and DQ2 Indications,” on page 51 to compare outputs for DQ2 and DQ6. See the following for additional information: Figure 9, “Toggle Bit Algorithm,” on page 50, “DQ6: Toggle Bit I” o n p a g e 4 9 , F i g u r e 4 1 , “ To g g l e B i t T i m i n g s (During Embedded Algorithm),” on page 76, and Table 22, “DQ6 and DQ2 Indications,” on page 51. DQ6 = Toggle? Yes No No DQ5 = 1? Yes Read Byte Twice (DQ7-DQ0) Adrdess = VA DQ6 = Toggle? No Yes FAIL PASS Note:The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 9. Toggle Bit Algorithm 50 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET Table 22. DQ6 and DQ2 Indications If device is programming, and the system reads at any address, at an address within a sector selected for erasure, actively erasing, at an address within sectors not selected for erasure, at an address within a sector selected for erasure, erase suspended, at an address within sectors not selected for erasure, programming in erase suspend at any address, returns array data, toggles, returns array data. The system can read from any sector not selected for erasure. is not applicable. toggles, does not toggle, does not toggle. toggles. then DQ6 toggles, toggles, and DQ2 does not toggle. also toggles. Reading Toggle Bits DQ6/DQ2 Refer to Figure 9, “Toggle Bit Algorithm,” on page 50 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (Figure 9, “Toggle Bit Algorithm,” on page 50). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be assumed to be less than tSEA, the system need not monitor DQ3. See also “Sector Erase Command Sequence” on page 38. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 51 DATA device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase com- SHEET mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 23 shows the status of DQ3 relative to the other status bits. Table 23. Status Standard Mode Embedded Program Algorithm Embedded Erase Algorithm Erase Suspended Sector Non-Erase Suspended Sector Write Operation Status DQ7 (Note 2) DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A RDY (Note 5) 0 0 High Impedance High Impedance 0 Erase Suspend Mode Erase-SuspendRead (Note 4) Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. 4. The system may read either asynchronously or synchronously (burst) while in erase suspend. 5. The RDY pin acts a dedicated output to indicate the status of an embedded erase or program operation is in progress. This is available in the Asynchronous mode only. 52 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied. . . . . . . . . . . . . . –65°C to +125°C Voltage with Respect to Ground: All Inputs and I/Os except as noted below (Note 1) . . . . . . . –0.5 V to VIO + 0.5 V VCC (Note 1) . . . . . . . . . . . . . . . . . . –0.5 V to +2.5 V VIO . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +2.5 V A9, RESET#, ACC (Note 1) . . . . . –0.5 V to +12.5 V Output Short Circuit Current (Note 3) . . . . . . 100 mA Notes: 1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to –2.0 V for periods of up to 20 ns. See Figure 10. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 11. 2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 3. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. VCC +2.0 V VCC +0.5 V 1.0 V 20 ns 20 ns 20 ns 20 ns +0.8 V –0.5 V –2.0 V 20 ns Figure 10. Maximum Negative Overshoot Waveform 20 ns Figure 11. Maximum Positive Overshoot Waveform OPERATING RANGES Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC ≥ VIO–100 mV VIO Supply Voltages . . . . . . . . . . . +1.65 V to +1.95 V Operating ranges define those limits between which the functionality of the device is guaranteed. VCC Supply Voltages . . . . . . . . . . .+1.65 V to +1.95 V May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 53 DATA SHEET DC CHARACTERISTICS CMOS COMPATIBLE Parameter Description ILI ILO Input Load Current Output Leakage Current Test Conditions Note: 1 & 2 VIN = VSS to VCC, VCC = VCCmax VOUT = VSS to VCC, VCC = VCCmax CE# = VIL, OE# = VIH, WE# = VIH, burst length =8 ICCB VCC Active burst Read Current CE# = VIL, OE# = VIH, WE# = VIH, burst length = 16 CE# = VIL, OE# = VIH, WE# = VIH, burst length = Continuous IIO1 VIO Non-active Output VCC Active Asynchronous Read Current (Note 3) VCC Active Write Current (Note 4) VCC Standby Current (Note 5) VCC Reset Current VCC Active Current (Read While Write) VCC Sleep Current Accelerated Program Current (Note 6) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Voltage for Autoselect and Temporary Sector Unprotect Voltage for Accelerated Program Low VCC Lock-out Voltage OE# = VIH 10 MHz ICC1 CE# = VIL, OE# = VIH, WE# = VIH 5 MHz 1 MHz ICC2 ICC3 ICC4 ICC5 ICC6 IACC VIL VIH VOL VOH VID VHH VLKO CE# = VIL, OE# = VIH, ACC = VIH CE# = RESET# = VCC ± 0.2 V RESET# = VIL, CLK = VIL CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH, VACC = 12.0 ± 0.5 V VIO = 1.8 V VIO = 1.8 V IOL = 100 µA, VIO = VCC = VCC min IOH = –100 µA, VIO = VCC = VCC min VCC = 1.8 V VIO – 0.1 11.5 11.5 1.0 12.5 12.5 1.4 VACC VCC –0.4 VIO – 0.4 54 MHz 9 Min Typ Max ±1 ±1 17 Unit µA µA mA 54 MHz 8 15.5 mA 54 MHz 7 1 20 10 3.5 15 0.2 1 25 1 7 5 14 40 30 15 5 40 40 40 60 40 15 10 0.4 VIO + 0.4 0.1 mA µA mA mA mA mA µA µA mA µA mA mA V V V V V V V Note: 1. Maximum ICC specifications are tested with VCC = VCCmax. 2. VIO= VCC 3. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 4. ICC active while Embedded Erase or Embedded Program is in progress. 5. Device enters automatic sleep mode when addresses are stable for tACC + 60 ns. Typical sleep mode current is equal to ICC3. 6. Total current during accelerated programming is the sum of VACC and VCC currents. 54 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET TEST CONDITIONS Table 24. Test Condition Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times CL Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Test Specifications All Speed Options 30 3 0.0–VIO VIO/2 VIO/2 Unit pF ns V V V Device Under Test Figure 12. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS SWITCHING WAVEFORMS VIO 0.0 V All Inputs and Outputs Input VIO/2 Measurement Level VIO/2 Output Figure 13. Input Waveforms and Measurement Levels May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 55 DATA SHEET AC CHARACTERISTICS VCC Power-up Parameter tVCS tVIOS tRSTH Description VCC Setup Time VIO Setup Time RESET# Low Hold Time Test Setup Min Min Min Speed 50 50 50 Unit µs µs µs tVCS VCCf tVIOS VIOf tRSTH RESET# Figure 14. Notes: 1. 2. VCC ≥ VIO–100 mV and VCC ramp rate exceeds 1 V/100 µs. VCC Power-up Diagram If the VCC ramp rate is less than 1 V /100 µs, a hardware reset will be required. CLK Characterization Parameter fCLK tCLK tCH tCL tCR tCF Description CLK Frequency CLK Period CLK High Time Min CLK Low Time CLK Rise Time Max CLK Fall Time 3 3 ns 6.0 7.4 ns Max Min 66 MHz 66 15 54 MHz 54 18.5 Unit MHz ns tCLK tCH tCL CLK tCR tCF Figure 15. CLK Characterization 56 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET AC CHARACTERISTICS Synchronous/Burst Read Parameter JEDEC Standard tIACC Description Latency (Even address in Reduced wait-state Handshaking mode) Latency (Standard Handshaking or Odd address in Reduced wait-state Handshaking mode Burst Access Time Valid Clock to Output Delay Address Setup Time to CLK (Note ) Address Hold Time from CLK (Note ) Data Hold Time from Next Clock Cycle Chip Enable to RDY Valid Output Enable to Output Valid Chip Enable to High Z Output Enable to High Z CE# Setup Time to CLK RDY Setup Time to CLK Ready Access Time from CLK Address Setup Time to AVD# (Note ) Address Hold Time to AVD# (Note ) CE# Setup Time to AVD# AVD# Low to CLK AVD# Pulse Access Time CLK to access resume CLK to High Z Output Enable Setup Time Read cycle for continuous suspend Max 66 MHz 56 54 MHz 69 Unit ns tIACC Max 71 87.5 ns tBACC tACS tACH tBDH tCR tOE tCEZ tOEZ tCES tRDYS tRACC tAAS tAAH tCAS tAVC tAVD tACC tCKA tCKZ tOES tRCC Max Min Min Min Max Max Max Max Min Min Max Min Min Min Min Min Max Max Max Min Max 11 4 6 3 11 11 8 8 4 4 11 4 6 0 4 10 50 11 8 4 1 13.5 5 7 4 13.5 13.5 10 10 5 5 13.5 5 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 12 55 13.5 10 5 ns ns ns ns ns ns ms Note: Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#. May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 57 DATA SHEET AC CHARACTERISTICS CE#f CLK tAVC AVD# tACS Addresses Aa tCES 1 2 3 7 cycles for initial access shown. tCEZ 6 7 4 5 tAVD tBDH tBACC Hi-Z tACH Data tIACC tACC OE# tCR RDY Hi-Z Da Da + 1 Da + n tOEZ tRACC Hi-Z tOE tRDYS Notes: 1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. 2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY. 3. The device is in synchronous mode. Figure 16. CLK Synchronous Burst Mode Read (rising active CLK) tCES 4 cycles for initial access shown. tCEZ 5 CE# CLK tAVC AVD# tACS Addresses Aa 1 2 3 4 tAVD tBDH tBACC Hi-Z tACH Data tIACC tACC OE# Hi-Z Da Da + 1 Da + n tOEZ tRACC Hi-Z tCR tOE RDY tRDYS Notes: 1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active falling edge. 2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY. 3. The device is in synchronous mode. Figure 17. CLK Synchronous Burst Mode Read (Falling Active Clock) 58 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET AC CHARACTERISTICS tCAS CE# 1 CLK tAVC AVD# tAAS Addresses Aa 7 cycles for initial access shown. tCEZ 5 6 7 2 3 4 tAVD tBDH tBACC Hi-Z tAAH Data tIACC tACC OE# tCR RDY Hi-Z Da Da + 1 Da + n tOEZ tRACC Hi-Z tOE tRDYS Notes: 1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active rising edge. 2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY. 3. The device is in synchronous mode. Figure 18. Synchronous Burst Mode Read tCES CE# 1 CLK tAVC AVD# tACS Addresses A6 7 cycles for initial access shown. 2 3 4 5 6 7 tAVD tBDH tBACC tIACC tACC tACH Data D6 D7 D0 D1 D5 D6 OE# tCR RDY Hi-Z tOE tRACC tRDYS Note: Figure assumes 7 wait states for initial access and automatic detect synchronous read. D0–D7 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 7th address in range (A6). See “Requirements for Synchronous (Burst) Read Operation”. The Set Configuration Register command sequence has been written with A18=1; device will output RDY with valid data. Figure 19. 8-word Linear Burst with Wrap Around May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 59 DATA SHEET AC CHARACTERISTICS tCES CE# 1 CLK tAVC AVD# tACS Addresses Aa 6 wait cycles for initial access shown. tCEZ 6 2 3 4 5 tAVD tBDH tBACC Hi-Z tACH Data tIACC tACC OE# tCR RDY Hi-Z Da Da+1 Da+2 Da+3 Da + n tRACC tOE tOEZ Hi-Z tRDYS Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY one cycle before valid data. Figure 20. Linear Burst with RDY Set One Cycle Before Data 60 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET AC CHARACTERISTICS Suspend Resume x x+1 x+2 x+3 x+4 x+5 x+6 x+7 x+8 CLK AVD# Addresses tCKZ tCKA tOES tOES OE# Data RDY tRACC D(20) D(20) D(21) D(22) D(23) D(23) D(23) D(24) tRACC Note: Figure is for any even address other than 3Eh (or multiple thereof). Figure 21. Reduced Wait-state Handshake Burst Suspend/Resume at an Even Address Suspend Resume x x+1 x+2 x+3 x+4 x+5 x+6 x+7 x+8 CLK AVD# Addresses tCKZ tCKA tOES tOES OE# Data RDY D(23) D(23) D(24) D(25) D(25) D(25) D(26) D(27) tRACC tRACC Note: Figure is for any odd address other than 3Fh (or multiple thereof). Figure 22. Reduced Wait-state Handshake Burst Suspend/Resume at an Odd Address May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 61 DATA SHEET AC CHARACTERISTICS Suspend Resume x x+1 x+2 x+3 x+4 x+5 x+6 x+7 x+8 x+9 x+10 CLK AVD# tOES Addresses tOES OE# tCKZ tCKA Data RDY D(3E) D(3E) D(3F) D(3F) D(3F) D(40) D(41) D(41) D(41) D(41) D(42) tRACC tRACC Figure 23. Reduced Wait-state Handshake Burst Suspend/Resume at Address 3Eh (or Offset from 3Eh) Suspend Resume x x+1 x+2 x+3 x+4 x+5 x+6 x+7 x+8 x+9 x+10 CLK AVD# tOES Addresses tOES OE# tCKZ tCKA Data RDY tRACC D(3F) D(3F) D(3F) D(3F) D(40) D(41) D(41) D(41) D(42) D(41) D(43) tRACC tRACC Figure 24. Reduced Wait-state Handshake Burst Suspend/Resume at Address 3Fh (or Offset from 3Fh by a Multiple of 64) 62 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET AC CHARACTERISTICS Suspend Resume CLK AVD# 1 2 3 4 5 6 7 x x+1 x+2 x+3 x+4 x+5 x+6 x+7 x+8 tOES tOES Addresses OE# Data(1) RDY(1) A(n) tCKA D(n) tACC tRACC D(n+1) D(n+2) 3F 3F D(3F) D(40) Data(2) RDY(2) D(n) D(n+1) D(n+2) D(n+3) D(n+4) D(n+5) D(n+6) tRACC Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY with valid data. 1) RDY goes low during the two-cycle latency during a boundary crossing. 2) RDY stays high when a burst sequence crosses no boundaries. Figure 25. Standard Handshake Burst Suspend Prior to Initial Access Suspend Resume CLK AVD# 1 2 3 4 5 6 7 8 9 x x+1 x+2 x+3 tOES tOES tOES Addresses OE#(1) Data(1) A(n) tCKA tCKZ D(n) tACC tRACC tRACC tCKA D(n) D(n+1) RDY(1) OE#(2) Data(2) RDY(2) tRACC D(n) tRACC D(n+1) tRACC tRACC D(n+1) D(n+2) Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY with valid data. 1) Burst suspend during the initial synchronous access 2) Burst suspend after one clock cycle following the initial synchronous access Figure 26. Standard Handshake Burst Suspend at or after Initial Access May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 63 DATA SHEET AC CHARACTERISTICS Suspend Resume CLK AVD# 1 2 3 4 5 6 7 8 9 x x+1 x+2 x+3 x+4 x+5 tOES tOES tOES Addresses OE# Data A(3D) tCKA tCKA tCKZ D(3F) D(3D) tACC D(3E) D(3F) D(3F) tRACC D(3F) D(4D) RDY tRACC tRACC Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY with valid data. Figure 27. Standard Handshake Burst Suspend at Address 3Fh (Starting Address 3Dh or Earlier) Suspend Resume CLK 1 2 3 4 5 6 7 8 x x+1 x+2 x+3 x+4 x+5 x+6 AVD# Addresses(1) OE# Data(1) tACC A(3E) tOES tOES tOES tCKA tCKZ D(3E) tRACC tRACC D(3E) D(3F) D(40) D(41) D(42) RDY(1) Addresses(2) Data(2) A(3F) tRACC D(3F) tRACC D(3F) D(40) D(41) D(42) D(43) RDY(2) tRACC tRACC Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY with valid data. 1) Address is 3Eh or offset by a multiple of 64 (40h). 2) Address is 3Fh or offset by a multiple of 64 (40h). Figure 28. Standard Handshake Burst Suspend at Address 3Eh/3Fh (Without a Valid Initial Access) 64 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET AC CHARACTERISTICS Suspend Resume CLK AVD# 1 2 3 4 5 6 7 8 9 x x+1 x+2 x+3 x+4 x+5 x+6 tOES tOES Addresses(1) OE# Data(1) RDY(1) (Even) Addresses(2) Data(2) RDY(2) (Odd) A(3E) tOES tCKZ tACC D(3E) tRACC D(3F) tRACC D(3F) tRACC D(40) D(41) D(42) tCKA A(3F) D(3F) tRACC D(40) tRACC D(40) D(41) D(42) D(43) tRACC Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY with valid data. 1) Address is 3Eh or offset by a multiple of 64 (40h) 2) Address is 3Fh or offset by a multiple of 64 (40h) Figure 29. Standard Handshake Burst Suspend at Address 3Eh/3Fh (with 1 Access CLK) Suspend Resume CLK AVD# 1 2 3 4 5 6 7 x x+1 x+2 x+3 x+4 x+5 tRCC x+6 x+7 x+8 tOES tOES Addresses OE# Data(1) RDY A(n) tCKA D(n) tACC tRACC D(n+1) D(n+2) D(3F) D(3F) D(3F) D(40) Data(2) CE# D(n) ??? tRCC ??? Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY with valid data. 1) Device crosses a page boundary prior to tRCC. 2) Device neither crosses a page boundary nor latches a new address prior to tRCC. Figure 30. Read Cycle for Continuous Suspend May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 65 DATA SHEET AC CHARACTERISTICS Asynchronous Mode Read Parameter JEDEC Standard Description tCE tACC tAVDP tAAVDS tAAVDH tOE tOEH tOEZ tCAS Access Time from CE# Low Asynchronous Access Time (Note 1) AVD# Low Time Address Setup Time to Rising Edge of AVD Address Hold Time from Rising Edge of AVD Output Enable to Output Valid Read Output Enable Hold Time Toggle and Data# Polling Max Max Min Min Min Max Min Min Max Min 8 8 0 5.5 8.5 75 MHz 45 45 10 4 6 11 0 10 10 66 MHz 50 50 54 MHz 55 55 12 5 7 13.5 Unit ns ns ns ns ns ns ns ns ns ns Output Enable to High Z (Note 2) CE# Setup Time to AVD# Notes: 1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#. 2. Not 100% tested. 66 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET AC CHARACTERISTICS CE# tOE tOEH WE# Data tACC Addresses tCAS AVD# tAVDP tAAVDS RA tAAVDH tCE Valid RD tOEZ OE# Note: RA = Read Address, RD = Read Data. Figure 31. Asynchronous Mode Read with Latched Addresses CE# tOE tOEH WE# Data tACC Addresses RA tCE Valid RD tOEZ OE# AVD# Note: RA = Read Address, RD = Read Data. Figure 32. Asynchronous Mode Read May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 67 DATA SHEET AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std tReadyw tReady tRP tRH tRPD Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode Max Max Min Min Min All Speed Options 20 500 500 200 20 Unit μs ns ns ns μs Note: Not 100% tested. CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms CE#, OE# tReadyw RESET# tRP Figure 33. Reset Timings 68 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET AC CHARACTERISTICS Erase/Program Operations Parameter JEDEC Standard Description tAVAV tAVWL tWC tAS Write Cycle Time (Note 1) Address Setup Time (Notes 2, 3) Address Hold Time (Notes 2, 3) AVD# Low Time Data Setup Time Data Hold Time Read Recovery Time Before Write CE# Setup Time to AVD# CE# Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations VACC Rise and Fall Time VACC Setup Time (During Accelerated Programming) VCC Setup Time CE# Setup Time to WE# AVD# Setup Time to WE# AVD# Hold Time to WE# Address Setup Time to CLK (Notes 2, 3) Address Hold Time to CLK (Notes 2, 3) AVD# Hold Time to CLK Clock Setup Time to WE# Sector Erase Accept Timeout Erase Suspend Latency Toggle Time During Sector Protection Toggle Time During Programming within a Protected Sector Synchronous Min Asynchronous Synchronous Min Asynchronous Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Max Max Typ Typ 5.5 4 5 50 35 100 1 4 4 4 6 15 20 20 0 500 1 50 0 5 5 5 7 5 15 10 20 0 0 0 0 30 20 20 20 12 45 ns ns ns ns ns ns ns ns ns ns µs µs ns ns ns ns ns ns ns µs µs µs µs 5.5 0 6 7 ns Min 75 MHz 45 4 66 MHz 50 54 MHz 55 5 ns Unit ns tWLAX tAH tAVDP tDVWH tWHDX tGHWL tDS tDH tGHWL tCAS tWHEH tWLWH tWHWL tCH tWP tWPH tSR/W tVID tVIDS tVCS tELWL tCS tAVSW tAVHW tACS tACH tAVHC tCSW tSEA tESL tASP tPSP Notes: 1. Not 100% tested. 2. Asynchronous mode allows both Asynchronous and Synchronous program operation. Synchronous mode allows both Asynchronous and Synchronous program operation. 3. In asynchronous program operation timing, addresses are latched on the falling edge of WE# or rising edge of AVD#. In synchronous program operation timing, addresses are latched on the first of either the falling edge of WE# or the active edge of CLK. 4. 5. See the “Erase and Programming Performance” section for more information. Does not include the preprogramming time. May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 69 DATA SHEET AC CHARACTERISTICS VIH Program Command Sequence (last two cycles) Read Status Data CLK VIL tAVDP AVD# tAS Addresses 555h tAH PA VA In Progress VA Data A0h PD tDS tDH Complete CE#f OE# tWP WE# tCS tCH tWHWH1 tWPH tWC tVCS VCCf Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. “In progress” and “complete” refer to status of program operation. 3. Amax–A12 are don’t care during command sequence unlock cycles. 4. CLK can be either VIL or VIH. 5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register. Figure 34. Asynchronous Program Operation Timings: AVD# Latched Addresses 70 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET AC CHARACTERISTICS Program Command Sequence (last two cycles) Read Status Data VIH CLK VIL tAVSW tAVHW AVD# tAS tAH Addresses 555h PA VA In Progress tAVDP VA Data A0h tDS tDH PD Complete CE#f OE# tWP WE# tCH tWHWH1 tCS tWC tVCS VCCf tWPH Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. “In progress” and “complete” refer to status of program operation. 3. Amax–A12 are don’t care during command sequence unlock cycles. 4. CLK can be either VIL or VIH. 5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register. Figure 35. Asynchronous Program Operation Timings: WE# Latched Addresses May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 71 DATA SHEET AC CHARACTERISTICS Program Command Sequence (last two cycles) tAVCH CLK tACS tACH AVD# tAVDP Addresses 555h PA VA In Progress Read Status Data VA Data tCAS CE#f A0h PD tDS tDH Complete OE# tCSW tWP tCH WE# tWHWH1 tWC tWPH tVCS VCCf Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. “In progress” and “complete” refer to status of program operation. 3. Amax–A12 are don’t care during command sequence unlock cycles. 4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK. 5. Either CE# or AVD# is required to go from low to high in between programming command sequences. 6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The Configuration Register must be set to the Synchronous Read Mode. Figure 36. Synchronous Program Operation Timings: WE# Latched Addresses 72 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET AC CHARACTERISTICS Program Command Sequence (last two cycles) tAVCH CLK tAS tAH AVD# tAVDP Addresses 555h PA VA In Progress Read Status Data VA Data tCAS CE#f A0h PD tDS tDH Complete OE# tCSW tWP tCH WE# tWHWH1 tWC tWPH tVCS VCCf Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. “In progress” and “complete” refer to status of program operation. 3. Amax–A12 are don’t care during command sequence unlock cycles. 4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK. 5. Either CE# or AVD# is required to go from low to high in between programming command sequences. 6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The Configuration Register must be set to the Synchronous Read Mode. Figure 37. Synchronous Program Operation Timings: CLK Latched Addresses May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 73 DATA SHEET AC CHARACTERISTICS VIH Erase Command Sequence (last two cycles) Read Status Data CLK VIL tAVDP AVD# tAS Addresses 2AAh tAH SA 555h for chip erase 10h for chip erase VA In Progress VA Data 55h 30h tDS tDH Complete CE# OE# tWP WE# tCS tVCS VCC tCH tWHWH2 tWPH tWC Figure 38. Notes: 1. SA is the sector address for Sector Erase. Chip/Sector Erase Command Sequence 2. Address bits Amax–A12 are don’t cares during unlock cycles in the command sequence. 74 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET AC CHARACTERISTICS CE# AVD# WE# Addresses Data Don't Care A0h PA Don't Care PD Don't Care OE# ACC VID 1 μs tVIDS tVID VIL or VIH Note: Use setup and hold times from conventional program operation. Figure 39. Accelerated Programming Timing May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 75 DATA SHEET AC CHARACTERISTICS AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA tOE tOEZ tCEZ Data Status Data Status Data Notes: 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data# Polling will output true data. 3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode. Figure 40. Data# Polling Timings (During Embedded Algorithm) AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA tOE tOEZ tCEZ Data Status Data Status Data Notes: 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. 3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode. Figure 41. Toggle Bit Timings (During Embedded Algorithm) 76 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET AC CHARACTERISTICS CE# CLK AVD# Addresses VA VA OE# tIACC tIACC Status Data Status Data Data RDY Notes: 1. The timings are similar to synchronous read timings. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. 3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active one clock cycle before data. Figure 42. Synchronous Data Polling Timings/Toggle Bit Timings Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete Erase Suspend Read DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. Figure 43. DQ2 vs. DQ6 May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 77 DATA SHEET AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std tVIDR tVHH tRSP tRRB Description VID Rise and Fall Time (See Note) VHH Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect RESET# Hold Time from RDY High for Temporary Sector Unprotect Min Min Min Min All Speed Options 500 250 4 4 Unit ns ns µs µs Note: Not 100% tested. VID RESET# VIL or VIH tVIDR Program or Erase Command Sequence CE# tVIDR VID VIL or VIH WE# tRSP RDY tRRB Figure 44. Temporary Sector Unprotect Timing Diagram 78 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET AC CHARACTERISTICS VID VIH RESET# SA, A6, A1, A0 Valid* Sector Protect/Unprotect Valid* Verify 40h Sector Protect: 150 µs Sector Unprotect: 15 ms Valid* Data 1 µs CE# 60h 60h Status WE# OE# * For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. Figure 45. Sector/Sector Block Protect and Unprotect Timing Diagram May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 79 DATA SHEET AC CHARACTERISTICS) Address boundary occurs every 64 words, beginning at address 00003Fh: 00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing. C60 CLK Address (hex) AVD# 3C (stays high) C61 3D C62 3E C63 3F C63 3F C63 3F C64 40 C65 41 C66 42 C67 43 tRACC RDY(1) tRACC RDY(2) latency latency tRACC tRACC Data D60 D61 D62 D63 D64 D65 D66 D67 Notes: 1. RDY active with data (A18 = 0 in the Configuration Register). 2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register). 3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not crossing a bank in the process of performing an erase or program. 4. If the starting address latched in is either 3Eh or 3Fh (or some 64 multiple of either), there is no additional 2 cycle latency at the boundary crossing. Figure 46. Latency with Boundary Crossing 80 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET AC CHARACTERISTICS Address boundary occurs every 64 words, beginning at address 00003Fh: (00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing. C60 CLK Address (hex) AVD# 3C (stays high) C61 3D C62 3E C63 3F C63 3F C63 3F C64 40 tRACC RDY(1) tRACC RDY(2) latency latency tRACC tRACC Data D60 D61 D62 D63 Invalid Read Status OE#, CE# (stays low) Notes: 1. RDY active with data (A18 = 0 in the Configuration Register). 2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register). 3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing a bank in the process of performing an erase or program. Figure 47. Latency with Boundary Crossing into Program/Erase Bank May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 81 DATA SHEET AC CHARACTERISTICS Data D0 D1 AVD# Rising edge of next clock cycle following last wait state triggers next burst data total number of clock cycles following AVD# falling edge OE# 1 CLK 0 1 2 3 4 5 6 7 2 3 4 5 number of clock cycles programmed Wait State Decoding Addresses: A14, A13, A12 = “111” ⇒ Reserved A14, A13, A12 = “110” ⇒ Reserved A14, A13, A12 = “101” ⇒ 5 programmed, 7 total A14, A13, A12 = “100” ⇒ 4 programmed, 6 total A14, A13, A12 = “011” ⇒ 3 programmed, 5 total A14, A13, A12 = “010” ⇒ 2 programmed, 4 total A14, A13, A12 = “001” ⇒ 1 programmed, 3 total A14, A13, A12 = “000” ⇒ 0 programmed, 2 total Note: Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”. Figure 48. Example of Wait States Insertion 82 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET AC CHARACTERISTICS Last Cycle in Program or Sector Erase Command Sequence Read status (at least two cycles) in same bank and/or array data from other bank Begin another write or program command sequence tWC tRC tRC tWC CE# OE# tOE tOEH WE# tWPH tWP tDS tDH Data PD/30h RD tGHWL tACC tOEZ tOEH RD AAh tSR/W Addresses PA/SA RA RA 555h tAS AVD# tAH Note: Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while checking the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure valid information. Figure 49. Back-to-Back Read/Write Cycle Timings May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 83 DATA SHEET ERASE AND PROGRAMMING PERFORMANCE Parameter 32 Kword Sector Erase Time 4 Kword 128 Mb Chip Erase Time 64 Mb Word Programming Time Accelerated Word Programming Time Chip Programming Time (Note 3) Accelerated Chip Programming Time 128 Mb 64 Mb 128 Mb 64 Mb 54 9 4 75.5 38 33 17 210 120 226.5 114 99 30 s µs µs s s s s Excludes system level overhead (Note 5) Excludes system level overhead (Note 5) 0.2 103 5 s Typ (Note 1) 0.4 Max (Note 2) 5 s Excludes 00h programming prior to erasure (Note 4) Unit Comments Notes: 1. Typical program and erase times assume the following conditions: 25°C, 1.8 V VCC, 1 million cycles. Additionally, programming typicals assumes a checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 1.65 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed. 4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 20, “Memory Array Command Definitions,” on page 46 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1 million cycles. BGA BALL CAPACITANCE Parameter Symbol CIN COUT CIN2 Notes: 1. 2. Sampled, not 100% tested. Test conditions TA = 25°C, f = 1.0 MHz. Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 4.2 5.4 3.9 Max 5.0 6.5 4.7 Unit pF pF pF DATA RETENTION Parameter Minimum Pattern Data Retention Time Test Conditions 150°C 125°C Min 10 20 Unit Years Years 84 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET PHYSICAL DIMENSIONS VBB080—80-ball Fine-Pitch Ball Grid Array (BGA) 11.5 x 9 mm Package D 0.05 C (2X) A D1 e 8 e 7 6 5 7 SE E1 E 4 3 2 1 M L K J H G F E D C B A INDEX MARK PIN A1 CORNER B 7 6 A1 CORNER 10 NXφb φ 0.08 M C φ 0.15 M C A B SD 0.05 C (2X) TOP VIEW BOTTOM VIEW A2 0.10 C A A1 SEATING PLANE C 0.08 C SIDE VIEW NOTES: PACKAGE JEDEC VBB 080 N/A 11.50 mm x 9.00 mm NOM PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME N φb e SD / SE 0.30 MIN --0.20 0.62 NOM ------11.50 BSC. 9.00 BSC. 8.80 BSC. 5.60 BSC. 12 8 80 0.35 0.80 BSC. 0.40 BSC. 0.40 MAX 1.00 --0.76 NOTE OVERALL THICKNESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT 6 7 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3233 \ 16-038.9h (A3-A6, B3-B6, L3-L6, -M3-M6) DEPOPULATED SOLDER BALLS Note: BSC is an ANSI standard for Basic Space Centering May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 85 DATA SHEET PHYSICAL DIMENSIONS VBD064—64-ball Fine-Pitch Ball Grid Array (BGA) 9 x 8 mm Package D 0.05 C (2X) A D1 8 7 e E 6 5 4 3 2 1 HGFEDCB A 7 SE E1 INDEX MARK PIN A1 CORNER 10 B 6 NXφb φ 0.08 M C φ 0.15 M C A B SD A1 CORNER TOP VIEW 0.05 C (2X) BOTTOM VIEW A A1 SEATING PLANE A2 0.10 C C 0.08 C SIDE VIEW NOTES: PACKAGE JEDEC VBD 064 N/A 8.95 mm x 7.95 mm NOM PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME N φb e SD / SE 0.30 MIN --0.20 0.62 NOM ------8.95 BSC. 7.95 BSC. 5.60 BSC. 5.60 BSC. 8 8 64 0.35 0.80 BSC. 0.40 BSC. NONE 0.40 MAX 1.00 0.30 0.76 NOTE OVERALL THICKNESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 6 7 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3246 \ 16-038.9 Note: BSC is an ANSI standard for Basic Space Centering 86 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006 DATA SHEET command. Updated PPB Program, Erase, Status commands to require Sector Block Address (SBA). DC Characteristics Updated IIO1, ICC1, ICC3, ICC4, ICC6 Test Conditions Updated Input Rise and Fall Times. VCC Power Up Added Ramp Rate information. CLK Characterization Added section. REVISION SUMMARY Revision A (November 5, 2002) Initial release. Revision B (February 2, 2004) Global Incorporated Am29BDS640H specifications from publication 27241. Removed 1.5 V VIO option. Changed 80 MHz speed grade to 75 MHz. In-System Sector Protection/Sector Unprotection Algorithms Changed “Wait 15 ms” to “Wait 1.5 ms.” Password Protection Mode Locking Bit; Persistent Sector Protection Mode Locking Bit Program Command; SecSi Sector Protection Bit Program Command; PPB Program Command; All PPB Erase Command Updated description for these sections. Command Definitions Changed WP to (01000010). Set Configuration Register command is not available in Unlock Bypass Mode Removed Password Protection Locking Bit Read command and Persistent Protection Locking Bit Read Revision B+1 (August 10, 2004) Global Incorporated Am29BDS640H specifications from publication 27241. Updated speed options offered. Revision B2 (September 30, 2005) Ordering Information Added package type VF (Pb-free Package (VBB080)) Revision B3 (May 10, 2006) Added migration and obsolescence information for Am29BDS640H. Removed Preliminary designation from document. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks Copyright © 2002–2006 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 87