XA7K160T-1FFG676Q

XA Kintex-7 FPGA Data Sheet: Overview DS175 (v1.1) May 30, 2019 Product Specification Summary Xilinx® XA Kintex®-7 (Automotive) FPGAs are optimized for performance and power for high-volume automotive applications. Designers can leverage more logic per watt compared to previous generation. Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable an unparalleled increase in system performance, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs. XA Kintex-7 FPGAs also offer many high-end features, such as integrated advanced Analog Mixed Signal (AMS) technology. Analog becomes the next level of integration through the seamless implementation of independent dual 12-bit, 1 MSPS, 17-channel analog-to-digital converters. Most importantly, XA Kintex-7 FPGAs proudly meet the high standards of the automotive grade with a maximum temperature of 125°C. Summary of XA Kintex-7 FPGA Features • Automotive Temperature: o • Q-Grade: Tj= –40°C to +125°C Automotive Standards: o ISO-TS16949 compliant o AEC-Q100 qualification o Production Part Approval Process (PPAP) documentation o Beyond AEC-Q100 qualification is available upon request • Advanced high-performance FPGA logic based on real 6-input look-up table (LUT) technology configurable as distributed memory • 36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering • High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,600 Mb/s. • High-speed serial connectivity with built-in serial transceivers from 500 Mb/s to maximum rate of 8.0 Gb/s, enabling 128 Gb/s bandwidth (full duplex) • A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors. • Single-ended and differential I/O standards with speeds of up to 1.25 Gb/s DS175 (v1.1) May 30, 2019 Product Specification www.xilinx.com 1 XA Kintex-7 FPGA Data Sheet: Overview • 600 DSP48 slices with up to 1,781 GMACs • Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter • Integrated block for PCI Express® (PCIe®), for up to x4 Gen2 Endpoint • Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction • Designed for high performance and lowest power with 28 nm, HKMG, HPL process, 1.0V core voltage process technology • Strong automotive-specific third-party ecosystem with IP, development boards, and design services XA Kintex-7FPGA Summary Tables Table 1: XA Kintex-7 FPGA Device-Feature Table Configurable Logic Blocks (CLBs) Device XA7K160T Logic Cells 162,240 Slices(1) Block RAM Blocks(3) Max Distributed RAM (Kb) 25,350 2,188 DSP48E1 Slices(2) CMTs(4) 18 Kb 36 Kb Max (Kb) 650 325 11,700 600 8 PCIe(5) 1 GTX XADC Blocks 8 1 Total I/O Banks(6) 8 Max User I/O 400 Notes: 1. Each 7 series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs. 2. Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator. 3. Block RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18 Kb blocks. 4. Each CMT contains one MMCM and one PLL. 5. XA Kintex-7 FPGA Interface Blocks for PCI Express support up to x4 Gen 2. 6. Does not include configuration Bank 0. Table 2: XA Kintex-7 FPGA Device-Package Combinations and Maximum I/Os Package(1) FFG676 Size (mm) 27 x 27 Ball Pitch (mm) Device XA7K160T 1.0 GTX(2) 8 I/O HR(3) HP(4) 250 150 Notes: 1. All packages listed are Pb-free. 2. GTX transceivers in FB packages support the following maximum data rates: 8.0Gb/s. Refer to Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS182) for details. 3. HR = High Range I/O with support for I/O voltage from 1.2V to 3.3V. 4. HP = High-performance I/O with support for I/O voltage from 1.2V to 1.8V CLBs, Slices, and LUTs Some key features of the CLB architecture include: • Real 6-input look-up tables (LUTs) • Memory capability within the LUT • Register and shift register functionality DS175 (v1.1) May 30, 2019 Product Specification www.xilinx.com 2 XA Kintex-7 FPGA Data Sheet: Overview The LUTs in 7 series FPGAs can be configured as either one 6-input LUT (64-bit ROMs) with one output, or as two 5-input LUTs (32-bit ROMs) with separate outputs but common addresses or logic inputs. Each LUT output can optionally be registered in a flip-flop. Four such LUTs and their eight flip-flops as well as multiplexers and arithmetic carry logic form a slice, and two slices form a configurable logic block (CLB). Four of the eight flip-flops per slice (one per LUT) can optionally be configured as latches. Between 25–50% of all slices can also use their LUTs as distributed 64-bit RAM or as 32-bit shift registers (SRL32) or as two SRL16s. Modern synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features. Clock Management Some of the key highlights of the clock management architecture include: • High-speed buffers and routing for low-skew clock distribution • Frequency synthesis and phase shifting • Low-jitter clock generation and jitter filtering The XA Kintex-7 FPGA has eight clock management tiles (CMTs), each consisting of one mixed-mode clock manager (MMCM) and one phase-locked loop (PLL). Mixed-Mode Clock Manager and Phase-Locked Loop The MMCM and PLL share many characteristics. Both can serve as a frequency synthesizer for a wide range of frequencies and as a jitter filter for incoming clocks. At the center of both components is a voltage-controlled oscillator (VCO), which speeds up and slows down depending on the input voltage it receives from the phase frequency detector (PFD). There are three sets of programmable frequency dividers: D, M, and O. The pre-divider D (programmable by configuration and afterwards via DRP) reduces the input frequency and feeds one input of the traditional PLL phase/frequency comparator. The feedback divider M (programmable by configuration and afterwards via DRP) acts as a multiplier because it divides the VCO output frequency before feeding the other input of the phase comparator. D and M must be chosen appropriately to keep the VCO within its specified frequency range. The VCO has eight equally-spaced output phases (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). Each can be selected to drive one of the output dividers (six for the PLL, O0 to O5, and seven for the MMCM, O0 to O6), each programmable by configuration to divide by any integer from 1 to 128. The MMCM and PLL have three input-jitter filter options: low bandwidth, high bandwidth, or optimized mode. Low-bandwidth mode has the best jitter attenuation but not the smallest phase offset. High-bandwidth mode has the best phase offset, but not the best jitter attenuation. Optimized mode allows the tools to find the best setting. DS175 (v1.1) May 30, 2019 Product Specification www.xilinx.com 3 XA Kintex-7 FPGA Data Sheet: Overview MMCM Additional Programmable Features The MMCM can have a fractional counter in either the feedback path (acting as a multiplier) or in one output path. Fractional counters allow non-integer increments of 1/8 and can thus increase frequency synthesis capabilities by a factor of 8. The MMCM can also provide fixed or dynamic phase shift in small increments that depend on the VCO frequency. At 1600 MHz, the phase-shift timing increment is 11.2 ps. Clock Distribution Each 7 series FPGA provides six different types of clock lines (BUFG, BUFR, BUFIO, BUFH, BUFMR, and the high-performance clock) to address the different clocking requirements of high fanout, short propagation delay, and extremely low skew. Global Clock Lines In the XA Kintex-7 FPGA, 32 global clock lines have the highest fanout and can reach every flip-flop clock, clock enable, and set/reset, as well as many logic inputs. There are 12 global clock lines within any clock region driven by the horizontal clock buffers (BUFH). Each BUFH can be independently enabled/disabled, allowing for clocks to be turned off within a region, thereby offering fine-grain control over which clock regions consume power. Global clock lines can be driven by global clock buffers, which can also perform glitchless clock multiplexing and clock enable functions. Global clocks are often driven from the CMT, which can completely eliminate the basic clock distribution delay. Regional Clocks Regional clocks can drive all clock destinations in their region. A region is defined as an area that is 50 I/O and 50 CLB high and half the chip wide. XA Kintex-7 FPGAs have between six and eight regions. There are four regional clock tracks in every region. Each regional clock buffer can be driven from any of four clock-capable input pins, and its frequency can optionally be divided by any integer from 1 to 8. I/O Clocks I/O clocks are especially fast and serve only I/O logic and serializer/deserializer (SerDes) circuits, as described in the I/O Logic section. The 7 series devices have a direct connection from the MMCM to the I/O for low-jitter, high-performance interfaces. DS175 (v1.1) May 30, 2019 Product Specification www.xilinx.com 4 XA Kintex-7 FPGA Data Sheet: Overview Block RAM Some of the key features of the block RAM include: • Dual-port 36 Kb block RAM with port widths of up to 72 • Programmable FIFO logic • Built-in optional error correction circuitry The XA Kintex-7 FPGA has 325 dual-port block RAMs, each storing 36 Kb. Each block RAM has two completely independent ports that share nothing but the stored data. Synchronous Operation Each memory access, read or write, is controlled by the clock. All inputs, data, address, clock enables, and write enables are registered. Nothing happens without a clock. The input address is always clocked, retaining data until the next operation. An optional output data pipeline register allows higher clock rates at the cost of an extra cycle of latency. During a write operation, the data output can reflect either the previously stored data, the newly written data, or can remain unchanged. Programmable Data Width Each port can be configured as 32K × 1, 16K × 2, 8K × 4, 4K × 9 (or 8), 2K × 18 (or 16), 1K × 36 (or 32), or 512 × 72 (or 64). The two ports can have different aspect ratios without any constraints. Each block RAM can be divided into two completely independent 18 Kb block RAMs that can each be configured to any aspect ratio from 16K × 1 to 512 × 36. Everything described previously for the full 36 Kb block RAM also applies to each of the smaller 18 Kb block RAMs. Only in simple dual-port (SDP) mode can data widths of greater than 18 bits (18 Kb RAM) or 36 bits (36 Kb RAM) be accessed. In this mode, one port is dedicated to read operation, the other to write operation. In SDP mode, one side (read or write) can be variable, while the other is fixed to 32/36 or 64/72. Both sides of the dual-port 36 Kb RAM can be of variable width. Two adjacent 36 Kb block RAMs can be configured as one cascaded 64K × 1 dual-port RAM without any additional logic. Error Detection and Correction Each 64-bit-wide block RAM can generate, store, and utilize eight additional Hamming code bits and perform single-bit error correction and double-bit error detection (ECC) during the read process. The ECC logic can also be used when writing to or reading from external 64- to 72-bit-wide memories. DS175 (v1.1) May 30, 2019 Product Specification www.xilinx.com 5 XA Kintex-7 FPGA Data Sheet: Overview FIFO Controller The built-in FIFO controller for single-clock (synchronous) or dual-clock (asynchronous or multirate) operation increments the internal addresses and provides four handshaking flags: full, empty, almost full, and almost empty. The almost full and almost empty flags are freely programmable. Similar to the block RAM, the FIFO width and depth are programmable, but the write and read ports always have identical width. First word fall-through mode presents the first-written word on the data output even before the first read operation. After the first word has been read, there is no difference between this mode and the standard mode. Digital Signal Processing - DSP Slice Some highlights of the DSP functionality include: • 25 × 18 twos complement multiplier/accumulator high-resolution (48 bit) signal processor • Power saving pre-adder to optimize symmetrical filter applications • Advanced features: optional pipelining, optional ALU, and dedicated buses for cascading DSP applications use many binary multipliers and accumulators, best implemented in dedicated DSP slices. All 7 series FPGAs have many dedicated, full custom, low-power DSP slices, combining high speed with small size while retaining system design flexibility. Each DSP slice fundamentally consists of a dedicated 25 × 18 bit twos complement multiplier and a 48-bit accumulator, both capable of operating up to 450 MHz. The multiplier can be dynamically bypassed, and two 48-bit inputs can feed a single- instruction-multiple-data (SIMD) arithmetic unit (dual 24-bit add/subtract/accumulate or quad 12-bit add/subtract/accumulate), or a logic unit that can generate any one of ten different logic functions of the two operands. The DSP includes an additional pre-adder, typically used in symmetrical filters. This pre-adder improves performance in densely packed designs and reduces the DSP slice count by up to 50%. The DSP also includes a 48-bit-wide Pattern Detector that can be used for convergent or symmetric rounding. The pattern detector is also capable of implementing 96-bit-wide logic functions when used in conjunction with the logic unit. The DSP slice provides extensive pipelining and extension capabilities that enhance the speed and efficiency of many applications beyond digital signal processing, such as wide dynamic bus shifters, memory address generators, wide bus multiplexers, and memory-mapped I/O register files. The accumulator can also be used as a synchronous up/down counter. DS175 (v1.1) May 30, 2019 Product Specification www.xilinx.com 6 XA Kintex-7 FPGA Data Sheet: Overview Input/Output Some highlights of the input/output functionality include: • High-performance SelectIO™ technology with support for 1600 Mb/s DDR3 • High-frequency decoupling capacitors within the package for enhanced signal integrity • Digitally Controlled Impedance that can be 3-stated for lowest power, high-speed I/O operation The number of I/O pins varies depending on device and package size. Each I/O is configurable and can comply with a large number of I/O standards. With the exception of the supply pins and a few dedicated configuration pins, all other package pins have the same I/O capabilities, constrained only by certain banking rules. The I/O in the XA Kintex-7 FPGA are classified as high range (HR) or high performance (HP). The HR I/Os offer the widest range of voltage support, from 1.2V to 3.3V. The HP I/Os are optimized for highest performance operation, from 1.2V to 1.8V. HR and HP I/O pins in the XA Kintex-7 FPGA are organized in banks, with 50 pins per bank. Each bank has one common VCCO output supply, which also powers certain input buffers. Some single-ended input buffers require an internally generated or an externally applied reference voltage (V REF). There are two VREF pins per bank (except configuration bank 0). A single bank can have only one VREF voltage value. I/O Electrical Characteristics Single-ended outputs use a conventional CMOS push/pull output structure driving High towards V CCO or Low towards ground, and can be put into a high-Z state. The system designer can specify the slew rate and the output strength. The input is always active but is usually ignored while the output is active. Each pin can optionally have a weak pull-up or a weak pull- down resistor. Most signal pin pairs can be configured as differential input pairs or output pairs. Differential input pin pairs can optionally be terminated with a 100Ω internal resistor. All 7 series devices support differential standards beyond LVDS: RSDS, BLVDS, differential SSTL, and differential HSTL. Each of the I/Os supports memory I/O standards, such as single-ended and differential HSTL as well as single-ended SSTL and differential SSTL. The SSTL I/O standard can support data rates of up to 1600 Mb/s for DDR3 interfacing applications. 3-State Digitally Controlled Impedance and Low Power I/O Features The 3-state Digitally Controlled Impedance (T_DCI) can control the output drive impedance (series termination) or can provide parallel termination of an input signal to V CCO or split (Thevenin) termination to VCCO/2. This allows users to eliminate off-chip termination for signals using T_DCI. In addition to board space savings, the termination automatically turns off when in output mode or when 3-stated, saving considerable power compared to off-chip termination. The I/Os also have low power modes for IBUF and IDELAY to provide further power savings, especially when used to implement memory interfaces. DS175 (v1.1) May 30, 2019 Product Specification www.xilinx.com 7 XA Kintex-7 FPGA Data Sheet: Overview I/O Logic I/O Registers and Input Delay All inputs and outputs can be configured as either combinatorial or registered. Double data rate (DDR) is supported by all inputs and outputs. Any input can be individually delayed by up to 32 increments of 78 ps, 52 ps, or 39 ps each. Such delays are implemented as IDELAY. The number of delay steps can be set by configuration and can also be incremented or decremented while in use. ISERDES and OSERDES Many applications combine high-speed, bit-serial I/O with slower parallel operation inside the device. This requires a serializer and deserializer (SerDes) inside the I/O structure. Each I/O pin possesses an 8-bit IOSERDES (ISERDES and OSERDES) capable of performing serial-to-parallel or parallel-to-serial conversions with programmable widths of 2, 3, 4, 5, 6, 7, or 8 bits. By cascading two IOSERDES from two adjacent pins (default from differential I/O), wider width conversions of 10 and 14 bits can also be supported. The ISERDES has a special oversampling mode capable of asynchronous data recovery for applications like a 1.25 Gb/s LVDS I/O-based SGMII interface. Serial Transceivers Some highlights of the serial transceivers include: • High-performance transceivers capable of up to 8.0 Gb/s • Low-power mode optimized for chip-to-chip interfaces Advanced Transmit pre and post emphasis, receiver linear equalization (CTLE), and decision feedback equalization (DFE) for long reach or backplane applications. Auto-adaption at receiver equalization and on-chip Eye Scan for easy serial link tuning. There are eight transceiver circuits in the XA Kintex-7 device. Each serial transceiver is a combined transmitter and receiver. The serial transceivers use ring oscillators to generate a wide frequency tuning range. Lower data rates can be achieved using FPGA logic-based oversampling. The serial transmitter and receiver are independent circuits that use an advanced PLL architecture to multiply the reference frequency input by certain programmable numbers up to 25 to become the bit-serial data clock. Each transceiver has a large number of user-definable features and parameters. All of these can be defined during device configuration, and many can also be modified during operation. DS175 (v1.1) May 30, 2019 Product Specification www.xilinx.com 8 XA Kintex-7 FPGA Data Sheet: Overview Transmitter The transmitter is fundamentally a parallel-to-serial converter with a conversion ratio of 16, 20, 32, or 40. This allows the designer to trade-off datapath width for timing margin in high-performance designs. These transmitter outputs drive the PC board with a single-channel differential output signal. TXOUTCLK is the appropriately divided serial data clock and can be used directly to register the parallel data coming from the internal logic. The incoming parallel data is fed through an optional FIFO and has additional hardware support for the 8B/10B, 64B/66B, or 64B/67B encoding schemes to provide a sufficient number of transitions. The bit-serial output signal drives two package pins with differential signals. This output signal pair has programmable signal swing as well as programmable pre- and post-emphasis to compensate for PC board losses and other interconnect characteristics. For shorter channels, the swing can be reduced to reduce power consumption. Receiver The receiver is fundamentally a serial-to-parallel converter, changing the incoming bit-serial differential signal into a parallel stream of words, each 16, 20, 32, or 40 bits. This allows the FPGA designer to trade-off internal datapath width versus logic timing margin. The receiver takes the incoming differential data stream, feeds it through programmable linear and decision feedback equalizers (to compensate for PC board and other interconnect characteristics), and uses the reference clock input to initiate clock recognition. There is no need for a separate clock line. The data pattern uses non-return-to-zero (NRZ) encoding and optionally guarantees sufficient data transitions by using the selected encoding scheme. Parallel data is then transferred into the FPGA logic using the RXUSRCLK clock. For short channels, the transceivers offers a special low power mode (LPM). Out-of-Band Signaling The transceivers provide out-of-band (OOB) signaling, often used to send low-speed signals from the transmitter to the receiver while high-speed serial data transmission is not active. This is typically done when the link is in a powered-down state or has not yet been initialized. This benefits PCI Express and SATA/SAS applications. Integrated Interface Blocks for PCI Express Designs Highlights of the integrated blocks for PCI Express include: • Compliant to the PCI Express Base Specification 2.1 with Endpoint and Root Port capability • Supports Gen1 (2.5 Gb/s), Gen2 (5 Gb/s), Gen 3 (8 Gb/s) • Advanced configuration options, Advanced Error Reporting (AER), and End-to-End CRC (ECRC) features The XA Kintex-7 device includes one integrated block for PCI Express technology that can be configured as an Endpoint or Root Port, compliant to the PCI Express Base Specification Revision 2.1. The Root Port can be used to build the basis for a compatible Root Complex, to allow custom FPGA-to-FPGA communication via the PCI Express protocol, and to attach ASSP Endpoint devices, such as Ethernet Controllers or Fibre Channel HBAs, to the FPGA. DS175 (v1.1) May 30, 2019 Product Specification www.xilinx.com 9 XA Kintex-7 FPGA Data Sheet: Overview This block is highly configurable to system design requirements and can operate 1, 2, or 4 lanes at the 2.5 Gb/s, 5.0 Gb/s, and 8.0 Gb/s data rates. For high-performance applications, advanced buffering techniques of the block offer a flexible maximum payload size of up to 1,024 bytes. The integrated block interfaces to the integrated high-speed transceivers for serial connectivity and to block RAMs for data buffering. Combined, these elements implement the Physical Layer, Data Link Layer, and Transaction Layer of the PCI Express protocol. Xilinx provides a light-weight, configurable, easy-to-use LogiCORE™ IP wrapper that ties the various building blocks (the integrated block for PCI Express, the transceivers, block RAM, and clocking resources) into an Endpoint or Root Port solution. The system designer has control over many configurable parameters: lane width, maximum payload size, FPGA logic interface speeds, reference clock frequency, and base address register decoding and filtering. Xilinx offers two wrappers for the integrated block: AXI4-Stream and AXI4 (memory mapped). Note that legacy TRN/Local Link is not available in 7 series devices for the integrated block for PCI Express. AXI4-Stream is designed for existing customers of the integrated block and enables easy migration to AXI4-Stream from TRN. AXI4 (memory mapped) is designed for Xilinx Platform Studio/EDK design flow and MicroBlaze™ processor based designs. More information and documentation on solutions for PCI Express designs can be found at: http://www.xilinx.com/technology/protocols/pciexpress.htm. Configuration There are many advanced configuration features, including: High-speed SPI and BPI (parallel NOR) configuration • Built-in MultiBoot and safe-update capability • 256-bit AES encryption with HMAC/SHA-256 authentication • Built-in SEU detection and correction • Partial reconfiguration The XA Kintex-7 FPGAs store their customized configuration in SRAM-type internal latches. The number of configuration bits is between 10 Mb and 31 Mb, depending on device size and user-design implementation options. The configuration storage is volatile and must be reloaded whenever the FPGA is powered up. This storage can also be reloaded at any time by pulling the PROGRAM_B pin Low. Several methods and data formats for loading configuration are available, determined by the three mode pins. The SPI interface (x1, x2, and x4 modes) and the BPI interface (parallel-NOR x8 and x16) are two common methods used for configuring the FPGA. Users can directly connect an SPI or BPI flash to the FPGA, and the FPGA's internal configuration logic reads the bitstream out of the flash and configures itself. The FPGA automatically detects the bus width on the fly, eliminating the need for any external controls or switches. Bus widths supported are x1, x2, and x4 for SPI, and x8 and x16 for BPI. The larger bus widths increase configuration speed and reduce the amount of time it takes for the FPGA to start up after power-on. DS175 (v1.1) May 30, 2019 Product Specification www.xilinx.com 10 XA Kintex-7 FPGA Data Sheet: Overview In master mode, the FPGA can drive the configuration clock from an internally generated clock, or for higher speed configuration, the FPGA can use an external configuration clock source. This allows high-speed configuration with the ease of use characteristic of master mode. Slave modes up to 32 bits wide are also supported by the FPGA that are especially useful for processor-driven configuration. The FPGA has the ability to reconfigure itself with a different image using SPI or BPI flash, eliminating the need for an external controller. The FPGA can reload its original design in case there are any errors in the data transmission, ensuring an operational FPGA at the end of the process. This is especially useful for updates to a design after the end product has been shipped. Customers can ship their products with an early version of the design, thus getting their products to market faster. This feature allows customers to keep their end users current with the most up-to-date designs while the product is already in the field. The dynamic reconfiguration port (DRP) gives the system designer easy access to the configuration and status registers of the MMCM, PLL, XADC, transceivers, and integrated block for PCI Express. The DRP behaves like a set of memory-mapped registers, accessing and modifying block-specific configuration bits as well as status and control registers. Encryption, Readback, and Partial Reconfiguration In the XA Kintex-7 device, the FPGA bitstream, which contains sensitive customer IP, can be protected with 256-bit AES encryption and HMAC/SHA-256 authentication to prevent unauthorized copying of the design. The FPGA performs decryption on the fly during configuration using an internally stored 256-bit key. This key can reside in battery-backed RAM or in nonvolatile eFUSE bits. Most configuration data can be read back without affecting the system's operation. Typically, configuration is an all-or-nothing operation, but the XA Kintex-7 FPGA supports partial reconfiguration. This is an extremely powerful and flexible feature that allows the user to change portions of the FPGA while other portions remain static. Users can time-slice these portions to fit more IP into smaller devices, saving cost and power. Where applicable in certain designs, partial reconfiguration can greatly improve the versatility of the FPGA. XADC (Analog-to-Digital Converter) Highlights of the XADC architecture include: • Dual 12-bit 1 MSPS analog-to-digital converters (ADCs) • Up to 17 flexible and user-configurable analog inputs • On-chip or external reference option • On-chip temperature (±4°C max error) and power supply (±1% max error) sensors • Continuous JTAG access to ADC measurements The XA Kintex-7 FPGA integrates a new flexible analog interface called XADC. When combined with the programmable logic capability of the FPGA, the XADC can address a broad range of data acquisition and monitoring requirements. For more information, go to http://www.xilinx.com/ams. DS175 (v1.1) May 30, 2019 Product Specification www.xilinx.com 11 XA Kintex-7 FPGA Data Sheet: Overview The XADC contains two 12-bit 1 MSPS ADCs with separate track and hold amplifiers, an on-chip analog multiplexer (up to 17 external analog input channels supported), and on-chip thermal and supply sensors. The two ADCs can be configured to simultaneously sample two external-input analog channels. The track and hold amplifiers support a range of analog input signal types, including unipolar, bipolar, and differential. The analog inputs can support signal bandwidths of at least 500 KHz at sample rates of 1MSPS. It is possible to support higher analog bandwidths using external analog multiplexer mode with the dedicated analog input (see UG480, 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide). The XADC optionally uses an on-chip reference circuit (±1%), thereby eliminating the need for any external active components for basic on-chip monitoring of temperature and power supply rails. To achieve the full 12-bit performance of the ADCs, an external 1.25V reference IC is recommended. If the XADC is not instantiated in a design, then by default it digitizes the output of all on-chip sensors. The most recent measurement results (together with maximum and minimum readings) are stored in dedicated registers for access at any time via the JTAG interface. User-defined alarm thresholds can automatically indicate over-temperature events and unacceptable power supply variation. A user-specified limit (for example, 100°C) can be used to initiate an automatic powerdown. DS175 (v1.1) May 30, 2019 Product Specification www.xilinx.com 12 XA Kintex-7 FPGA Data Sheet: Overview XA Kintex-7 FPGA Ordering Information Table 3 shows the speed and temperature grades available in the different devices. Some devices might not be available in every speed and temperature grade. Table 3: XA Kintex-7 FPGA Speed Grade and Temperature Range Speed Grade and Temperature Range Device Automotive (Q) –40°C to +125°C XA Kintex-7 -1Q The XA Kintex-7 FPGA ordering information, shown in Figure 1, applies to all packages including Pb-Free. Refer to the Package Marking section of UG475, 7 Series FPGAs Packaging and Pinout for a more detailed explanation of the device markings. X-Ref Target - Figure 1 Example: X A 7 K 1 6 0 T - 1 F F G 676 Q Device Type Temperature Range: I = Industrial (Tj = –40°C to +100°C) Q = Q-Grade (Tj = –40°C to +125°C) Speed Grade (-1, -2) Number of Pins(1) Pb-Free Package Type 1) Some package names do not exactly match the number of pins present on that package. See UG475, 7 Series FPGAs Packaging and Pinout User Guide for package details. DS197_01_040819 Figure 1: Ordering Information DS175 (v1.1) May 30, 2019 Product Specification www.xilinx.com 13