AMIS-42700

AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet 1.0 Key Features Controller area network (CAN) is a serial communication protocol, which supports distributed real-time control and multiplexing with high safety level. Typical applications of CAN-based networks can be found in automotive and industrial environments. The AMIS-42700 Dual-CAN transceiver is the interface between up to two physical bus lines and the protocol controller and will be used for serial data interchange between different electronic units at more than one bus line. It can be used for both 12V and 24V systems. The circuit consists of following blocks: • Two differential line transmitters • Two differential line receivers • Interface to the CAN protocol handler • Interface to expand the number of CAN busses • Logic block including repeater function and the feedback suppression • Thermal shutdown circuit (TSD) • Short to battery treatment circuit Due to the wide common-mode voltage range of the receiver inputs, the AMIS-42700 is able to reach outstanding levels of electromagnetic susceptibility (EMS). Similarly, extremely low electromagnetic emission (EME) is achieved by the excellent matching of the output signals. 2.0 Key Features • Fully compatible with the ISO 11898-2 standard • Certified “Authentication on CAN Transceiver Conformance (d1.1)” • High speed (up to 1 Mbit/s) • Ideally suited for 12V and 24V industrial and automotive applications • Low EME common-mode-choke is no longer required • Differential receiver with wide common-mode range (+/- 35V) for high EMS • No disturbance of the bus lines with an un-powered node • Transmit data (TxD) dominant time-out function • Thermal protection • Bus pins protected against transients in an automotive environment • Power down mode in which the transmitter is disabled • Short circuit proof to supply voltage and ground • Logic level inputs compatible with 3.3V devices • ESD protection guaranteed up to ±8KV 3.0 Technical Characteristics Table 1: Technical Characteristics Symbol Parameter DC voltage at pin CANH VCANH DC voltage at pin CANL VCANL Differential bus output voltage in dominant state Vi(dif)(bus_dom) Propagation delay TxD to RxD tpd(rec-dom) Propagation delay TxD to RxD t pd(dom-rec) CM-range Input common-mode range for comparator Common-mode peak Common-mode step VCM-peak VCM-step Conditions 0 < VCC < 5.25V; no time limit 0 < VCC < 5.25V; no time limit 42.5Ω < RLT < 60Ω See Figure 7 See Figure 7 Guaranteed differential receiver threshold and leakage current See Figure 8 and 9 (note) See Figure 8 and 9 (note) Min. -45 -45 1.5 70 100 -35 -500 -150 Max. +45 +45 3 245 245 +35 500 150 Unit V V V ns ns V mV mV Notes: The parameters VCM-peak and VCM-step guarantee low EME. AMI Semiconductor – Rev. 1.4, May 05 - Preliminary www.amis.com 1 AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet 4.0 Ordering Information Marketing Name AMIS 42700FHA Package SOIC-20 300 G Temp. Range -40°C…125°C 5.0 Block Diagram VCC 12 Thermal shutdown POR 2 x timer clock VCC CANH1 CANL1 13 Feedbeck Surpression Timer 14 Driver control AMIS-40700 Feedbeck Surpression VCC 19 Timer Driver control 18 CANH2 CANL2 Logic Unit Vcc/2 + Ri(cm) Ri(cm) COMP Ri(cm) COMP Vcc/2 + Ri(cm) PC20050502.1 8 10 3 4 7 9 2 5 6 15 16 17 VREF ENB1 Text Tx0 Rx0 Rint ENB2 GND Figure 1: Block Diagram 6.0 Typical Application 6.1 Application Description AMIS-42700 is especially designed to provide the link between a CAN controller (protocol ic) and two physical busses. It is able to operate in three different modes: • Dual CAN • A CAN bus extender • A CAN bus repeater AMI Semiconductor – Rev. 1.4, May 05 - Preliminary www.amis.com 2 AMIS-42700 Dual High-Speed CAN Transceiver 6.2 Application Schematics Preliminary Data Sheet VBAT CAN BUS 1 CAN BUS 2 5V-reg VCC EN1 10 12 EN2 2 Rx0 7 Tx0 4 3 9 5 PC20050511.6 CD 100 nF Vref 8 13 CANH1 RLT 14 CANL1 CANH2 60 Ω AMIS-42700 19 Text Rint RLT 6 15 16 17 18 CANL2 60 Ω GND Figure 2: Application Diagram CAN-Bus Repeater VBAT CAN BUS 1 CAN BUS 2 5V-reg VCC CD 100 nF VCC EN1 10 EN2 2 Rx0 12 CD 100 nF Vref 8 13 CANH1 RLT 14 CANL1 CANH2 60 Ω µC 7 4 3 9 CAN controller GND Tx0 Text Rint AMIS-42700 19 RLT 5 6 15 16 17 18 CANL2 60 Ω PC20050502.3 GND Figure 3: Application Diagram Dual-CAN AMI Semiconductor – Rev. 1.4, May 05 - Preliminary www.amis.com 3 AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet VBAT CAN BUS 1 CAN BUS 2 5V-reg VCC CD 100 nF VCC EN1 10 12 EN2 2 Rx0 CD 100 nF Vref 8 13 +5 CANH1 RLT 60 Ω µC 7 4 3 9 14 CANL1 CANH2 CAN controller GND Tx0 Text Rint AMIS-42700 19 RLT 5 6 15 16 17 18 CANL2 60 Ω GND +5 CAN BUS 3 CD 100 nF VCC EN1 10 EN2 2 Rx0 Tx0 Text Rint 7 4 3 9 5 6 15 16 17 18 12 CAN BUS 4 Vref 8 13 CANH1 RLT 14 CANL1 CANH2 60 Ω AMIS-42700 19 RLT CANL2 60 Ω PC20050502.9 GND Figure 4: Application Diagram CAN Bus Extender AMI Semiconductor – Rev. 1.4, May 05 - Preliminary www.amis.com 4 AMIS-42700 Dual High-Speed CAN Transceiver 6.3 Pin Description 6.3.1 Pinout (top view) Preliminary Data Sheet NC EN2 Text T x0 GND GND Rx0 Vref1 Rint EN1 1 2 3 20 19 18 NC CANH2 CANL2 GND GND GND CANL1 CANH1 VCC NC AMIS-42700 4 5 6 7 8 9 10 17 16 15 14 13 12 11 PC20050502.2 Figure 4: Pin Configuration 6.3.2 Pin Description Table 2: Pinout Pin Name 1 NC 2 ENB2 3 Text 4 Tx0 5 GND 6 GND 7 Rx0 8 VREF1 9 Rint 10 ENB1 11 NC 12 VCC 13 CANH1 14 CANL1 15 GND 16 GND 17 GND 18 CANL2 19 CANH2 20 NC Description Not connected Enable input, bus system 2 Multi system transmitter input Transmitter input Ground connection, note 1 Ground connection, note 1 Receiver output Reference voltage Multi system receiver output Enable input, bus system 1 Not connected Positive supply voltage CANH transceiver I/O bus system 1 CANL transceiver I/O bus system 1 Ground connection, note 1 Ground connection, note 1 Ground connection, note 1 CANL transceiver I/O bus system 2 CANH transceiver I/O bus system 2 Not connected Notes: 1) In order to ensure the chip performance, these pins need to be connected to GND on the PCB. AMI Semiconductor – Rev. 1.4, May 05 - Preliminary www.amis.com 5 AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet 7.0 Functional Description 7.1 Overall Functional Description The CAN transceiver is specially designed to provide the link between the protocol IC (CAN controller) and two physical bus lines. Data interchange between those two bus lines is realized via the interface. Bitwise arbitration is extended on both buses. A fault like short circuit is limited to that bus line where it occurs. Data interchange from the protocol IC to the other bus system and on this bus system itself can be continued. The transceiver can also be used for only one bus system. If the connections for the second bus system are simply left open it serves as a single transceiver for an electronic unit. For correct operation it is necessary to terminate an open bus. If not, the open bus will disturb the other one, e.g. in case of open load. The bus lines can have two logical states, dominant or recessive. A bus is in the recessive state when the driving sections of all transceivers connected to the bus are passive. The differential voltage between the two wires is approximately zero. If at least one driver is active the bus changes into the dominant state. This state is represented by a differential voltage greater than a minimum threshold and therefore by a current flow through the terminating resistors of the bus line. The recessive state is overwritten by the dominant state. To provide an independent switch-off of the transceiver units for both bus systems by a third device (e.g. the µC) enables inputs for the corresponding driving and receiving sections to be included. 7.2 Transmitter The transceiver includes two transmitters, one for each bus line and a driver control circuit. Each transmitter is implemented as a push and a pull driver. The drivers will be active if the transmission of a dominant bit is required. During the transmission of a recessive bit all drivers are passive. The transmitters have a built-in current limiting circuit that protects the driver stages from damage caused by accidental short circuit to either positive supply voltage or to ground. Additionally a thermal protection circuit is integrated. The driver control circuit ensures that the drivers are switched on and off with a controlled slope to limit EME. The driver control circuit will be controlled itself by the thermal protection circuit, the timer circuit, the ENBx inputs, and the logic unit. The dominant time out timer circuit prevents the output drivers from driving a permanent dominant state (blocking all network communication) if pin Tx0 or the bus lines of the other bus are forced permanently dominant by a hardware and/or software failure (see tdom(TxD)). The enable signal ENBx allows the transmitter to be switched off by a third device (e.g. the µC). In the disabled state (ENBx = high) the corresponding transmitter behaves as in the recessive state and does not depend on the input voltage at Tx0 nor on the state of the other bus system. 7.3 Receiver Two bus receiving sections sense the states of the bus lines. Each receiver section consists of an input filter and a fast and accurate comparator. The aim of the input filter is to improve the immunity against high-frequency disturbances and also to convert the voltage at the bus lines CANHx and CANLx, which can vary from –12V to +12V, to voltages in the range 0 to 5V, which can be applied to the comparators. The output signal of the comparators is gated by the ENBx signal. In the disabled state (ENBX = high) the output signal of the comparator will be replaced by a permanently recessive state and does not depend on the bus voltage. In the enabled state the receiver signal sent to the logic unit is identical to the comparator output signal. AMI Semiconductor – Rev. 1.4, May 05 - Preliminary www.amis.com 6 AMIS-42700 Dual High-Speed CAN Transceiver 7.4 Feedback Suppression Preliminary Data Sheet To provide proper function a feedback suppression must be included. This circuit replaces the reception of a dominant bit detected by the receiving section with a recessive bit if the corresponding transmitter is active. The feedback suppression must be activated immediately after the transmitter is requested to drive, i.e. before the receiver detects the dominant state at the bus. After deactivating the transmitter, the feedback suppression must stay active long enough to guarantee that the corresponding receiver has sufficient time to change its state from dominant to recessive. Including the feedback, suppression is possible because a transmitter becomes active if the other bus system or Tx0 is in the dominant state, so the reception of a dominant bit is already realized and need not be done additionally by this receiving section. Without feedback suppression the whole system would stay constantly in the dominant state after the occurrence of one dominant bit. The logic is implemented in such a way that the suppression blocks in the two busses work independently of each other, and are identical so that both busses have the same priority. Furthermore the oscillation or single pulsing, that could occur at the dominant to recessive edge when the transceiver has received acknowledges from both busses, is avoided with this implementation. If both buses are driven externally and go from dominant to recessive with some delay between each other, no spurious pulses are seen at RINT and Rx0. However, it is possible to have the driving section of one bus going active while that bus is still driven externally. To minimize the chance of this condition, an additional delay of typical 50ns is added that blocks the requirement to drive the driving section after the bus is forced externally from dominant to recessive. 7.5 Logic Unit and CAN Controller Interface The central logic unit provides data transfer from/to the digital interface to/from the two busses and from one bus to the other bus. Digital input stages convert the input voltage at Tx0 and TEXT into a logical value for the logic unit. All digital inputs, including ENBx, have an internal pull up resistor to ensure a recessive state when the input is not connected or is accidentally interrupted. Output stages convert the logical value provided by the logic unit into voltages corresponding to the input signal specification of the CAN controller at Rx0 and RINT. A dominant state on the bus line is represented by a low-level at the digital interface, a recessive state is represented by a high-level. Vref provides an analog voltage of Vcc/2 as a reference for CAN controller with analog inputs. Input and output signals of the logic unit are related in such a way that a dominant state on any bus or Tx0 causes a dominant state on both buses, RINT and Rx0. The output signal at Rx0 corresponds to the inputs Tx0 and TEXT, independent of the state of the two enable inputs. This is realized by an internal logical connection. The pins TEXT and RINT are used for connecting the internal logics of several ICs to obtain versions with more than two bus outputs. If a dominant bit is received from at least one of the two bus systems (under the condition of feedback suppression) or from Tx0, RINT carries the low-level. Otherwise RINT is high. A low-level at TEXT activates both transmitters causing a dominant state on both busses and sets Rx0 to the low-level. A high-level at TEXT does not influence the transceiver. 7.6 Power-on-Reset (POR) While Vcc voltage is below the POR level, the POR circuit makes sure that: • The counter is kept in the reset mode and stable state without current consumption • Inputs are disabled (don't care) • Outputs are high impedant; only Rx0 = high-level • Analog blocks are in power down • Oscillator not running and in power down • CANHx and CANLx are recessive • VREF output high impedant for POR not released AMI Semiconductor – Rev. 1.4, May 05 - Preliminary www.amis.com 7 AMIS-42700 Dual High-Speed CAN Transceiver 7.7 Time Out Timer Preliminary Data Sheet The Tx0 dominant time out timer circuit prevents the output drivers from driving a permanent dominant state (blocking all network communication) if pin Tx0 or the bus lines of the other bus are forced permanently dominant by a hardware and/or software failure. The timer is triggered by a negative edge of the TIMERIN signal. If the duration of the low-level on TIMERIN exceeds the internal timer value TIMERDEL, the timer output TIMEROUT becomes high, disabling the transmitter (bus returns into the recessive state). The timer is reset by a positive edge of the TIMERIN signal. 7.8 Over Temperature Detection A thermal protection circuit is integrated to prevent the transceiver from damage if the junction temperature exceeds thermal shutdown level. Because the transmitter dissipates most of the total power, the transmitter will be switched off only to reduce power dissipation and IC temperature. All other IC functions continue to operate. 7.9 Fault Behavior A fault like a short circuit is limited to that bus line where it occurs, hence data interchange from the protocol IC to the other bus system is not affected. When the voltage at the bus lines is going out of the normal operating range (-12V to +12V), the receiver is not allowed to erroneously detect a dominant state. 7.10 Short Circuits As specified in the maximum ratings, short circuits of the bus wires CANHx and CANLx to the positive supply voltage Vbat or to ground must not destroy the transceiver. To provide sufficient safety for automotive applications the voltage range for permanent short circuits is extended to 50V dc. A short circuit between CANHx and CANLx must not destroy the IC as well. The dedicated comparator (L2VBAT) on CANL pin detects the short to battery and after debounce time-out switches off the affected driver only. The receiver of the affected driver has to operate normally. 7.11 Faulty Supply In case of a faulty supply (missing connection of the electronic unit or the transceiver to ground, missing connection of the electronic unit to Vbat or missing connection of the transceiver to Vcc) the power supply module of the electronic unit will operate such that the transceiver is not supplied, i.e. the voltage Vcc is below the POR level. In this condition the bus connections of the transceiver must be in the POR state. If the ground line of the electronic unit is interrupted, Vbat may be applied to the Vcc pin (measured relative to the original ground potential, to which the other units on the bus are connected). 7.12 Reverse Electronic Unit (ECU) Supply If the connections for ground and supply voltage of an electronic unit (ECU) (max. 50V) which provides Vcc for the transceiver are exchanged, this transceiver has a ground potential which may be up to 50V higher than that of the other transceivers. In this case no transceiver must be destroyed even if several of them are connected via the bus system. Any exchange among the six connections CANH1, CANH2, CANL1, CANL2, ground, and supply voltage of the electronic unit at the connector of the unit must never lead to the destruction of any transceiver of the bus system. AMI Semiconductor – Rev. 1.4, May 05 - Preliminary www.amis.com 8 AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet 8.0 Electrical Characteristics 8.1 Definitions All voltages are referenced to GND. Positive currents flow into the IC. Sinking current means that the current is flowing into the pin. Sourcing current means that the current is flowing out of the pin. 8.2 Absolute Maximum Ratings Stresses above those listed in the following table may cause permanent device failure. Exposure to absolute maximum ratings for extended periods may affect device reliability. Table 3: Absolute Maximum Ratings Symbol Parameter Conditions Min. Max. Unit VCC VCANH VCANL VTxD VRxD VS VREF Vtran(CANH) Vtran(CANL) Vtran(VSPLIT) Vesd(CANL/CANH) Vesd Latch-up Supply voltage DC voltage at pin CANH DC voltage at pin CANL DC voltage at pin TxD DC voltage at pin RxD DC voltage at pin S DC voltage at pin VREF Transient voltage at pin CANH Transient voltage at pin CANL Transient voltage at pin Vsplit ESD voltage at CANH and CANL pin ESD voltage at all other pins Static latch-up at all pins Storage temperature Ambient temperature Maximum junction temperature Note 1 Note 1 Note 1 Note 2 Note 4 Note 2 Note 4 Note 3 0 < VCC < 5.25V; no time limit 0 < VCC < 5.25V; no time limit -0.3 -45 -45 -0.3 -0.3 -0.3 -0.3 -150 -150 -150 -8 -500 -2 -250 -55 -40 -40 +7 +45 +45 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 +150 +150 +150 +8 +500 +2 +250 100 +155 +125 +150 V V V V V V V V V V kV V kV V mA °C °C °C Tstg Tamb Tjunc Notes: 1) Applied transient waveforms in accordance with “ISO 7637 part 3”, test pulses 1, 2, 3a, and 3b (see Figure 4). 2) Standardized human body model (HBM) ESD pulses in accordance to MIL883 method 3015. Supply pin 8 is ±2 kV. 3) Static latch-up immunity: static latch-up protection level when tested according to EIA/JESD78. 4) Standardized charged device model ESD pulses when tested according to EOS/ESD DS5.3-1993. 8.3 Thermal Characteristics Symbol Parameter Conditions Value Unit Rth(vj-a) Rth(vj-s) Thermal resistance from junction to ambient in SO8 package Thermal resistance from junction to substrate of bare die In free air In free air 145 45 K/W K/W AMI Semiconductor – Rev. 1.4, May 05 - Preliminary www.amis.com 9 AMIS-42700 Dual High-Speed CAN Transceiver 8.4 DC Characteristics VCC = 4.75 to 5.25V; V33 = 2.9 to 3.6V; Tjunc = -40 to +150°C; RLT =60Ω unless specified otherwise. Table 4: DC Characteristics Symbol Parameter Supply (pin VCC) Conditions Min. Preliminary Data Sheet Typ. Max. Unit ICC Supply current Dominant; VTXD =0V Recessive; VTXD =VCC Output recessive Output dominant VTxD =VCC VTxD =0V Not tested Silent mode High-speed mode VS =2V VSTB =0.8V 2.0 -0.3 -1 -75 2.0 -0.3 20 15 0.6 x VCC -5 5 0.45 x VCC 0.40 x VCC 2.0 2.0 -2.5 -2.5 3.0 0. 5 1.5 -120 -45 45 0.5 45 4 0 -200 5 30 30 0.75 x VCC 0.25 -10 10 0.50 x VCC 0.50 x VCC 2.5 2.5 3.6 1.4 2.25 0 -70 70 0.7 65 8 VCC +0.8 +1 -350 10 VCC +0.8 50 45 mA mA V V µA µA pF V V µA µA V V mA mA V V V V mA mA V V V mV mA mA V Transmitter Data Input (pin TxD) High-level input voltage VIH Low-level input voltage VIL High-level input current IIH Low-level input current IIL Input capacitance Ci Mode Select (pin S) High-level input voltage VIH Low-level input voltage VIL High-level input current IIH Low-level input current IIL Receiver Data Output (pin RxD) High-level output voltage VOH Low-level output voltage VOL High-level output current Ioh Low-level output current Iol Reference Voltage Output (pin VREF) Reference output voltage VREF Reference output voltage for full common VREF_CM mode range Bus Lines (pins CANH and CANL) Recessive bus voltage at pin CANH Vo(reces)(CANH) Recessive bus voltage at pin CANL Vo(reces)(CANL) IRXD = - 10mA IRXD = 6mA Vo=0.7 x VCC Vo=0.3 x VCC -50µA < IVREF < +50µA -35V