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AMIS-52150

AMIS-52150

  • 厂商:

    AMI

  • 封装:

  • 描述:

    AMIS-52150 - Low-Power Transceiver with Clock and Data Recovery - AMI SEMICONDUCTOR

  • 数据手册
  • 价格&库存
AMIS-52150 数据手册
AMIS-52150 Low-Power Transceiver with Clock and Data Recovery Data Sheet 1.0 Introduction The AMIS-52150 is a cost-effective, ultra-low power single-chip wireless transceiver. It combines the proven Amplitude Shift Key/On-Off Key (ASK/OOK) modulation technology of the AMIS-52050 with data clock recovery. Based on key features, such as dual independent receive channels, Quick Start crystal oscillator, Sniff Mode™ signal acquisition, and data clock recovery, the AMIS-52150 is ideally suited for a wide range of applications, including point-to-point wireless data links, costoptimized wireless monitor solutions, and very low power remote wireless sensors, among others. 2.0 Key Features • • • • • • • • • • • • • • • Data clock recovery Auto slicing of data Very low-power single-chip transceiver Minimal external components Low-power RC oscillator Quick Start crystal oscillator Ultra-low power RF Sniff Mode™, with wake-up on RSSI Internal trim functions reduce external component requirements I2C control interface Serial TX/RX data port Clock generation for an external microprocessor Wake-up on RSSI Antenna diversity dual receiver Internal VCO/PLL tuning varactor Wake-up interrupt to external controller 3.0 Technical Features • Operating frequency range: o Quick Start, from 350MHz to 448MHz o Non-Quick Start, from 300MHz to 768MHz • TX output power: +12dBm • RX sensitivity: o Sniff Mode: -93dBm minimum o Receive: -117dBm minimum @ 1Kbps, with CDR • Data rate: o 1-8Kbps with Manchester Coding o 1-16Kbps with NRZ data • Power requirements: o Receive: 7.5mA (Continuous) o Transmit: 25mA @ full power (50 percent duty-cycle) o Sniff Mode: 75uA (One percent duty-cycle) o Standby: 500nA (RC oscillator running) • Operating voltage: 2.3V to 3.6V • Modulation: ASK/OOK • Xtal start time: 15us (Quick Start) • Sniff ModeTM polling: 0.5ms to 16s (0.5ms or 64ms steps) • PLL lock time: threshold Resolution is set to 0.5mS per step Resolution is set to 64mS per step Delay from RX wakeup to data sampled 2 Time I C and TX/RX are active to indicate a wakeup Delay from wakeup to RSSI being checked Time that receiver is off in Sniff Mode Time allowing receiver to power up (typically >40uS) Delay from data detection to pre-clock output Figure 9: Receiver Data Acquisition in Sniff ModeTM AMI Semiconductor – Apr. 07 – M-20535-006 www.amis.com 15 AMIS-52150 Low-Power Transceiver with Clock and Data Recovery Data Sheet Figure 10: Sniff Timing at RF Energy Detection 9.4 Quick Start There are two oscillators in the AMIS-52150, a low power 10kHz RC oscillator and a crystal oscillator, respectively. The RC oscillator is used to keep the AMIS-52150 running in the ultra-low power mode. This oscillator is used to generate the clock signals for the Sniff ModeTM timers as well as the wake-up timers. Figure 11 shows a block diagram of the clocks in the AMIS-52150. The crystal oscillator provides the reference frequency which is used to generate the RF frequencies for transmission and receiving of data. It is also the reference for all the timing functions in the AMIS-52150. The RC oscillator is in turn used to produce a “kicker” signal when the Quick Start function of the crystal oscillator is needed. Figure 11: Internal Clocks AMI Semiconductor – Apr. 07 – M-20535-006 www.amis.com 16 AMIS-52150 Low-Power Transceiver with Clock and Data Recovery Data Sheet A “kicker” circuit stimulates the crystal oscillator circuit with oscillations close to the final frequency. This significantly reduces the time it TM takes for the oscillator to reach and lock to the final frequency. The Quick Start function is necessary for operation in Sniff Mode . Table 25 lists the Quick Start control registers. For further details, refer to the application note titled “Quick Start Crystal Oscillator Circuit Operation and Set-up”. Table 25: Quick Start Control Registers Quick Start Control Registers Register (HEX) Name 0x03 Kicker Trim 0x0e Kick Config1 Kick Config2 Bits All 4 5 States 0 1 0 1 Comments Trim the internal RC OSC to form a kick-start to the XTAL oscillator Common mode clamp disabled (startup) Common mode clamp enabled (normal) Normal operation Continuous kick On 9.5 Data Detection The RSSI circuit creates an analog voltage waveform (18mV/dB) that follows the signal strength of the RF signal. The data slice circuit then samples that waveform to create the digitized data. The slice circuit in the AMIS-52150 can be programmed to operate in one of three modes; DAC mode, Average mode or Peak mode. The DAC mode compares a fixed slice threshold value to the level in the slice output. The digital data state is determined by the level of the slice output being above or below that fixed threshold. For further details, refer to the application note titled “Setting Up the AMIS-52150 Data Slicing Modes”. Figure 12 shows a typical waveform for the DAC mode, while Table 26 shows the control registers for the auto slice modes. Figure 12: DAC Slice Mode Waveform In the Average mode, the threshold value is generated automatically. This threshold value is then compared to the output of the slice circuit to re-create the digital data. The slice circuit along with an external capacitor are used to generate a charging time constant which is equal to charging to 95 percent of a bit level in two bit time periods. The data protocol should add a header to the data to allow the slice circuit to determine the average level. For further details, refer to the application note titled “Setting Up the AMIS-52150 Data Slicing Modes”. Figure 13 shows a typical waveform for the Average mode. Table 26 shows the control registers for the auto slice modes. AMI Semiconductor – Apr. 07 – M-20535-006 www.amis.com 17 AMIS-52150 Low-Power Transceiver with Clock and Data Recovery Data Sheet Figure 13: Average Slice Mode Waveform In the Peak mode, a threshold value is generated automatically as well. This threshold value is then compared to the output of the slice circuit to re-create the digital data. The operation of the slice circuit is based on an external capacitor with an internal peak detector, in order to arrive at the peak value of the data waveform. The threshold value is set 6dB below this peak value. The capacitor value should be selected so that the peak detector does not discharge during periods of continuous zeros, while being small enough to allow the peak detector to reach the peak value quickly. For further details, refer to the application note titled “Setting Up the AMIS-52150 Data Slicing Modes”. Figure 14 shows a typical waveform for the Peak mode. Figure 14: Peak Slice Mode Waveform AMI Semiconductor – Apr. 07 – M-20535-006 www.amis.com 18 AMIS-52150 Low-Power Transceiver with Clock and Data Recovery Table 26: Auto Slice Control Registers Auto Slice Control Registers Register (HEX) Name 0x0a DATA SLICE THRESHOLD 0x0f HYSTERESIS Data Sheet Bits All 0,1 States AUTOSLICE 2,3 00 01 10 11 00 01 10 11 Comments Set a fixed reference level for the slice output to be compared to in the DAC mode 0mV hysteresis used in the threshold circuit 20mV hysteresis used in the threshold circuit 50mV hysteresis used in the threshold circuit 100mV hysteresis used in the threshold circuit DAC mode used for data detection (DEFAULT) Average mode used for data detection Peak mode used for data detection DAC mode used for data detection 9.6 Data and Clock Recovery Data recovered in a noisy environment or from a weak RF signal is usually jittery. The AMIS-52150 can remove much of that data jitter by recovering a synchronous clock signal from the incoming data. The device can be set to achieve auto slice data detection. The clock and data recovery circuits can be programmed to generate a data clock for synchronously clocking the data output from the transceiver, removing much of the jitter in this process. The AMIS-52150 has an internal PLL that must be programmed to the frequency of the data by setting the values in the FWORD register and setting the coefficients of the filter. If these values are close to the data rate, the device will recover the data clock from the incoming detected data. The CDR circuit can also be set to a given tolerance with respect to the frequency difference between the target data rate and the actual data rate, in order to improve the performance of the CDR function. The CDR circuit can also be configured to reset after a programmed number of data time periods if no data is received. This “stop and check” function allows the CDR circuit to re-acquire the clock data when new data is received, maintaining better clock to data synchronization. Table 27 lists the registers associated with the data and clock recovery function. For further details, refer to the application note titled “AMIS-52150 Clock and Data Recovery Circuit Operation and Set-Up”. AMI Semiconductor – Apr. 07 – M-20535-006 www.amis.com 19 AMIS-52150 Low-Power Transceiver with Clock and Data Recovery Table 27: Data and Clock Recovery Control Registers Data and Clock Recovery Associated Registers Register (HEX) Name Bits States 0x07 FWOR D LSB All 0x08 FWORD All 0x09 FWOR D MSB All 0x0d DATA MUX 6 0 1 CLKMUX 7 0 1 0x10 K0 0,1,2 000 001 010 011 100 101 110 111 K1 4,5,6 000 001 010 011 100 101 110 111 0x11 K2 0,1,2 000 001 010 011 100 101 110 111 FsDIV 4,5,6 000 001 010 011 100 101 110 111 0x12 STOP CHECK 0,1 00 01 10 11 LOOPCLAMP 2,3 00 01 10 11 FREERUN 4 0 1 CRD RESET 5 0 1 AUTO/MANUAL 6 0 RESET 1 SAMPLE 7 00 WINDOW 00 Data Sheet Comments Sets the initial internal clock frequency for the clock and data recovery circuits TX/RX normal signals Recovered data on TX/RX Normal CLKOUT signals Recovered CLOCK output on CLKOUT Filter coefficient gain is 1 Filter coefficient gain is 2 Filter coefficient gain is 4 Filter coefficient gain is 8 Filter coefficient gain is 16 Filter coefficient gain is 32 Filter coefficient gain is 64 Filter coefficient gain is 128 Filter coefficient gain is 1 Filter coefficient gain is 2 Filter coefficient gain is 4 Filter coefficient gain is 8 Filter coefficient gain is 16 Filter coefficient gain is 32 Filter coefficient gain is 64 Filter coefficient gain is 128 Filter coefficient gain is 0.125 Filter coefficient gain is 0.250 Filter coefficient gain is 0.500 Filter coefficient gain is 1.000 Filter coefficient gain is 2 Filter coefficient gain is 4 Filter coefficient gain is 8 Filter coefficient gain is 16 Sample frequency divider is 2 Sample frequency divider is 4 Sample frequency divider is 8 Sample frequency divider is 16 Sample frequency divider is 20 Sample frequency divider is 32 Sample frequency divider is 40 Sample frequency divider is 48 StopCheck bits: disabled StopCheck bits: 2 StopCheck bits: 4 StopCheck bits: 8 Loop clamp value is: +-BaudClk/8 Loop clamp value is: +-BaudClk/16 Loop clamp value is: +-BaudClk/32 Loop clamp value is: +-BaudClk/64 Phase alignment enabled Phase alignment disabled CDR reset disabled CDR reset enabled POR reset (auto) CDR reset enabled (manual) Sampling starts with bit start edge Sampling centered around bit center The clock and data recovery function is dependent on the receiver’s ability to recover the data from the incoming RF signal. There exists a technique to test the clock and data recovery function without having to set up the receiver to receive data. This is a test mode that allows an input data stream (square wave at 1/2 the data rate) on the RSSI pin, with the recovered clock data appearing on the CLKOUT pin and the recovered data appearing on the TX/RX pin, respectively. Once the AMIS-52150 is configured for clock and data AMI Semiconductor – Apr. 07 – M-20535-006 www.amis.com 20 AMIS-52150 Low-Power Transceiver with Clock and Data Recovery Data Sheet recovery (see the application note titled “AMIS-52150 Clock and Data Recovery Circuit Operation and Set-Up”), the register shown in Table 28 can be used to define the test mode operation. Table 28: Clock and Data Recovery Test Mode Clock and Data Recovery Test Control Register Register (HEX) Binary Code HEX Code 0x1d 00001110 0x0e 00001111 0x0f Comments Normal RSSI digital input CDR start bit digital input to RSSI 9.7 Wake-Up Function Ultra-low power applications can take advantage of the wake-up function of the AMIS-52150. The AMIS-52150 can be placed in a low power or “sleep” state until an interrupt based on the programmable wake-up timer is generated. This wakes up the transceiver, which then flags the external microcontroller to perform the required application-specific operations. The wake-up interrupt is also generated based on detection of RF energy (Sniff ModeTM). Communication with the microcontroller takes place via the I2C bus. In addition, when the AMIS-52150 is in the “sleep’” state, the wake-up signal can be generated by the microcontroller. Table 29 lists the registers associated with the wake-up function. Table 29: Application Wake-Up Control Registers Application Wakeup Control Registers Register (HEX) Name Bits 0x14 AW TIMER DIV All 0x15 AW TIMER All 0x17 PRE/POST AW All DELAY States Comments Divides the RC oscillator to form a clock for the AW Number of AW clock periods before a AW wakeup Number of CLKOUT clock periods before the TX/RX pin goes low for a AW cycle 9.8 I2C Interface The I2C is a two pin bi-directional serial interface communication bus, with a data line and a clock line, respectively. Serial data on the data pin is clocked into or out of the AMIS-52150 by the clock pin. The AMIS-52150 is implemented as a slave device, which means that the external controller is the master device. The clock signal for all transmissions between the master (controller) and the slave (AMIS-52150) is generated by the controller. The serial communication bit rate can be as high as 400Kbps. A communication link is initiated based on a start sequence. Bi-directional communication continues as long as the master and slave acknowledge the write or read sequences, and is terminated with a stop sequence. This is illustrated in Figure 15, Figure 16 and Figure 17, respectively. AMI Semiconductor – Apr. 07 – M-20535-006 www.amis.com 21 AMIS-52150 Low-Power Transceiver with Clock and Data Recovery Data Sheet Figure 15: 12C Valid Control Waveforms Figure 16: 12C Protocol in a Write 68 (Hex) or a Data Write Request AMI Semiconductor – Apr. 07 – M-20535-006 www.amis.com 22 AMIS-52150 Low-Power Transceiver with Clock and Data Recovery Data Sheet Figure 17: 12C Write and Read Protocol 9.9 Registers The AMIS-52150 is comprised of 31 registers. For further details, refer to the application note titled “AMIS-52150 Register Definitions and Functions”. 9.10 Power-On-Reset/Brown-Out Detection The POR/brown-out detection circuit ensures that the AMIS-52150 will be in a reset state when VDD drops below a certain threshold voltage, and remains in this state until VDD rises above another threshold voltage. The characteristics of the POR circuit are shown in Figure 18. Figure 18: Power-on-Reset Characteristics AMI Semiconductor – Apr. 07 – M-20535-006 www.amis.com 23 AMIS-52150 Low-Power Transceiver with Clock and Data Recovery Data Sheet 9.11 Alternative Wake-Up Functions Figure 19: Wakeup Circuits The AMIS-52150 will wake up from the low power mode upon a) reception of RF energy, b) an interrupt generated by the wake-up timer, or c) an interrupt generated by the external controller. In this low power mode, the RF circuits, the crystal oscillator, and the CLKOUT circuits are shut off, and only the RC oscillator and the wake-up divider circuitry are active. Once the AMIS-52150 receiver detects RF energy and wakes up, the RX/TX pin is set “low” while the I2CDATA and I2CCLK pins can remain “high”. In addition, when 2 the wake-up timer wakes up the AMIS-52150 to in turn flag the external controller, the TX/RX and I CDATA pins are set “low” while the 2 I CCLK pin can remain “high”. The external controller can also signal the AMIS-52150 to wake up by setting both the I2CDATA and 2 I CCLK lines low. These functions are shown in Table 30. Table 30: Wakeup Truth Table Wakeup Truth Table Wakeup Source SNIFF HK Cycle External TX/RX 0 0 1 I CDATA 1 0 0 2 I CCLK 1 1 0 2 CLKOUT XTAL out RC oscillator Don’t care Comments Wake on RF energy detect Wake due to HK timer timeout Wake due to external controller 10.0 Ordering Information Table 31: Ordering Information Ordering Code Device Number 19293-001-XTP (or -XTD) AMIS-52150 Package Type 20-pin SSOP (209mil, shrink small outline package) Industry Application Industrial, Automotive, other Shipping Configuration Tape & Reel (-XTP) Tube/Tray (-XTD) AMI Semiconductor – Apr. 07 – M-20535-006 www.amis.com 24 AMIS-52150 Low-Power Transceiver with Clock and Data Recovery Data Sheet 11.0 Company or Product Inquiries For more information about AMI Semiconductor‘s products and technologies, visit our Web site at: http://www.amis.com. Devices sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMIS makes no warranty of merchantability or fitness for any purposes. AMIS reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI Semiconductor's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMIS for such applications. Copyright ©2007 AMI Semiconductor, Inc. AMI Semiconductor – Apr. 07 – M-20535-006 www.amis.com 25
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