AMIS-53000

AMIS-53000 Frequency Agile Transceiver Data Sheet AMIS-53000 Frequency Agile Transceiver Data Sheet AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 1 AMIS-53000 Frequency Agile Transceiver Table of Contents Data Sheet 1.0 Overview of the AMIS-53000 .............................................................................................................................................................. 5 1.1 Applications for the AMIS-53000 ...................................................................................................................................................... 5 1.2 Key Features .................................................................................................................................................................................... 5 1.3 Technical Features ........................................................................................................................................................................... 5 1.4 Circuit Overview ................................................................................................................................................................................ 6 1.4.1. Transmitter .......................................................................................................................................................................................................... 6 1.4.2. Receiver ............................................................................................................................................................................................................... 6 2.0 Operational Specifications ................................................................................................................................................................ 8 2.1 Absolute Maximum Ratings .............................................................................................................................................................. 8 2.2 Recommended Operating Conditions ............................................................................................................................................... 8 2.2.1. Parametric Voltage and Current Levels ............................................................................................................................................................ 8 2.3 Operational Specifications ................................................................................................................................................................ 9 3.0 Block Diagrams ................................................................................................................................................................................ 12 3.1 AMIS-53000 Overall Block Diagram ............................................................................................................................................... 12 3.2 Package .......................................................................................................................................................................................... 12 3.2.1. Pin Definition ..................................................................................................................................................................................................... 12 3.2.2. Block Diagram/Pin Definition ........................................................................................................................................................................... 13 3.2.3. Physical Characteristics................................................................................................................................................................................... 14 4.0 Acronyms .......................................................................................................................................................................................... 15 5.0 Hardware Description ...................................................................................................................................................................... 16 5.1 Frequency ....................................................................................................................................................................................... 16 5.2 Receiver .......................................................................................................................................................................................... 18 5.2.1. Receiver Low Noise Amplifier (LNA) ............................................................................................................................................................... 19 5.2.2. IF Filter ............................................................................................................................................................................................................... 20 5.2.3. Data Filter........................................................................................................................................................................................................... 20 5.3 Transmitter ...................................................................................................................................................................................... 20 5.4 Single Antenna Option .................................................................................................................................................................... 21 5.5 Peak................................................................................................................................................................................................ 22 5.6 ADC ................................................................................................................................................................................................ 23 5.7 Control Interface Serial Bus ............................................................................................................................................................ 23 5.8 TX/RX Data Interface Serial Bus .................................................................................................................................................... 24 5.9 System Clock .................................................................................................................................................................................. 25 5.10 Power and Grounds ...................................................................................................................................................................... 25 5.11 Design Suggestions ...................................................................................................................................................................... 26 6.0 User’s Guide ..................................................................................................................................................................................... 28 6.1 Control Serial Interface Bus Description ......................................................................................................................................... 28 6.1.1. Control Interface Protocol ................................................................................................................................................................................ 28 AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 2 AMIS-53000 Frequency Agile Transceiver Data Sheet 6.1.2. Serial Control Interface: Configuration ........................................................................................................................................................... 30 6.1.3. 3-Wire Interface Mode ....................................................................................................................................................................................... 31 2 6.1.4. I C Interface ....................................................................................................................................................................................................... 32 6.2 Command Register ......................................................................................................................................................................... 35 6.3 Functional Flow Diagrams .............................................................................................................................................................. 36 6.4 Frequency ....................................................................................................................................................................................... 40 6.4.1. Frequency Control ............................................................................................................................................................................................ 40 6.4.2. 10kHz Oscillator ................................................................................................................................................................................................ 44 6.4.3. System Clock..................................................................................................................................................................................................... 44 6.4.4. Quick Start ......................................................................................................................................................................................................... 45 6.4.5. Self Calibration .................................................................................................................................................................................................. 45 6.5 Receiver .......................................................................................................................................................................................... 47 6.5.1. Receiver Circuit Brief Overview ...................................................................................................................................................................... 48 6.6 Transmitter ..................................................................................................................................................................................... 57 6.6.1. TX Config ........................................................................................................................................................................................................... 58 6.6.2. Output Power..................................................................................................................................................................................................... 59 6.6.3. Preamble Length ............................................................................................................................................................................................... 59 6.6.4. FM Transmit Data Shaping ............................................................................................................................................................................... 59 6.7 Idle .................................................................................................................................................................................................. 60 6.7.1. Idle Config.......................................................................................................................................................................................................... 60 6.7.2. Sniff Mode Operation ........................................................................................................................................................................................ 61 6.7.3. Burst Transmit Data .......................................................................................................................................................................................... 65 6.7.4. Housekeeping.................................................................................................................................................................................................... 67 6.8 Idle Return ...................................................................................................................................................................................... 68 6.9 EE ................................................................................................................................................................................................... 69 6.9.1. Write EE ............................................................................................................................................................................................................. 69 6.9.2. Load EE .............................................................................................................................................................................................................. 69 6.10 Calibrate ....................................................................................................................................................................................... 69 6.10.1. Internal Trim .................................................................................................................................................................................................... 70 6.10.2. Calibrate Quick Start Oscillator ..................................................................................................................................................................... 71 6.10.3. Calibrate 10kHz Oscillator .............................................................................................................................................................................. 71 6.10.4. Calibrate PLL ................................................................................................................................................................................................... 71 6.10.5. Calibrate LNA .................................................................................................................................................................................................. 71 6.11 ROM 2 REGS ............................................................................................................................................................................... 71 6.12 Chip Reset .................................................................................................................................................................................... 72 6.13 ADC Conversion ........................................................................................................................................................................... 72 6.13.1. ADC Conversion Results................................................................................................................................................................................ 72 6.13.2. Single ADC Conversion .................................................................................................................................................................................. 73 6.13.3. Continuous ADC Conversion......................................................................................................................................................................... 74 7.0 Data Interface .................................................................................................................................................................................... 75 7.1.1. Chip Address MSB1 .......................................................................................................................................................................................... 77 7.1.2. Chip Address LSB............................................................................................................................................................................................. 77 7.1.3. Data Rate/Format .............................................................................................................................................................................................. 77 7.1.4. General Options A............................................................................................................................................................................................. 78 7.1.5. General Options B............................................................................................................................................................................................. 79 7.1.6. Start of Frame .................................................................................................................................................................................................... 80 7.1.7. Data Rate 1......................................................................................................................................................................................................... 80 7.1.8. Data Rate 0......................................................................................................................................................................................................... 80 7.1.9. CRC Polynomial ................................................................................................................................................................................................ 80 7.1.10. Default Length of Packet ................................................................................................................................................................................ 81 7.1.11. Broadcast ID 1 ................................................................................................................................................................................................. 81 7.1.12. Broadcast ID 0 ................................................................................................................................................................................................. 81 7.2 TX/RX Data Interface Protocol ........................................................................................................................................................ 81 7.2.1. AMIS-53000 in Master Mode ............................................................................................................................................................................. 83 7.2.2. AMIS-53000 in Slave Mode ............................................................................................................................................................................... 84 AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 3 AMIS-53000 Frequency Agile Transceiver Data Sheet 7.2.3. Manchester Operation ...................................................................................................................................................................................... 84 7.2.4. Packet Framing ................................................................................................................................................................................................. 84 7.2.5. Use ID ................................................................................................................................................................................................................. 85 7.2.6. Length of Packet Enable .................................................................................................................................................................................. 85 7.2.7. CRC Enable........................................................................................................................................................................................................ 85 7.2.8. SOF Byte ............................................................................................................................................................................................................ 86 7.2.9. Timing Diagrams for Various Packet Framing Modes ................................................................................................................................... 86 8.0 General System Functions .............................................................................................................................................................. 90 8.1 Pull up Disable ................................................................................................................................................................................ 90 8.2 Brown-Out POR .............................................................................................................................................................................. 90 8.3 Temperature Sensor ....................................................................................................................................................................... 90 8.3.1. Crystal Temperature Compensation ............................................................................................................................................................... 91 8.4 Software.......................................................................................................................................................................................... 91 8.4.1. AMIS Part Revision Code ................................................................................................................................................................................. 91 9.0 Built-in Test Functions..................................................................................................................................................................... 92 9.1 TM Unlock Register ........................................................................................................................................................................ 92 9.2 Test Registers ................................................................................................................................................................................. 92 9.2.1. IF Amp Manual Trim A ...................................................................................................................................................................................... 92 9.2.2. IF Amp Manual Trim B ...................................................................................................................................................................................... 92 9.2.3. PLL Manual Trim ............................................................................................................................................................................................... 92 9.2.4. PLL Test Modes................................................................................................................................................................................................. 93 9.2.5. Power Down RF Sections ................................................................................................................................................................................. 93 9.2.6. Analog Test Mode ............................................................................................................................................................................................. 93 9.2.7. RF Test Modes................................................................................................................................................................................................... 93 9.2.8. Analog Test MUX............................................................................................................................................................................................... 93 9.2.9. RF Test MUX ...................................................................................................................................................................................................... 94 9.2.10. Digital Test MUX A .......................................................................................................................................................................................... 94 9.2.11. Digital Test MUX B .......................................................................................................................................................................................... 94 9.2.12. Digital Test MUX C .......................................................................................................................................................................................... 95 9.2.13. Digital Test Mode A ......................................................................................................................................................................................... 95 9.2.14. Digital Test Mode B ......................................................................................................................................................................................... 95 9.2.15. Digital Test Mode C ......................................................................................................................................................................................... 95 9.2.16. Digital Test Mode D ......................................................................................................................................................................................... 95 9.2.17. Memory Test Mode Address .......................................................................................................................................................................... 95 9.2.18. Memory Test Mode Data ................................................................................................................................................................................. 95 10.0 Register Definition.......................................................................................................................................................................... 96 11.0 Applications .................................................................................................................................................................................... 98 12.0 Ordering Information...................................................................................................................................................................... 99 13.0 Company or Product Inquiries ...................................................................................................................................................... 99 AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 4 AMIS-53000 Frequency Agile Transceiver Data Sheet 1.0 Overview of the AMIS-53000 The AMIS-53000 is the latest highly flexible member of AMI Semiconductor’s ASTRIC™ family of single-chip wireless transceivers. It is ideally suited for low to moderate data rate, low power, sub 1GHz, narrow band, FSK/GFSK/OOK, multiple channel, wireless applications in the medical, automotive and industrial markets. The AMIS-53000 can easily be interfaced to a base band processor via a serial interface bus. 1.1 Applications for the AMIS-53000 • • • • • • • • • • • Medical Implantable Communication Systems (MICS) Wireless Medical Telemetry Systems Wireless Sensors RFID Remote Monitoring Access Control and Security Keyless Entry Mobile Wireless Data Terminals Keyless Entry Tire Pressure Monitors Wireless Toys 1.2 Key Features • • • • • • • • • • • • • • Medical implant communication protocol support Very low power single-chip CMOS transceiver Patented Quick Start crystal oscillator Low power receive Sniff Mode™ Periodic transmit using Burst mode Internal low power 10kHz oscillator Internal self calibration functions SPI/I2C interface bus 3-wire/4-wire serial data interface Two analog to digital converter channels Internal fractional N frequency synthesizer On/off shift key/frequency shift key modulation/Gaussian FSK (BT = 1) Internal temperature sensor Minimal external components 1.3 Technical Features • • • • • • Operating voltage range: 2.2 to 3.3V Operating temperature range: -40° to +85oC Operating frequency range: 300 to 928MHz Data rate: o 1 to 19.2kbps (OOK) o 2 to 128kbps (FSK/GFSK) Transmit output power: o +15dBm max (high power) o +0dBm max (low power) Transmit current: 50mA typical (15dBm) AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 5 AMIS-53000 Frequency Agile Transceiver • • • Receiver sensitivity o –115dBm (OOK @ 1kbps) o –105dBm (FSK @ 20kbps) Receiver current: 12mA (continuous) Minimum RX energy detect time: 130uS (Sniff) Data Sheet 1.4 Circuit Overview 1.4.1. Transmitter The AMIS-53000 uses a driver and class E power amplifier to output the on/off shift keyed or frequency shift keyed RF waveforms. The class E power amplifier has two output power ranges allowing more efficient output power for the one setting up to 0dBm output and the other setting for output power greater than 0dBm. The class E power amplifier can achieve output power of +12dBm to +15dBm for frequencies in the range of 300MHz to 915MHz. The output power is programmable in each of the two output power bands. The transmit data can be NRZ or Manchester encoded. Data can also be modulated as on/off shift keyed or frequency shift keyed. Data rates for the OOK modulation can be as high as 19.2kbps. Data rates for the FSK/GFSK modulation can be as high as 128kbps. The carry frequency deviation for the FSK modulation is programmable, typically one half to one times the data rate. The transmit data output can be wave shaped with a Gaussian format. This can reduce the occupied bandwidth of the signal. 1.4.2. Receiver The AMIS-53000 has a single receiver channel and a single transmit channel, which can be connected to individual antennas or can be combined into a single antenna. The receiver uses four different methods to receive and recover data that has been on/off shift keyed or frequency shift keyed modulated. The FSK/GFSK data is recovered using either a PLL circuit or a FFT circuit along with a CDR circuit. The OOK data is recovered using an RSSI circuit along an optional CDR circuit. It is suggested that the CDR circuit be used when receiving OOK signals. 1.4.2.1. On/Off Shift Key Modulation The AMIS-53000 uses a logarithmic received signal strength indicator (RSSI) detector to recover the data from the on/off shift keyed modulated waveform. Data rates can be up to 19.2kbps. The AMIS-53000 has eight discrete data filters for common baud rates. The receiver can detect either NRZ or Manchester encoded data. 1.4.2.2. Low Data Rate Frequency Shift Key Modulation The AMIS-53000 uses a digital PLL detector to recover the data from the frequency shift keyed data below 20kbps. The recovered data waveform is applied to the clock and data recovery circuit to produce the digital data and a synchronized clock. The receiver can detect either NRZ or Manchester encoded data. 1.4.2.3. High Data Rate Frequency Shift Key Modulation The AMIS-53000 uses a fast fourier transform (FFT) to recover data from frequency shift keyed modulated waveforms when the data rate is higher than 20kbps. The data rate can be as high as 128kbps. The demodulated data waveform is applied to the clock and data recovery circuit to produce the digital data and a synchronized clock. The receiver can detect either NRZ or Manchester encoded data. 1.4.2.4. Clock and Data Recovery The AMIS-53000 uses a clock and data recovery circuit along with the frequency shift keyed or on/off shift keyed data detector circuits to recover the data stream. The CDR circuit synchronizes a clock with the data rate of the received data. This same circuit can be used with the on/off shift keyed waveform. AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 6 AMIS-53000 Frequency Agile Transceiver Data Sheet 1.4.2.5. Manchester Data Encoding The AMIS-53000 can encode the data as NRZ or Manchester. 1.4.2.6. Oscillators The AMIS-53000 requires a single external crystal working with the internal VCO and PLL to generate frequencies from 300MHz to 928MHz. The AMIS-53000 has internal capacitors that eliminate the need for external load capacitors when using a typical 24MHz external crystal. The VCO requires an external inductor and capacitor (including internal capacitance) to produce the desired transmit or receive RF frequency. The AMIS-53000 generates the desired RF transmit and receive frequencies from 300MHz to 928MHz by selecting the proper inductor and capacitor value along with programming the frequency in the AMIS-53000. A patented Quick Start circuit is used to force the crystal oscillator on to the desired frequency in microseconds rather than in milliseconds. A low power internal 10kHz oscillator provides the timing for Sniff, Burst and housekeeping. The AMIS-53000 self-calibration circuits can tune this oscillator to within two percent of 10kHz. 1.4.2.7. Interface Serial Bus The AMIS-53000 has separate interfaces for data and control. The transfer of TX/RX data between the AMIS-53000 and an external host/controller is done with a 3-wire serial interface or a 4-wire SPI compatible serial interface. Control information is written to the 2 AMIS-53000 registers or read from the AMIS-53000 registers using either a 3-wire serial interface or a 2-wire I C compatible serial interface. Once the AMIS-53000 configuration registers have data written to them for various operational modes such as, TX, RX, Sniff or other, placing the AMIS-53000 into one of these modes is accomplished through a single write to the command register. TX/RX Data Interface The transmit or receive data interface of the AMIS-53000 can be programmed to be either a proprietary 3-wire serial interface or a 4-wire SPI compatible serial bus. The data interface can be set up to do either data transfers into a buffer in the AMIS-53000 or streaming data (data is transmitted as it is received by the AMIS-53000 or data is sent to the host/controller as it is recovered in the AMIS-53000 receiver). When using the buffered data mode, the AMIS-53000 can be the master or slave, but it must be the master to do streaming data. Once the AMIS-53000 is first powered on, an external host/controller sets the type of interface to the AMIS-53000 (3-wire or I2C) by simply writing to the AMIS-53000 with the desire protocol. The AMIS-53000 will continue to use that interface protocol until power is removed from the AMIS-53000. The AMIS-53000 is always a slave device for the control interface. Control Interface AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 7 AMIS-53000 Frequency Agile Transceiver Data Sheet 2.0 Operational Specifications 2.1 Absolute Maximum Ratings Table 1: Absolute Maximum Ratings Symbol Parameter Vdd Vin Iin Tstrg Tlead ESDHBM ESDCDM ESDMM DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature Human Body Model Charged-Device Model Machine Model Min. -0.3 -0.3 -10.0 -55 Max. 3.6 Vdd+0.3 10.0 150 300 2 750 200 Units V V mA C C kV V V Notes 25C SSOP 10 SEC 2.2 Recommended Operating Conditions Table 2: Operating Conditions Symbol Parameter Vdd Idd Idds Vss Ta DC Supply Dynamic Current Standby Current (off current) Ground Ambient Temperature 0.0 -40 Min. 2.2 Max. 3.3 70 2 0.0 85 Units V mA uA V C Notes (1) Continuous TX (2) Notes: 1. Dynamic current is with the transmitter enabled at maximum output power + 15dBm in FSK mode at 928MHz. 2. Standby current is with all analog cells in power down. Other logic powered up with no clocks running. All outputs unloaded and inputs tied high or low. No floating inputs. 2.2.1. Parametric Voltage and Current Levels (Testing for the below currents assumes a static test setup with measurements performed while static data is applied to the device.) 2.2.1.1. Inputs Iil (1) Max. (V) 1.0 1.0 Min. uA 0.0 0.0 0.0 Max. uA 1.0 1.0 1.0 Min. uA -1.0 -30 -1.0 Iih (1) Max. uA 0.0 -90 0.0 Notes (2) Table 3: Pin Input Parameters Pin Min. (V) AI DISU DISC 0.0 0.0 0.3 0.3 0.8 0.8 Vil Max. (V) Min. (V) Vih Analog input CMOS with pull up Schmitt CMOS Schmitt Notes: 1. Iil and Iih are tested at Vdd = VDDmax volts. Not tested at less than room temperature. 2. PU = Pull up, PD = Pull down, SC = Schmitt, SU = Schmitt & Pull up and SD = Schmitt and Pull down. 3. CMOS values are 'Vin * VDD' and TTL values are absolute voltages. AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 8 AMIS-53000 Frequency Agile Transceiver Data Sheet 2.2.1.2. Outputs Iol (1,3) Min. Max. mA mA 2 Ioh (2,3) Min. mA -2 Max. mA Analog outputs CMOS Table 4: Pin Output Parameters Vol Voh Pin (1) (2) Min. Max. Min. Max. (V) (V) (V) (V) AO DO 0 0.4 Vdd-.4 Notes Notes: 1. Vol, Iol are tested at Vdd = VDDmin volts unless otherwise stated. 2. Voh, Ioh are tested at Vdd = VDDmin volts unless otherwise stated. 3. Polarity on currents indicates direction of current: (+) for sinking and (-) for sourcing. 2.2.1.3. I/O Pins Vol V Max. (1) 0.4 Voh V Min. (2) Vdd-.4 Iol mA Min. (1) 2 Ioh mA Min. (2) -2 Iozl uA Max. (3) 1 Iozh uA Max. (3) -1 Table 5: I/O Pin Parameters Pin A IO DIO 0 0.3 0.8 1 0 Vdd Schmitt Vil V Min. Vil V Max. Vih V Min. Vih V Max. Vol V (1) Voh V (2) Notes Notes: 1. Vol, Iol are tested at Vdd = 3.1 volts. 2. Voh, Ioh are tested at Vdd = 3.1 volts. 3. Ioz is tested with Vdd = 3.5 volts. *** Leakage on I/O pins is typically checked for +/- 10 microamps with the output device turned off and no PU or PD device present. 2.3 Operational Specifications Table 6: Operational Specifications Parameter Min. Typ. Receiver Frequency Range Sensitivity Noise Figure IIP2 IIP3 Image Rejection Input Impedance RSSI Gain IIN ISB Ton TRX_TX/ TTX_RX LAN Input Trim Output Trim 1.2 0.32 4 0.912 pF pF Internal capacitor range for the receiver input Internal capacitor range for the output of the LNA in the receiver Full Shutdown Crystal Mode 14 30 300 -107 -104 6.0 7.8 +60 +5 40 15-j35 72-j62 16 8 2 2 100 100 18 50 928 -114 -111 9.0 MHz dBm dBm dB dBm dBm dB Ω Ω mV/dB mA uA mA us us Receiver current consumption at 900MHz Standby current (no clocks enabled) System clock output enabled (6MHz) Standby to receiver on time Transition time from RX to TX or TX to RX Dual tone test using RSSI Dual tone test using RSSI Modulated desired, single tone interferer @ 900MHz series equivalent @ 433MHz series equivalent @ 10kHz data rate (FSK/GFSK modulation) @ 10kHz data rate (OOK modulation) Max. Units Comment AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 9 AMIS-53000 Frequency Agile Transceiver Table 6: Operational Specifications (Continued) Parameter Min. Typ. Max. Transmitter Frequency Range Ton TTX_RX OOK On/Off Ratio FSK Frequency Separation CW Output Power PHARMONICS TX P A Output Cap. Output Switch R On/Off Ratio Output Harmonics Operating Current Operating Current High MAX Power Power Lo w Power High MAX Power Power Lo w Power Crystal Oscillator Center Frequency Tolerance Startup Time Startup Time Trim Cap Trim Resolution Idd Idd 10kHz Oscillator Output Frequency Operating Current Duty Cycle ADC Resolution FSR Ci Vref Reference Offset fclk Conversion Rate Conversion Time 10 0.01 Vss 1 2.0 1 2 200 8 Vref Bits V pF V %FSR MHz KSPS Tclk Clock frequency Clock rate = 2MHz Full scale input range Input capacitance Internal voltage reference 9.8 300 10 375 50 10.2 450 kHz nA % After trimming After trimming 0 145 160 800 1.5 50 2 50 12 14 -1 15.8 3 16.5 4.5 16.5 4 2 5 60 -35 68 24 17 5.7 17 5 7.5 18 pF Ω dB dBc mA mA dBm dBm dBm dBm Matching network for 50Ω 433MHz high With typical 50Ω matching circuits 15dBm CW 0dBm CW Matching network for 50Ω 928MHz high Internal capacitor range for the PA adjustable trim 300 100 100 60 0 -20 -25 35 200 15 0 928 MHz us us dB kHz dBm dBm dBc Allowable transmit/receive peak deviation Range of output power in the high power mode Range of output power in the low power mode With complete matching network Standby to transmitter on time Transition time from TX to RX Units Comment Data Sheet 24 20 100 5 45 175 MHz ppm us ms pF fF uA mA Trimmed Required crystal tolerance Quick Start enabled Quick Start disabled Internal trim capacitor (self calibration sets) Normal operation During Quick Start AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 10 AMIS-53000 Frequency Agile Transceiver Table 6: Operational Specifications (Continued) Parameter Min. Typ. Max. Data Filter 3dB Down Point Temperature Sensor Output Voltage Voltage Range Slope RSSI Buffer Input Range Operating Current Unity Gain-BW PLL Reference Input Frequency Resolution VCO Gain Constant Settling Time Phase Noise Phase Noise Max Spurious Level POR Delay Time Brown-out Trip 28 1.2 9.62 25.6 12 16 91.55 12 32 100 -90 -120 -70 -80 -110 -50 14.4 38.4 MHz MHz Hz MHz/V MHz/V us dBc/Hz dBc/Hz dBc Transmit mode (24MHz external crystal) Receive mode (24MHz external crystal) Frequency step size @ 900MHz, although layout PCB @ 400MHz parasitics and component @ 900MHz placement will change this value Internal loop filter Internal loop filter @ 10kHz offset Internal loop filter @ 3MHz offset Internal loop filter 0 135 615 185 1000 Vdd 250 1700 V uA kHz 100kΩ/100pF load 0.93 0.61 0.97 0.97 -5.24 1.01 1.4 V V mv/ C o Data Sheet Units %FDATA Comment AM data filter bandwidth (relative to associated defined data rates) At 27 C Output dV/dT o 110 120 130 43 1.6 60 1.8 ms V AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 11 AMIS-53000 Frequency Agile Transceiver Data Sheet 3.0 Block Diagrams 3.1 AMIS-53000 Overall Block Diagram Figure 1: AMIS-53000 Block Diagram 3.2 Package 3.2.1. Pin Definition Table 7: Pin Defi nitions Pin# -001 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LNAvdd RFin RFvss RFout RFpwr Avdd ADC1 ADC2 RSSI PEAK Avss XTAL2 XTAL1 INT Dopt Dssn -002 LNAvdd RFin RFvss RFout RFpwr Avdd ADC1 ADC2 RSSI PEAK Avss XTAL2 XTAL1 INT Dopt Dssn Pin Type Power Analog Input Ground Analog Output Analog Output Power Analog Input Analog Input Analog IO Analog Ground Analog Analog Digital Output Digital Input Digital IO Description A DC short (inductor) is connected to VDD from this pin The RF input to the receiver circuits Ground for the RF circuits RF transmit output Variable DC voltage output to power the RF transmitter (requires a DC short {inductor} connection to Rfout) Vdd power for the analog circuits Input to the analog to digital conversion circuit Input to the analog to digital conversion circuit Analog voltage related to the strength of the received RF Analog voltage for external auto-slice capacitor Ground for the analog circuits Connection to an external crystal Connection to an external crystal Interrupt to external controller Optional data pin for the 4-wire data interface mode Active low select line for the data interface AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 12 AMIS-53000 Frequency Agile Transceiver Table 7: Pin Definitions (Continued) Pin# -001 -002 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Drxtx Dclk SYSclk Dvss Dvdd CoreReg SCLK SDATA xBURST LOOPout LOOPin LOvss LOn LOp LOvdd RFvdd Drxtx Dclk SYSclk Dvss Dvdd SSN SCLK SDATA xBURST LOOPout LOOPin LOvss LOn LOp LOvdd RFvdd Data Sheet Pin Type Digital IO Digital IO Digital Output Ground Power Digital Digital Digital Digital Input Analog Analog Ground Analog Analog Power Power Description Serial data input (transmit) or output (received) Recovered clock output (data interface clock) System clock output Ground for the digital circuits Vdd power for the digital circuits -001 (control and status for the serial data interface) -002 (decoupling capacitor pin for the internal regulator) Bi-directional clock for the 2-wire serial interface Bi-directional data for the 2-wire serial interface Active low input interrupt that will immediately cause a Burst transmission Output to the optional external loop filter Input from the optional external loop filter Ground for the local oscillator circuits Negative side of the VCO tank Positive side of the VCO tank Vdd for the local oscillator circuits Vdd power for the RF circuits 3.2.2. Block Diagram/Pin Definition Figure 2: Block Diagram/Pin Definition * * Not actual package markings. Please see marking format in 3.2.3.3. AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 13 AMIS-53000 Frequency Agile Transceiver Data Sheet 3.2.3. Physical Characteristics 3.2.3.1. Package Type 32 pin LQFP 3.2.3.2. Package Dimensions Table 8: AMIS-53000 LQFP Package Dimensions Symbol Min. Nom. Max. Units Thickness D D1 E E1 e 1.60 mm mm mm mm mm mm 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.80 BSC Figure 3: Package 3.2.3.3. Package Marking Format (AMIS Logo) AMIS53000a 19608-bbb XXXXYZZ Where: a is the market application bbb is the AMIS device version XXXXYZZ is the date and tractability code**** is the country of origin (found on underside of chip). The year in which the mask work was first fixed in a semiconductor chip product may also appear. AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 14 AMIS-53000 Frequency Agile Transceiver Data Sheet 4.0 Acronyms The following acronyms are used in this document. AM ASIC ASK ASSP CCA CDR CRC CW DAC dB dBm DFFT DPLL EE FFT FM FSK GFSK IF kbps kHz LO LOP MHz MICS mV OOK OTA PLL POR RF RSSI SOF VCO Amplitude Modulated signal Integrated circuit designed for a single customer requirement Amplitude Shift Key A custom integrated circuit, that may be used in general designs Clear Channel Assessment Clock and Data Recovery, data is recovered from the received signal using a synchronous clock Cyclic Redundancy Checking; data error checking Continuous Wave, a single frequency or modulated signal carrier Digital to Analog Conversion Decibels; a logarithmic measure of signal level Logarithmic measure of signal level above a milli-watt Digital or Discrete Fast Fourier Transform Digital Phase Locked Loop circuit to create a precise frequency Electrical Erasable Memory Fast Fourier Transform; transform between time and frequency Frequency Modulated signal Frequency Shift Key Gaussian Data Waveform Modulated signal Intermediate Frequency Data rate in thousand bits per second Frequency in kilohertz per second Local Oscillator frequency; used to convert signals between RF frequency and IF frequency Byte indicating the length of a packet Frequency in megahertz Medical Implantable Communication System Milli-volts On/Off method of creating an amplitude modulated signal Transconductance Amplifier Phase Locked Loop circuit to create a precise frequency Power-on-Reset is a threshold circuit for limiting operation at low voltages Radio Frequency Received Signal Strength Indication; measurement of RF signal strength Byte indicating start of packet in data protocol Voltage controlled variable frequency oscillator ASTRIC AMI Semiconductor’s family of wireless products AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 15 AMIS-53000 Frequency Agile Transceiver Data Sheet 5.0 Hardware Description 5.1 Frequency The AMIS-53000 uses an internal VCO, PLL and trim capacitors with an external oscillator crystal to generate the RF frequencies for both TX and RX. The external crystal is a parallel resonant mode crystal with required loading capacitors. The AMIS-53000 contains internal load capacitors, typically sufficient for use with the suggested 24MHz. It is suggested that a 24MHz with 20ppm tolerance be used with the AMIS-53000. Figure 4: External Crystal Circuit The internal VCO requires an external parallel LC to set the frequency for RX or TX. There is an internal capacitance that needs to be considered when selecting the values of the inductor and capacitor. The AMIS-53000 is sensitive to the positioning of the LC components in the layout of the PCB. The traces to the LC need to be as symmetrical as is possible. The location of the LC needs to be as close to the AMIS-53000 pins as is practical. A simple layout change to these parameters can mean that the AMIS-53000 VCO frequency will change causing a need to change the values of the inductor, capacitor and/or the values in the registers controlling the RF frequency. The value of the inductor and/or the capacitor may need to be adjusted to allow the AMIS-53000 to calibrate the PLL for a given frequency of operation. The layout of the printed circuit board for the inductor and capacitor should route traces connecting other components away from the inductor and capacitor pads. The VCO in the AMIS-53000 is a differential negative resistance oscillator (DNRO), commonly found in the literature. It uses an internal voltage variable capacitor (varactor) in combination with an external L and C to provide the desired frequency. The output frequency is found simply by: Where: Ltot and Ctot are the total inductance and capacitance respectively at the VCO pins. This includes the internal capacitance of approximately 2pF. AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 16 AMIS-53000 Frequency Agile Transceiver Data Sheet Figure 5: VCO External LC Circuit The AMIS-53000 has an internal loop filter to work with the PLL in creating the frequency of the device. There is an option to use an external loop filter. Table 9: Internal Loop Parameters Filter Component Value R1 Second Order C1 C2 Additional Pole R C 60 64 3 110 1 Units kΩ pF pF kΩ pF Comments AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 17 AMIS-53000 Frequency Agile Transceiver Data Sheet Figure 6: Optional External Loop Filter Circuit An internal 10kHz oscillator provides timing for functions; Sniff Mode, Burst transmit and housekeeping, when the AMIS-53000 is in its lowest power mode (idle/standby). This oscillator requires no external components. The 10kHz oscillator’s internal trim capacitor is trimmed by 8 bits of trim control in a self calibration. Once the trim is set, the oscillator frequency will be accurate to within two percent over specified voltages and temperatures. 5.2 Receiver The AMIS-53000 has a single channel receiver. The LNA for the receiver input requires a DC connection to ground on the input (must not be an RF ground connection). The LNA for the receiver input requires a DC connection to RFVDD on the output. These connections are supplied through inductors becoming part of the matching circuit for the receiver input. Figure 7: Receiver Input Matching Circuit AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 18 AMIS-53000 Frequency Agile Transceiver 5.2.1. Receiver Low Noise Amplifier (LNA) Data Sheet The receiver input of the AMIS-53000 is a single ended input and single ended output device. The input is matched to 50Ω using an external matching network, which provides a DC path to ground for biasing the receiver’s LNA. The output of the LNA is tuned to the desired operating frequency using an external inductor and on-chip capacitor. The inductor is also provides the LNA with DC supply voltage. On-chip tuning capacitors are binary weighted and digitally controlled. The internal input capacitance is 1.2pF to 4pF. With this capacitance set to the mid value (register set to 0X80), the impedance of the receiver is shown in Figure 8. The internal output capacitance is 0.32pF to 0.912pF. Figure 8: RX Input Impedance AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 19 AMIS-53000 Frequency Agile Transceiver Data Sheet Figure 9: Receiver LNA Output Inductor Selection 5.2.2. IF Filter A passive poly-phase filter and active filtering are used in the AMIS-53000 for frequency selectivity and rejection of the image frequency. It is designed to provide an optimal image rejection of 50dB at 500kHz. 5.2.3. Data Filter The OOK low-pass data filter is used for additional post-detection signal filtering in accordance with the OOK signal data rate (1.2, 1.8, 2.4, 4.8, 7.2, 9.6, 14.4, 19.2kHz). The RSSI buffer is used to drive the RSSI signal off chip for external monitoring, and can also be internally configured for monitoring other signals such as the analog temp sense voltage or bandgap voltage. 5.3 Transmitter The AMIS-53000 transmitter is a two-stage output amplifier. When both stages are selected, the highest output power at frequencies from 300MHz to 928MHz is +15dBm. When only one stage is used, the AMIS-53000 can output up to 0dBm with better power efficiency than when outputting the same power level with both stages. The voltage output level on the RFPWR pin controls the RF output power level of the AMIS-53000. A DC connection must be made between the RFOUT pin and the RFPWR pin. The non-linear output of the AMIS-53000 may require external components to match to a load and to reduce the spurious harmonics. The output impedance of the AMIS-53000 can be matched to the impedance of an external load, using the spreadsheet AMIS53RFMATCH.xls provided by AMIS. This spreadsheet is explained in the application note, AMIS-52X00 Antenna Impedance Matching Considerations. The goal of the transmit output matching with this spreadsheet is to optimize the output power while reducing the harmonic power. AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 20 AMIS-53000 Frequency Agile Transceiver Data Sheet Figure 10: Transmitter Output Matching Circuit 5.4 Single Antenna Option The AMIS-53000 is designed such that when the transmitter is off or the receiver is off, the pins are grounded. This provides a known impedance for the off port (transmit or receive) in combining the receiver and the transmitter to a single antenna. Figure 11: Single Antenna Port T/R Matching Circuit AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 21 AMIS-53000 Frequency Agile Transceiver 5.5 Peak Data Sheet The AMIS-53000 has three modes for slicing the received signal to recover the data. One method is to set a threshold value that is fixed and to which the receiver compares the recovered signal. The other two methods have the AMIS-53000 automatically setting a threshold level to which the receiver compares the recovered signal. Both of these automatic threshold methods require an external capacitor on the PEAK pin to operate. In the averaging method, the AMIS-53000 simply adds a low pass filter with a cutoff frequency set below the data rate filter setting. This second filter extracts an average RSSI level as the data slice threshold. The capacitor on the PEAK pin sets the time constant (corner frequency) for this filter. A typical capacitor value would allow the average level to settle to 95 percent of the RSSI level in 2 bit intervals (remember that Manchester encoding may have transitions twice the data rate). The average threshold method will have chatter before a signal is received and after the signal ends which the external host/controller must be able to handle. In the peak method the AMIS-53000 uses a peak detector to find the maximum input signal level and then sets the threshold 6dB lower than that level. The external peak capacitor is used to bleed or discharge the peak voltage in the circuit. The voltage swing on the -3 RSSI for a typical 12dB signal to noise ratio at 10 BER is 240mV. The capacitor value should not change the voltage by more than this 240mV during a string of zeros. The value is dependent on the number of zeros that are allowed in the chosen data protocol, NRZ or Manchester encoded. Figure 12: Peak Capacitance Circuit AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 22 AMIS-53000 Frequency Agile Transceiver Data Sheet 5.6 ADC The ADC is a successive approximation analog to digital converter, using an internal 8 bit DAC as the reference. The ADC data for the selected input channel(s) will be stored in the associated register, allowing for external access to the conversion data through the serial interface. Conversion speed is register selectable up to 128kS/s. Commands in the control register allow for single or continuous operation of the ADC. A voltage regulator generates the 2.0V reference for the ADC and DAC based upon an internal bandgap voltage source. The ADC has six inputs, two of which are available to the designer for use in their application. 5.7 Control Interface Serial Bus The AMIS-53000 uses a 3-wire or 2-wire I2C interface to communicate with the AMIS-53000 internal registers. The AMIS-53000 will automatically determine which interface to use by determining the states of the three lines; SDATA, SCLK and SSN (the interface is set when the external host/controller writes the first data to the AMIS-53000). Once the AMIS-53000 has determined the type of interface, it will continue with that configuration until power is removed from the part or the part is reset. 2 2 2 I C: If SSN is high and an I C start bit is detected, I C mode is enabled. SPI: If SSN is low, and a negative edge on SCLK detected, SPI mode is enabled. The AMIS-53000 is designed to conform to the Philip Semiconductor I2C standard with the AMIS-53000 as the slave device. Figure 13: I2C Serial Bus Connections AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 23 AMIS-53000 Frequency Agile Transceiver Data Sheet Figure 14: 3-Wire Control Bus Connections 5.8 TX/RX Data Interface Serial Bus The AMIS-53000 uses a 3-wire or 4-wire SPI serial data interface to transfer data between the external host controller and the AMIS-53000. The interface is selected by writing to a register in the AMIS-53000. The DOPT line is undefined in the 3-wire interface. The 4-wire interface of the AMIS-53000 is designed to be compatible with the definition of a standard SPI interface. The AMIS-53000 can be a slave or master device. The status of the AMIS-53000, master or slave, and the interface mode, read or write, determine the definition of the DRXTX and DOPT pin’s as outputs or inputs. Figure 15: SPI Compatible Serial Data Interface AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 24 AMIS-53000 Frequency Agile Transceiver Data Sheet Figure 16: 3-Wire Serial Data Interface 5.9 System Clock The system clock can provide a clock to the external host controller. The clock can be divided down from the 24MHz crystal frequency of the AMIS-53000. When a design desires to use the system clock as the clock to an external host/controller, the system clock can be output under the following: • • • Will be output in RX or TX, unless the output is off in general options B (Bit 1:0). The output will start back up in idle mode after a packet is received. The output will start back up in housekeeping if wake up external host/controller is enabled in housekeeping configuration (Bit 6). Table 10: System Clock Control Mode Control 0X0D General Options B RX TX Standby Idle General Options A Idle Config Bits 1:0 Outputs Frequency: 12, 6, 3MHz or off Comments 2:1 0 4:3 POR state: standby, idle, RX, TX Output in standby Clock cycles before stop 5.10 Power and Grounds The AMIS-53000 has four different power inputs and two different grounds. This allows the design of the AMIS-53000 in an application to separate RF power from the analog and digital power. The same applies to the grounds, where a separate ground plane for the RF grounds can reduce the amount of noise induced into the sensitive RF circuits. AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 25 AMIS-53000 Frequency Agile Transceiver Data Sheet 5.11 Design Suggestions The following schematic and layout suggests at least one way to create a printed circuit board for applications using the AMIS-53000. Figure 17: Typical Design Schematic Figure 18: Typical Design Layout Suggestion AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 26 AMIS-53000 Frequency Agile Transceiver Data Sheet Figure 19: Minimum Design Schematic Figure 20: Minimum Design Layout Suggestion AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 27 AMIS-53000 Frequency Agile Transceiver 6.0 User’s Guide Data Sheet This user’s guide divides the control register description of the AMIS-53000 into functional areas; command register flow diagrams, frequency generation, receiver, transmitter, idle, data/control interfaces, Burst transmit, and MICS features. 6.1 Control Serial Interface Bus Description Table 11: Control Interface Physical Configuration Interface IC 3-Wire 2 Function Control Control Clock Pin SCLK SCLK Source Master Master Data Output SDATA SDATA Input SDATA SDATA Select None SSN AMIS-53000 Slave only Slave only The AMIS-53000 employs two different control interfaces. Communication with the AMIS-53000 control registers is through either a 3-wire bus or through a 2-wire (with third line for control/status) I2C compatible bus. The state of the control bus is detected by the 2 2 AMIS-53000 at the first communication, I C or 3-wire, and is set in that function (3-wire or I C) as long as power remains applied to the part. 3-wire control communication bus 2 I C control communication bus AMIS-53000 is always the slave 6.1.1. Control Interface Protocol The AMIS-53000 control interface allows an external controller to write instructions to the registers of the AMIS-53000 and control the functions of the AMIS-53000. The external controller can also read the registers and status of the AMIS-53000. The control interface 2 can be configured as a slave device in either a 2-wire I C interface bus or a 3-wire serial interface. Figure 21: Control I2C Protocol Format AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 28 AMIS-53000 Frequency Agile Transceiver Table 12: I C Addressing Address 0110100X 01101000 01101001 Description AMIS-53000 I C Address AMIS-53000 Write Command AMIS-53000 Read Command 2 2 Data Sheet Figure 22: 3-Wire Control Protocol Format Table 13: 3-Wire Control (IN1 and IN0) Control Word Bits IN1 0 0 1 1 IN0 0 1 0 1 Single Register Read Single Register Write Sequential Register Read Sequential Register Write Description I2C device address: o 0x68 HEX for device write o 0x69 HEX for device read External controller can write registers AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 29 AMIS-53000 Frequency Agile Transceiver External controller can read registers External controller can issue a immediate transmit via the xBURST input External controller can receive an interrupt (xINT) from the AMIS-53000 Setup registers descriptions: I2C/3-wire select- First write to the interface sets the type of interface until AMIS-53000 is power cycled. Data Sheet 6.1.2. Serial Control Interface: Configuration The AMIS-53000 can automatically detect the type of interface for the serial control bus. The interface pins are then given the definitions as shown in Table 14. The detection depends on the status of the AMIS-53000 pins as shown in Figure 23. Table 14: Control Port Pin Definitions Pin Name SCLK SDATA SSN I C Mode SCL SDA Internal pull up 2 3-Wire Mode SCLK R/W controlled SSN Figure 23: Control Interface Selection Simply addressing the part with the desired protocol performs initial interface selection. After the first communication with the part, the selection is locked until power is removed from the device. The internal logic for determining which protocol to use on initial power up is as follows: 2 2 2 I C: If SSN is high and an I C start bit is detected, I C mode is enabled. 3-wire: If SSN is low, and a negative edge on SCLK detected, 3-wire mode is enabled. The internal pull ups on SCLK and SDATA can also be disabled for I2C applications using external pull ups. Table 15: Control Interface Pull Up Control Mode IC 3-wire 2 SCLK, SDATA Pull Ups Controlled by bit 3 of the general options A register Controlled by bit 3 of the general options A register SSN Pin Configuration Not used (internal pull up) SSN: normal mode AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 30 AMIS-53000 Frequency Agile Transceiver Data Sheet 6.1.3. 3-Wire Interface Mode The AMIS-53000 is always the slave device. Figure 24: Master/Slave for Bi-Directional 3-Wire Mode Figure 24 illustrates the connections between the master SPI port and the slave 3-wire port in the AMIS-53000. Figure 25: Single Control Register Read/Write Using the 3-Wire Interface AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 31 AMIS-53000 Frequency Agile Transceiver Data Sheet Figure 25 shows a single read or single write control data transfer. The operation starts with SSN transitioning low to indicate a start of transfer. The first two bits transferred are the instruction for the slave interface of the AMIS-53000, IN1 and IN0. Following the instruction are the six address bits to specify which address to read or write from. If the instruction is to write a register, the data to be written to address location A is specified with the next 8 bits, D. If the operation is a read, the slave output buffer is enabled at the end of the address bits, and the data bits D are buffered out of the part MSB first. For single read/write, the SSN line can remain active between successive read and write operations. Figure 26: Sequential Control Register Read/Write Using the 3-Wire Interface Figure 26 is a diagram for sequential reads or sequential writes for 3-wire control data transfer. The format of the instruction and address is identical to that for a single read/write operation, with the address corresponding to the first register location to read or write. The first 8 bits of data transferred correspond to the address selected. The address is internally incremented after each data byte transferred. This task is most useful for writing to or reading from variables spanning over multiple address locations such as the fractional PLL word (registers 03-05). The SSN line must be de-asserted at the completion of a sequential read/write in order for the slave SPI controller to correctly interpret the next 8 bits as a command and not data. 2 6.1.4. I C Interface The I2C interface for the AMIS-53000 is compatible with the Philip Semiconductor I2C standard, with the AMIS-53000 as the slave device. AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 32 AMIS-53000 Frequency Agile Transceiver 6.1.4.1. I2C Device Addressing Data Sheet A control byte is the first byte received following the start condition from the master device. The control byte consists of a 7-bits for the device address, and 1-bit for a read or write command. For the AMIS-53000, the device address is ‘0110100’ binary. The last bit of the control byte defines the operation to be performed. When set to ‘1’, a read operation is selected. When set to ‘0’, a write operation is selected. Following the start condition, the AMIS-53000 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving its device address, the AMIS-53000 outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the AMIS-53000 will select a read or write operation. 6.1.4.2. Single Register Write Figure 27: Single Control Data Read/Write with the I2C Interface The master device issues the start condition, then issues the device address, and then issues the single R/W bit, a logic low state. This indicates to the addressed slave receiver that a byte with a register address will follow after the slave has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the register address to be written with data. After receiving another acknowledge signal from the AMIS-53000, the master device will transmit the data word to be written, and the AMIS-53000 will acknowledge again. The write cycle ends with the master generating a stop condition. A similar approach is used to read a register value. The master device issues the start condition, then issues the device address, and then issues the single R/W bit, a logic low state. This indicates to the addressed slave receiver that a byte with a register address will follow after the slave has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the register address to be read. After receiving another acknowledge signal from the AMIS-53000, the master device will immediately follow with another start sequence, however, the R/W bit is now set high telling the slave device that the master wants the contents of the register (addressed with the write command) to be placed on the SDA bus line. After 8 bits of data are read by the master, the master does not acknowledge but sends the stop sequence. AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 33 AMIS-53000 Frequency Agile Transceiver Data Sheet 6.1.4.3. Sequential Register Write Figure 28: Sequential Control Data Read/Write with the I2C Interface When setting the AMIS-53000 up for an application it sometimes is nice to write data to a number of registers one after the other. The write control byte, register address and first data byte are transmitted to the AMIS-53000 in the same way as in a byte write. However, instead of generating a stop condition, the master can continue to write register locations. Upon receipt of each word, the address is internally incremented by ‘1’. If the master should transmit more words than the AMIS-53000 has address locations, the address will roll over. It is a similar approach to read a register value. The write control byte and register address are transmitted to the AMIS-53000 in the same way as in a byte write. After receiving another acknowledge signal from the AMIS-53000, the master device will immediately follow with another start sequence, however, the R/W bit is now set high telling the slave device that the master wants the contents of the register (addressed with the write command) to be placed on the SDA bus line. After the 8 bits are read by the master, the master acknowledges the reception. The AMIS-53000 will increment the register address and continue to output register values. After the last register value is received by the master, the master does not respond with an acknowledge but sends the stop sequence. 6.1.4.4. Current Address Read The internal address counter maintains the last address addressed, incremented by ‘1’. If the last instruction received was to access register N, the current address read operation will read the contents from register N+1. The timing for the current address read is to send a start bit followed by the 7-bit device address, with the R/W bit set to one. The slave will acknowledge, after which the 8-bit register contents will be transmitted. The master does not acknowledge the transmission, but does generate a stop bit. AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 34 AMIS-53000 Frequency Agile Transceiver Data Sheet 6.1.4.5. Interface Options 2 Table 16: I C Address Auto Increment Register Number (HEX) 0X0C 0X0D Name General Options A General Options B Bits 3 5,4 3 Function Disable the internal pull up resistors on SDATA and SSN lines Select a clock rate for the interface when the AMIS-53000 is master Disable auto increment for I C control interface register addressing 2 Additional interface options give the AMIS-53000 the flexibility to tailor the interface to specific requirements. These options are available in the interface options register, and can be stored into EE at board assembly to best suit the application. 6.1.4.6. Pull Up Disable The AMIS-53000 includes built in pull up resistors for use with the I2C operation to reduce the overall system component count. The pull ups are asserted at POR until mode selection occurs. If mode is determined to be 3-wire, the pull ups are removed. If mode is 2 determined to be I C, this option bit determines whether the pull ups are to be removed. 6.2 Command Register The AMIS-53000 contains a single 8-bit register that allows single writes to the register to place the AMIS-53000 into a desired mode. It is very important to remember that all registers associated with that mode must be preprogrammed for the single write to this register to operate correctly. The command register allows the user application to issue a single register write to the AMIS-53000 to initiate the function listed in Table 17. When the function is started, the AMIS-53000 uses the register values associated with the function selected as the parameters of the function. These register values will be the default values or the values the user application has written to the registers before the function is called out in the command register. Table 17: Command - 0X00 [0] Bit Command [7:4] [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1111 [5:0] XXXXXX 100000 XXXXXX 100000 Standby Receive Transmit Idle Idle Return Write EE Read EE Calibrate QS Osc Calibrate RC Calibrate PLL Calibrate LNA ROM2Regs Global Reset Single ADC Conversion Continuous ADC Conversions Comment Put the part into standby Put the part into receive mode Put the part into transmit mode Put the part into idle mode Use to return to idle after interrupt for HK or receive during sniff Write the content of the working registers into EE Read the contents of the EE Calibrates the Quick Start oscillator Calibrates the 10kHz RC oscillator Calibrates the PLL Calibrates the LNA matching Write the content of the ROM into the shadow registers Resets the part completely Do an ADC one time on the channel selected loop filter output Do an ADC on the channel selected continuously loop filter output 0000 [7:6] 01 11 Standby is both a state for the transceiver, and a command given to the transceiver. The actual operation of standby mode can be either a low-power mode where all internal circuitry of the AMIS-53000 except for the interface will be disabled, or a clock-only mode where the crystal oscillator will be enabled to continue providing a system clock for an external microprocessor. A bit available in the general options A register allows selection of power-down or clock-only operation in standby mode. AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 35 AMIS-53000 Frequency Agile Transceiver Data Sheet Many of the instructions for the part are finite in duration and the end point of the task is controlled by the AMIS-53000, such as the calibration instructions. For these instructions, the AMIS-53000 will return to its standby mode at the completion of the task. The user may poll the Status/Flag 1 register busy bit to determine the completion of the calibration instruction. Other instructions such as receive or transmit are indefinite in length and user controlled. To return to the standby state, the AMIS-53000 waits for the standby instruction to end receive or transmit, at which point the transceiver will return to its standby state. Note that there are two low-power modes for the AMIS-53000; standby and idle. Standby allows the SYSCLK output Idle is the very low power state without SYSCLK output 6.3 Functional Flow Diagrams Figure 29: Receiver Flow Diagram AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 36 AMIS-53000 Frequency Agile Transceiver Data Sheet Figure 30: Transmit Flow Diagram AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 37 AMIS-53000 Frequency Agile Transceiver Data Sheet Figure 31: Multi-Channel TX/RX AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 38 AMIS-53000 Frequency Agile Transceiver Data Sheet Figure 32: Idle State Flow Diagram AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 39 AMIS-53000 Frequency Agile Transceiver Data Sheet Figure 33: EE Flow Diagram 6.4 Frequency The AMIS-53000 uses an internal PLL/VCO to generate the RF frequencies for both transmit and receive. Only one set of registers needs to be programmed to generate the TX frequency and to generate the LO frequency to produce the mixing frequency for converting the received signal to the low IF (about 500kHz). The AMIS-53000 can do a self-calibration, which will trim internal capacitance to tune the TX and RX frequencies. The AMIS-53000 needs to run the self-calibration (must be started by the external host/controller) at least once between startup and entering a command such as TX, RX, Sniff, etc. 6.4.1. Frequency Control AMIS has developed an executable program (AMIS-53CALC.exe, available from AMIS, which generates the register values for the frequency divider and fractional word to produce a given frequency. First, the AMIS-53000 must have the correct LC for the desired frequency connected to the VCO pins. There is internal capacitance that is part of the capacitance for determining the value of the inductor. The following equation can be used to determine the approximate value of the LC components. Remember that the VCO is sensitive to the placement of the LC components - they should be placed as close to the AMIS-53000 as practical (even short traces add significant parasitics) and the traces to the components should be made symmetrical. Where: Ltot and Ctot are the total inductance and capacitance respectively at the VCO pins. This includes the internal capacitance of approximately 2pF. The RF PLL is a 24-bit Sigma Delta based fractional N synthesizer used to provide the LO signal for receive, and a direct RF output for transmit. AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 40 AMIS-53000 Frequency Agile Transceiver Setup registers descriptions: Data Sheet RF Divider- The RF frequency of the receiver must be configured. This is done in two steps, one is setting the RF divider and the other is setting the fractional N word. RF Frequency- Program the 3 register fractional N word. Peak Deviation- When the data modulation is to be FSK, the 2 register peak deviation must also be set. The deviation should be set to a value between ½ and 1 times the data rate. PLL- Configure the parameters for the PLL. Loop Filter- Configure the parameters for the loop filter. 6.4.1.1. RF Divider Setting the RF channel frequency is done through the RF divider register, along with the RF frequency 2, 1 and 0 registers. The RF divider register is used to specify the integer portion of the divide value, and the RF frequency 2, 1 and 0 registers are used to specify the fraction. The values are calculated as follows: Where FChannel is the desired RF center frequency. The value for the RF divider register is found by, Where integer is the value used for RF divider. The last step is to calculate the fractional value. This is done as, Fraction is the value to be used in the RF frequency 2, 1 and 0 registers. As an example, if the desired RF frequency channel is 903.5MHz, For this example, the RF divider register is written to 0x26, RF frequency 2 is written to 0xFE, RF frequency 1 to 0x95, and RF frequency 0 to 0x54.This value +/- 1 is fed directly to the PLL as N0 and N1. (i.e. if 63, send 64 and 65 to the PLL) Table 18: RF Divider - 0X05 [5] Bit Name 7:0 RF_divide [7:0] Comment 00h through 0Bh: not allowed 1Ah: divide by 26 1Bh: divide by 27 ----------4Ah: divide by 74 4Bh: divide by 75 4Ch through FFh: not allowed AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 41 AMIS-53000 Frequency Agile Transceiver Data Sheet 6.4.1.2. RF Frequency 2 Table 19: RF Frequency 2 = 0X06 [6] Bit Name Comment 7:0 RF_FREQ [23:16] Upper 8 bits of the RF fraction 6.4.1.3. RF Frequency 1 Table 20: RF Frequency 1 - 0X07 [7] Bit Name Comment 7:0 RF_FREQ [15:8] Center 8 bits of the RF fraction 6.4.1.4. RF Frequency 0 Table 21: RF Frequency 0 - 0X08 [8] Bit Name Comment 7:0 RF_FREQ [7:0] Lower 8 bits of the RF fraction 6.4.1.5. Peak Deviation 1 The peak deviation for FSK transmissions is determined by the peak deviation 1 register and the peak deviation 0 register. This value is also used inside the DFT FSK detector. Calculation of the value for the peak deviation is straightforward: The result of this equation, converted to Hex, is entered into the peak deviation registers. Table 22: Peak Deviation 1 - 0X09 [9] Bit Name Comment 7:0 PEAK_DEV [15:8] Upper 8 bits of the peak deviation 6.4.1.6. Peak Deviation 0 Table 23: Peak Deviation 0 - 0X0A [10] Bit Name Comment 7:0 PEAK_DEV [7:0] Lower 8 bits of the peak deviation AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 42 AMIS-53000 Frequency Agile Transceiver Data Sheet 6.4.1.7. RF PLL Options Contains general options for the setup of the RF PLL. Table 24: RF PLL Options - 0X28 [40] Bit Name State 7 6 5 4 3 2 Internal Loop Filter Charge Pump Current 1 0 1 0 11 01 10 00 50uA 25uA Ivco= 1.2mA Ivco= 800uA Ivco= 600uA Ivco= auto level control Enable using the internal loop filter for the PLL (used for calibration) 1 Kicker Calibration Status Temperature Compensation Curve 0 1 0 Comment The kicker has been calibrated The kicker has not been calibrated Use the Type 1 compensation for external crystal with curves similar to Type 1 (See Figure 32) Use the Type 2 compensation for external crystal with curves similar to Type 2 (See Figure 33) 1 Ivco[1:0] Figure 34: Typical Crystal Temperature Curve for Crystal with Type 1 Characteristics AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 43 AMIS-53000 Frequency Agile Transceiver Data Sheet Figure 35: Typical Crystal Temperature Curve for Crystal with Type 2 Characteristics 6.4.1.8. Loop Filter Table 25: Loop Filter - 0X39 [57] Bit Name 7:0 LOOP_FILTER [7:0] Comment Internal loop filter 6.4.2. 10kHz Oscillator The AMIS-53000 has an internal 10kHz oscillator. This oscillator is running whenever the AMIS-53000 is in standby or idle modes. This very low power oscillator provides the clock for timing functions such as Sniff receive, Burst transmit or housekeeping. The oscillator is trimmed in the calibration instructions. Setup registers descriptions: 10k Oscillator Trim- The value of the calibration for the 10kHz oscillator. (See Section 6.10.1.4)** 6.4.3. System Clock The AMIS-53000 provides a divided version of the external reference oscillator (typically 24MHz) as an output to an external host/controller or other circuits needing a clock. AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 44 AMIS-53000 Frequency Agile Transceiver Table 26: System Clock Control Register Number (HEX) Name Bits Data Sheet Function 11 POR starts in TX 0X0C General Options A 2,1 10 POR starts in RX 01 POR starts in idle 00 POR starts in standby Standby mode with system clock output 11 External XTAL reference divided by 2 (12MHz) 10 External XTAL reference divided by 4 (6MHz) 01 External XTAL reference divided by 8 (3MHz) 00 System clock off 11 System clock continues for 1024 clock cycles 10 System clock continues for 512 clock cycles 01 System clock continues for 256 clock cycles 00 System clock shuts down after idle command ASAP 0 0X0D General Options B 1,0 0X10 Idle Config 4,3 Setup registers descriptions: Crystal Oscillator Trim- The value of the calibration for the 10kHz oscillator. (See Section 6.10.1.1)** 6.4.4. Quick Start The AMIS-53000 includes the ASTRIC family patented Quick Start oscillator. This circuit uses a “kicker” to force the crystal oscillator close to the final desired frequency. This reduces the time required for the crystal oscillator to settle to the RF frequency. Table 27: Kicker Calibration Register Number (HEX) 0X28 Name RF PLL Options Bits 7 Function Kicker calibration status Setup registers descriptions: Quick Start Trim- The value of the calibration for the kicker. (See Section 6.10.1.3)** 6.4.5. Self Calibration The AMIS-53000 has internal trim functions for the PLL, TX PLL, RX PLL, 10kHz oscillator, and kicker (Quick Start). A self calibration is started by writing an instruction to the command register. This self calibration needs to be done at least once after the AMIS-53000 has been powered on and before the AMIS-53000 is placed into any mode such as transmit or receive. The application should monitor the status registers and trim value registers to determine that the calibration was successful. Table 28: Self Calibration Command Register Number (HEX) Name Code 0X07 0X00 Command 0X08 0X09 0X0A 0X1B Housekeeping Config Bit 2 Bit 1 Bit 0 Function Calibrate the Quick Start (kicker) Calibrate the 10kHz oscillator Calibrate the PLL Calibrate the LNA Calibrate PLL during HK Calibrate 10kHz oscillator during HK Calibrate kicker during HK AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 45 AMIS-53000 Frequency Agile Transceiver Setup registers descriptions: Status- Contains the results of calibrations, instructions and activity in the AMIS-53000. Software State- Shows the current mode of the AMIS-53000. Data Sheet 6.4.5.1. Status/Flag1 The purpose of the Status1 register is to provide information back to the host on the status of the part. This register should be queried at the completion of calibration sequences to ensure proper operation. The flags will be reset when the register is read. CheckSum indicates whether an attempt to read or write the EE has failed due to an incorrect CheckSum. Instruction enable indicates that the AMIS-53000 is ready to receive an instruction. This can be used to insure that the AMIS-53000 does not miss a command instruction due to the AMIS-53000 not being ready. Along with the busy flag, these status flags can police the flow of commands to the AMIS-53000. Table 29: Status/Flag1 - 0X01 [1] Bit Name State 7 6 5 4 3 2 1 0 PLL xLock TX PLL Cal RX PLL Cal RC Cal Quick Start Cal CheckSum Instruction Enable ADC Done 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ADC conversion complete The AMIS-53000 is in a state of operation that can accept instructions EE CheckSum failed Quick Start calibration failed 10kHz RC oscillator calibration failed PLL calibration for receive failed PLL calibration for transmit failed Comment PLL out of lock on startup (RX, TX, Sniff, Burst) 6.4.5.2. Status/Flag2 The Status2 register provides information on the operating status of the part. The busy bit is asserted for any of the following reasons: Calibration: The busy bit will remain high for the duration of a calibration sequence. Status2 can be repeatedly polled during a calibration sequence to determine when it’s complete. Read/Write EE: While the AMIS-53000 is reading from or writing to the EE, the busy bit will remain set. Buffered RX: When in receive mode, and a valid chip ID is found, the AMIS-53000 will begin processing of this packet. During the time the packet is being processed, the busy bit will be set high. Buffered TX: After the command is given for transmit with the buffered packet option enabled, the busy bit will remain high until the part has completed the actual transmission of the packet. Housekeeping: Busy is asserted during a housekeeping cycle. Burst TX: Busy is asserted during a Burst transmission. AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 46 AMIS-53000 Frequency Agile Transceiver Data Sheet Status2 also contains information on the reason an interrupt was issued to the external host. The CCA channel status bits provide information back to the host on which channel within the MICS band is being used for communication. After a CCA enabled transmission, these bits will be set to indicate which channel was used. For MICS enabled receivers performing multi-channel Sniff, these bits are used to indicate the channel upon which either energy or an entire packet was found. If CCA is enabled for operation other than MICS, bit 0 (CCA failed) is used to indicate whether or not the channel is clear. The flags will be reset when the register is read. Table 30: Status/Flag2 - 0X02 [2] Bit Name State CCA Channel 7:4 [3:0] 111 110 101 Interrupt Type 100 3:1 011 010 001 000 1 0 Busy 0 Comment Indicates channel selected during CCA RX CRC failed Receive energy dwell timer timed out CCA failed Transmit complete Buffer data for TX Data has been received Housekeeping Low battery AMIS-53000 is busy 6.4.5.3. Software State Displays the current mode of the AMIS-53000. This status register can be used to monitor the activity of the AMIS-53000. Table 31: Software State - 0X3C [60] Bit Name State 1111 1011 1010 1001 1000 0111 Software State 7:0 0110 0101 0100 0011 0010 0001 0000 Comment Undetermined Startup Copying ROM data to registers Calibrating LNA Calibrating PLL Calibrating 10kHz oscillator Calibrating Quick Start (kicker) oscillator Reading EE data Writing EE data Idle Transmitting Receiving Standby 6.5 Receiver The AMIS-53000 receiver is designed for either on/off shift key (AM) modulated signals or frequency shift key (FM) modulated signals. The receiver includes all the circuitry to recover data from either the OOK or the FSK modulated signal carrier. The receiver operates on fixed frequencies in the operating frequency range of 300 to 928MHz using an internal fractional N PLL to set the frequency. The receiver can reduce power consumption using the Sniff Mode to acquire the incoming signal. The receiver can set a user defined fixed threshold for data detection or it can form a threshold from the incoming signal for determining the presence of signal and the state of the recovered waveform. The receiver can use a synchronous data detector to extract the data clock and the data from the incoming signal (FSK modulation always uses this method of data detection). OOK modulation (AM) o Manchester encoding option o CDR data detection option (recommended that this be used) o Common data rates from 1.2kbps to 19.2kbps or user defined FSK/GFSK modulation (FM) AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 47 AMIS-53000 Frequency Agile Transceiver o o o Manchester encoding FFT or PLL demodulation (depends on data rate) Common data rates from 1.2kbps to 128kbps or user defined Data Sheet The AMIS-53000 receiver is a low IF frequency single down conversion, sub-sampling, image rejection architecture with a common AM/FM IF chain. Three demodulators are used for signal detection with additional post-detection and filtering capabilities for data recovery. A complex FFT demodulator is used for FSK signals with data rates > 20kbps. A digital PLL demodulator is used for FSK signals with data rates less than 20kbps. A logarithmic (RSSI) detector is used for OOK/ASK signals. 6.5.1. Receiver Circuit Brief Overview Clock and Data Recovery: The AMIS-53000 can extract a synchronous clock signal from the received data. In this mode, the data in the received signal is detected, filtered and then fed into the clock and data recovery block where additional digital filtering is performed. The waveform is sampled using a data clock in the AMIS-53000 to synchronously recover the data. Signal sensitivity is improved and the recovered data jitter is reduced by this method. LO Frequency: A sub-sampling LO frequency architecture is implemented that down converts the incoming RF signal to the IF frequency of about 500kHz. The LO frequency is produced from the internal VCO frequency. The frequency design of the LO signal reduces the power consumption of the AMIS-53000 and simplifies the receiver, achieving reliable, quadrature LO signal generation. IF Topology: The receiver implements a quadrature down-conversion architecture improving image rejection and creating the signals required for the complex FFT FSK signal detection. The receiver uses this quadrature down-conversion and a combination of passive and active poly-phase filtering to provide image suppression. Sniff Signal Acquisition: As with earlier ASTRIC devices, the AMIS-53000 can reduce the receiver power requirements by implementing the Sniff Mode for RF signal detection. Sniff Mode is a method using the Quick Start oscillator to quickly wake the receiver, check for signal energy and return to sleep or start the receive function. The Quick Start can start the receiver crystal oscillator in as little as 10 micro-seconds. Using this fast start time, the Sniff Mode can turn on the receiver, check for signal energy and return to sleep in as little as 130 micro-seconds. More information about this Sniff Mode is in Section 6.7.2. Table 32: Receive Command Register Number (HEX) 0X00 Name Command Code 0X01 Function Instruction to place the AMIS-53000 into receive (remember that all parameters for receive must be set before issuing this command) Setup registers descriptions: RX Config- Options for the receiver must be set. RF Frequency- The RF frequency of the receiver must be configured. (See Section 6.4.1.1) AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 48 AMIS-53000 Frequency Agile Transceiver Data Sheet 6.5.1.1. RX Configuration Figure 36: Receiver Timing Chart Table 33: Receiver Timing Symbol TPRE TE TID TLOP Timing Min. MOD 0 0 1 Default 1 Comments Typ. MOD 1 Max. Units D Bits The TX preamble should be made long enough to allow the receiver to acquire the signal The energy dwell timer should be set long enough to allow the receiver to 2 detect the energy The ID dwell timer should be set long enough to allow the receiver to detect 2 the chip ID or global ID The length of packet will turn the receiver off after the number of data bits is received 255 255 255 D Bits D Bits D Bits Notes: 1. The need for a preamble and the type of preamble is determined by the data modulation selected. 2. The dwell timers need to be long enough to allow the receiver to stay active from the time it turns on due to energy and the time that the desired event occurs. However, making this number the maximum may in the case of false energy detection or signal corruption may waste system power unnecessarily. AMI Semiconductor – Aug. 05, Rev. 1.0 www.amis.com 49 AMIS-53000 Frequency Agile Transceiver The RX Config register is used to set options for receive mode operation. Data Sheet Wake on Energy: When enabled, the CDR circuit is held in reset until the energy threshold is met. This option can be used to make the normal receiver function to perform similar to sniff. The energy dwell timer is used to determine how long the receiver will stay on checking for energy (With FF in the energy dwell time register, the receiver will stay on until the threshold is met). Gate on Energy: This option can be used in FM receive mode only, and will gate the data interface while the energy on RSSI is below the energy threshold. AM_FM_RX: Sets the mode of operation for receive. Force MICS Channel: When this bit is set, the bits in Status2 used to show which channel the radio is on can be overwritten to force a particular channel. Table 34: RX Config - 0X0E [14] Bit Name State 7 6 5 LNA Mode[1:0] 4 3 2 1 0 Force MICS Channel AM_FM_RX Gate on Energy Wake on Energy RSSI Active Multi Channel 1 0 1 0 11 10 01 00 1 0 1 0 1 0 1 Clock and data disabled until energy threshold met No operation defined Linear mode High gain mode Normal gain mode Force receive mode on a specific MICS channel (status2) AM receive mode FM receive mode Clock and data outputs gated for RSSI20k – 128k >20k – 128k