A49FL004TX-33

A49FL004 4 Mbit CMOS 3.3Volt-only Firmware Hub/LPC Flash Memory Preliminary Document Title 4 Mbit CMOS 3.3 Volt-only Firmware Hub/LPC Flash Memory Revision History Rev. No. 0.0 History Initial issue Issue Date September 23, 2005 Remark Preliminary PRELIMINARY (September, 2005, Version 0.0) AMIC Technology, Corp. A49FL004 4 Mbit CMOS 3.3Volt-only Firmware Hub/LPC Flash Memory Preliminary FEATURES • Single Power Supply Operation Low voltage range: 3.0 V - 3.6 V • Standard Intel Firmware Hub/LPC Interface Read compatible to Intel® 82802 Firmware Hub devices Conforms to Intel LPC Interface Specification Revision 1.1 • Memory Configuration 512K x 8 (4 Mbit) • Block Architecture Uniform 4 KBytes Sectors Uniform 64 KByte overlay blocks Support full chip erase for Address/Address Multiplexed (A/A Mux) mode • Automatic Erase and Program Operation Build-in automatic program verification for extended product endurance Typical 10 µs/byte programming time Typical x s sector erase time Typical y s block erase time Typical z s chip erase time • Two Configurable Interfaces In-System hardware interface: Auto detection of Firmware Hub (FWH) or Low Pin Count (LPC) Interface for in-system read and write operations Address/Address Multiplexed (A/A Mux) Interface for programming on EPROM Programmers during manufacturing • Firmware Hub (FWH)/Low Pin Count (LPC) Mode 33 MHz synchronous operation with PCI bus 5-signal communication interface for in-system read and write operations Standard SDP Command Set Data Polling and Toggle Bit features Block Locking Register for all blocks Register-based read and write protection for each block 4 ID pins for multiple chips selection 5 GPI pins for General Purpose Input Register TBL pin for hardware write protection to Boot Block WP pin for hardware write protection to whole memory array except Boot Block • Address/Address Multiplexed (A/A Mux) Mode 11-pin multiplexed address and 8-pin data I/O interface Supports fast programming on EPROM programmers Standard SDP Command Set Data Polling and Toggle Bit features • Lower Power Consumption Typical 12mA active read current Typical 17mA program/erase current • High Product Endurance Guarantee 100,000 program/erase cycles per single sector (preliminary) Minimum 20 years data retention • Compatible Pin-out and Packaging 32-pin (8 mm x 14 mm) TSOP 32-pin PLCC Optional lead-free (Pb-free) package • Hardware Data Protection PRELIMINARY (September, 2005, Version 0.0) 1 AMIC Technology, Corp. A49FL004 GENERAL DESCRIPTION The A49FL004 is a 4 Mbit 3.0 Volt-only Flash Memories used for BIOS storage in PCs and Notebooks. This device is designed to use a single low voltage, ranging from 3.0 Volt to 3.6 Volt, power supply to perform in-system or off-system read, erase and program operations. The device conforms to Intel® Low Pin Count (LPC) Interface specification revision 1.1 and also is compatible with Intel 82802 Firmware Hub (FWH) for most PC and Notebook applications. The A49FL004 supports two configurable interfaces: In-system hardware interface which can automatic detect the FWH or LPC memory cycle for in-system read and write operations, and Address/Address Multiplexed (A/A Mux) interface for fast manufacturing on EPROM Programmers. This device is designed to work with both Intel Family chipset and Non-Intel Family Chipset, it will provide PC and Notebook manufacturers great flexibility and simplicity for design, procurement, and material inventory. The memory array of A49FL004 is divided into 128 uniform 4 KByte sectors or 8 uniform 64 KByte blocks (sector group consists of sixteen adjacent sectors). The sector or block erase feature in the A49FL004 allows user to flexibly erase a memory area as 4Kbyte or 64 KByte by one single erase operation without affecting the data in others. The chip erase feature allows the whole memory to be erased in one single erase operation. The device can be programmed on a byteby-byte basis after performing the erase operation. The program operation of A49FL004 is executed by issuing the program command code into command register. The internal control logic automatically handles the programming voltage ramp-up and timing. The erase operation of the device is also executed by issuing the sector, block, or chip erase command code into command register. The internal control logic automatically handles the erase voltage rampup and timing. The device offer Data Polling and Toggle Bit functions in FWH/LPC and A/A Mux modes, the progress or completion of program and erase operation can be detected by reading the Data Polling on I/O7 or Toggle Bit on I/O6. The A49FL004 has a 64 KByte top boot block. The boot block can be write protected by a hardware method controlled by the TBL pin or a register-based protection turned on/off by the Block Locking Registers (FWH or LPC mode only). The rest of blocks except boot block in the device also can be write protected by WP pin or Block Locking Registers (FWH or LPC mode only). The A49FL004 is manufactured on AMIC ‘s advanced nonvolatile technology. The device is offered in 32-pin TSOP and PLCC packages with optional environmental friendly lead-free package. PRELIMINARY (September, 2005, Version 0.0) 2 AMIC Technology, Corp. A49FL004 PIN CONFIGURATIONS Figure 1: 32-Pin PLCC FWH GPI2 GPI3 VDD RST CLK CLK R/C GPI4 A10 GPI4 NC NC NC GPI2 GPI3 A/A Mux RST RST LPC 32 31 30 FWH GPI1 GPI0 WP TBL ID3 ID2 ID1 ID0 FWH0 LPC GPI1 GPI0 WP TBL RES RES RES RES LAD0 A/A Mux A7 A6 A5 A4 A3 A2 A1 A0 I/O0 5 6 7 8 9 10 11 12 13 VDD A8 A9 VDD A/A Mux 29 28 27 26 IC GND NC NC VDD OE WE NC I/O7 LPC IC GND NC NC VDD INIT NC RES FWH IC GND NC NC VDD INIT NC RES 4 3 2 32-pin PLCC 1 25 24 23 22 21 LFRAME FWH4 14 15 16 17 18 19 I/O5 RES RES A/A Mux GND I/O4 I/O2 I/O3 LAD1 LAD2 GND LAD3 LPC RES FWH1 FWH FWH2 GND FWH3 Figure 2: 32-Pin TSOP FWH VD D NC NC GND IC GPI4 CLK VD D NC RST GPI3 GPI2 GPI1 GPI0 WP TBL LPC VD D NC NC GND IC GPI4 CLK VD D NC RST GPI3 GPI2 GPI1 GPI0 WP TBL A/A Mux VD D NC NC GND IC A10 R/C VD D NC RST A9 A8 A7 A6 A5 A4 A/A Mux OE WE VDD I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 LPC INIT LFRAME N C RES RES RES RES LAD3 GND LAD2 LAD1 LAD0 RES RES RES RES FWH INIT LFRAME NC RES RES RES RES LAD3 GND LAD2 LAD1 LAD0 RES RES RES RES 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RES RES RES I/O6 I/01 20 32-lead TSOP ( 8 MM X 14 MM ) Top View 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PRELIMINARY (September, 2005, Version 0.0) 3 AMIC Technology, Corp. A49FL004 Figure 3: BLOCK DIAGRAM TBL WP INIT FWH[3:0] or LAD[3:0] FWH4 or LFRAME CLK GPI[4:0] A[10:0] I/O[7:0] WE OE R/C IC RST Address Latch Y-Decoder X-decoder Y - Gating Memory Array Control Logic A/A Mode Interface Erase/Program Voltage Generator I/O Buffers FWH/LPC Mode Interface High Voltage Switch Data Latch Sense Amp PRELIMINARY (September, 2005, Version 0.0) 4 AMIC Technology, Corp. A49FL004 Table 1: Pin Description Symbol Type Interface A/A X FWH LPC Addresses Inputs: For inputting the multiplex address in A/A Mux mode. Row A[10:0] IN and column address are latched during a read or write cycle controlled by R/ C pin. Data Inputs/Outputs: Used for A/A Mux mode only, to input command/data during write operation and to output data during Read operation. The data pins float to tri-state when OE is high. OE WE Descriptions I/O[7:0] I/O X IN IN X X Output Enable: Control the device’s output buffers during a read cycle. OE is a active low. Write Enable: Active the device for write operation. WE is active low. Interface Configuration Select: This pin determines which mode is selected. When pulls high, the device enters into A/A Mux mode. When pulls low, FWH/LPC mode is selected. This pin must be setup during power-up or system reset, and stays no change during operation. This pin is internally pulled down with a resistor between 20-100 KΩ. Initialize: This is the second reset pin for in-system use. INIT and RST pin are internally combined and initialize a device reset when driven low. These four pins are part of the mechanism that allows multiple FWH devices to be attached to the same bus. The strapping of these pins is used to identify the component. The boot device must have ID[3:0]=0000b and it is recommended that all subsequent devices should use sequential up-count strapping. These pins are internally pulled-down with a resistor between 20-100 KΩ. FWH/LPC General Purpose Inputs: Used to set the GPI_REG for system design purpose only. The value of GPI_REG can be read through FWH interface. The state of these pins can be read immediately at boot, through FWH/LPC internal registers. These pins should be set at desired state before the start of the PCI clock cycle for read operation and should remain on change until the end of the Read cycle. Unused GPI pins must not be floated. IC IN X X X INIT IN X X ID[3:0] IN X GPI[4:0] IN X X TBL FWH[3:0] CLK FWH4 RST WP IN I/O IN IN IN IN X X X X X X X X Top Block Lock: When pulls low, it enables the hardware write protection the state for top boot block. When pulls high, it disables the hardware write protection. FWH Address and Data: The major I/O pins for transmitting data, address and command code in FWH mode. X FWH/LPC Clock: To provide a synchronous clock for FWH and LPC mode operations. FWH Input: To indicate the start of a FWH memory cycle operation. Also used to abort a FWH memory cycle in progress. X X Reset: To reset the operation of the device and return to standby mode. Write Protect: When pulls low, it enables the hardware write protection to the memory array except the top boot block. When pulls high, it disables hardware write protection except the top boot block. Row/Column Select: To indicate to the row or column address in A/A Mux mode. When this pin goes low, the row address is latched. When this pin goes high, the column address is latched. R/ C LAD[3:0] LFRAME RES VDD VSS NC IN I/O IN X X X X X X X X X X X X X LPC Address and Data: The major i/o pins for transmitting data, addresses and command code in LPC mode. LPC Frame: To indicate the start of a LPC memory cycle operation. Also used to abort a LPC memory cycle in progress. Reserved. Reserved function pins for future use. Device power supply. Ground. No Connection. Notes: IN=Input, I/O=Input/Output. PRELIMINARY (September, 2005, Version 0.0) 5 AMIC Technology, Corp. A49FL004 FWH MODE SELECTION The A49FL004 can operate in two configurable interfaces: The In-System Hardware interface and Address/Address Multiplexed (A/A Mux) interface controlled by IC pin. If the IC pin is set to logic high (VIH), the devices enter into A/A Mux interface mode. If the IC pin is set logic low (VIL), the device will be in in-system hardware interface mode. During the insystem hardware interface mode, the device can automatically detect the Firmware Hub (FWH) or Low Pin Count (LPC) memory cycle sent from host system and response to the command accordingly. The IC pin must be setup during power-up or system reset, and stays no change during device operation. When working in-system, typically on a PC or Notebook for Intel Platform, the A49FL004 enters into the FWH mode automatically. The device is configured to interface with its host using Intel’s Firmware Hub proprietary protocol. Communication between the host (Intel ICH) and the A49FL004 occurs via the 4-bit I/O communication signal, FWH[3:0] and FWH4. In A/A Mux mode, the device is programmed via 11-bit address A[10:0] and 8-pin data I/O[7:0] interfaces. The address inputs are multiplexed in row and column selected by column the control signal R/ C . The column addresses are mapped to the higher internal addresses, and the row addresses are mapped to the lower internal addresses. FWH Write Operation FWH Write operations write the FWH Interface or FWH registers. A valid FWH Write operation starts when FWH4 is Low as CLK rises and a START value “1110b” is on FWH[3:0]. Addresses and data are transferred to and from the device decided by a series of “fields”. Field sequences and contents are strictly defined for FWH Write operations. Refer to Table 3 for FWH Write Cycle Definition. FWH Abort Operation The FWH4 signal indicates the start of a memory cycle or the termination of a cycle in FWH mode. Asserting FWH4 for one or more clock cycle with a valid START value on FWH[3:0] will initiate a memory read or memory write cycle. If the FWH4 is driven low again for one or more clock cycles during this cycle, this cycle will be terminated and the device will wait for the ABORT command “1111b” to release the FWH[3:0] bus. If the abort occurs during the program or erase operation such as checking the operation status with Data Polling (I/O7) or Toggle Bit (I/O6) pins, the read status cycle will be aborted but the internal program or erase operation will not be affected. Only the reset operation initiated by RST or INIT pin can terminate the program or erase operation. Response To Invalid Fields FWH MODE OPERATION In FWH mode, the A49FL004 is connected through a 5-pin communication interface - FWH[3:0] and FWH4 pins to work with Intel® Family of I/O Controller Hubs (ICH) chipset platforms. The FWH mode also supports JEDEC standard Software Data Protection (SDP) product ID entry, byte program, sector erase, and block erase command sequences. The chip erase command sequence is only available in A/A Mux mode. The addresses and data are transmitted through the 4-bit FWH[3:0] bus synchronized with the input clock on CLK pin during a FWH memory cycle operation. The address or data on FWH[3:0] bus is latched on the rising edge of the clock. The device enters standby mode when FWH4 is high and no internal operation is in progress. The device is in ready mode when FWH4 is low and no activity is on the bus. FWH Read Operation During FWH operations, the device will not explicitly indicate that it has received invalid field sequences. The response to specific invalid fields or sequences is as follows: Address out range: The FWH address sequence is 7 fields long (28 bits), but only the last five address fields (20 bits) will be decoded by A49FL004. Address A22 has the special function of directing reads and writes to the flash memory (A22=1) or to the register space (A22=0). Invalid IMSIZE Field: If the FWH device receives and invalid size field during a Read or Write operation, the device will reset and no operation will be attempted. The A49FL004 will not generate any kind of response in this situation. Invalid size field for a Read/Write cycles are anything but “0000b”. FWH Read Operations read from the memory cells or specific registers in the FWH device. A valid FWH Read operation starts when FWH4 is Low as CLK rises and a START value “1101b” is on FWH[3:0]. Addresses and data are transferred to and from the device decided by a series of “fields”. Field sequences and contents are strictly defined for FWH Read Operations. Refer to Table 2 for FWH Read Cycle definition. PRELIMINARY (September, 2005, Version 0.0) 6 AMIC Technology, Corp. A49FL004 Table 2: FWH Read Cycle Clock Cycle Field FWH[3:0] Direction Descriptions 1 START 1101 IN Start of Cycle: “1101b” to indicate the start of a memory read cycle. FWH4 must be active (low) for the part to respond. Only the last start field (before FWH4 transition high) should be recognized. The start field contents indicate and FWH read cycle. ID Select Cycle: Indicates which FWH device should respond. If the IDSEL field matches the value set on ID[3:0] pins, then the particular FWH device will respond to subsequent commands. Address Cycle: This is the 28-bit memory address. The addressed transfer most-significant nibble first and least-significant nibble last. (i.e., a27-24 on FWH[3:0] first, and A3-A0 on FWH[3:0] last). Memory Size Cycle: Indicates how many bytes will be or transferred during multi-byte operations. The A49FL004 only support “0000b” for one byte operation. Turn-Around cycle 0: The master (Intel ICH) has driven the bus to all”1”s and then float the bus. Turn-Around cycle 1: The device takes control of the bus during this cycle. Ready Sync: The FWH device indicates the least-significant nibble of data byte will be ready in next clock cycle. Data Cycles: The 8-bits data transferred with least-significant nibble first and most-significant nibble last. (i.e., I/O3 – I/O0 on FWH[3:0] first, then I/O7 – I/O4 on FWH[3:0] last). Turn-Around cycle 0: The FWH device has driven the bus to all “1”s and then float the bus. Turn-Around cycle 1: The master (Intel ICH) resumes control of the bus during this cycle. 2 IDSEL 0000 to 1111 IN 3-9 IMADDR YYYY IN 10 11 12 13 14-15 16 17 IMSIZE TAR0 TAR1 RSYNC DATA TAR0 TAR1 0000 1111 1111 (Float) 0000 (READY) YYYY 1111 1111 (Float) IN IN then Float Float then OUT OUT OUT OUT then Float Float then IN Figure 4: FWH Memory Read Cycle Waveforms 1 CLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 FWH4 FWH[3:0] START IDSEL IMADDR IMSIZE TAR0 TAR1 RSYNC DATA TAR0 TAR1 PRELIMINARY (September, 2005, Version 0.0) 7 AMIC Technology, Corp. A49FL004 Table 3: FWH Write Cycle Clock Cycle Field FWH[3:0] Direction Descriptions 1 START 1101 IN Start of Cycle: “1101b” to indicate the start of a memory write cycle. FWH4 must be active (low) for the part to respond. Only the last start field (before FWH4 transitioning high) should be recognized. The START field contents indicate an FWH write cycle. ID Select Cycle: Indicates which FWH device should respond. If the IDSEL field matches the value set on ID[3:0] pins, then the particular FWH device will respond to subsequent commands. Address Cycle: This is the 28-bit memory address. The addressed transfer most-significant nibble first and least-significant nibble last. (i.e., a27-24 on FWH[3:0] first, and A3-A0 on FWH[3:0] last). Memory Size Cycle: Indicates how many bytes will be or transferred during multi-byte operations. The A49FL004 only supports “0000b” for one byte operation. Data Cycles: The 8-bits data transferred with least-significant nibble first and most-significant nibble last. (i.e., I/O3 – I/O0 on FWH[3:0] first, then I/O7 – I/O4 on FWH[3:0] last). 2 IDSEL 0000 to 1111 IN 3-9 IMADDR YYYY IN 10 IMSIZE 0000 IN 11-12 13 14 15 16 17 DATA TAR0 TAR1 RSYNC TAR0 TAR1 YYYY 1111 1111 (Float) 0000 (Ready) 1111 1111 (Float) IN IN Turn-Around cycle 0: The master (Intel ICH) has driven the bus to then Float all”1”s and then float the bus. Float Turn-Around cycle 1: The device takes control of the bus during this then OUT cycle. OUT Ready Sync: The FWH device indicates that it has received the data or command. OUT Turn-Around cycle 0: The FWH device has driven the bus to all “1”s then Float and then float the bus. Float then IN Turn-Around cycle 1: The master (Intel ICH) resumes control of the bus during this cycle. Figure 5: FWH Write Waveforms 1 CLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 FWH4 FWH[3:0] START IDSEL IMADDR IMSIZE DATA TAR0 TAR1 RSYNC TAR0 TAR1 PRELIMINARY (September, 2005, Version 0.0) 8 AMIC Technology, Corp. A49FL004 LPC MODE SELECTION The A49FL004 can operate in two configurable interfaces: The In-System Hardware interface and Address/Address Multiplexed (A/A Mux) interface controlled by IC pin. If the IC pin is set to logic high (VIH), the devices enter into A/A Mux interface mode. If the IC pin is set logic low (VIL), the devices will be in in-system hardware interface mode. During the insystem hardware interface mode, the devices can automatically detect the Firmware Hub (FWH) or Low Pin Count (LPC) memory cycle sent from host system and response to the command accordingly. The IC pin must be setup during power-up or system reset, and stays no change during device operation. When working in-system, typically on a PC or Notebook for non Intel Platform, the A49FL004 is connected to the host system through a 5-pin communication interface operated based on a 33-MHz synchronous clock. The 5-pin interface is defined as LAD[3:0] and LFRAME pins under LPC mode for easy understanding as to those existing compatible products. When working off-system, typically on a EPROM Programmer, the device is operated through 11-pin multiplexed address - A[10:0] and 8-pin data I/O - I/O[7:0] interfaces. The memory addresses of device are input through two bus cycles as row and column addresses controlled by a R/ C pin. the rising edge of the clock. The pulse of LFRAME signal inserted for one or more clocks indicates the start of a LPC memory read or write cycle. Once the LPC memory cycle is started, asserted by LFRAME , a START value “0000b” is expected by the device as a valid command cycle. Then a CYCTYPE + DIR value (“010xb” for memory read cycle or “011xb” for memory write cycle) is used to indicates the type of memory cycle. Refer to Table 4 and 5 for LPC Memory Read and Write Cycle Definition. There are 8 clock fields in a LPC memory cycle that gives a 32 bit memory address A31 - A0 through LAD[3:0] with the most-significant nibble first. The memory space of A49FL004 is mapped directly to top of 4 Gbyte system memory space. See Figure 8 for System Memory Map. The A49FL004 is mapped to the address location of (FFFFFFFFh - FFF80000h), the A31- A19 must be loaded with “1” to select and activate the device during a LPC memory operation. Only A18 - A0 is used to decode and access the 512 KByte memory. LPC Abort Operation The LFRAME is driven low for one or more clock cycles during a LPC cycle, the cycle will be terminated and the device will wait for the ABORT command. The host may drive the LAD[3:0] with “1111b” (ABORT command) to return the device to the ready mode. If abort occurs during a Write operation such as checking the operation status with Data Polling (I/O7) or Toggle Bit (I/O6) pins, the read status cycle will be aborted but the internal program or erase operation will not be affected. In this case, only the reset operation initiated by RST or INIT pin can terminate the write operation. Response TO Invalid Fields LPC MODE OPERATION In LPC mode, the A49FL004 is connected through a 5-pin communication interface - LAD[3:0] and LFRAME pins to work with non Intel® Family of South Bridge chipset platforms. The LPC mode also supports JEDEC standard Software Data Protection (SDP) product ID entry, byte program, sector erase, and block erase command sequences. The chip erase command sequence is only available in A/A Mux mode. The addresses and data are transmitted through the 4-bit LAD[3:0] bus synchronized with the input clock on CLK pin during a LAD memory cycle operation. The address or data on LAD[3:0] bus is latched on the rising edge of the clock. The pulse of LFRAME pin is inserted for one clock indicates the start of a LPC memory read or memory write cycle. The address or data on LAD[3:0] is latched on the rising edge of CLK. The device enters standby mode when LFRAME is high and no internal operation is in progress. The device is in ready mode when LFRAME is low and no activity is on the LPC bus. LPC Mode Memory Read/Write Operation During LPC operations, the A49FL004 will not explicitly indicate that it has received invalid field sequences. The responses to specific invalid fields or sequence is as follows: Address out of range: The A49FL004 will only response to address range as specified in Table 9. Address A22 has the special function of directing reads and writes to the flash memory (A22=1) or to the register space (A22=0). ID mismatch: The A49FL004 will compare ID bits in the address field with the hardware strapping. If there is a mismatch, the device will ignore the cycle. In LPC mode, the A49FL004 uses the 5-pin LPC interface includes 4-bit LAD[3:0] and LFRAME pins to communicate with the host system. The addresses and data are transmitted through the 4-bit LAD[3:0] bus synchronized with the input clock on CLK pin during a LPC memory cycle operation. The address or data on LAD[3:0] bus is latched on PRELIMINARY (September, 2005, Version 0.0) 9 AMIC Technology, Corp. A49FL004 Table 4: LPC Memory Read Cycle Definition Clock Cycle Field LAD[3:0] Direction Descriptions 1 START 0000 IN Start of Cycle: “0000b” indicates the start of a LPC memory cycle. LFRAME must be active low (low) for the part to respond. Only the last field latched before LFRAME transitions high will be recognized. Cycle Type: Indicates the type of a LPC memory read cycle. CYCTYPE: Bits 3-2 must be “01b” for memory cycle. DIR: Bit 1 = “0b” indicates the type of cycle for Read. Bit 0 is reserved. Address Cycles: This is the 32-bit memory address. The addressed transfer most-significant nibble first and least-significant nibble last. (i.e., a31-28 on LAD[3:0] first, and A3-A0 on LAD[3:0] last). Turn-Around cycle 0: The host has driven the bus to all”1”s and then float the bus. Turn-Around cycle 1: The A49FL004 takes control of the bus during this cycle. Sync: The device indicates the least-significant nibble of data byte will be ready in next clock cycle. Data Cycles: The 8-bits data transferred with least-significant nibble first and most-significant nibble last. (i.e., I/O3 – I/O0 on LAD[3:0] first, then I/O7 – I/O4 on LAD[3:0] last). Turn-Around cycle 0: The host has driven the bus to all “1”s and then float the bus. Turn-Around cycle 1: The A49FL004 resumes control of the bus during this cycle. 2 CYCTYPE + DIR 010x IN 3-10 ADDR YYYY IN IN Then Float Float then OUT OUT OUT IN then Float Float then OUT 11 12 13 14-15 16 17 TAR0 TAR1 SYNC DATA TAR0 TAR1 1111 1111 (Float) 0000 1111 1111 1111 (Float) Figure 6: LPC Single-Byte Read Waveforms 1 LCLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 LFRAME LAD[3:0] START CYCTYPE + DIR ADDRESS TAR0 TAR1 SYNC DATA TAR0 TAR1 PRELIMINARY (September, 2005, Version 0.0) 10 AMIC Technology, Corp. A49FL004 Table 5: LPC Memory Write Cycle Definition Clock Cycle Field LAD[3:0] Direction Descriptions 1 START 0000 IN Start of Cycle: “0000b” to indicate the start of a LPC memory cycle. LFRAME must be active low (low) for the part to respond. Only the last field latched before LFRAME transitions high will be recognized. Cycle Type: Indicates the type of a LPC memory write cycle. CYCTYPE: Bits 3-2 must be “01b” for memory cycle. DIR: Bit 1 = “1b” indicates the type of cycle for Write. Bit 0 is reserved. Address Cycles: This is the 32-bit memory address. The addressed transfer most-significant nibble first and least-significant nibble last. (i.e., a31-28 on LAD[3:0] first, and A3-A0 on LAD[3:0] last). Data Cycles: The 8-bits data transferred with least-significant nibble first and most-significant nibble last. (i.e., I/O3 – I/O0 on LAD[3:0] first, then I/O7 – I/O4 on LAD[3:0] last). Turn-Around cycle 0: The host has driven the bus to all”1”s and then float the bus. Turn-Around cycle 1: The A49FL004 takes control of the bus during this cycle. Sync: The device indicates the least-significant nibble of data byte will be ready in next clock cycle. Turn-Around cycle 0: The A49FL004 has driven the bus to all “1”s and then float the bus. Turn-Around cycle 1: The host resumes control of the bus during this cycle. 2 CYCTYPE + DIR 011x IN 3-10 ADDR YYYY IN 11-12 13 14 15 16 17 DATA TAR0 TAR1 SYNC TAR0 TAR1 YYYY 1111 1111 (Float) 0000 1111 1111 (Float) IN IN then Float Float then OUT OUT OUT then Float Float then IN Figure 7: LPC Write Waveforms 1 LCLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 LFRAME LAD[3:0] START CYCTYPE + DIR ADDRESS DATA TAR0 TAR1 SYNC TAR0 TAR1 PRELIMINARY (September, 2005, Version 0.0) 11 AMIC Technology, Corp. A49FL004 Multiple Device Selection Multiple A49FL004 devices may be strapped to increase memory densities in a system. The four ID pins, ID[3:0], allow up to 16 devices to be attached to the same bus by using different ID strapping in a system, BIOS support, bus loading, or the attaching bridge may limit this number. The boot device must have an ID of “0000b” (determined by ID[3:0]); subsequent devices use incremental numbering, equal density must be used with multiple devices. Multiple Device Selection for LPC Memory Cycle For LPC Memory Read/Write cycles, ID information is included in the address bits of every cycle. The ID bits in the address field are the reverse of the hardware strapping. See Table x2 for multiple device selection configurations. The A49FL004 will compare these bits with ID[3:0]’s strapping values. If there is a mismatch, the device will ignore the remainder of the cycle. Table 7: LPC Configuration Device # 0 (Boot Device) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Multiple Device Selection Multiple Device Selection for Firmware Hub Memory Cycle For Firmware Memory Read/Write cycles, hardware strapping values on ID[3:0] must match the values in IDSEL field. See Table x for multiple device selection configurations. The A49FL004 will compare the IDSEL field with ID[3:0] ‘s strapping values. If there is a mismatch, the device will ignore the reminder of the cycle. Table 6: FWH Configuration Device # 0 (Boot Device) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Multiple Device Selection ID[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 IDSEL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ID[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Address Range 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 PRELIMINARY (September, 2005, Version 0.0) 12 AMIC Technology, Corp. A49FL004 Register The A49FL004 has two registers include the General Purpose Inputs Register (GPI_REG) and Block Locking Register (BL_REG). Both registers are available in FWH and LPC mode only. The GPI_REG can be read at FFBC0100h in the 4 GByte system memory map. The BL_REG can be read through FFBx0002h where x=F-0h. Refer to table 9 for BL_REG. General Purpose Inputs Register Table 8: General Purpose Inputs Register Bit Bit Name Function Pin Number 32-PLCC 32-TSOP 30 6 3 11 4 12 5 13 6 14 7:5 4 3 2 1 0 GPI[4] GPI[3] GPI[2] GPI[1] GPI[0] Reserved GPI_REG Bit 4 GPI_REG Bit 3 GPI_REG Bit 2 GPI_REG Bit 1 GPI_REG Bit 0 The A49FL004 contains and 8-bit General Purpose Inputs Register (GPI_REG) available in FWH and LPC modes. Only Bit 4 to Bit 0 are used in the current version, and bit 7 to bit 5 are reserved for the future use. The GPI_REG is a pass-through register with the value set by GPI[4:0] pin during power-up. The GPI_REG is used for the system design purpose only, the device does not use this register. This register is read only and can be read at address location FFBC0100h in the 4 Gbyte system memory map through a memory read cycle. Refer to Table 8 for General Purpose Input Register Definition. Block Locking Registers The A49FL004 supports block read-lock, write-lock, and lockdown features through a set of Block Locking Registers. Each memory block has an associated 8-bit read/writable block locking register. Only Bit 2 to Bit 0 are used in current version and Bit 7 to Bit 3 are reserved for future use. The default value of BL_REG is “01h” at power up. The definition of BL_REG is listed in Table 8. The FWH/LPC Register Configuration Map of A49FL004 is shown in Table 9. Unused register will be read as 00h Table 9: A49FL004 Block Locking Register Address Memory Address Protected Block Address Range Mnemonic Register Name FFBF0002h FFBE0002h FFBD0002h FFBC0002h FFBB0002h FFBA0002h FFB90002h FFB80002h T_BLOCK_LK T_MINUS01_LK T_MINUS02_LK T_MINUS03_LK T_MINUS04_LK T_MINUS05_LK T_MINUS06_LK T_MINUS07_LK Top Block Lock Register (Block 64) Top Block [-1] Lock Register (Block 64) Top Block [-2] Lock Register (Block 64) Top Block [-3] Lock Register (Block 64) Top Block [-4] Lock Register (Block 64) Top Block [-5] Lock Register (Block 64) Top Block [-6] Lock Register (Block 64) Top Block [-7] Lock Register (Block 64) 70000h – 7FFFFh 60000h – 6FFFFh 50000h – 5FFFFh 40000h – 4FFFFh 30000h – 3FFFFh 20000h – 2FFFFh 10000h – 1FFFFh 00000h – 0FFFFh PRELIMINARY (September, 2005, Version 0.0) 13 AMIC Technology, Corp. A49FL004 Table 10: Block Lock Register Bit Definition Reserved Bit 7:3 Read-Lock Bit 2 Lock-Down Bit 1 Write-Lock Bit 0 Data Function 00h 01h 02h 03h 04h 05h 06h 07h 00000 00000 00000 00000 00000 00000 00000 00000 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Full Access. Write locked. Default state at power-up. Locked open (full access locked down). Write-locked down. Read locked. Read and Write locked. Read-locked down Read-locked and Write-locked down Data Function Reserved Read-Lock 7:3 2 1 = Prevents read operations in the block where set 0 = Normal operation for reads in the block where clear. This is the default state. Lock-Down 1 = Prevents further set or clear operations to the Write-Lock and Read-Lock bits. Lock-Down only can be set 1 but not clear. The block will remain lock-down until reset (with RST or INIT ), or until the device is power-on reset. 0 = Normal operation for Write-Lock and Read-Lock bit altering in the block where clear. This is the default state. Write-Lock 0 1 = Prevents program or erase operations in the block where set. This is the default state. 0 = Normal operation for programming and erase in the block where clear. PRELIMINARY (September, 2005, Version 0.0) 14 AMIC Technology, Corp. A49FL004 ADDRESS/ADDRESS MULTIPLEXED (A/A MUX) MODE Read/Write Operation The A49FL004 offers a Address/Address Multiplexed (A/A Mux) mode for off-system operation, typically on an EPROM Programmer, similar to a traditional Flash memory except the address input is multiplexed. In the A/A Mux mode, the programmer must drive the OE pin to low (VIL) for read or WE pins to low for write operation. The devices have no The 11 multiplex address pins - A[10:0] and a R/ C pin are used to load the row and column addresses for the target memory location. The row addresses (internal address A10 A0) are latched on the falling edge of R/ C pin. The column addresses (internal address A21 - A11) are latched on the rising edge of R/ C pin. The A49FL004 use A18 - A0 respectively. During a read operation, the OE signal is used to control the output of data to the 8 I/O pins - I/O[7:0]. During a write operation, the WE signal is used to latch the input data from I/O[7:0]. See Table 11 for Bus Operation Modes. Chip Enable ( CE ) pin for chip selection and activation as traditional Flash memory. The R/ C , OE and WE pins are used to activate the device and control the power. Table 11: A/A Mux Mode Operation Selection Mode RST VIH VIH VIH VIH VIL OE VIL VIH VIH VIH X WE VIH VIL VIH X X Address I/O Read Write Standby Output Disable Reset X (1) X X X X A2 – A21 = X, A1 = VIL, A0 = VIL, DOUT DIN High Z High Z High Z Manufacturer ID (2) Device ID Product Identification VIH VIL VIH and A1 = VIH, A0 = VIH A2 – A21= X, A1 = VIL, A0 = VIH Notes: 1. X can be VIL OR VIH. 2. Refer to Table 12 for the Manufacturer ID and Device ID of devices. The A49FL004 provides three levels of data protection for the critical BIOS code of PC and Notebook. It includes memory hardware write protection, hardware data protection and software data protection. the six-byte command sequence through six consecutive write memory cycles with Block Erase Command (50h), and Block address (BA) in the last bus cycle. In A/A Mux mode, an erase operation is activated by writing the six-byte command in six consecutive bus cycles. Preprograms the block is not required prior to an erase operation. Sector-Erase Operation The A49FL004 contains 128 uniform 4 KByte sectors. A sector erase command is used to erase an individual sector. See Table 11 for Sector/Block Address Table. In FWH/LPC mode, an erase operation is activated by writing the six-byte command sequence through six consecutive write memory cycles with Sector Erase Command (30h), and sector address (SA) in the last bus cycle. In A/A Mux mode, an erase operation is activated by writing the six-byte command in six consecutive bus cycles. Preprograms the sector is not required prior to an erase operation. Chip-Erase The entire memory array can be erased by chip erase operation available under the A/A Mux mode operated by EPROM Programmer only. Pre-programs the device is not required prior to the chip erase operation. Chip erase starts immediately after a six-bus-cycle chip erase command sequence. All commands will be ignored once the chip erase operation has started. The Data Polling on I/O7 or Toggle Bit on I/O6 can be used to detect the progress or completion of erase operation. The device will return back to standby mode after the completion of the chip erase. Block-Erase Operation The A49FL004 contains eight uniform 64 KByte blocks. A block erase command is used to erase an individual block. See Table 13 for Sector/Block Address Table. In FWH/LPC mode, an erase operation is activated by writing Write Operation Status Detection In program operation, the data is programmed into the devices (to a logical “0”) on a byte-by-byte basis. In FWH and LPC mode, a program operation is activated by writing the three-byte command sequence and program address/data PRELIMINARY (September, 2005, Version 0.0) 15 AMIC Technology, Corp. A49FL004 through four consecutive memory write cycles. In A/A Mux mode, a program operation is activated by writing the threebyte command sequence and program address/data through four consecutive bus cycles. The row address (A10 - A0) is latched on the falling edge of R/ C and the column address (A21 - A11) is latched on the rising edge of R/ C . The data is latched on the rising edge of WE . Once the program operation is started, the internal control logic automatically handles the internal programming voltages and timing. A data “0” can not be programmed back to a “1”. Only erase operation can convert “0”s to “1”s. The Data Polling on I/O7 or Toggle Bit on I/O6 can be used to detect when the programming operation is completed in FWH, LPC, and A/A Mux modes. protected. Any attempt to erase or program a sector or block within this area will be ignored. Both TBL and WP pins must be set low (VIL) for protection or high (VIH) for un-protection prior to a program or erase operation. A logic level change on TBL or WP pin during a program or erase operation may cause unpredictable results. The TBL and WP pins work in combination with the block locking registers. When active, these pins write protect the appropriate blocks regardless of the associated block locking registers setting. Hardware Data Protection Hardware data protection protects the devices from unintentional erase or program operation. It is performed by the device automatically in the following three ways: (a) VDD Detection: if VDD is below 1.8 V (typical), the program and erase functions are inhibited. Data Polling (I/O7) The device provides a Data Polling feature to indicate the progress or the completion of a program or erase operation in all modes. During a program operation, an attempt to read the device will result in the complement of the last loaded data on I/O7. Once the program cycle is complete, the true data of the last loaded data is valid on all outputs. During an erase operation, an attempt to read the device will result a “0” on I/O7. After the erase cycle is complete, an attempt to read the device will result a “1” on I/O7. (b) Write Inhibit Mode: holding any of the signal OE low, or WE high inhibits a write cycle (A/A Mux mode only). (c) Noise/Glitch Protection: pulses of less than 5 ns (typical) on the WE input will not initiate a write cycle (A/A Mux mode only). Reset Any read, program, or erase operation to the devices can be reset by the INIT or RST pins. INIT and RST pins are internally hard-wired and have same function to the devices. The INIT pin is only available in FWH and LPC modes. The RST pin is available in all modes. It is required to drive INIT or RST pins low during system reset to ensure proper initialization. During a memory read operation, pulls low the INIT or RST pin will reset the devices back to standby mode and then the FWH[3:0] of FWH interface or the LAD[3:0] of LPC interface will go to high impedance state. During a program or erase operation, pulls low the INIT or RST pin will abort the program or erase operation and reset the devices back to standby mode. A reset latency will occur before the devices resume to standby mode when such reset is performed. When a program or erase operation is reset before the completion of such operation, the memory contents of devices may become invalid due to an incomplete program or erase operation. Toggle Bit (I/O6) The A49FL004 also provides a Toggle Bit feature to detect the progress or the completion of a program or erase operation. During a program or erase operation, an attempt to read data from the devices will result in I/O6 toggling between “1” and “0”. When the program or erase operation is complete, I/O6 will stop toggling and valid data will be read. Toggle bit may be accessed at any time during a program or erase operation. Data Protection The device features a software data protection function to protect the device from an unintentional erase or program operation. It is performed by JEDEC standard Software Data Protection (SDP) command sequences. See Table 14 for SDP Command Definition. A program operation is initiated by three memory write cycles of unlock command sequence. A chip (only available in A/A Mux mode), sector or block erase operation is initiated by six memory write cycles of unlock command sequence. During SDP command sequence, any invalid command or sequence will abort the operation and force the device back to standby mode. Memory Hardware Write Protection The A49FL004 has a 64 KByte top boot block. When working in-system, the memory hardware write protection feature can Product Identification The product identification mode can be used to read the Manufacturer ID and the Device ID by a software Product ID Entry command in both in-system hardware interface and A/A Mux interface modes. The product identification mode is activated by three-bus-cycle command. Refer to Table 12 for the Manufacturer ID and Device ID of A49FL004 and Table 14 for the SDP Command Definition. In FWH mode, the product identification can also be read directly at FFBC0000h for Manufacturer ID - “99h” and FFBC0001h for Device ID in the 4 GByte system memory map. be activated by two control pins - Top Block Lock ( TBL ) and Write Protection ( WP ) for both FWH and LPC modes. When TBL is pulled low (VIL), the boot block is hardware write protected. A sector erase, block erase, or byte program command attempts to erase or program the boot block will be ignored. When WP is pulled low (VIL), the Block 0 ~ Block 6 of A49FL004 (except the boot block) are hardware write PRELIMINARY (September, 2005, Version 0.0) 16 AMIC Technology, Corp. A49FL004 Table 12: Product Identification Description Address Data Manufacturer ID Device ID A49FL004 00000h 00003h 00001h 37h 7Fh 99h Figure 8: System Memory Map and Device Memory Map for A49FL004 S y s te m M e m o r y (T o p 4 M B y t e s ) FFFFFFFFh A 49FL004 D e v ic e M e m o r y 07FFFF B lo c k 7 (6 4 K B y te s ) 070000 06FFFF B lo c k 6 (6 4 K B y te s ) 060000 05FFFF B lo c k 5 (6 4 K B y te s ) 050000 04FFFF B lo c k 4 (6 4 K B y te s ) 040000 03FFFF B lo c k 3 (6 4 K B y te s ) 030000 02FFFF B lo c k 2 (6 4 K B y te s ) 020000 01FFFF B lo c k 1 (6 4 K B y te s ) 010000 00FFFF TBL WP fo r B lo c k 6 ~ 0 FFF80000h B lo c k 0 (6 4 K B y te s ) 000000 R a n g e fo r A d d itio n a l F W H D e v ic e s FFC 0000h PRELIMINARY (September, 2005, Version 0.0) 17 AMIC Technology, Corp. A49FL004 Table 13: Sector/Block Address Table Block Size Sector Hardware Block (Kbytes) Sector Size (K bytes) Sector Number 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 Address Range 7F000h - 7FFFFh 7E000h – 7EFFFh 7D000h – 7DFFFh 7C000h – 7CFFFh 7B000h – 7BFFFh 7A000h – 7AFFFh 79000h – 79FFFh 78000h – 78FFFh 77000h – 77FFFh 76000h – 76FFFh 75000h – 75FFFh 74000h – 74FFFh 73000h - 73FFFh 72000h – 72FFFh 71000h – 71FFFh 70000h - 70FFFh 60000h - 6FFFFh 50000h - 5FFFFh 40000h - 4FFFFh 30000h - 3FFFFh 20000h - 2FFFFh 10000h - 1FFFFh 00000h - 0FFFFh TBL Block 7(Boot Block) 64 16 4 Kbytes/Sector Block 6 Block 5 Block 4 WP 64 64 64 64 64 64 64 16 16 16 16 16 16 16 4 Kbytes/Sector 4 Kbytes/Sector 4 Kbytes/Sector 4 Kbytes/Sector 4 Kbytes/Sector 4 Kbytes/Sector 4 Kbytes/Sector 111 - 96 95 - 80 79 - 64 63 - 48 47 - 32 31 -16 15 - 0 Block 3 Block 2 Block 1 Block 0 PRELIMINARY (September, 2005, Version 0.0) 18 AMIC Technology, Corp. A49FL004 Table 14: Software Data Protection Command Definition Command 1st Cycle (1) Bus Cycles Addr(2) Data 2nd Cycle Addr Data 3rd Cycle Addr Data 4th Cycle Addr Data 5th Cycle Addr Data 6th Cycle Addr Data Block Erase Read Sector Erase Chip Erase (1) 6 1 6 6 4 3 1 3 5555H Addr 5555H 5555H 5555H 5555H XXXXH AAH 2AAAH DOUT AAH 2AAAH AAH 2AAAH AAH 2AAAH AAH 2AAAH F0H AAH 2AAAH 55H 55H 55H 55H 55H 55H 5555H 5555H 5555H 5555H 5555H 5555H 80H 80H 80H A0H 90H F0H 5555H 5555H 5555H Addr AAH 2AAAH AAH 2AAAH AAH 2AAAH DIN 55H 55H 55H BA (4) 50H 30H 10H SA (3) 5555H Byte Program Product ID Entry Product ID Exit (5) Product ID Exit (5) 5555H Notes: 1. Chip erase is available in A/A Mux Mode only. 2. Address A[15:0] is used for SDP command decoding internally and A15 must be “0” in FWH/LPC and A/A Mux modes. AMS - A16 = Don’t care where AMS is the most-significant address of A49FL004. 3. SA = Sector address to be erased. 4. BA = Block address to be erased. 5. Either one of the Product ID Exit command can be used. PRELIMINARY (September, 2005, Version 0.0) 19 AMIC Technology, Corp. A49FL004 DC and AC Operating Range Range A49FL004 Operating Temperature VDD Power Supply 0°C to +70°C 3.0V –3.6V Table 15: DC Operating Characteristics Symbol Parameter Min Limits Typ Max Units Test Conditions ICC1 ICC2 (2) ISB IRY II ILI ILO VIH VIL VOL VOH VCC Active Read Current (FWH/LPC) VCC Program/Erase Current Standby VCC Current (FWH/LPC Mode) Ready Mode VCC Current (FWH/LPC Mode) Input Leakage Current for IC, ID[3:0] Pins Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output Low Voltage Output High Voltage 0.9VDD 0.7VDD -0.5 2 7 15 20 500 10 100 ±1 ±1 mA mA µA FWH4 or LFRAME = VIL, f = 33MHz, IOUT = 0mA, VDD = VDD Max FWH4 or LFRAME = VIH, f = 33MHz, VDD = VDD Max FWH4 or LFRAME = VIL, f = 33MHz, IOUT = 0mA, VDD = VDD Max VIN = 0V to VDD, VDD = VDD Max VIN = 0V to VDD, VDD = VDD Max VI/O = 0V to VDD, VDD = VDD Max mA µA µA µA VDD+0.5 0.3VDD 0.1VDD V V V V IOL= 2.0mA, VDD = VDD Min IOH = -100µA, VDD = VDD Min Notes: 1. Characterized but not 100％ tested. Table 16: Pin Impedance (VDD=3.3V, T=25°C, f=1MHz) Parameter Description Test Condition Max CI/O (1) CIN (1) LPIN (2) I/O Pin Capacitance Input Capacitance Pin Inductance VI/O = 0V VIN = 0V 12pF 12pF 20nH Notes: 1. These parameters are characterized but not 100％ tested. 2. Refer to PCI specification. Table 17: FWH/LPC Interface Clock Characteristics Symbol Parameter Min Max Units tCYC tHIGH tLOW CLK Cycle Time CLK High Time CLK Low Time CLK Slew Rate (peak-to-peak) INIT or RST Slew Rate 30 11 11 1 50 4 ns ns ns V/ns mV/ns PRELIMINARY (September, 2005, Version 0.0) 20 AMIC Technology, Corp. A49FL004 Table 18: FWH/LPC Memory Read/Write Operations Characteristics Symbol Parameter Min Max Units tCYC tSU tH tVAL tON tOFF Clock Cycle Time Input Set Up Time Input Hold Time Clock to Data Out Clock to Active Time (Float to Active Delay) Clock to Inactive Time (Active to Float Delay) 30 7 0 2 2 28 11 ns ns ns ns ns ns Table 19: FWH/LPC Interface Measurement Condition Parameters Symbol Value Units VTH4 VTL1 VTEST VMAX1 0.6 VDD 0.2 VDD 0.4 VDD 0.4 VDD V V V V Input Signal Edge Rate 1V/ns Notes: The input test environment is done with 0.1 VDD of overdrive over VIH and VIL. Timing parameters must be met with no more overdrive that this. VMAX specifies the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use different voltage values, but must correlate results back to these parameters. Figure 9: Input Timing Parameters VTH CLK VTEST VTL TSU TDH FWH[3:0] or LAD[3:0] (Valid Input Data) Valid Inputs VMAX PRELIMINARY (September, 2005, Version 0.0) 21 AMIC Technology, Corp. A49FL004 Figure 10: Output Timing Parameters V TH CLK V TEST V TL T VAL FWH[3:0] or LAD[3:0] (Valid Output Data) FWH[3:0] or LAD[3:0] (Float Output Data) T ON T OFF PRELIMINARY (September, 2005, Version 0.0) 22 AMIC Technology, Corp. A49FL004 Table 20: FWH/LPC Interface AC Input/Output Characteristics Symbol Parameter Test Conditions Min Max Units 0 < VOUT ≤ 0.3VDD IOH (AC) Switching Current High (Test Point) IOL (AC) Switching Current Low (Test Point) ICL ICH slewr (2) -12 VDD -17.1(VDD-VOUT) Equation C -32 VDD 16VDD -17.1(VDD – VOUT) Equation D (1) 38VDD -25+(VIN+1)/0.015 25+(VIN-VDD-1)/0.015 1 1 4 4 (1) mA mA mA mA mA mA mA mA V/ns V/ns 0.3VDD < VOUT ≤ 0.9VDD 0.7VDD < VOUT ≤ VDD VOUT = 0.7VDD VDD > VOUT ≥ 0.6VDD 0.6VDD > VOUT > 0.1VDD 0.18VDD > VOUT > 0 VOUT=0.18VDD -3 < VIN ≤ -1 VDD+4 > VIN > VDD+1 0.2VDD-0.6VDD load 0.6VDD-0.2VDD load Low Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate slewf (2) Notes: 1. See PCI specification. 2. PCI specification output load is used. Table 21: FWH Mode Interface Reset Timing Parameters, VDD=3.0-3.6V Symbol Parameter Min Max Units tPRST tKRST tRSTP tRSTF tRST (1) Reset Active Time to VCC Stable Reset Active Time to Clock Stable Reset Pulse Width Reset Active to Output Float Delay Reset Inactive Time to Input Active 1 100 100 50 1 ms µs ns ns ns Note: There will be an 10 µs reset latency if a reset procedure is performed during a programming or erase operation. Figure 11: Reset Timing Diagram VDD CLK TKRST RST / INIT TRSTF FWH[3:0] or LAD[3:0] FWH4 TRSTE TRST Program or Erase Operation Aborted TPRST TRSTP PRELIMINARY (September, 2005, Version 0.0) 23 AMIC Technology, Corp. A49FL004 Figure 12: A/A Mux Mode AC Input/Output Reference Waveforms VIHT INPUT VILT AC test inputs are driven at V IHT (0.9VDD) for a logic HIGH and VILT (0.1VDD) for a logic LOW. Measurement reference points for inputs and outputs are VIT (0.5VDD) and VOT (0.5VDD). Input rise and fall times (10% 90%) are < 5ns Note: V IT: VINPUT Test V OT: VOUTPUT Test V IHT: VINPUT HIGH Test V ILT: VINPUT LOW Test VIT Reference Points VOT OUTPUT Figure 13: A/A Mux Mode Test Load Condition TO TESTER TO DUT CL=30pF PRELIMINARY (September, 2005, Version 0.0) 24 AMIC Technology, Corp. A49FL004 A/A MUX MODE AC CHARACTERISTICS Table 22: A/A Mux Mode Read Operations Characteristics Symbol tRC Parameter Min Max Units Read Cycle Time RST High to Row Address Setup Time R/ C Address Set-up Time R/ C Address Hold Time Address to Output Delay OE to Output Delay OE Output High Z 270 1 45 45 120 50 0 50 0 30 ns ms ns ns ns ns ns µs tRST tAS tAH tAA tOE tDF tVCS tOH VDD Setup Time Output Hold from OE or Address, whichever occurred first ns Table 21: A/A Mux Write (Program/Erase) Operations Characteristics Symbol tRST Parameter Min Max Units RST High to Row Address Setup Time R/ C Address Setup Time R/ C Address Hold Time R/ C to WE High Time OE High Setup Time OE High Hold Time 1 50 50 50 20 20 100 100 50 5 40 80 50 ms ns ns ns ns ns ns ns ns ns µs tAS tAH tCWH tOES tOEH tWP tWPH tDS tDH tBP tEC tVCS Write Pulse Width WE Pulse Width High Data Setup Time Data Hold Time Byte Programming Time Chip, Sector or Block Erase Cycle Time VDD Setup Time ms µs Figure 14: A/A Mux Mode Read Cycle Timing Diagram TRSTP RST TRST Row Address TRC Column Address Row Address Column Address Address TAS R/C VIH TAH TAS TAH WE TAA TOH OE TOE High-Z TOLZ Data Valid TOHZ High-Z I/O7-I/O0 PRELIMINARY (September, 2005, Version 0.0) 25 AMIC Technology, Corp. A49FL004 Figure 15: A/A Mux Mode Write Cycle Timing Diagram TR STP RS T Address TRST R ow A ddress C olumn A ddress TAS R/C TA H TAS TA H TCWH O E TOES T WP T OEH TWPH WE TDS I/O7 -I/O0 High-Z D ata Valid TD H Figure 16: A/A Mux Mode Data# Polling Timing Diagram Address Row Address Column Address Row Address Column Address Row Address Column Address Row Address Column Address R/C WE TOEP OE High-Z I/O7 Data In Data# Data# Data Final Input Command Status Bit Status Bit Data Command Input Write Operation In Progress Write Operation Complete Figure 17: A/A Mux Mode Toggle Bit Timing Diagram A ddress Row Address Column Address Row Address Column Address Row Address Column Address Row Address Column Address R/C WE T OET OE High-Z I/O 6 Data In Data Final Input Command Status Bit Status Bit Data Command Input Write Operation In Progress Write Operation Complete PRELIMINARY (September, 2005, Version 0.0) 26 AMIC Technology, Corp. A49FL004 Figure 18: A/A Mux Mode Byte Program Timing Diagram Four-Byte Byte Program Command Sequence 5555 Address 2AAA 5555 PA R/C OE TWP TWPH TBP WE High-Z AA 55 A0 PD I/O7-I/O0 Byte Program Command Input PA = Byte Program Address PD = Byte Program Data Byte Program Operation In Progress Figure 19: A/A Mux Mode Block Erase Timing Diagram Six-Byte Block Erase Command Sequence 5555 Address 2AAA 5555 5555 2AAA BA R/C OE TWP TWPH TBE WE High-Z AA 55 80 AA 55 30/50 I/O7-I/O0 Block Erase Command Input BA = Block Address Block Erase Operation In Progress PRELIMINARY (September, 2005, Version 0.0) 27 AMIC Technology, Corp. A49FL004 Figure 20: A/A Mux Mode Chip Erase Timing Diagram Six-Byte Chip Erase Command Sequence 5555 Address 2AAA 5555 5555 2AAA 5555 R/C OE TWP TWPH TSCE WE High-Z AA 55 80 AA 55 10 I/O7-I/O0 Chip Erase Command Input Chip Erase Operation In Progress Figure 21: A/A Mux Mode Product ID Entry and Read Timing Diagram Three-Byte Product ID Entry Command Sequence 5555 Address 2AAA 5555 0000 0001 0003 R/C OE TWP TWPH TIDA WE High-Z AA 55 90 37 TAA 95 7F I/O7-I/O0 Figure 22: A/A Mux Mode Product ID Exit and Reset Timing Diagram Three-Byte Product ID Exit and Reset Command Sequence 5555 Address 2AAA 5555 R/C OE TWP TWPH WE High-Z AA 55 F0 I/O7-I/O0 PRELIMINARY (September, 2005, Version 0.0) 28 AMIC Technology, Corp. A49FL004 Figure 23: Automatic Byte Program Algorithm Start Write Command Address: 5555H Data: AAH Write Command Address: 2AAAH Data: 55H Write Command Address: 5555H Data: A0H Write Command Address: PA Data: PD NO I/O7 = Data ? Or I/O6 Stop Toggle? YES Byte Program Completed PA: Byte Program Address PD: Byte Program Data PRELIMINARY (September, 2005, Version 0.0) 29 AMIC Technology, Corp. A49FL004 Figure 24: Automatic Block Erase Algorithm Start Write Command Address: 5555H Data: AAH Write Command Address: 2AAAH Data: 55H Write Command Address: 5555H Data: 80H Write Command Address: 5555H Data: AAH NO Write Command Address: 2AAAH Data: 55H I/O7 = Data ? Or I/O6 Stop Toggle? YES Write Command Address: BA Data: 30H or 50H Block Erase Completed BA: Block Address PRELIMINARY (September, 2005, Version 0.0) 30 AMIC Technology, Corp. A49FL004 Figure 25: Automatic Chip Erase Algorithm Start Write Command Address: 5555H Data: AAH Write Command Address: 2AAAH Data: 55H Write Command Address: 5555H Data: 80H Write Command Address: 5555H Data: AAH NO Write Command Address: 2AAAH Data: 55H I/O7 = Data ? Or I/O6 Stop Toggle? YES Write Command Address: 5555H Data: 10H Chip Erase Completed PRELIMINARY (September, 2005, Version 0.0) 31 AMIC Technology, Corp. A49FL004 Figure 26: Product ID Command Flowchart Start Start OR Write Command Address: 5555H Data: AAH Write Command Address: 5555H Data: AAH Write Command Address: 2AAAH Data: 55H Write Command Address: 2AAAH Data: 55H Write Command Address: 5555H Data: 90H Write Command Address: 5555H Data: F0H Write Command Address: XXXXH Data: F0H Enter Product ID Mode Exit Product ID Mode PRELIMINARY (September, 2005, Version 0.0) 32 AMIC Technology, Corp. A49FL004 Ordering Information A49FL004T x - 33 C Temperature Range C = Commercial (0°C to +85°C) Clock Frequency 33 = 33MHz Package Type L = PLCC X = TSOP (8mmX14mm) Device Number 4 Mbit FWH Flash Memory Part No. Clock Frequency (MHz) Boot Block Location Top Temperature Range 0°C to +85°C 0°C to +85°C 0°C to +85°C 0°C to +85°C Package Type A49FL004TL-33 32-pin PLCC A49FL004TL-33F Top 33 Top Top 32-pin Pb-Free PLCC 32-pin TSOP (8mm X 14 mm) 32-pin Pb-Free TSOP (8mm X 14 mm) A49FL004TX-33 A49FL004TX-33F PRELIMINARY (September, 2005, Version 0.0) 33 AMIC Technology, Corp. A49FL004 Package Information PLCC 32L Outline Dimension HD D 13 5 unit: inches/mm 14 4 32 20 30 21 29 A2 A HE 1 E b1 GD y D A1 e b GE θ Dimensions in inches Dimensions in mm Min 0.47 2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91 0° Nom 2.80 0.71 0.46 0.254 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29 Max 3.40 2.93 0.81 0.54 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.075 10° Symbol A A1 A2 b1 b C D E e GD GE HD HE L y θ Min 0.0185 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075 0° Nom 0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090 - Max 0.134 0.115 0.032 0.021 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.003 10° Notes: 1. Dimensions D and E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only. PRELIMINARY (September, 2005, Version 0.0) 34 AMIC Technology, Corp. L c A49FL004 Package Information TSOP 32L TYPE I (8 X 14mm) Outline Dimensions unit: inches/mm Pin1 0.254 Gage Plane θ L Detail "A" A2 E D1 D Detail "A" A1 c e b y D Dimensions in inches Symbol A A1 A2 b c E e D D1 L y θ Min 0.002 0.037 0.0067 0.004 0.311 0.543 0.484 0.020 0.000 0° Nom 0.039 0.0087 0.315 0.0197 0.551 0.488 0.024 3° Max 0.047 0.006 0.041 0.0106 0.0083 0.319 0.559 0.492 0.028 0.003 5° Dimensions in mm Min 0.05 0.95 0.17 0.10 7.90 13.80 12.30 0.50 0.00 0° Nom 1.00 0.22 8.00 0.50 14.00 12.40 0.60 3° Max 1.20 0.15 1.05 0.27 0.21 8.10 14.20 12.50 0.70 0.076 5° Notes: 1. Dimension E does not include mold flash. 2. Dimension D1 does not include interlead flash. 2. Dimension b does not include dambar protrusion. PRELIMINARY (September, 2005, Version 0.0) 35 AMIC Technology, Corp. A