A63L73321

A63L73321 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output Preliminary Document Title 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flowthrough Data Output Revision History Rev. No. 0.0 0.1 0.2 0.3 0.4 History Initial issue Change fast access times from 8.5/9.5/10 ns to 9.5/10/12 ns Change ICC1 from 300mA to 350mA(max.) Add description for 100/91/83 MHz Add description for 2E1D at page 1 Modify waveform at page 11 Delete -9.5 & -10 part number Change -12 cycle time from 12ns to 15ns Issue Date December 14, 1998 June 9, 1999 December 19, 1999 June 20, 2000 August 29, 2001 Remark Preliminary PRELIMINARY (August, 2000, Version 0.4) AMIC Technology, Inc. A63L73321 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output Preliminary Features n n n n n Fast access times: 12ns at 66MHz Single +3.3V+10% or +3.3V-5% power supply Synchronous burst function Individual Byte Write control and Global Write Double-cycle enable, single-cycle deselect n Three separate chip enables allow wide range of options for CE control, address pipelining n Selectable BURST mode n SLEEP mode (ZZ pin) provided n Available in 100-pin LQFP package General Description The A63L73321 is a high-speed, low-power SRAM containing 4,194,304 bits of bit synchronous memory, organized as 131,072 words by 32 bits. The A63L73321 combines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output buffer and a 128K X 32 SRAM core to provide a wide range of data RAM applications. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. Synchronous inputs include all addresses (A0 A16), all data inputs (I/O1 - I/O32), active LOW chip enable ( CE ), two additional chip enables (CE2, CE2 ), burst control inputs ( ADSC , ADSP , ADV ), byte write enables ( BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write ( GW ). Asynchronous inputs include output enable ( OE ), clock (CLK), BURST mode (MODE) and SLEEP mode (ZZ). Burst operations can be initiated with either the address status processor ( ADSP ) or address status controller ( ADSC ) input pin. Subsequent burst sequence burst addresses can be internally generated by the A63L73321 and controlled by the burst advance ( ADV ) pin. Write cycles are internally self-timed and synchronous with the rising edge of the clock (CLK). This feature simplifies the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/O1 - I/O8, BW2 controls I/O9 - I/O16, BW3 controls I/O17 - I/O24, and BW4 controls I/O25 - I/O32, all on the condition that BWE is LOW. GW LOW causes all bytes to be written. PRELIMINARY (August, 2000, Version 0.4) 1 AMIC Technology, Inc. A63L73321 Pin Configuration ADSC ADSP BWE BW4 BW3 BW2 BW1 GND VCC ADV CLK CE2 CE2 GW OE CE A6 A7 A8 82 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 NC I/O17 I/O18 VCCQ GNDQ I/O19 I/O20 I/O21 I/O22 GNDQ VCCQ I/O23 I/O24 NC VCC NC GND I/O25 I/O26 VCCQ GNDQ I/O27 I/O28 I/O29 I/O30 GNDQ VCCQ I/O31 I/O32 NC 100 81 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 NC I/O16 I/O15 VCCQ GNDQ I/O14 I/O13 I/O12 I/O11 GNDQ VCCQ I/O10 I/O9 GND NC VCC ZZ I/O8 I/O7 VCCQ GNDQ I/O6 I/O5 I/O4 I/O3 GNDQ VCCQ I/O2 I/O1 NC A63L73321E 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VCC NC NC NC GND NC A10 A11 A12 A13 A14 A15 MODE A16 A5 A4 A3 A2 A1 A0 x PRELIMINARY (August, 2000, Version 0.4) 2 AMIC Technology, Inc. A63L73321 Block Diagram ZZ MODE MODE LOGIC ADV CLK CLK LOGIC ADSC ADSP BURST LOGIC ADDRESS COUNTER CLR A0-A16 ADDRESS REGISTERS 17 8 BYTE1 WRITE DRIVER 8 GW BWE BW1 BW2 BW3 BW4 BYTE WRITE ENABLE LOGIC 8 BYTE2 WRITE DRIVER BYTE3 WRITE DRIVER BYTE4 WRITE DRIVER 8 8 128KX8X4 32 MEMORY OUTPUT BUFFER ARRAY 8 8 8 32 4 DATA-IN REGISTERS 4 CHIP ENABLE LOGIC CE CE2 CE2 OE I/O1 - I/O32 OUTPUT ENABLE LOGIC PRELIMINARY (August, 2000, Version 0.4) 3 AMIC Technology, Inc. A63L73321 Pin Description Pin No. 32 - 37, 44 - 50, 81, 82, 99, 100 89 87, 93 - 96 88 86 92, 97, 98 83 84 85 31 Symbol A0 - A16 Address Inputs Description CLK BWE , BW1 - BW4 GW OE CE2 ,CE2, CE ADV ADSP ADSC MODE Clock Byte Write Enables Global Write Output Enable Chip Enables Burst Address Advance Processor Address Status Controller Address Status Burst Mode: HIGH or NC (Interleaved burst) LOW (Linear burst) Asynchronous Power-Down (Snooze): HIGH (Sleep) LOW or NC (Wake up) Data Inputs/Outputs 64 ZZ 2, 3, 6 - 9, 12, 13, 18, 19, 22 - 25, 28, 29, 52, 53, 56 - 59, 62, 63, 68, 69, 72 - 75, 78, 79 1, 14, 16, 30, 38, 39, 42, 43, 51, 66, 80 15, 41, 65, 91 17, 40, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 I/O1- I/O32 NC No Connection VCC GND VCCQ Power Supply Ground Isolated Output Buffer Supply GNDQ Isolated Output Buffer Ground PRELIMINARY (August, 2000, Version 0.4) 4 AMIC Technology, Inc. A63L73321 Synchronous Truth Table (See Notes 1 Through 5) Operation Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Address Used NONE NONE NONE NONE NONE External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE H L L L L L L L L L X X H H X H X X H H X H CE2 CE2 X L X L X H H H H H X X X X X X X X X X X X ADSP X L L H H L L H H H H H X X H X H H X X H X ADSC ADV X X X X X X X X X X L L L L L L H H H H H H WRITE OE X X X X X L H X L H L H L H X X L H L H X X CLK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H X X H X H L L L L L X X X X X X X X X X X X L X X L L X X L L L H H H H H H H H H H H H X X X X X X X L H H H H H H L L H H H H L L I/O Operation High-Z High-Z High-Z High-Z High-Z Dout High-Z Din Dout High-Z Dout High-Z Dout High-Z Din Din Dout High-Z Dout High-Z Din Din PRELIMINARY (August, 2000, Version 0.4) 5 AMIC Technology, Inc. A63L73321 Notes: 1. X = "Disregard", H = Logic High, L = Logic Low. 2. WRITE = L means: 1) Any BWx ( BW1, BW2 , BW3 , or BW4 ) and BWE are low or 2) GW is low. 3. All inputs except OE must be synchronized with setup and hold times around the rising edge (L-H) of CLK. 4. For write cycles that follow read cycles, OE must be HIGH before the input data request setup time and held HIGH throughout the input data hold time. 5. ADSP LOW always initiates an internal Read at the L-H edge of CLK. A Write is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. Refer to the Write timing diagram for clarification. Write Truth Table Operation READ READ WRITE Byte 1 WRITE all bytes WRITE all bytes GW H H H H L BWE H L L L X BW1 X H L L X BW2 X H H L X BW3 X H H L X BW4 X H H L X PRELIMINARY (August, 2000, Version 0.4) 6 AMIC Technology, Inc. A63L73321 Linear Burst Address Table (MODE = LOW) First Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 Second Address (Internal) X . . . X01 X . . . X10 X . . . X11 X . . . X00 Third Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 Fourth Address (Internal) X . . . X11 X . . . X00 X . . . X01 X . . . X10 Interleaved Burst Address Table (MODE = HIGH or NC) First Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 Second Address (Internal) X . . . X01 X . . . X00 X . . . X11 X . . . X10 Third Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 Fourth Address (Internal) X . . . X11 X . . . X10 X . . . X01 X . . . X00 Absolute Maximum Ratings* Power Supply Voltage (VCC) . . . . . . . . . . -0.5V to +4.6V Voltage Relative to GND for any Pin Except VCC (Vin, Vout) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 2W Operating Temperature (Topr) . . . . . . . . . . . 0°C to 70°C Storage Temperature (Tbias) . . . . . . . . . . -10°C to 85 °C Storage Temperature (Tstg) . . . . . . . . . . . -55°C to 125°C *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (0°C ≤ TA ≤ 70°C, VCC, VCCQ = 3.3V+10% or 3.3V-5%, unless otherwise noted) Symbol VCC VCCQ GND VIH VIHQ VIL Parameter Supply Voltage (Operating Voltage Range) Isolated Input Buffer Supply Supply Voltage to GND Input High Voltage Input High Voltage (I/O Pins) Input Low Voltage Min. 3.135 3.135 0.0 2.0 2.0 -0.3 Typ. 3.3 3.3 Max. 3.6 VCC 0.0 VCC+0.3 VCC+0.3 0.8 Unit V V V V V V 1, 2 1, 2 Note PRELIMINARY (August, 2000, Version 0.4) 7 AMIC Technology, Inc. A63L73321 DC Electrical Characteristics (0°C ≤ TA ≤ 70°C, VCC, VCCQ = 3.3V+10% or 3.3V-5%, unless otherwise noted) Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Min. Max. ±2.0 ±2.0 Unit µA µA Test Conditions All inputs VIN = GND to VCC OE = VIH, Vout = GND to VCC Device selected; VCC = max. Iout = 0mA, all inputs = VIH or VIL Cycle time = tKC min. Device deselected; VCC = max. All inputs are fixed. All inputs ≥ VCC - 0.2V or ≤ GND + 0.2V Cycle time = tKC min. ZZ ≥ VCC - 0.2V IOL = 8 mA IOH = -4 mA Note ICC1 Supply Current - 350 mA 3, 11 ISB1 Standby Current - 25 mA 11 ISB2 VOL VOH Output Low Voltage Output High Voltage 2.4 10 0.4 - mA V V Capacitance Symbol CIN CI/O Parameter Input Capacitance Input/Output Capacitance Typ. 3 4 Max. 4 5 Unit pF pF Conditions TA = 25 C; f = 1MHz VCC = 3.3V * These parameters are sampled and not 100% tested. PRELIMINARY (August, 2000, Version 0.4) 8 AMIC Technology, Inc. A63L73321 AC Characteristics (0°C ≤ TA ≤ 70°C, VCC = 3.3V+10% or 3.3V-5%) Symbol Parameter Min. tKC tKH tKL tKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ Clock Cycle Time Clock High Time Clock Low Time Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock to Output in High-Z OE to Output Valid OE to Output in Low-Z OE to Output in High-Z 15 4.0 4.0 3.0 4.0 0 -12 Max. 12 5.0 5.0 5.0 ns ns ns ns ns ns ns ns ns ns 5, 6 5, 6 8 5, 6 5, 6 Unit Note Setup Times tAS tADSS tADVS tWS Address Address Status ( ADSC , ADSP ) Address Advance ( ADV ) Write Signals ( BW1, BW2 , BW3 , BW4 , BWE , GW ) tDS tCES Data-in Chip Enable ( CE , CE2, CE2 ) 2.5 2.5 ns ns 7, 9 7, 9 2.5 2.5 2.5 2.5 ns ns ns ns 7, 9 7, 9 7, 9 7, 9 PRELIMINARY (August, 2000, Version 0.4) 9 AMIC Technology, Inc. A63L73321 AC Characteristics (continued) Symbol Parameter Min. Hold Times tAH tADSH tAAH tWH Address Address Status ( ADSC , ADSP ) Address Advance ( ADV ) Write Signal ( BW1, BW2 , BW3 , BW4 , BWE , GW ) tDH tCEH Data-in Chip Enable ( CE , CE2, CE2 ) 0.5 0.5 ns ns 7, 9 7, 9 0.5 0.5 0.5 0.5 ns ns ns ns 7, 9 7, 9 7, 9 7, 9 -12 Max. Unit Note Notes: 1. All voltages refer to GND. 2. Overshoot: VIH ≤ +4.6V for t ≤ tKC/2. Undershoot: VIL ≥ -0.7V for t ≤ tKC/2. Power-up: VIH ≤ +3.6 and VCC ≤ 3.1V for t ≤ 200ms 3. ICC1 is given with no output current. ICC1 increases with greater output loading and faster cycle times. 4. Test conditions assume the output loading shown in Figure 1, unless otherwise specified. 5. For output loading, CL = 5pF, as shown in Figure 2. Transition is measured ±150mV from steady state voltage. 6. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tQELZ. 7. A WRITE cycle is defined by at least one Byte Write enable LOW and ADSP HIGH for the required setup and hold times. A READ cycle is defined by all byte write enables HIGH and ( ADSC or ADV LOW) or ADSP LOW for the required setup and hold times. 8. OE has no effect when a Byte Write enable is sampled LOW. 9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP or ADSC is LOW and the chip is enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP or ADSC is LOW to remain enabled. 10. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the given DC values. AC I/O curves are available upon request. 11. "Device Deselected" means device is in POWER-DOWN mode, as defined in the truth table. "Device Selected" means device is active (not in POWER-DOWN mode). 12. MODE pin has an internal pulled-up, and ZZ pin has an internal pulled-down. All of then exhibit an input leakage current of 10µA. 13. Snooze (ZZ) input is recommended that users plan for four clock cycles to go into SLEEP mode and four clocks to emerge from SLEEP mode to ensure no data is lost. PRELIMINARY (August, 2000, Version 0.4) 10 AMIC Technology, Inc. A63L73321 Timing Waveforms tKC CLK tKH tADSS ADSP tADSS ADSC tAS ADDRESS A1 tWS GW,BWE BW1-BW4 tCES CE (NOTE 2) tADVS ADV ADV suspends burst OE (NOTE 3) tOEQ tKQLZ DOUT High-Z tKQ Single READ Q(A1) tOELZ tOEHZ tKQ tKQX Q(A2) Q(A2+1) (NOTE *1) BURST READ Q(A2+2) Q(A2+3) tKQX Q(A3) tKQHZ tADVH tCEH Deselect with CE tWH tAH A2 A3 tADSH Deselect cycle tADSH tKL Don't Care Undefined Read Timing Notes: 1. QA(2) refers to output from address A2. Q(A2+1) refers to output from the next internal burst address following A2. 2. CE and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE does not cause Q to be driven until after the following clock rising edge. PRELIMINARY (August, 2000, Version 0.4) 11 AMIC Technology, Inc. A63L73321 Timing Waveforms (continued) tKC CLK tKH tADSS ADSP tADSS ADSC tAS ADDRESS A1 tAH A2 BYTE WRITE signals are ignored for first cycle when ADSP initiates burst BWE,BW1-BW4 (NOTE 5) tWS GW tCES CE (NOTE 2) tADVS ADV (NOTE 4) ADV suspends burst tADVH tCEH tWH A3 tWS tWH tADSH ADSC extends burst tADSS tADSH tADSH tKL OE (NOTE 3) tDS tDH D(A1) tOEHZ D(A2) D(A2+1) (NOTE 1) D(A2+1) D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2) DIN High-Z DOUT BURST READ Single WRITE Extended BURST WRITE Don't Care Undefined Write Timing Notes: 1. D(A2) refers to output from address A2. D(A2+1) refers to output from the internal burst address immediately following A2. 2. Timing for CE2 and CE2 is identical to that for CE . As shown in the above diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. 3. OE must be HIGH before the input data setup, and held HIGH throughout the data hold period. This prevents input/output data contention for the period prior to the time Byte Write enable inputs are sampled. 4. ADV must be HIGH to permit a Write to the loaded address. 5. Byte Write enables are decided by means of a Write truth table. PRELIMINARY (August, 2000, Version 0.4) 12 AMIC Technology, Inc. A63L73321 Timing Waveforms (continued) tKC CLK tKH tADSS ADSP tADSH tKL ADSC tAS tAH ADDRESS A1 A2 A3 tWS GW,BWE, BW1-BW4 (NOTE 3) tCES CE (NOTE 2) tCEH tWH A4 A5 A6 ADV OE tKQ DIN High-Z tOEHZ tKQ DOUT Q(A1) Q(A2) Single WRITE Q(A4) (NOTE 1) Q(A4+1) Q(A4+2) Q(A4+3) Back-to-Back WRITEs tDS tDH tOELZ D(A5) D(A6) D(A3) Back-to-Back READs BURST READ Don't Care Undefined Read/Write Timing Notes: 1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the next internal burst address following A4. 2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE is LOW and CE2 is HIGH, When CE is HIGH, CE2 is HIGH and CE2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP , ADSC , or ADV cycle is performed. 4. Byte Write enables are decided by means of a Write truth table. 5. Back-to-back READs may be controlled by either ADSP or ADSC PRELIMINARY (August, 2000, Version 0.4) 13 AMIC Technology, Inc. A63L73321 AC Test Conditions Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3V 1.5ns 1.5V 1.5V See Figures 1 and 2 Q 350Ω 5pF Q ZO=50Ω RL=50Ω VT=1.5V Figure 1. Output Load Equivalent +3.3V 320Ω Figure 2. Output Load Equivalent PRELIMINARY (August, 2000, Version 0.4) 14 AMIC Technology, Inc. A63L73321 Ordering Information Part No. A63L73321E-12 Access Times (ns) 12 Frequency (MHz) 66 Package 100L LQFP PRELIMINARY (August, 2000, Version 0.4) 15 AMIC Technology, Inc. A63L73321 Package Information LQFP 100L Outline Dimensions unit: inches/mm HE E 80 51 A2 A1 y D 81 50 HD D 100 31 1 30 e b c θ Symbol A1 A2 b c HE E HD D e L L1 y θ Dimensions in inches Min. 0.002 0.053 0.011 0.005 0.860 0.783 0.624 0.547 Nom. 0.055 0.013 0.866 0.787 0.630 0.551 0.026 BSC 0.018 0.024 0.039 REF 0° 3.5° 0.004 7° 0.030 Max. 0.057 0.015 0.008 0.872 0.791 0.636 0.555 Dimensions in mm Min. 0.05 1.35 0.27 0.12 21.85 19.90 15.85 13.90 Nom. 1.40 0.32 22.00 20.00 16.00 14.00 0.65 BSC 0.45 0.60 1.00 REF 0° 3.5° 0.1 7° 0.75 Max. 1.45 0.37 0.20 22.15 20.10 16.15 14.10 Notes: 1. Dimensions D and E do not include mold protrusion. 2. Dimensions b does not include dambar protrusion. Total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. L L1 PRELIMINARY (August, 2000, Version 0.4) 16 AMIC Technology, Inc.