A64S0616G-70I

A64S16161 Preliminary Features ● Memory Cell : Dynamic memory( DRAM ) ● Refresh: Completely free ● Power Down: Control by CS2( No Data Retention ) ● Byte Control : Capable of single byte operation ● Power Consumption: 100μA( Standby Current ) ● Operating Temperature Range: -40’C~+85’C ● Composition:2,097,152 Word X 16 Bit ● Supply Power Voltage:2.70V to 3.30V ● Access Time: 70nS ● Access Time ( Page Access Read ): 30nS ● I/O Terminal :Input / Output Common 3-state output 2M X 16 Bit Low Voltage Super RAM 1 A B C D E F G H LB# 2 OE# 3 A0 4 A1 5 A2 6 CE2 DQ8 UB# A3 A4 CE1# DQ0 DQ9 DQ10 A5 A6 DQ1 DQ2 VSS DQ11 A17 A7 DQ3 VCC Pin Description Pin Name CS1# CS2 WE# OE# A0 to A20 IO0-7 IO8-15 LB# UB# VCC VSS Description Chip select 1 ( Low Active ) Chip select 2 ( High Active ) Write enable ( Low Active ) Output enable ( Low Active ) Address Input ( A0 to A2 : Page Address) Lower Byte Input / Output Upper Byte Input / Output Lower Byte Control ( Low Active ) Upper Byte Control ( Low Active ) Power Supply Ground ( 0V) VCC DQ12 NC A16 DQ4 VSS DQ14 DQ13 A14 A15 DQ5 DQ6 DQ15 A19 A12 A13 WE# DQ7 A18 A8 A9 A10 A11 A20 Description A64S16161 is a virtually static RAM, which uses DRAM type memory cells, but it has refresh transparency, so that you need not to imply refresh operation. Furthermore the interface is completely compatible to a low power Asynchronous type SRAM, you can operate as same as the Asynchronous SRAM. A64S16161 is a 2,097,152 Words X 16 bit asynchronous random access memory on a monolithic CMOS chip with marvelous low power consumption technology. Its low power and also low noise makes it ideal for mobile applications. PRELIMINARY (December, 2003, Version 0.0) 1 AMIC Technology Corp. A64S16161 Block Diagram A0 A1 A2 A3 A4 A5 A6 Row Decoder A7 A8 Address Buffer A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 8 Column Decoder 256 Column Gate 256X16 13 8192 Memory Cell ATD Control 16 Refresh Control CS1# CS2 CS1#,CS2 Control Input / Output Buffer WE# OE# LB# UB# WE#,OE# LB#,UB# Control I / O0 ．．．．．．．．．．．．．． I / O15 PRELIMINARY (December, 2003, Version 0.0) 2 AMIC Technology Corp. A64S16161 Functions Truth Table A0-20 V V V V V V V V X X CS1# L L L L L L L L H X CS2 H H H H H H H H H L WE# H H H H H L L L X X OE# L L L X H H H H X X LB# L L H H X L L H X X UB# L H L H X L H L X X I/O0~7 Data-Out Data-Out High-Z High-Z High-Z Data-In Data-In High-Z High-Z High-Z I/O8~15 Data-Out High-Z Data-Out High-Z High-Z Data-In High-Z Data-In High-Z High-Z Mode Read Read Read Output Disable Output Disable Write Write Write Standby Power Down*¹ V : Valid Address. X : High or Low .*1 No Data Retention Read Operation It is possible to control data width by LB# and UB# pins. (1)Reading data from lower byte Date can be read when the address is set while holding CS1#=L, CS2=H, OE #=L , WE #= H and LB #=L. (2)Reading data from upper byte Date can be read when the address is set while holding CS1#=L, CS2=H, OE #=L , WE #= H and UB #=L. (3)Reading date from both bytes Date can be read when the address is set while holding CS1#=L, CS2=H, OE #=L , WE #= H , LB #=L and UB #=L. (4)Page access read Date can be read by changing A0-A2 when A3-A20 is set while holding CS1#=L, CS2=H, WE #=H, OE #=L, LB #=L and UB #=L. Writing Operation (1) Writing data into lower byte ( WE # control ) Data can be written by adding L pulse into WE # when the address is set while holding CS1#=L, CS2=H, OE #=H, LB #=L and UB #=H. The data on lower byte are latched up into the memory cell during WE # =L and LB # =L. (2) Writing data into lower byte (LB # control) Data can be written by adding L pulse into LB # when the address is set while holding CS1#=L, CS2 =H, OE#=H, UB# =H and WE#=L. The data on lower byte are latched up into the memory cell during WE# =L and LB# = L. (3) Writing data into upper byte (WE # control) Data can be written by adding L pulse into WE # when the address is set while holding CS1 #=L, CS2 =H, OE #=H, LB # =H and UB #=L. The data on upper byte are latched up into the memory cell during WE # =L and UB # = L. PRELIMINARY (December, 2003, Version 0.0) 3 AMIC Technology Corp. A64S16161 (4) Writing data into upper byte (UB # control) Data can be written by adding L pulse into UB # when the address is set while holding CS1 #=L, CS2 =H, OE #=H, LB # =H and WE #=L. The data on upper byte are latched up into the memory cell during WE #=L and UB #=L. (5) Writing data into both byte ( WE # control) Data can be written by adding L pulse into WE # when the address is set while holding CS1 #=L, CS2=H, OE #=H, LB #=L and UB #=L. The data are latched up into the memory cell during WE #=L, LB #=L and UB #=L. (6) Writing data into both byte (LB #, UB # control) Data can be written by adding L pulse into LB# and UB# when the address is set while holding CS1#=L, CS2=H, OE #=H and WE #=L. The data are latched up into the memory cell during WE #=L, LB #=L and UB #=L Read or write with using both LB # and UB #, the timing edge of LB # and UB # must be same. While I/O pins are in the output state, the data that is opposite to the output data should not be given. Standby cycle When CS1# is H, the device will be in the standby cycle. In this case data I/O pins are Hi-Z and all input pins are inhibited. Power Down When CS2 is L, the device will be in the power down. In this case, an internal refresh stops and the data might be lost. ABSOLUTE MAXIMUM RATINGS (VSS=0V) Parameter Supply voltage Input voltage Input / Output voltage Input / Output voltage Operating temperature Storage temperature Symbol VCC VI V I/O PD Topr Tstg Ratings -0.5 to 3.6 -0.5* to VCC+0.3 -0.5* to VCC+0.3 0.5 -40 to 85 -65 to 150 Unit V V V W ＇C ｀C * If pulse width is less than 5ns it is – 1.0V PRELIMINARY (December, 2003, Version 0.0) 4 AMIC Technology Corp. A64S16161 ELECTRICAL CHARACTERISTICS DC Recommended Operating Conditions (Ta=-40~85＇C) Parameter Supply voltage Symbo1 VCC VSS VIH Input voltage VIL * If pulse width is less than 5ns it is –1.0V -0.3* 0.3 V Min 2.70 0 VCC-0.3 Max 3.30 0 VCC+0.3 Unit V V V DC ELECTRICAL CHARACTERISTICS DC Characteristics (Ta=-40~85’C) Parameter Input leakage current Output leakage current Symbol ILI ILO Condition VI=0V to VCC LB# and UB#=H or CS1#=H or WE#=L or OE#=H or CS2=L VI/O=0V to VCC High level output voltage Low level output voltage Power Down Current Standby Current Operating current Operating current Operating current VOH VOL IDDPD IDDS IDDA1 IDDA2 IDDA3 IOH=-0.5ｍA IOL=0.5ｍA CS2≦0.2V VCC-0.2V≦CS1# I I/O=0ｍA, tcyc=70ns*² I I/O=0ｍA, tcyc=1uS*² I I/O=0ｍA, tcyc=70ns*³ Vcc-0.3 ﹣ ﹣ ﹣ ﹣ ﹣ ﹣ ﹣ ﹣ 60 25 3.0 20 ﹣ 0.3 25 100 30 3.5 30 V V µA µA ｍA ｍA ｍA Min -1 -1 Typ*¹ ﹣ ﹣ Max 1 1 Unit µA µA *1:Typical values are measured at Ta=25’C and VCC =3.0V *2:Random access *3:Page access read Terminal Capacitance (Ta=25’C f=1MHz) Parameter Input Capacitance I/O Capacitance Symbol CI C I/O Conditions VI=0V V I/O=0V Min ﹣ ﹣ Max 8 10 Unit pF pF Note：This parameter is measured by sampling , not of all products. PRELIMINARY (December, 2003, Version 0.0) 5 AMIC Technology Corp. A64S16161 AC Electrical Characteristics Read Cycle (Ta = - 30 ~ 85’C) Parameter Read cycle time Page read cycle time Address access time Page address access time CS1 # access time OE # access time LB # , UB # access time CS1# high pulse width Address set up to OE L # CS1 # output set time CS1 # output floating time LB # , UB # output set time LB # , UB # output floating time OE # output set time OE # output floating time Output hold time Symbol tRC tRCP tACC tACCP tACS tOE tAB tC1H tASO tCHZ tCLZ tBLZ tBLZ tOLZ tOHZ tOH Teat Conditions 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 1 Min 70 30 30 -5 0 0 0 5 Max 32000 32000 70 30 70 35 25 15 15 15 Unit nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS Write Cycle (Ta= - 40~85’C) Parameter Write cycle time Chip select time CS1# H pulse width Address enable time Address set up time Write pulse width LB,UB select time Address hold time Data set up time Data hold time Symbol tWC tCW tC1H tAW tAS tWP tBW tWR tDW tDH 1 1 1 1 1 1 1 Test Conditions 1 1 Min 70 60 30 60 0 40 60 0 30 0 nS nS nS nS nS nS nS Max 32000 Unit nS nS PRELIMINARY (December, 2003, Version 0.0) 6 AMIC Technology Corp. A64S16161 Power Down Cycle(Ta= - 40~85＇C) Parameter CS1 # H set up time for Power Down entry CS1 # H hold time before Power Down exit CS2 L pulse width CS1 # H hold time after Power Down exit Symbol tSSP tSHP TC2LP tHPD Test Conditions 1 1 1 1 Min 0 0 30 300 Max Unit nS nS nS µS Power Up Timing Requirement(Ta= - 40~85＇C) Parameter CS1 # CS2 set up time after Power Up Standby hold time after Power Up Symbol tSHU tHPU Test Conditions 1 1 Min 0 300 Max Unit nS µS Data Retention Timing Requirement(Ta= - 40~85＇C) Parameter A3 to A20 hold time during active CS1# L hold time for A3 to A20 fix Either tBAH or tCSH required for data retention. Symbol tBAH tCSH Test Conditions 1 1 Min Max 32 32 Unit nS nS Address Skew Timing Requirement(Ta= - 40~85＇C) Parameter Maximum address skew Symbol tSKEW Test Conditions 1 Min Max 10 Unit nS PRELIMINARY (December, 2003, Version 0.0) 7 AMIC Technology Corp. A64S16161 TEST CONDITION 1 Input pulse voltage level Input ascend / descend time Input output timing reference level Output load VCC – 0.3V / 0.3V tr=tf=3nS 2.0V/0.8V CL=50pF(Includes Jig capacity)+1TTL TEST CONDITION 2 Input pulse voltage level Input ascend / descend time Input output timing reference level Output load VCC – 0.3V / 0.3V tr=tf=3nS ±100mV(The level change from stable voltage CL=5pF(Includes Jig capacity)+1TTL I/O CL PRELIMINARY (December, 2003, Version 0.0) 8 AMIC Technology Corp. A64S16161 TIMING CHART Read Cycle tRC Address tACC tACS tOH CS1# tCHZ LB#/UB# tASO tAB tBHZ tOE OE# tOLZ tOHZ tBLZ tCLZ Dout CS2 and WE # must be H level for entire read cycle. Read Cycle ( Page Access [1] ) Address (A20-A3) tRC No Change tRCP tRCP Address (A2-A0) CS1# tCHZ tACS tACCP tACCP OE# tOH tCLZ tOH tOH Dout CS2 and WE # must be H level for entire read cycle. PRELIMINARY (December, 2003, Version 0.0) 9 AMIC Technology Corp. A64S16161 Read Cycle ( Page Access [2] ) Address (A20-A3) tRC No Change tRCP tRCP Address (A2-A0) CS1# tASO tACS tOE tACCP tACCP tCHZ OE# tOH tOLZ tOH tOH Dout CS2 and WE # must be H level for entire read cycle. Write Cycle ( WE # Control ) tWC Address tAW CS1# tCW tBW LB# / UB# tWR tAS tWP WE# tDW tDH Din CS2 and OE # must be H level for entire read cycle. PRELIMINARY (December, 2003, Version 0.0) 10 AMIC Technology Corp. A64S16161 Write Cycle ( LB # / UB # Control ) tWC Address tAW CS1# tAS tCW tBW tWR LB# / UB# tWP WE# tDW tDH Din CS2 and OE # must be H level for entire read cycle. Standby tC1H CS1# Active Standby Active PRELIMINARY (December, 2003, Version 0.0) 11 AMIC Technology Corp. A64S16161 Power Down Mode Entry / Exit CS1# tSHP tC2LP tHPD CS2 tSSP Power Up CS1# tSHU tHPU CS2 VCC VCC(min) Data Retention(1) tBAH Address (A20-A3) CS1# This applies for both read and write. PRELIMINARY (December, 2003, Version 0.0) 12 AMIC Technology Corp. A64S16161 Data Retention (2) Address (A20-A3) tCSH No Change CS1# This applies for both read and write. Address Skew(1) A0-20 tSKEW tRC / tWC CS1# tSKEW is from first address change to last address change Address Skew(2) A0-20 tRC / tWC tSKEW CS1# tSKEW is from first address change to last address change PRELIMINARY (December, 2003, Version 0.0) 13 AMIC Technology Corp. A64S16161 Address Skew(3) A0-20 tSKEW CS1# tSKEW is from first address change to stand-by Reference External Wiring Diagram Address Input Control Input / Output I / O0 I / O15 WE# OE# CS1# CS2 BU# LB# A0 A20 A64S16161 PRELIMINARY (December, 2003, Version 0.0) 14 AMIC Technology Corp. A64S16161 Ordering Information Operating Current Max. (mA) Power Down Mode Standby Current Max. (µA) 25 Part No. Access Time (ns) Package A64S0616G-70I 70 30 48B Mini BGA Note: -I is for industrial operating temperature range PRELIMINARY (December, 2003, Version 0.0) 15 AMIC Technology Corp. A64S16161 48 Pins FBGA Package outline drawing -A6.00 PIN#1 -B0.08 C CAVITY 0.96 0.10 C C 8.00 -C- 0.10 0.1 C SOLDER BALL SEATING PLANE 0.25 DETAIL : A 0.2 “A＂ SECTION C-C 3.75 0.75 M C A B 0.1 M C H G B 0.35 F E D C B A “B＂ 1 2 DETAIL : B 5.25 A 1 2 3 4 5 6 16 PRELIMINARY (December, 2003, Version 0.0) AMIC Technology Corp.