A65H83181P-5

A65H73361/A65H83181 Series Preliminary Document Title 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output Revision History Rev. No. 2.0 History Add JTAG standard Issue Date February 12, 1999 Remark Preliminary PRELIMINARY (February, 1999, Version 2.0) AMIC Technology, Inc. A65H73361/A65H83181 Series Preliminary Features n n n n 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output Fast access times: 2.5/3.0/3.5ns 128k x 36 or 256k x 18 organizations CMOS technology Register to register synchronous operation with selftimed late write n Single +3.3V ±5% power supply n Individual byte write and global write n n n n n n n HSTL input & output levels Boundary scan(JTAG) IEEE 1149.1 compatible Asynchronous output enable Sleep mode (ZZ) Programmable impedance output drivers JEDEC Standard pinout and boundary scan order 7 x 17 bump plastic ball grid array (PBGA) package General Description The A65H73361 and A65H83181 are 128k words by 36 bits and 256k words by 18 bits late write synchronous 4Mb SRAMS built using high performance CMOS process. The differential clock are used to control the timing of read/write operation and all internal operations are selftimed. The positive edge triggered CK clock input controls all addresses write-enables and Synchronous select and data ins are registered. The data outs are controlled by the output registers off the next positive clock edge to be updated. The internal write buffer enables write data to be accepted on the rising edge of the clock one cycle after address and control signals. The SRAM uses HSTL I/O interfaces with programmable impedance output drivers allowing the outputs to match the impedance of the circuit traces which reduces signal reflections. PRELIMINARY (February, 1999, Version 2.0) 1 AMIC Technology, Inc. A65H73361/A65H83181 Series Pin Configuration A65H73361 1 2 3 4 5 6 7 1 2 A65H83181 3 4 5 6 7 A VDDQ B NC C NC D DQ 18 E DQ 20 F VDDQ G DQ 23 H DQ 25 J VDDQ K DQ 34 L DQ 32 M VDDQ N DQ 29 P DQ 27 R NC T NC U VDDQ TMS TDI TCK TDO NC VDDQ NC SA3 SA2 SA13 NC ZZ SA4 M1 VDD M2 SA12 NC DQ 25 VSS SA1 VSS DQ 1 DQ 0 DQ 30 VSS SA0 VSS DQ 3 DQ 2 DQ 31 DQ 33 SBWd VSS CK SW SBWa VSS DQ 6 DQ 4 DQ 5 DQ 35 VSS CK VSS DQ 8 DQ 7 VDD Vref VDD Vref VDD VDDQ DQ 26 DQ 24 SBWC VSS NC NC SBWb VSS DQ 15 DQ 17 DQ 14 DQ 22 VSS G VSS DQ 13 VDDQ DQ 21 VSS SS VSS DQ 12 DQ 11 DQ 19 VSS ZQ VSS DQ 10 DQ 9 SA6 SA9 VDD SA10 SA15 NC NC SA8 NC SA11 NC NC SA5 SA7 NC SA16 SA14 VDDQ A VDDQ B NC C NC D DQ 9 E NC F VDDQ G NC H DQ 16 J VDDQ K NC L DQ 14 M VDDQ N DQ 11 P NC R NC T NC U VDDQ TMS TDI TCK TDO NC VDDQ SA2 SA3 NC SA17 SA12 ZZ SA4 M1 VDD M2 SA13 NC DQ 10 VSS SA1 VSS NC DQ 0 NC VSS SA0 VSS DQ 3 NC VDDQ DQ 13 VSS SW NC VSS CK SBWa VSS DQ 6 NC NC VDDQ DQ 17 VSS CK VSS NC DQ 7 VDD Vref VDD Vref VDD VDDQ DQ 16 NC DQ 15 SBWb VSS NC NC VSS VSS NC DQ 8 DQ 5 NC NC VSS G VSS DQ 4 VDDQ DQ 12 VSS SS VSS NC DQ 2 NC VSS ZQ VSS DQ 1 NC SA6 SA9 VDD SA10 SA15 NC NC SA8 NC SA11 NC NC SA5 SA7 NC SA16 SA14 VDDQ PRELIMINARY (February, 1999, Version 2.0) 2 AMIC Technology, Inc. A65H73361/A65H83181 Series Block Diagram SA0-SA17 CK SS ZZ SW SW Register Latch RD Add Register WR Add Register Row Decoder 128Kx36 or 256Kx18 Array Column Decoder Read/Write Amp 2:1 MUX SW Register SBW Latch SBW Register SBW Register Match 2:1 MUX Write Buffer Data Out Registor SS Register SS Register G DQ0 - DQ35 Pin Description SA0-SA17 Address input (X18 : SA0 - SA17, X36 : SA0 - SA16) DQ0-DQ35 Data I/O (X18 : DQ0 - DQ17, X36 : DQ0 - DQ35) G Asynchronous output enable SS M1, M2 VREP(2) VDD VSS VDDQ ZZ ZQ NC Synchronous select CK , CK Differential input register clocks Write enable. Global Write enable. Byte a (DQ0-DQ8) Write enable. Byte b (DQ9-DQ17) Write enable. Byte c (DQ18-DQ26) Write enable. Byte d (DQ27-DQ35) IEEE 1149.1 test inputs(LVTTL levels) IEEE 1149.1 test output(LVTTL level) For boundary scan purpose HSTL input reference voltage Power supply (+3.3V) Ground Output power supply Asynchronous sleep mode Output driver impedance control No connect SW SBWa SBWb SBWc SBWd TMS, TDI, TCK TDO PRELIMINARY (February, 1999, Version 2.0) 3 AMIC Technology, Inc. A65H73361/A65H83181 Series Clock Truth Table K LÕ H LÕ H LÕ H LÕ H LÕ H LÕ H LÕ H LÕ H X ZZ L L L L L L L L H SS L L L L L L L H X SW H L L L L L L X X SBWa SBWb SBWc SBWd DQ(n) X L H H H L H X X X H L H H L H X X X H H L H L H X X X H H H L L H X X X X X X X X X X High-Z DQ(n+1) MODE DOUT 0-35 Read Cycle ALL Bytes DIN 0-8 DIN 9-17 DIN 18-26 DIN 27-35 DIN 0-35 High-Z High-Z High-Z Write Cycle 1st Byte Write Cycle 2nd Byte Write Cycle 3rd Byte Write Cycle 4th Byte Write Cycle ALL Byte Abort Write Cycle Deselect Cycle Sleep Mode Clock Truth Table Operation Read Read Sleep(ZZ=H) Write( SW =L) Deselect( SS =H) G L H X X X DQ DOUT 0-35 High-Z High-Z DIN High-Z PRELIMINARY (February, 1999, Version 2.0) 4 AMIC Technology, Inc. A65H73361/A65H83181 Series Absolute Maximum Ratings* Power Supply Voltage(VDD) . . . . . . . . . . -0.5V to +4.6V Voltage Relative to GND for any Pin Except VDD(VIN, VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Power Dissipation (PD) . . . . . . . . .. . . . . . . . . . .. . .1.0W Operating Temperature (Topr). . . . . . . . .. . 0° to 70° C C Storage Temperature (Tbias) . . . . . . .. .. . -10° to 85° C C Storage Temperature(Tstg). . . . . . . . . . .-55° to 125° C C *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure the absolute maximum rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TJ = 0 to 110° ) C Parameter Supply Voltage Output Driver Supply Voltage Input High Voltage Input Low Voltage Input reference Voltage Clocks Signal Voltage Differential Clocks Signal Voltage Clocks Common Mode Voltage Output Current Symbol VDD VDDQ VIH VIL VREF VIN-CLK VDIF-CLK VCM-CLK IOUT Min. 3.15 1.4 VREF+0.1 -0.3 0.68 -0.3 0.1 0.55 Typ. 3.3 1.5 0.75 5 Max. 3.47 1.6 VDDQ+0.3 VREF-0.1 0.90 VDDQ+0.3 VDDQ+0.6 0.90 8 Units V V V V V V V V mA Notes 1 1 1, 2 1, 3 1, 6 1, 4 1, 5 1 1.All voltage reference to VSS. All VDD VDDQ and VSS pins must be connected. 2.VIH(Max)DC = VDD + 0.3V, VIH(Max)AC = VDD + 1.5V (pulse width ≤ 4.0ns). 3.VIL(Min)DC = -0.3V, VIL(Min)AC = -1.5 V (pulse width ≤ 4.0ns). 4.VIN-CLK specifies the maximum allowable DC excursions of each differential clock ( CK , CK ). 5.VDIF-CLK specifies the minimum clock differential voltage required for switching. 6.Peak to Peak AC component superimposed on VREF may not exceed 5% of VREF. PRELIMINARY (February, 1999, Version 2.0) 5 AMIC Technology, Inc. A65H73361/A65H83181 Series DC Electrical Characteristics (TJ = 0 to +110° VDD = 3.3V ± 5%) C, Parameter Average Power Supply Operating Current-X36 (IOUT = 0, VIN = VIH or VIL, ZZ & SS = VIL) Average Power Supply Operating Current-X18 (IOUT = 0, VIN = VIH or VIL, ZZ & SS = VIL) Power Supply Standby Current (ZZ = VIH, All other inputs = VIH or VIL, Iout =0) ( SS = VIH, ZZ = VIL. All their inputs = VIH or VIL, lOUT = 0 ) Input Leakage Current (VIN = VSS or VDD) Output Leakage Current (VOUT = VSS or VDD, DQ in High = Z) Output High Level Voltage(lOH = -6mA @ VDDQ/2+0.3) Output Low Level Voltage(lOL = +6mA @ VDDQ/2-0.3) 1. lOUT = Chip Output Current. 2.Minimum Impedance Output Driver. Symbol lDD5 lDD6 lDD7 lDD5 lDD6 lDD7 Lsbzz lSBss lLI lLO VOH VOL VDDQ-.4 VSS ±1.0 ±1.0 VDDQ VSS+.4 Min. Max. TBD Units mA Notes 1 TBD mA 1 TBD mA mA µA µA V V 1 1 2 2 PRELIMINARY (February, 1999, Version 2.0) 6 AMIC Technology, Inc. A65H73361/A65H83181 Series Capacitance (TJ = 0 to +110° VDD = 3.3V ± 5%, f = 1MHz) C, Parameter Input Capacitance Data I/O Capacitance (DQ0-DQ35) Symbol CIN COUT Test Condition VIN = 0V VOUT= 0V Max. 3 4 Units pF pF AC Input Characteristics Item AC Input Logic High AC Input Logic Low Clock Input Differential Voltage VREF Peak to Peak ac Voltage Symbol VIN (ac) VIL (ac) VDIF (ac) VREF (ac) TBD 5% VREF (dc) Min. TBD TBD Max. Notes 3 3 2 1 1.The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. 2.Performance is a function on VIH and VIL levels to clock inputs. 3.See AC input Definition figure on page 7. AC Input Definition VIH(ac) VREF VIL(ac) PRELIMINARY (February, 1999, Version 2.0) 7 AMIC Technology, Inc. A65H73361/A65H83181 Series Programmable Impedance Output Driver DC Electrical Characteristics (TJ = 0 to +110° VDD = 3.3V ± 5%) C, Parameter Output High Level Voltage Output Low Level Voltage Symbol VOH VOL Min. VDDQ/2 VSS Max. VDDQ VDDQ/2 Units V V Notes 1 2 1.lOH = (VDDQ/2)/(RQ/5) 7.5% @ VOH = VDDQ/2 For :150Ω ≤ RQ ≤ 350Ω 2.lOL = (VDDQ/2)/(RQ/5) 7.5% @ VOL = VDDQ/2 For :150Ω ≤ RQ ≤ 350Ω AC Test Conditions (TJ = 0 to +110° VDD = 3.3V ± 5%, VDDQ = 1.5V) C, Parameter Output High Level Voltage Output Low Level Voltage Input Reference Voltage Differential Clocks Voltage Input Rise Time Input Fall Time I/O Signals Reference Level Clocks Reference level Output Load Conditions 1.See AC Test Loading figure on page 8. Symbol VIH VIL VREF VDIF-CLK TR TF Conditions 1.25 0.25 0.75 0.75 0.5 0.5 0.75 Differential Cross Point units V V V V ns ns V V 1 Notes AC Test Loading 0.75V VDDO/2 VREF DEVICE UNDER TEST 250Ω ZQ 50Ω 50Ω PRELIMINARY (February, 1999, Version 2.0) 8 AMIC Technology, Inc. A65H73361/A65H83181 Series AC Characteristics (TJ = 0 to +110° VDD = 3.3V ± 5%) C, Parameter Symbol Min. Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock to Output Valid Address Setup Time Address Hold Time Sync Select Setup Time Sync Select Hold Time Write Enables Setup Time Write Enables Hold Time Data In Setup Time Data In Hold Time Data Out Hold Time Clock High to Output High-z Clock high to Output Active Output Enable to High-z Output Enable to Low-z Output Enable to Output Valid Output Enable Setup Time Output Enable Hold Time Sleep Mode Recovery Time Sleep Mode Enable Time tKHKH tKHKL tKLKH tKHQV tAVKH tKHAX tSVKH tKHSX tWVKH tKHWX tDVKH tKHDX tKHQX tKHQZ tXHQX4 tGHQZ tGLQX tGLQV tGHKH tKHGX tZZR tZZE 5 1.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 0.5 0.5 1.5 5 -5 Max. 2.5 2.5 2.5 2.5 5 0.5 0.5 1.5 6 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 Min. 6.0 1.5 1.5 -6 Max. 3.0 3.0 3.0 3.0 6 Min. 7.0 1.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 0.5 0.5 1.5 7 -7 Max. 3.5 3.5 3.5 3.5 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 4 4 4 4 4 4 4 4 1 1, 2 1, 2 1, 2 1, 2 1 1, 3 1, 3 Units Notes 1.See AC Test Loading figure on page 8. 2.Transitions are measured ± 200mV from steady state voltage. 3.Output Driver Impedance update specifications for G induced updates. Write and Deselect cycles will also induce Output Driver Updates during High-z. 4.Inuse conditions VIH, VIL, Trise, Tfall of inputs must be withim 20% of VIH, VIL, Trise, Tfall of Clock. PRELIMINARY (February, 1999, Version 2.0) 9 AMIC Technology, Inc. A65H73361/A65H83181 Series Timing Diagram (Read and Deselect Cycles) tKLKH tKHKL tKHKH CK tAVKH SA A1 A2 A3 A3 A4 tKHAX tKHSX SS tWVKH tSVKH SW tKHWX tGLQV G tGHQZ tKHQX tKHQZ DQ Q1 Q2 Q3 Q4 tGLQX tKHQV tKHQX4 tKHQV PRELIMINARY (February, 1999, Version 2.0) 10 AMIC Technology, Inc. A65H73361/A65H83181 Series Timing Diagram (Read Write Cycles) tKLKH tKHKL tKHKH CK tAVKH SA A1 A2 A3 A2 A4 tKHAX tSVKH SS tKHSX tKHWX tXHWX SW tWVKH tKHWX tWVKH tXHWX SBW tWVKH tWVKH G tGHQZ tKHQZ tKHDX tKHQV DQ Q1 D2 Q3 Q2 D4 tKHQV tDVKH tKHQX4 tDVKH tKHDX NOTES: 1.D2 is the input data write in memory location A2. 2.Q2 is output data read from the write buffer, as a result of address A2 being a match from the last write cycle address. PRELIMINARY (February, 1999, Version 2.0) 11 AMIC Technology, Inc. A65H73361/A65H83181 Series Timing Diagram (Sleep Mode) tKHKH CK zz tZZR tZZE DQ PRELIMINARY (February, 1999, Version 2.0) 12 AMIC Technology, Inc. A65H73361/A65H83181 Series IEEE 1149.1 TAP AND BOUNDARY SCAN The SRAM provides a limited set of JTAG functions intended to test the interconnection between SRAM I/Os and printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM core. In conformance with IEEE std. 1149.1, the SRAM contains a TAP controller, Instruction register, Boundary Scan register, Bypass register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. Signal List l TCK : Test Clock l TMS : Test Mode Select l TDI : Test Data In l TDO : Test Data Out Caution: TCK, TMS, TDI must be tied down, even if JTAG is not used. JTAG Recommended DC Operating Conditions (TJ = 0 to 110 ° C) Parameter JTAG Input High Voltage JTAG Input Low Voltage JTAG Output High Level JTAG Output Low Level Symbol VIH1 VIL1 VOH1 VOL1 Min. 2.2 -03 2.4 Typ. Max. VDD + 0.3 0.8 0.4 Units V V V V Notes 1 1 1,2 1,3 1. All JTAG Inputs/Outputs are LVTTL Compatible only. 2. IOH1 = -8mA at 2.4V. 3. IOL1 = +8mA at 0.4V. JTAG Recommended DC Operating Conditions (TJ = 0 to 110 ° C) Parameter Input Pulse High Level Input Pulse Low Level Input Rise Time Input Fall Time Input and Output Timing Reference Level 1. See AC Test Loading on page 8. Symbol VIH1 VIL1 TR1 TF1 Conditions 3.0 0.0 2.0 2.0 1.5 Units V V ns ns V 1 Notes PRELIMINARY (February, 1999, Version 2.0) 13 AMIC Technology, Inc. A65H73361/A65H83181 Series JTAG AC Characteristics (TJ = 0 to 110 ° VDD = 3.3V ± 5%) C, Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Setup TMS Hold TDI Setup TDI Hold TCK Low to Valid Data 1. See AC Test Loading on page 8. Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tDVTH tTHDX tTLOV Min. 20 7 7 4 4 4 4 Max. 7 Units ns ns ns ns ns ns ns ns 1 Notes JTAG Timing Diagram tTHTL tTLTH tTHTH TCK tTHMX TMS tTHDX tMVTH TDI tDVTH TDO tTLOV PRELIMINARY (February, 1999, Version 2.0) 14 AMIC Technology, Inc. A65H73361/A65H83181 Series Scan Register Definition Register Name Instruction Bypass ID Boundary Scan* Bit Size X18 3 1 32 51 Bit Size X 36 3 1 32 70 * The Boundary Scan chain consists of the following bits : •36 or 18 bits for Data Inputs Depending on X 18 or X 36 Configuration •15 bits for SA0 - SA14 for X 36, 16 bits for SA0 - SA15 for X 18 •4 bits for SBWa - SBWd in X 36, 2 bits for SBWa and SBWb X 18 •9 bits for CK, CK , ZQ, SS , G , SW , ZZ, M1 and M2 •6 bits for Place Holders * CK and CK clocks connect to a differential receiver that generates a single-ended clock signal. This signal and its inverted value are used for Boundary Scan sampling. ID Register Definition Field Bit Number and Description Part Device Density Revision Number Vender Definition Manufacture JEDEC Start and Configuration (31 : 28) (17 : 12) Code (11 : 1) Bit (0) (27 : 18) 0001 0001 100 000 0110 011 100 1101 000001 100001 000 101 111 11 000 101 111 11 1 1 256K X 18 128K X 36 Instruction Set Code 000 001 010 011 100 101 110 111 Instruction SAMPLE-Z IDCODE SAMPLE-Z PRIVATE SAMPLE PRIVATE PRIVATE BYPASS Notes 1 1 1 3 4 3 3 3 1. Places DQs in High-Z in order to sample all input data regardless of the other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. BYPASS register is initiated to Vss when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded TDI when exiting the Shift DR state. 4. SAMPLE instruction does not place DQs in High-Z List of IEEE 1149.1 standard violations : • 7.2.1.b,e • 7.7.1.a-f • 10.1.1.b,e • 10.7.1.a-d • 6.1.1.d PRELIMINARY (February, 1999, Version 2.0) 15 AMIC Technology, Inc. A65H73361/A65H83181 Series Boundary Scan Order (X 36) Exit Order 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Signal M2 SA1 SA2 SA12 SA13 ZZ DQ1 DQ0 DQ3 DQ2 DQ4 DQ6 DQ5 DQ8 DQ7 SBWa Bump # 5R 4P 4T 6R 5T 7T 6P 7P 6N 7N 6M 6L 7L 6K 7K 5L 4L 4K 4F 5G 7H 6H 7G 6G Exit Order 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Signal DQ13 DQ11 DQ12 DQ9 DQ10 SA14 SA15 SA10 SA16 NC SA11 SA8 NC SA7 SA9 SA6 SA5 DQ19 DQ18 DQ21 DQ20 DQ22 DQ24 DQ23 Bump # 6F 7E 6E 7D 6D 6A 6C 5C 5A 6B 5B 3B 2B 3A 3C 2C 2A 2D 1D 2E 1E 2F 2G 1G Exit Order 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Signal DQ26 DQ25 SBWc Bump # 2H 1H 3G 4D 4E 4G 4H 4M 3L 1K 2K 1L 2L 2M 1N 2N 1P 2P 3T 2R 4N 3R ZQ SS NC NC SW SBWd DQ34 DQ35 DQ32 DQ33 DQ31 DQ29 DQ30 DQ27 DQ28 SA3 SA4 SA0 M1 CK CK G SBWb DQ16 DQ17 DQ14 DQ15 PRELIMINARY (February, 1999, Version 2.0) 16 AMIC Technology, Inc. A65H73361/A65H83181 Series Boundary Scan Order (X 18) Exit Order 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Signal M2 SA12 SA1 SA13 SA17 ZZ DQ0 DQ3 DQ6 DQ7 SBWa Bump # 5R 6T 4P 6R 5T 7T 7P 6N 6L 7K 5L 4L 4K 4F 6H 7G 6F 7E 6D 6A 6C 5C 5A 6B 5B 3B Exit Order 27 28 29 30 31 32 33 43 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Signal NC SA7 SA9 SA6 SA5 DQ9 DQ12 DQ15 DQ16 SBWb Bump # 2B 3A 3C 2C 2A 1D 2E 2G 1H 3G 4D 4E 4G 4H 4M 2K 1L 2M 1N 2P 3T 2R 4N 2T 3R ZQ SS CK CK G NC NC SW DQ8 DQ5 DQ4 DQ2 DQ1 SA14 SA15 SA10 SA16 NC SA11 SA8 DQ17 DQ14 DQ13 DQ11 DQ10 SA3 SA4 SA0 SA2 M1 PRELIMINARY (February, 1999, Version 2.0) 17 AMIC Technology, Inc. A65H73361/A65H83181 Series TAP Controller State Machine 1 Test Logic Reset 0 0 Run Test Idle 1 Select DR 0 1 Capture DR 0 Shift DR 1 1 Exit1 DR 0 Pause DR 1 Exit2 DR 0 1 1 Update DR 0 1 1 Update IR 0 0 1 0 1 1 Select IR 0 Capture IR 0 Shift IR 1 Exit1 IR 0 Pause IR 1 Exit2 IR 0 0 0 1 PRELIMINARY (February, 1999, Version 2.0) 18 AMIC Technology, Inc. A65H73361/A65H83181 Series Ordering Information Part Number A65H83181P-5 A65H83181P-6 A65H83181P-7 A65H73361P-5 A65H73361P-6 A65H73361P-7 Organization 256K x 18 256K x 18 256K x 18 128K x 36 128K x 36 128K x 36 Speed 2.5ns Access / 5 ns Cycle 3.0ns Access / 6 ns Cycle 3.5ns Access / 7 ns Cycle 2.5ns Access / 5 ns Cycle 3.0ns Access / 6 ns Cycle 3.5ns Access / 7 ns Cycle Package 7 x 17 PBGA 7 x 17 PBGA 7 x 17 PBGA 7 x 17 PBGA 7 x 17 PBGA 7 x 17 PBGA PRELIMINARY (February, 1999, Version 2.0) 19 AMIC Technology, Inc. A65H73361/A65H83181 Series Package Information PIN #1 14.00±0.10 1.96 (Min) 2.36 (Max) 30°±2 -A7654321 A B C D E F G H J K L M N P R T U -B7.62±0.10 119X φ0.80±0.1 1.56 0.30 S C A S B S 0.10 S C NOTE: 1. ALL DIMENSIONS ARE MILLIMETERS. 2. DETAILS OF MOLDED PLASTIC BODY MAY VARY FROM THAT SHOWN. 22.00 ±0.10 20.00 ±0.05 1.27 TYP. 1.00±0.05 0.60±0.10 12.00±0.05 SEATING PLANE 1.270 TYP. 0.56 0.15 C -C- D 20.32 ±0.10 PRELIMINARY (February, 1999, Version 2.0) 20 AMIC Technology, Inc.