A82DL3224TG-70UF

A82DL32x4T(U) Series Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash Memory and 4M (256Kx16 Bit) Static RAM Preliminary Document Title Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash Memory and 4M (256Kx16 Bit) Static RAM Revision History Rev. No. 0.0 History Initial issue Issue Date August 21, 2005 Remark Preliminary PRELIMINARY (August, 2005, Version 0.0) AMIC Technology, Corp. A82DL32x4T(U) Series Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash Memory and 4M (256Kx16 Bit) Static RAM Preliminary DISTINCTIVE CHARACTERISTICS MCP Features Single power supply operation 2.7 to 3.6 volt High Performance - Access time as fast as 70ns Package 69-Ball TFBGA (8x11x1.4 mm) Industrial operating temperature range: -40°C to 85°C for –U; -25°C to 85°C for –I - Suspends erase operations to allow programming in same bank Data Polling and Toggle Bit - Provides a software method of detecting the status of program or erase cycles Unlock Bypass Program command - Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES Any combination of sectors can be erased Ready/ Busy output (RY/ BY ) - Hardware method for detecting program or erase cycle completion Hardware reset pin ( RESET ) - Hardware method of resetting the internal state machine to reading array data WP /ACC input pin - Write protect ( WP ) function allows protection of two outermost boot sectors, regardless of sector protect status - Acceleration (ACC) function accelerates program timing Sector protection - Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector - Temporary Sector Unprotect allows changing data in protected sectors in-system Flash Features ARCHITECTURAL ADVANTAGES Simultaneous Read/Write operations - Data can be continuously read from one bank while executing erase/program functions in other bank - Zero latency between read and write operations Multiple bank architectures - Three devices available with different bank sizes (refer to Table 2) Package - 69-Ball TFBGA (8x11x1.4 mm) Top or bottom boot block Manufactured on 0.18 µm process technology - Compatible with AM42DL32x4G devices Compatible with JEDEC standards - Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS High performance - Access time as fast as 70ns - Program time: 7µs/word typical utilizing Accelerate function Ultra low power consumption (typical values) - 2mA active read current at 1MHz - 10mA active read current at 5MHz - 200nA in standby or automatic sleep mode Minimum 1 million write cycles guaranteed per sector 20 Year data retention at 125°C - Reliable operation for the life of the system SOFTWARE FEATURES Supports Common Flash Memory Interface (CFI) Erase Suspend/Erase Resume LP SRAM Features Power supply range: 2.7V to 3.6V Access times: 70 ns (max.) Current: Very low power version: Operating: 35mA(max.) Standby: 10uA (max.) Full static operation, no clock or refreshing required All inputs and outputs are directly TTL-compatible Common I/O using three-state output Output enable and two chips enable inputs for easy application Data retention voltage: 2.0V (min.) PRELIMINARY (August, 2005, Version 0.0) 1 AMIC Technology, Corp. A82DL32x4T(U) Series GENERAL DESCRIPTION The A82DL32x4T(U) family consists of 32 megabit, 3.0 voltonly flash memory devices, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on I/O0–I/O15; byte mode data appears on I/O0– I/O7. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 70ns. The devices are offered in 69-ball Fine-pitch BGA. Standard control pins—chip enable ( CE_F ), write enable ( WE ), and output enable ( OE )—control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A82DL32x4T(U) Features The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device status bits: RY/ BY pin, I/O7 ( Data Polling) and I/O6/I/O2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-s y s t e m or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The A82DL32x4T(U) devices uses multiple bank architectures to provide flexibility for different applications. Three devices are available with these bank sizes: Device DL3224 DL3234 DL3244 Bank 1 4 Mb 8 Mb 16 Mb Bank 2 28 Mb 24 Mb 16 Mb PRELIMINARY (August, 2005, Version 0.0) 2 AMIC Technology, Corp. A82DL32x4T(U) Series Pin Configurations 69-Ball TFBGA Top View Flash only A1 A5 A6 A10 NC B1 B3 B4 NC B5 NC B6 B7 B8 NC SRAM only Shared NC C2 A7 C3 LB_S C4 WP/ACC C5 WE C6 A8 C7 A11 C8 C9 A3 D2 A6 D4 UB_S D4 RESET D5 CE2_S D6 A19 D7 A12 D8 A15 D9 A2 E1 E2 A5 E3 A18 E4 RY/BY NC A9 E7 A13 E8 NC E9 E10 NC F1 A1 F2 A4 F3 A17 F4 A10 F7 A14 F8 NC F9 NC F10 NC A0 G2 VSS G3 I/O1 G4 G5 G6 I/O6 G7 NC G8 A16 G9 NC CE_F H2 OE H3 I/O9 H4 I/O3 H5 I/O4 H6 I/O13 H7 I/O15(A-1) BYTE_F H8 H9 CE1_S I/O0 J3 I/O10 J4 VCC_F J5 VCC_S J6 I/O12 J7 I/O7 J8 VSS I/O8 K1 I/O2 I/O11 K5 NC K6 I/O5 I/O14 K10 NC NC NC NC Special Handling Instructions for TFBGA Package Special handling is required for Flash Memory products in TFBGA packages. Flash memory devices in TFBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time PRELIMINARY (August, 2005, Version 0.0) 3 AMIC Technology, Corp. A82DL32x4T(U) Series Product Information Guide Part Number Speed Options Max Access Time (ns) CE_F / CE_S Access (ns) Standard Voltage Range: VCC_F/VCC_S=2.7-3.6V A82DL32x4T(U) 70 70 70 40 OE Access (ns) MCP Block Diagram VCC_F A20 to A0 A20 to A0 BYTE_F WP/ACC CE_F RESET VSS RY/BY 32M Bit Flash Memory I/O15 (A-1) to I/O0 I/O15 (A-1) to I/O0 VCC_S VSS A17 to A0 WE OE LB_S UB_S CE1_S CE2_S 4M Bit Static RAM I/O15 (A-1) to I/O0 PRELIMINARY (August, 2005, Version 0.0) 4 AMIC Technology, Corp. A82DL32x4T(U) Series Flash Block Diagram VCC_F VSS OE BYTE_F Y-Decoder A0-A20 Upper Bank Address Upper Bank Latches and Control Logic RY/BY X-Decoder A0-A20 RESET WE CE_F BYTE_F WP/ACC STATE CONTROL & COMMAND REGISTER Status I/O0-I/O15 Control I/O0-I/O15 X-Decoder Latches and Control Logic Y-Decoder I/O0-I/O15 BYTE_F A0-A19 Upper Bank A0-A20 Lower Bank Address OE PRELIMINARY (August, 2005, Version 0.0) 5 AMIC Technology, Corp. I/O0-I/O15 A0-A19 A82DL32x4T(U) Series Pin Descriptions Pin No. A0 – A20 I/O0 - I/O14 I/O15 I/O15 (A-1) A-1 Description Address Inputs Data Inputs/Outputs Data Input/Output, Word Mode LSB Address Input, Byte Mode Chip Enable (Flash) Chip Enable (SRAM) Write Enable Output Enable Hardware Write Protect/Acceleration Pin Hardware Reset Pin, Active Low Selects 8-bit or 16-bit Mode Ready/ BUSY Output Ground Power Supply (Flash) Power Supply (SRAM) Pin Not Connected Internally CE_S CE_F 21 A0-A20 16 or 8 I/O0-I/O15(A-1) Logic Symbol CE_F CE_S WE OE WP /ACC OE WE WP/ACC RESET BYTE_F RY/BY RESET BYTE_F RY/ BY VSS VCC_F VCC_S NC PRELIMINARY (August, 2005, Version 0.0) 6 AMIC Technology, Corp. A82DL32x4T(U) Series SRAM Block Diagram A0 DECODER A16 A17 512 X 8192 MEMORY ARRAY VCC_S VSS I/O0 INPUT DATA CIRCUIT I/O7 COLUMN I/O INPUT DATA CIRCUIT I/O8 I/O15 CE1_S CE2_S LB_S UB_S OE WE CONTROL CIRCUIT PRELIMINARY (August, 2005, Version 0.0) 7 AMIC Technology, Corp. A82DL32x4T(U) Series DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail. Table 1-1. Device Bus Operations – Flash Byte Mode ( BYTE_F Operation (Notes 1, 2) Read from Flash = VIH) WP /ACC (Note 4) CE_F CE1_S H CE2_S X OE L WE H A0A20 AIN LB_S UB_S RESET (Note3) (Note3) I/O7– I/O0 IOUT I/O15– I/O0 IOUT L X H L X X X H L/H Write to Flash L X L X H X L H H L AIN X X H (Note 4) IIN IIN Standby VCC ± 0.3 V X L X X X L X X VCC ± 0.3 V H High-Z High-Z Output Disable L H X L X L H H X X L H L/H High-Z High-Z Flash Hardware Reset X X H X X X X X L L/H High-Z High-Z Sector Protect (Notes) X L H H X L SA, A6 = L, A1 = H, A0 = L SA, A6 = H, A1 = H, A0 = L X X VID L/H IIN X Sector Unprotect (Note 5) L X L H L X X VID (Note 6) IIN X Temporary Sector Unprotect H X X X X L H L H L L H L H X H X X AIN X X VID (Note 6) IIN IOUT High-Z IOUT IIN High-Z IIN High-Z IOUT IOUT High-Z IIN IIN High-Z Read from SRAM H L H L H AIN L L H Write to SRAM H L H X L AIN Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, IIN = Data In, IOUT = Data Out Notes: 1.Other operations except for those indicated in this column are inhibited. 2.Do not apply CE_F = VIL, CE1_S = VIL and CE2_S = VIH at the same time. 3.Don’t care or open LB_S or UB_S . 4.The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 5. If WP /ACC = VIL, the two outermost boot sectors remain protected. If WP /ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP /ACC = VHH, all sectors will be unprotected. PRELIMINARY (August, 2005, Version 0.0) 8 AMIC Technology, Corp. A82DL32x4T(U) Series Table 1-2. Device Bus Operations – Flash Byte Mode ( BYTE_F Operation (Notes 1, 2) Read from Flash = VIL) RESET WP /ACC (Note 4) CE_F CE1_S H CE2_S X OE L WE H A0-A20 LB_S UB_S (Note3) (Note3) I/O7– I/O0 IOUT I/O15– I/O8 High-Z I/O14–8 =Hi-Z; I/O15=A-1 High-Z L X H L X AIN X X H L/H Write to Flash L X L X H X L H L AIN X X H (Note 3) IIN Standby VCC ± 0.3 V X L H X H X X X X X L X X X VCC_F ± 0.3 V H High-Z Output Disable L H H L H L/H High-Z High-Z Flash Hardware Reset H X X H X X L X H L L X H L L X X X AIN X X VID (Note 6) IIN High-Z L H L L H L H H H X H X IOUT High-Z IOUT IIN High-Z IIN IOUT IOUT High-Z IIN IIN High-Z SA, A6 = L, A1 = H, A0 = L SA, A6 = H, A1 = H, A0 = L X X VID L/H IIN X X X X X L L/H High-Z High-Z Sector Protect (Notes) L X H Sector Unprotect (Note 5) L X H X X X X VID (Note 6) IIN X Temporary Sector Unprotect Read from SRAM H L H L H AIN H L H Write to SRAM H L H X L AIN L L Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In (for Flash Byte Mode, I/O15=A-1), IIN = Data In, IOUT = Data Out Notes: 1.Other operations except for those indicated in this column are inhibited. 2.Do not apply CE_F = VIL, CE1_S = VIL and CE2_S = VIH at the same time. 3.Don’t care or open LB_S or UB_S . 4.The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 5. If WP /ACC = VIL, the two outermost boot sectors remain protected. If WP /ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP /ACC = VHH, all sectors will be unprotected. PRELIMINARY (August, 2005, Version 0.0) 9 AMIC Technology, Corp. A82DL32x4T(U) Series Word/Byte Configuration The BYTE_F pin determines whether the I/O pins I/O15-I/O0 operate in the byte or word configuration. If the BYTE_F pin is set at logic ”1”, the device is in word configuration, I/O15I/O0 are active and controlled by CE_F and OE . If the BYTE_F pin is set at logic “0”, the device is in byte configuration, and only I/O0-I/O7 are active and controlled by CE_F and OE . I/O8-I/O14 are tri-stated, and I/O15 pin is used as an input for the LSB(A-1) address function. Characteristics" section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP /ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP /ACC pin returns the device to normal operation. Note that the WP /ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. In addition, the WP /ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on I/O7-I/O0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE_F and OE pins to VIL. CE_F is the power control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at VIH. The BYTE_F pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. See "Requirements for Reading Array Data" for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 11 for the timing waveform, lCC1_F in the DC Characteristics table represents the active current specification for reading array data. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 18 shows how read and write cycles may be initiated for simultaneous operation with zero latency. ICC6_F and ICC7_F in the DC Characteristics table represent the current specifications for read-while-program and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE input. The device enters the CMOS standby mode when the CE_F & RESET pins are both held at VCC_F ± 0.3V. (Note that this is a more restricted voltage range than VIH.) If CE_F and RESET are held at VIH, but not within VCC_F ± 0.3V, the device will be in the standby mode, but the standby current will be greater. The device requires the standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3_F in the DC Characteristics tables represent the standby current specification. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE and CE_F to VIL, and OE to VIH. For program operations, the BYTE_F pin determines whether the device accepts program data in bytes or words, Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word / Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequence. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables 3-4 indicate the address range that each sector occupies. The device address space is divided into two banks: Bank 1 contains the boot/parameter sectors, and Bank 2 contains the larger, code sectors of uniform size. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. ICC2_F in the DC Characteristics table represents the active current specification for the write mode. The "AC PRELIMINARY (August, 2005, Version 0.0) 10 AMIC Technology, Corp. A82DL32x4T(U) Series Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC +30ns. The automatic sleep mode is independent of the CE_F , WE and OE control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4_F in the DC Characteristics table represents the automatic sleep mode current specification. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET is asserted during a program or erase operation, the RY/ BY pin remains a “0” (busy) until the internal reset operation is complete, which requires a time tREADY (during Embedded Algorithms). The system can thus monitor RY/ BY to determine whether the reset operation is complete. If RESET is asserted when a program or erase operation is not executing (RY/ BY pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET pin return to VIH. Refer to the AC Characteristics tables for RESET parameters and diagram. RESET : Hardware Reset Pin The RESET pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET pin low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET pulse. When RESET is held at VSS ± 0.3V, the device draws CMOS standby current (ICC4_F ). If RESET is held at VIL but not within VSS ± 0.3V, the standby current will be greater. Output Disable Mode When the OE input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Table 2. A82DL32x4T(U) Device Bank Divisions Device Part Number A82DL3224 A82DL3234 A82DL3244 Bank 1 Megabits 4 Mbit 8 Mbit 16 Mbit Sector Sizes Eight 8 Kbyte/4 Kword, three 64 Kbyte/32 Kword Eight 8 Kbyte/4 Kword, seven 64 Kbyte/32 Kword Eight 8 Kbyte/4 Kword, fifteen 64 Kbyte/32 Kword Megabits 28 Mbit 24 Mbit 16 Mbit Bank 2 Sector Sizes Fifty-six 64 Kbyte/32 Kword Forty-eight 64 Kbyte/32 Kword Thirty-two 64 Kbyte/32 Kword PRELIMINARY (August, 2005, Version 0.0) 11 AMIC Technology, Corp. A82DL32x4T(U) Series Table 3. Sector Addresses for Top Boot Sector Devices A29DL324T A29DL323T A29DL322T Sector Sector Address A20–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 000000xxx 000001xxx 000010xxx 000011xxx 000100xxx 000101xxx 000110xxx 000111xxx 001000xxx 001001xxx 001010xxx 001011xxx 001100xxx 001101xxx 001110xxx 001111xxx 010000xxx 010001xxx 010010xxx 010011xxx 010100xxx 010101xxx 010110xxx 010111xxx 011000xxx 011001xxx 011010xxx 011011xxx 011100xxx 011101xxx 011110xxx 011111xxx 100000xxx 100001xxx 100010xxx 100011xxx 100100xxx 100101xxx 100110xxx 100111xxx 101000xxx 101001xxx 101010xxx 101011xxx 101100xxx 101101xxx 101110xxx 101111xxx 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 000000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–1FFFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 090000h–097FFFh 098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h–17FFFFh Bank 2 Bank 2 Bank 1 Bank 2 PRELIMINARY (August, 2005, Version 0.0) 12 AMIC Technology, Corp. A82DL32x4T(U) Series Table 3 Sector Addresses for Top Boot Sector Devices A29DL324T A29DL323T A29DL322T Sector Sector Address A20–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 000000xxx 000001xxx 000010xxx 000011xxx 000100xxx 000101xxx 000110xxx 000111xxx 001000xxx 001001xxx 001010xxx 001011xxx 001100xxx 001101xxx 001110xxx 001111xxx 010000xxx 010001xxx 010010xxx 010011xxx 010100xxx 010101xxx 010110xxx 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 3F2000h-3F3FFFh 3F4000h-3F5FFFh 3F6000h-3F7FFFh 3F8000h-3F9FFFh 3FA000h-3FBFFFh 3FC000h-3FDFFFh 3FE000h-3FFFFFh 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h–1F8FFFh 1F9000h–1F9FFFh 1FA000h–1FAFFFh 1FB000h–1FBFFFh 1FC000h–1FCFFFh 1FD000h–1FDFFFh 1FE000h–1FEFFFh 1FF000h–1FFFFFh Bank 1 Bank 1 Bank 1 Note: The address range is A20: A-1in byte mode ( BYTE_F =VIL) or A20:A0 in word mode ( BYTE_F =VIH). The bank address bits are A20-A18 for A29DL3224T, A20 and A19 for A29DL3234T, and A20 for A29DL3244T. Bank 2 PRELIMINARY (August, 2005, Version 0.0) 13 AMIC Technology, Corp. A82DL32x4T(U) Series Table 4. Sector Addresses for Bottom Boot Sector Devices A29DL323U A29DL322U A29DL324U Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 Sector Address A20–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range 000000000 000000001 000000010 000000011 000000100 000000101 000000110 000000111 000001XXX 000010XXX 000011XXX 000100XXX 000101XXX 000110XXX 000111XXX 001000XXX 001001XXX 001010XXX 001011XXX 001100XXX 001101XXX 001110XXX 001111XXX 010000XXX 010001XXX 010010XXX 010011XXX 010100XXX 010101XXX 010110XXX 010111XXX 011000XXX 011001XXX 011010XXX 011011XXX 011100XXX 011101XXX 011110XXX 011111XXX 100000XXX 100001XXX 100010XXX 100011XXX 100100XXX 100101XXX 100110XXX 100111XXX 101000XXX 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-009FFFh 00A000h-00BFFFh 00C000h-00DFFFh 00E000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh Bank 2 Bank 1 Bank 2 Bank 2 Bank 2 Bank 1 PRELIMINARY (August, 2005, Version 0.0) 14 AMIC Technology, Corp. A82DL32x4T(U) Series A29DL323U A29DL322U A29DL324U Sector Sector Address A20–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 101001XXX 101010XXX 101011XXX 101100XXX 101101XXX 101110XXX 101111XXX 111000XXX 111001XXX 110010XXX 110011XXX 110100XXX 110101XXX 110110XXX 110111XXX 111000XXX 111001XXX 111010XXX 111011XXX 111100XXX 111101XXX 111110XXX 111111XXX 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh Bank 2 Bank 2 Note: The address range is A20: A-1in byte mode ( BYTE_F =VIL) or A20:A0 in word mode ( BYTE_F =VIH). The bank address bits are A20-A18 for A29DL3224U, A20 and A19 for A29DL3234U, and A20 for A29DL3244U. Bank 2 PRELIMINARY (August, 2005, Version 0.0) 15 AMIC Technology, Corp. A82DL32x4T(U) Series Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on I/O7 - I/O0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (8.5V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 5. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. (see Table 3-4). Table 5 shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on I/O7 - I/O0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 12. This method does not require VID. Refer to the Autoselect Command Sequence section for more information. Table 5. A82DL32x4T(U) Autoselect Codes (High Voltage Method) Description CE OE WE A20 to A12 BA BA BA BA X SA A11 to A10 X X X X X X A9 A8 to A7 X X X X X X A6 A5 to A4 X X X X X X I/O8 to I/O15 A3 A2 A1 A0 BYTE BYTE = VIH = VIL X X X X X X X 22h 22h 22h X X I/O7 to I/O0 37h 55h (T), 56h (U) 50h (T), 53h (U) 5Ch (T), 5Fh (U) 7Fh 01h (protected), 00h (unprotected) Manufacturer ID: AMIC Device ID: A29DL8224 Device ID: A29DL8234 Device ID: A29DL8244 Continuation ID Read Sector Status L L L L L L L L L L L L H H H H H H VID VID VID VID VID VID L L L L L L L X X X X L L X X X X L L L L L H H L H H H H L L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care, BA=Bank Address Note: The autoselect codes may also be accessed in-system via command sequences. PRELIMINARY (August, 2005, Version 0.0) 16 AMIC Technology, Corp. A82DL32x4T(U) Series Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Tables 6 and 7). Table 6. Top Boot Sector/Sector Block Addresses for Protection/Unprotection Table 6. Top Boot Sector/Sector Block Addresses for Protection/Unprotection Table 7. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection Sector / Sector Block SA70 SA69- SA67 SA66- SA63 SA62- SA59 SA58- SA55 SA54- SA51 SA50- SA47 SA46-SA43 A20–A12 111111XXXX 111110XXX, 111101XXX, 111100XXX 1110XXXXX 1101XXXXX 1100XXXXX 1011XXXXX 1010XXXXX 1001XXXXX 1000XXXXX 0111XXXXX 0110XXXXX 0101XXXXX 0100XXXXX 0011XXXXX 0010XXXXX 0001XXXXX 000001XXX, 000010XXX, 000011XXX 000000111 000000110 000000101 000000100 000000011 000000010 000000001 000000000 Sector / Sector Block Size 64 Kbytes 192 (3x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 192 (3x64) Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes Sector / Sector Block SA0 SA1-SA3 SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 SA32-SA35 SA36-SA39 SA40-SA43 SA44-SA47 SA48-SA51 SA52-SA55 SA56-SA59 SA60-SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 A20–A12 000000XXX 000001XXX, 000010XXX, 000011XXX 0001XXXXX 0010XXXXX 0011XXXXX 0100XXXXX 0101XXXXX 0110XXXXX 0111XXXXX 1000XXXXX 1001XXXXX 1010XXXXX 1011XXXXX 1100XXXXX 1101XXXXX 1110XXXXX 111100XXX, 111101XXX, 111110XXX 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111 Sector / Sector Block Size 64 Kbytes 192 (3x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 192 (3x64) Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes SA42-SA39 SA38-SA35 SA34-SA31 SA30-SA27 SA26-SA23 SA22-SA19 SA18-SA15 SA14-SA11 SA10-SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 PRELIMINARY (August, 2005, Version 0.0) 17 AMIC Technology, Corp. A82DL32x4T(U) Series The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection and unprotection can be implemented via two methods. The primary method requires VID on the RESET pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 23 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The sector unprotect algorithm unprotects all sectors in parallel. All previously protected sectors must be individually re-protected. To change data in protected sectors efficiently, the temporary sector unprotect function is available. See “Temporary Sector/Sector Block Unprotect”. The alternate method for protection and unprotection is by software temporary sector /sector block unprotect command. See Figure 2 for Command Flow. The device is shipped with all sectors unprotected. It is possible to determine whether a sector is protected or unprotected. See the Autoselect Mode section for details. Write Protect ( WP /ACC) The Write Protect function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP /ACC pin. If the system asserts VIL on the WP /ACC pin, the device disables program and erase functions in the two “outermost” 8 Kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. If the system asserts VIH on the WP /ACC pin, the device reverts to whether the two outermost 8 Kbyte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. Note that the WP /ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Temporary Sector/Sector Block Unprotect (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Tables 6 and 7). This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET pin to VID (8.5V-12.5V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 22 shows the timing diagrams, for this feature. PRELIMINARY (August, 2005, Version 0.0) 18 AMIC Technology, Corp. A82DL32x4T(U) Series START START RESET = VID (Note 1) 555/AA + 2AA/55 + 555/77 (Note 1) Perform Erase or Program Operations Perform Erase or Program Operations RESET = VIH XXX/F0 (Reset Command) Temporary Sector Unprotect Completed (Note 2) Soft-ware Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected (If WP/ACC=VIL, outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again. Notes: 1. All protected sectors unprotected (If WP/ACC=VIL, outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again. Figure 1-1. Temporary Sector Unprotect Operation by RESET Mode Figure 1-2. Temporary Sector Unprotect Operation by Software Mode PRELIMINARY (August, 2005, Version 0.0) 19 AMIC Technology, Corp. A82DL32x4T(U) Series START Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address START PLSCNT=1 PLSCNT=1 RESET=VID RESET=VID Wait 1 us Wait 1 us Temporary Sector Unprotect Mode No First Write Cycle=60h? Yes Set up sector address No First Write Cycle=60h? Yes All sectors protected? Yes Set up first sector address No Temporary Sector Unprotect Mode Sector Protect: Write 60h to sector address with A6=0, A1=1, A0=0 Wait 150 us Verify Sector Protect: Write 40h to sector address with A6=0, A1=1, A0=0 Sector Unprotect: Write 60h to sector address with A6=1, A1=1, A0=0 Reset PLSCNT=1 Increment PLSCNT Wait 15 ms Verify Sector Unprotect : Write 40h to sector address with A6=1, A1=1, A0=0 Read from sector address with A6=0, A1=1, A0=0 No PLSCNT =25? Yes Device failed No Data=01h?** Increment PLSCNT Read from sector address with A6=1, A1=1, A0=0 No Set up next sector address Yes Protect another sector? No Remove VID from RESET Write reset command Yes PLSCNT= 1000? No Data=00h?** Yes Device failed Yes Last sector verified? Yes Remove VID from RESET No Sector Protect Algorithm Sector Protect complete Sector Unprotect Algorithm Write reset Command Sector Unprotect complete Note: The term “sector” in the figure applies to both sectors and sector blocks * No other command is allowed during this process ** Read access time is 200ns-300ns Figure 2-1. High Voltage Sector/Sector Block Protection and Unprotection Algorithms PRELIMINARY (August, 2005, Version 0.0) 20 AMIC Technology, Corp. A82DL32x4T(U) Series START START PLSCNT=1 555/AA + 2AA/55 + 555/77 Wait 1 us Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address PLSCNT=1 555/AA + 2AA/55 + 555/77 Wait 1 us Temporary Sector Unprotect Mode No First Write Cycle=60h? Yes Set up sector address No First Write Cycle=60h? Yes All sectors protected? Yes Set up first sector address No Temporary Sector Unprotect Mode Sector Protect: Write 60h to sector address with A6=0, A1=1, A0=0 Wait 150 us Verify Sector Protect: Write 40h to sector address with A6=0, A1=1, A0=0 Sector Unprotect: Write 60h to sector address with A6=1, A1=1, A0=0 Reset PLSCNT=1 Increment PLSCNT Wait 15 ms Verify Sector Unprotect : Write 40h to sector address with A6=1, A1=1, A0=0 Read from sector address with A6=0, A1=1, A0=0 No PLSCNT =25? Yes Device failed No Data=01h?** Increment PLSCNT Read from sector address with A6=1, A1=1, A0=0 No Set up next sector address Yes Protect another sector? No Write reset command Yes PLSCNT= 1000? No Data=00h?** Yes Device failed Yes Last sector verified? Yes No Sector Protect Algorithm Sector Protect complete Sector Unprotect Algorithm Note: The term “sector” in the figure applies to both sectors and sector blocks * No other command is allowed during this process ** Access time is 200ns-300ns Write reset Command Sector Unprotect complete Figure 2-2. Software Sector/Sector Block Protection and Unprotection Algorithms PRELIMINARY (August, 2005, Version 0.0) 21 AMIC Technology, Corp. A82DL32x4T(U) Series Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 12 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC_F power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC_F is less than VLKO, the device does not accept any write cycles. This protects data during VCC_F power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC_F is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC_F is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5ns (typical) on OE , CE_F or Power-Up Write Inhibit If WE = CE_F = VIL and OE = VIH during power up, the device does not accept commands on the rising edge of WE . The internal state machine is automatically reset to reading array data on power-up. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 8-11. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 8-11. The system must write the reset command to return the device to the autoselect mode. WE do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE = VIL, CE_F = VIH or WE = VIH. To initiate a write cycle, CE_F and WE must be a logical zero while OE is a logical one. Table 8. CFI Query Identification String Addresses (Word Mode) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Addresses (Byte Mode) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query Unique ASCII string “QRY” Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) PRELIMINARY (August, 2005, Version 0.0) 22 AMIC Technology, Corp. A82DL32x4T(U) Series Table 9. System Interface String Addresses (Word Mode) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Addresses (Byte Mode) 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch Data 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h VCC Min. (write/erase) Description I/O7- I/O4 : volt, I/O3- I/O0: 100 millivolt VCC Max. (write/erase) I/O7- I/O4: volt, I/O3- I/O0: 100 millivolt Vpp Min. voltage (00h = no Vpp pin present) Vpp Max. voltage (00h = no Vpp pin present) Typical timeout per single byte/word write 2N µs Typical timeout for Min. size buffer write 2N µs (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) Table 10 Device Geometry Definition Addresses (Word Mode) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3BH 3Ch Addresses (Byte Mode) 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 40h 72h 74h 76h 78h Data 0015h 0002h 0000h 0000h 0000h 0002h 0007h 0000h 0020h 0000h 001Eh 0000h 0000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Erase Block Region 4 Information Erase Block Region 3 Information Erase Block Region 2 Information Erase Block Region 1 Information (refer to the CFI specification) Max. number of byte in multi-byte write = 2 (00h = not supported) N N Device Size = 2 byte Description Flash Device Interface description Number of Erase Block Regions within device PRELIMINARY (August, 2005, Version 0.0) 23 AMIC Technology, Corp. A82DL32x4T(U) Series Table 11. Primary Vendor-Specific Extended Query Addresses (Word Mode) 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah Addresses (Byte Mode) 80h 82h 84h 86h 88h 8Ah 8Ch 8Eh 90h 92h 94h Data 0050h 0052h 0049h 0031h 0032h 0000h 0002h 0001h 0001h 0004h 00XXh Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock 0 = Required, 1 = Not Required Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 04 = A29L800 mode Simultaneous Operation XX = 38 (A29DL8224) XX = 30 (A29DL8234) XX = 20 (A29DL8244) 4Bh 4Ch 96h 98h 0000h 0000h Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 4Eh 4Fh 9Ah 9Ch 9Eh 0085h 0095h 000Xh ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 02h = Bottom Boot Device, 03h = Top Boot Device Bank 1 Region Information – Number of Sectors on Bank 1 58h B0h 00XXh XX = 0F (A29DL322) XX = 17 (A29DL323) XX = 27 (A29DL324) Bank 2 Region Information – Number of Sectors in Bank 2 59h B2h 00XXh XX = 38 (A29DL322) XX = 30 (A29DL323) XX = 20 (A29DL324) 5Ah 5Bh B4h B6h 0000 0000 Bank 3 Region Information – Number of Sector in Bank 3 Bank 4 Region Information – Number of Sector in Bank 4 Description Query-unique ASCII string “PRI” PRELIMINARY (August, 2005, Version 0.0) 24 AMIC Technology, Corp. A82DL32x4T(U) Series COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 12 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE or CE_F , whichever happens later. All data is latched on the rising edge of WE or CE_F , whichever happens first. Refer to the AC Characteristics section for timing diagrams. (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 12 shows the address and data requirements. This method is an alternative to that shown in Table 5, which is intended for PROM programmers and requires VID on address pin A9. The autoselect command sequence may be written to an address wit h in a bank that is either in t he read or erasesuspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. T he bank then enter s the autoselect mode. The system may read at any address within the same bank any number of times without initiating another autoselect command sequence: A read cycle at address (BA)XX00h (where BA is the bank address) returns the manufacturer code. A read cycle at address (BA)XX01h in word mode (or (BA)XX02h in byte mode) returns the device code. A read cycle to an address containing a sector address (SA) within the same bank, and the address 02h on A7-A0 in word mode (or the address 04h on A6-A-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. (Refer to Tables 3-4 for valid sector addresses). The system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in Erase Suspend). Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erasesuspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if I/O5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read parameters, and Figure 11 shows the timing diagram. Byte/Word Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE_F pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 12 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, that bank then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using I/O7, I/O6, or RY/ BY . Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set I/O5 = 1, or cause the I/O7 and I/O6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” 25 Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to reading array data. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If I/O5 goes high during a program or erase operation, writing the reset command returns the banks to reading array data PRELIMINARY (August, 2005, Version 0.0) AMIC Technology, Corp. A82DL32x4T(U) Series Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 12 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the twocycle unlock bypass reset command sequence. The device then returns to reading array data. The device offers accelerated program operations through the WP /ACC pin. When the system asserts VHH on the WP /ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP /ACC pin to accelerate the operation. Note that the WP /ACC pin must not be at VHH any operation other than accelerated programming, or device damage may result. In addition, the WP /ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 3 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 15 for timing diagrams. START Write Program Command Sequence Embedded Program algorithm in progress Data Poll from System Verify Data ? No Yes Increment Address No Last Address ? Yes Programming Completed Note : See Table 14 for program command sequnce. Figure 3. Program Operation PRELIMINARY (August, 2005, Version 0.0) 26 AMIC Technology, Corp. A82DL32x4T(U) Series Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 12 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using I/O7, I/O6, I/O2, or RY/ BY . Refer to the Write Operation Status section for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 17 section for timing diagrams. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading I/O7, I/O6, I/O2, or RY/ BY in the erasing bank. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 17 section for timing diagrams Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase timeout, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on I/O7–I/O0. The system can use I/O7, or I/O6 and I/O2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the I/O7 or I/O6 status bits, just as in the standard Byte Program operation. Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the Autoselect Mode and Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is ignored when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 12 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase timeout of 50 µs occurs. During the time-out period, additional sector addresses and sector erase commands within the bank may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to reading array data. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor I/O3 to determine if the sector erase timer has timed out (See the section on I/O3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE pulse in the command sequence. PRELIMINARY (August, 2005, Version 0.0) 27 AMIC Technology, Corp. A82DL32x4T(U) Series START Write Erase Command Sequence (Notes 1,2) Data Poll to Erasing Bank from System Embedded Erase algorithm in progress No Data = FFh ? Yes Erasure Completed Note : 1. See Table 14 for erase command sequence. 2. See the section on I/O3 for information on the sector erase timer. Figure 4. Erase Operation PRELIMINARY (August, 2005, Version 0.0) 28 AMIC Technology, Corp. A82DL32x4T(U) Series Command Definitions Table 12. A82DL32x4T(U) Command Definitions Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Autoselect (Note 8) Manufacturer ID Device ID Continuation ID Sector Protect Verify (Note 9) Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte First Addr Data RA XXX 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA XXX XXX 555 AAA 555 AAA XXX XXX 55 AA RD F0 AA AA AA AA AA AA AA A0 90 AA AA B0 30 98 Second Addr Data Bus Cycles (Notes 2–5) Third Fourth Addr Data Addr Data Cycle Fifth Addr Data Sixth Addr Data 1 1 4 4 4 4 3 4 3 2 2 6 6 1 1 Word Byte 1 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 PA XXX 2AA 555 2AA 555 55 55 55 55 55 55 55 PD 00 55 55 (BA)555 (BA)AAA (BA)555 (BA)AAA 90 90 90 90 77 A0 20 (BA)X00 (BA)X01 37 (see (BA)X02 Table5) 555 AAA (BA)555 (BA)AAA X03 X06 (SA) (SA)X04 7F 00/01 Command Temporary Sector Unprotect (Note15) Program Unlock Bypass 555 AAA 555 AAA 555 AAA PA PD Unlock Bypass Program (Note 10) Unlock Bypass Reset (Note 11) Chip Erase Sector Erase Erase Suspend (Note 12) Erase Resume (Note 13) CFI Query (Note 14) Word Byte Word Byte 555 AAA 555 AAA 80 80 555 AA A 555 AAA AA AA 2AA 555 2AA 555 55 55 555 AAA SA 10 30 Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE or CE_F pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE_F pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20 - A12 select a unique sector. BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. Note: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits I/O15-I/O8 are don’t care in command sequences. Except for RD and PD. 5. Unless otherwise noted, address bits A20-A11 are don’t cares. 6. No unlock or command cycles required when bank is reading array data. 7. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if I/O5 goes high (while the bank is providing status information). 8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacture ID, or device ID information. Data bits I/O15-I/O8 are don’t care. See the Autoselect Command Sequence section for more information. 9. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 10. The Unlock Bypass command is required prior to the Unlock Bypass Program Command. 11. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and require the bank address. 13. The Erase Resume command is valid only during the Erase. 14. Command is valid when device is ready to read array data or when device is in autoselect mode. 15. Once reset command is applied, software temporary unprotect is exit to return read array data. But under erase suspend condition, this command is still effective even a reset command has been applied. The reset command which can deactivate the software temporary unprotect command is useful only after the erase command is complete. PRELIMINARY (August, 2005, Version 0.0) 29 AMIC Technology, Corp. A82DL32x4T(U) Series WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: I/O2, I/O3, I/O5, I/O6, and I/O7. Table 13 and the following subsections describe the function of these bits. I/O7 and I/O6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/ BY , to determine whether an Embedded Program or Erase operation is in progress or has been completed. START Read I/O7-I/O0 Address = VA I/O7: Data Polling The Data Polling bit, I/O7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data Polling is valid after the rising edge of the final WE pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on I/O7 the complement of the datum programmed to I/O7. This I/O7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to I/O7. The system must provide the program address to read valid status information on I/O7. If a program address falls within a protected sector, Data Polling on I/O7 is active for approximately 1µs, then the device returns to reading array data. During the Embedded Erase algorithm, Data Polling produces a "0" on I/O7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data Polling produces a "1" on I/O7. The system must provide an address within any of the sectors selected for erasure to read valid status information on I/O7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on I/O7 is active for approximately 100µs, then the bank returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads I/O7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, I/O7 may change asynchronously with I/O0– I/O6 while Output Enable ( OE ) is asserted low. That is, the device may change from providing status information to valid data on I/O7. Depending on when the system samples the I/O7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and I/O7 has valid data, the data outputs on I/O0-I/O6 may be still invalid. Valid data on I/O0-I/O7 will appear on successive read cycles. Table 13 shows the outputs for Data Polling on I/O7. Figure 5 shows the Data Polling algorithm. Figure 19 in the AC Characteristics section shows the Data Polling timing diagram. I/O7 = Data ? Yes No No I/O5 = 1? Yes Read I/O7 - I/O0 Address = VA Yes I/O7 = Data ? No FAIL PASS Note : 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. I/O7 should be rechecked even if I/O5 = "1" because I/O7 may change simultaneously with I/O . 5 Figure 5. Data Polling Algorithm PRELIMINARY (August, 2005, Version 0.0) 30 AMIC Technology, Corp. A82DL32x4T(U) Series RY/ BY : Ready/ Busy The RY/ BY is a dedicated, open-drain output pin that indicates whether an Embedded algorithm is in progress or complete. The RY/ BY status is valid after the rising edge of the final WE pulse in the command sequence. Since RY/ BY is an open-drain output, several RY/ BY pins can be tied together in parallel with a pull-up resistor to VCC_F. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 13 shows the outputs for RY/ BY . START Read I/O7-I/O0 Read I/O7-I/O0 (Note 1) I/O6: Toggle Bit I Toggle Bit I on I/O6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause I/O6 to toggle. The system may use either OE or CE_F to control the read cycles. When the operation is complete, I/O6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, I/O6 toggles for approximately 100µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use I/O6 and I/O2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), I/O6 toggles. When the device enters the Erase Suspend mode, I/O6 stops toggling. However, the system must also use I/O2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use I/O7 (see the subsection on " I/O7: Data Polling"). If a program address falls within a protected sector, I/O6 toggles for approximately 1µs after the program command sequence is written, then returns to reading array data. I/O6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 13 shows the outputs for Toggle Bit I on I/O6. Figure 6 shows the toggle bit algorithm. Figure 20 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 23 shows the differences between I/O2 and I/O6 in graphical form. See also the subsection on I/O2: Toggle Bit II. Toggle Bit = Toggle ? Yes No No I/O5 = 1? Yes Read I/O7 - I/O0 Twice (Notes 1,2) Toggle Bit = Toggle ? No Yes Program/Erase Operation Not Commplete, Write Reset Command Program/Erase Operation Complete Note: The system should recheck the toggle bit even if I/O5=”1" because the toggle bit may stop toggling as I/O5 changes to “1”. See the subsections on I/O6 and I/O2 for more information. Figure 6. Toggle Bit Algorithm PRELIMINARY (August, 2005, Version 0.0) 31 AMIC Technology, Corp. A82DL32x4T(U) Series I/O2: Toggle Bit II The "Toggle Bit II" on I/O2, when used with I/O6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE pulse in the command sequence. I/O2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE_F to control the read cycles.) But I/O2 cannot distinguish whether the sector is actively erasing or is erase-suspended. I/O6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 8 to compare outputs for I/O2 and I/O6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section " I/O2: Toggle Bit II" explains the algorithm. See also the " I/O6: Toggle Bit I" subsection. Figure 20 shows the toggle bit timing diagram. Figure 21 shows the differences between I/O2 and I/O6 in graphical form. I/O5: Exceeded Timing Limits I/O5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions I/O5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. The device may output a “1” on I/O5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, I/O5 produces a “1.” . Under both these conditions, the system must write the reset command to return to reading array data (or to the erasesuspend-read mode if a bank was previously in the erasesuspend-program mode). I/O3: Sector Erase Timer After writing a sector erase command sequence, the system may read I/O3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, I/O3 switches from "0" to "1." The system may ignore I/O3 if the system can guarantee that the time between additional sector erase commands will always be less than 50µs. See also the "Sector Erase Command Sequence" section. After the sector erase command sequence is written, the system should read the status on I/O7 ( Data Polling) or I/O6 (Toggle Bit 1) to ensure the device has accepted the command sequence, and then read I/O3. If I/O3 is "1", the internally controlled erase cycle has begun; all further commands (Except Erase Suspend) are ignored until the erase operation is complete. If I/O3 is "0", the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of I/O3 prior to and following each subsequent sector erase command. If I/O3 is high on the second status check, the last command might not have been accepted. Table 13 shows the status of I/O3 relative to the other status bits. Reading Toggle Bits I/O6, I/O2 Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read I/O7-I/O0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on I/O7-I/O0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of I/O5 is high (see the section on I/O5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as I/O5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and I/O5 has not gone high. The system may continue to monitor the toggle bit and I/O5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6). PRELIMINARY (August, 2005, Version 0.0) 32 AMIC Technology, Corp. A82DL32x4T(U) Series Table 13. Write Operation Status Status Standard Embedded Program Algorithm Mode Embedded Erase Algorithm Erase Erase Suspend Erase-Suspend- Suspended Sector Mode Read Non-Erase Suspend Sector Erase-Suspend-Program Notes: 1. I/O5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on I/O5 for more information. 2. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. I/O7 (Note 2) I/O6 I/O5 (Note 1) Toggle Toggle No toggle Data Toggle 0 0 0 Data 0 N/A 1 N/A Data N/A I/O3 I/O2 (Note 2) No toggle Toggle Toggle Data N/A 0 0 1 1 0 RY/ BY I/O7 0 1 Data I/O7 PRELIMINARY (August, 2005, Version 0.0) 33 AMIC Technology, Corp. A82DL32x4T(U) Series ABSOLUTE MAXIMUM RATINGS* Storage Temperature Plastic Packages. . . -65°C to + 150°C Ambient Temperature with Power Applied. -65°C to + 125°C Voltage with Respect to Ground VCC_F/VCC_S (Note 1) . . . . . . . .. . . . ……. . -0.5V to +4.0V A9, OE & RESET (Note 2) . . . . . . . . . . . . -0.5V to +12.5V *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. WP /ACC . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +10.5V All other pins (Note 1) . . . . . . -0.5V to VCC_F/VCC_S + 0.5V Output Short Circuit Current (Note 3) . . . . . . . …. . 200mA OPERATING RANGES Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . -40°C to +85°C VCC Supply Voltages VCC_F/VCC_S for all devices . .. . . . . . . …...+2.7V to +3.6V Operating ranges define those limits between which the functionally of the device is guaranteed. Notes: 1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0V for periods of up to 20ns. Maximum DC voltage on input and I/O pins is VCC_F/VCC_F +0.5V. See Figure 7. During voltage transitions, input or I/O pins may overshoot to VCC_F/VCC_S +2.0V for periods up to 20ns. See Figure 8. 2. Minimum DC input voltage on A9, OE , RESET and WP /ACC is -0.5V. During voltage transitions, A9, OE , WP /ACC and RESET may overshoot VSS to -2.0V for periods of up to 20ns. See Figure 7. Maximum DC input voltage on A9 is +12.5V which may overshoot to 14.0V for periods up to 20ns. Maximum DC input voltage on WP /ACC is +9.5V which may overshoot to +12.0V for period up to 20ns. 3. No more than one output is shorted to ground at a time. Duration of the short circuit should not be greater than one second. Figure 7. Maximum Negative Overshoot Waveform 20ns +0.8V 20ns -0.5V -2.0V 20ns Figure 8. Maximum Positive Overshoot Waveform 20ns VCC_F//VCC_S +2.0V VCC_F/VCC_S +0.5V 2.0V 20ns 20ns PRELIMINARY (August, 2005, Version 0.0) 34 AMIC Technology, Corp. A82DL32x4T(U) Series DC CHARACTERISTICS CMOS Compatible Parameter Symbol ILI ILIT ILO Parameter Description Input Load Current A9 Input Load Current Output Leakage Current Test Description VIN = VSS to VCC_F. VCC_F= VCC_F Max VCC = VCC Max, A9 =12.5V VOUT = VSS to VCC_F. VCC = VCC_F Max Min. Typ. Max. ±1.0 35 ±1.0 Unit µA µA µA CE_F = VIL, OE = VIH Byte Mode ICC1_F VCC_F Active Read Current (Notes 1, 2) 5 MHz 1 MHz 5 MHz 1 MHz 10 2 10 2 20 0.2 0.2 0.2 16 4 16 4 30 5 5 5 mA µA µA µA mA CE_F = VIL, OE = VIH Word Mode ICC2_F ICC3_F ICC4_F ICC5_F VCC_F Active Write Current (Notes 2, 3) VCC_F Standby Current (Note 2) VCC_F Reset Current (Note 2) Automatic Sleep Mode (Note 2, 4) VCC_F Active Read-While-Program Current (Notes 1, 2) VCC_F Active Read-While-Erase Current (Notes 1, 2) VCC_F Active Program-While-Erase-Suspended Current (Notes 2, 5) ACC Accelerated Program Current, Word or Byte Input Low Level Input High Level Voltage for WP /ACC Sector Protect/Unprotect and Program Acceleration Voltage for Autoselect and Temporary Unprotect Sector Output Low Voltage Output High Voltage CE_F = VIL, OE =VIH CE_F = VIH, RESET = VCC_F ± 0.3V RESET = VSS ± 0.3V VIH = VCC_F ± 0.3V; VIL = VSS ± 0.3V ICC6_F CE_F = VIL, OE = VIH CE_F = VIL, OE = VIH CE_F = VIL, OE = VIH CE_F = VIL, OE = VIH Byte Word Byte Word 21 21 21 21 17 45 mA 45 45 mA 45 35 10 mA 30 0.8 VCC_F + 0.3 9.5 V V mA ICC7_F ICC8_F ACC pin VCC_F pin -0.5 0.7 x VCC_F 5 15 IACC VIL VIH VHH VID VOL VOH1 VOH2 VLKO VCC_F = 3.0 V ± 10% 8.5 V VCC_F = 3.0 V ± 10% IOL = 4.0mA, VCC_F = VCC_F Min IOH = -2.0 mA, VCC_F = VCC_F Min IOH = -100 µA, VCC_F = VCC Min 8.5 12.5 0.45 V V V V 0.85x VCC_F VCC_F 0.4 2.3 2.5 Low VCC_F Lock-Out Voltage (Note 5) V Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE at VIH. 2. Maximum ICC specifications are tested with VCC_F = VCC_F max. 3. ICC active while Embedded Algorithm (program or erase) is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC_F + 30ns. Typical sleep mode current is 200nA. 5. Not 100% tested. PRELIMINARY (August, 2005, Version 0.0) 35 AMIC Technology, Corp. A82DL32x4T(U) Series TEST CONDITIONS Table 14. Test Specifications Test Condition Output Load Output Load Capacitance, CL(including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 30 5 0.0 - 3.0 1.5 1.5 -70 1 TTL gate pF ns V V V Unit Figure 9. Test Setup 3.3 V 2.7 KΩ Device Under Test CL 6.2 KΩ Diodes = IN3064 or Equivalent Figure 10. Input Waveforms and Measurement Levels 3.0V Input 0.0V 1.5V Measurement Level 1.5V Output PRELIMINARY (August, 2005, Version 0.0) 36 AMIC Technology, Corp. A82DL32x4T(U) Series AC CHARACTERISTICS Read Only Operations Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ Std tRC tACC tCE tOE tDF tDF Read Cycle Time (Note 1) Min. Description Test Setup Speed -70 70 70 70 30 16 16 ns ns ns ns ns ns Unit CE_F = VIL Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Notes 1,3) Output Enable to Output High Z (Notes 1,3) Output Hold Time from Addresses, CE or OE , Whichever Occurs First Output Enable Hold Time (Note 1) Read Toggle and OE = VIL OE = VIL Max. Max. Max. Max. Max. tAXQX tOH tOEH Min. Min. Min. 0 0 10 ns ns ns Data Polling Notes: 1. Not 100% tested. 2. See Figure 9 and Table 14 for test specifications. 3. Measurements performed by placing a 50-ohm termination on the data pin with a bias of (VCC_F)/2. The time from OE high to the data bus driven to (VCC_F)/2 is taken as tDF. Figure 11. Read Operation Timings tRC Addresses tACC CE_F tRH tRH OE tOEH WE Output High-Z tCE Output Valid tOH High-Z tOE tDF Addresses Stable RESET RY/BY 0V PRELIMINARY (August, 2005, Version 0.0) 37 AMIC Technology, Corp. A82DL32x4T(U) Series AC CHARACTERISTICS Hardware Reset ( RESET ) Parameter JEDEC Std tREADY tREADY tRP tRH tRB tRPD Description Test Setup Max Max Min Min Min Min All Speed Options 20 500 500 50 0 20 Unit µs ns ns ns ns µs RESET Pin Low (During Embedded Algorithms) to Read or Write (See Note) RESET Pin Low (Not During Embedded Algorithms) to Read or Write (See Note) RESET Pulse Width RESET High Time Before Read (See Note) RY/ BY Recovery Time RESET Low to Standby Mode Note: Not 100% tested. Figure 12. RESET Timings RY/BY 0V CE_F, OE tRH RESET tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY ~~ ~~ tRB CE_F, OE ~ ~ RESET tRP PRELIMINARY (August, 2005, Version 0.0) 38 AMIC Technology, Corp. A82DL32x4T(U) Series AC CHARACTERISTICS Word/Byte Configuration ( BYTE_F ) Parameter JEDEC Std tELFL/tELFH tFLQZ tHQV Description Speed Option -70 Unit CE_F to BYTE_F Switching Low or High BYTE_F Switching Low to Output High-Z BYTE_F Switching High to Output Active Max Max Min 5 25 70 ns ns ns Figure 13. BYTE_F Timings for Read Operations CE_F OE BYTE_F tELFL BYTE_F Switching from word to byte mode I/O0-I/O14 Data Output (I/O0-I/O14) Data Output (I/O0-I/O7) I/O15 (A-1) tELFH I/O15 Output tFLQZ Address Input BYTE_F I/O0-I/O14 Data Output (I/O0-I/O7) Data Output (I/O0-I/O14) BYTE _F Switching from byte to word mode I/O15 (A-1) Address Input tFHQV I/O15 Output Figure 14. BYTE_F Timings for Write Operations CE_F The falling edge of the last WE signal WE BYTE_F tSET (tAS) tHOLD (tAH) Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. PRELIMINARY (August, 2005, Version 0.0) 39 AMIC Technology, Corp. A82DL32x4T(U) Series AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC tAVAV tAVWL Std tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tGHWL tCS tCH tWP tWPH tSR/W Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE low during toggle bit polling Address Hold Time Address Hold Time From CE_F or OE high during toggle bit polling Data Setup Time Data Hold Time Output Enable High during toggle bit polling Read Recover Time Before Write ( OE high to WE low) Min. Min. Min. Min. Min. Min. Min. Min. Min. Typ. Typ. Typ. Typ. Min. Min Min Min. Min. Min. Description Speed -70 70 0 15 45 0 35 0 20 0 0 0 30 30 0 5 µs Word 7 4 0.7 50 0 90 sec sec µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit CE_F Setup Time CE_F Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Byte Programming Operation (Note 2) Accelerated Programming Operation, Word or Byte (Note 2) Byte tWHWH1 tWHWH1 tWHWH1 tWHWH2 tWHWH1 tWHWH2 tvcs tRB tBUSY Sector Erase Operation (Note 2) VCC_F Set Up Time (Note 1) Recovery Time from RY/ BY Program/Erase Valid to RY/ BY Delay Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. PRELIMINARY (August, 2005, Version 0.0) 40 AMIC Technology, Corp. A82DL32x4T(U) Series AC CHARACTERISTICS Figure 15. Program Operation Timings Program Command Sequence (last two cycles) Read Status Data (last two cycles) Addresses 555h PA ~ ~ tWC tAS PA PA tAH CE_F tCH OE tWP WE tCS tDS Data A0h tWPH tDH PD ~ ~ tWHWH1 ~ ~ ~ ~ ~~ ~~ Status DOUT tRB tBUSY RY/BY tVCS VCC_F Note : 1. PA = program address, PD = program data, Dout is the true data at the program address. 2. Illustration shows device in word mode. Figure 16. Accelerated Program Timing Diagram VHH WP/ACC VIL or VIH tVHH tVHH ~~ ~~ ~ ~ VIL or VIH PRELIMINARY (August, 2005, Version 0.0) 41 AMIC Technology, Corp. A82DL32x4T(U) Series AC CHARACTERISTICS Figure 17. Chip/Sector Erase Operation Timings Erase Command Sequence (last two cycles) Read Status Data Addresses 2AAh SA 555h for chip erase ~ ~ VA tWC tAS VA tAH CE_F OE tCH tWP WE tCS tDS Data 55h tDH 30h 10h for chip erase tWPH ~ ~ tWHWH2 ~ ~ ~~ ~~ In Progress ~ ~ Complete tRB tBUSY RY/BY tVCS VCC_F Note : 1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus"). 2. Illustration shows device in word mode. ~ ~ ~ ~ PRELIMINARY (August, 2005, Version 0.0) 42 AMIC Technology, Corp. A82DL32x4T(U) Series AC CHARACTERISTICS Figure 18. Back-to-back Read/Write Cycle Timings tWC Addresses Valid PA tAH tRC Valid RA tWC Valid PA tWC Valid PA tACC tCE tCPH CE_F tOE tCP OE tWP WE tWPH tDS tDH Data Valid In tSR/W WE Controlled Write Cycle tOEH tGHWL tDF tOH Valid Out Valid In Valid In Read Cycle CE Controlled Write Cycles Figure 19. Data Polling Timings (During Embedded Algorithms) tRC Addresses VA tACC CE_F tCH tCE ~ ~ VA VA OE tOEH WE tDF tOH High-Z I/O7 Complement Complement True Valid Data High-Z High-Z tBUSY RY/BY Status Data ~ ~ I/O0 - I/O6 ~ ~ ~ ~ ~ ~ tOE ~~ ~~ Status Data True Valid Data Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data read cycle. ~ ~ PRELIMINARY (August, 2005, Version 0.0) 43 AMIC Technology, Corp. A82DL32x4T(U) Series AC CHARACTERISTICS Figure 20. Toggle Bit Timings (During Embedded Algorithms) tAHT Addresses tAHT tASO tAS CE_F tOEH tCEPH WE OE tOEPH tDH I/O6 , I/O2 Valid Status Valid Status (first read) tOE ~ ~ ~ ~ Valid Status (second read) Valid Status ~ ~ ~ ~ ~ ~ Valid Data (stop togging) RY/BY Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Figure 21. I/O2 vs. I/O6 Enter Embedded Erasing WE Erase Suspend Enter Erase Suspend Program Erase Resume ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ Erase Erase Suspend Read Erase Suspend Program Erase Suspend Read Erase ~ ~ Erase Complete ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ I/O6 ~ ~ ~ ~ I/O2 I/O2 and I/O6 toggle with OE and CE_F Note : Both I/O6 and I/O2 toggle with OE or CE_F. See the text on I/O6 and I/O2 in the section "Write Operation Status" for more information. PRELIMINARY (August, 2005, Version 0.0) 44 AMIC Technology, Corp. ~ ~ ~ ~ A82DL32x4T(U) Series AC CHARACTERISTICS Temporary Sector/Sector Block Unprotect Parameter JEDEC Std tVIDR tVHH tRSP tRRB Description VID Rise and Fall Time (See Note) VHH Rise and Fall Time (See Note) Min Min Min Min All Speed Options 500 250 4 4 Unit ns µs µs µs RESET Setup Time for Temporary Sector/Sector Block Unprotect RESET Hold Time from RY/ BY High for Temporary Sector/Sector Block Unprotect Note: Not 100% tested. Figure 22. Temporary Sector/Sector Block Unprotect Timing Diagram VID VSS, VIL, or VIH RESET tVIDR CE_F VID VSS, VIL, or VIH Program or Erase Command Sequence ~ ~ tVIDR ~ ~ WE ~~ ~~ tRSP RY/BY tRRB Program/Erase Command Sequence CE_F WE Address 555 2AA 555 ~ ~ XXX I/O0 - I/O7 AA 55 77 ~~ ~~ FQ RY/BY ~ ~ PRELIMINARY (August, 2005, Version 0.0) 45 AMIC Technology, Corp. A82DL32x4T(U) Series AC CHARACTERISTICS Figure 23. Sector/Sector Block Protect and Unprotect Timing Diagram VID RESET VIH SA, A6, A1, A0 Valid* Sector Protect/Unprotect ~ ~ Valid* Valid* ~ ~ Verify Data 1us 60h 60h Sector Protect:150us Sector Unprotect:15ms ~ ~ 40h Status CE WE OE Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0 ~ ~ 200ns-300ns PRELIMINARY (August, 2005, Version 0.0) 46 AMIC Technology, Corp. A82DL32x4T(U) Series AC CHARACTERISTICS Alternate CE_F Controlled Erase and Program Operations Parameter JEDEC tAVAV tAVEL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL Std tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recover Time Before Write ( OE High to WE Low) Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Byte Word Typ. Typ. Typ. Typ. Description Speed -70 70 0 45 35 0 0 0 0 30 30 5 7 4 0.7 µs sec ns ns ns ns ns ns ns ns ns ns Unit WE Setup Time WE Hold Time CE_F Pulse Width CE_F Pulse Width High Programming Operation (Note 2) Accelerated Programming Operation, Word or Byte (Note 2) Sector Erase Operation (Note 2) tWHWH1 tWHWH1 µs tWHWH1 tWHWH2 tWHWH1 tWHWH2 Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. PRELIMINARY (August, 2005, Version 0.0) 47 AMIC Technology, Corp. A82DL32x4T(U) Series AC CHARACTERISTICS Figure 24. Alternate CE_F Controlled Write (Erase/Program) Operation Timings 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data Polling ~ ~ Addresses tWC tAS PA WE OE CE_F tWS tDS tCPH tBUSY tDH ~ ~ ~ ~ tCP tWHWH1 or 2 ~ ~ tGHEL ~ ~ tWH tAH ~ ~ Data tRH I/O7 DOUT A0 for program 55 for erase RESET RY/BY Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. I/O7 is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode. ~ ~ ~ ~ PD for program 30 for sector erase 10 for chip erase PRELIMINARY (August, 2005, Version 0.0) 48 AMIC Technology, Corp. A82DL32x4T(U) Series SRAM DC Electrical Characteristics Symbol Parameter Min. ⎜ILI⎥ Input Leakage Current (TA = -40°C to +85°C, VCC_S = 2.7V to 3.6V, GND = 0V) - 70 ns Max. 1 µA VIN = GND to VCC_S Unit Conditions ⎜ILO⎥ Output Leakage Current - 1 µA CE1_S = VIH or CE2_S = VIL or OE = VIH or W E = VIL VI/O = GND to VCC ICC_S Active Power Supply Current - 3 mA CE1_S = VIL, CE2_S = VIH II/O = 0mA Min. Cycle, Duty = 100% ICC1_S Dynamic Operating Current ICC2_S - 30 mA CE1_S = VIL, CE2_S = VIH II/O = 0mA CE1_S = VIL, CE2_S = VIH 3 mA VIH = VCC_S, VIL = 0V f = 1 MHZ, II/O = 0mA ISB_S Standby Power Supply Current ISB1_S VOL VOH Output Low Voltage Output High Voltage - 0.5 mA VCC_S ≤ 3.3V, CE1_S = VIH or CE2_S =VIL VCC ≤ 3.3V, CE1_S ≥ VCC - 0.2V or CE2_S ≤ 0.2V, VIN ≥ 0V IOL = 2.1mA IOH = -1.0mA 2.2 5 0.4 - µA V V Truth Table Mode CE1_S CE2_S OE X X H L X WE X X H H L I/O Operation Supply Current Standby H X X L H H H High Z High Z High Z DOUT DIN ISB, ISB1 ISB, ISB1 ICC, ICC1, ICC2 ICC, ICC1, ICC2 ICC, ICC1, ICC2 Output Disable Read Write Note: X = H or L L L L PRELIMINARY (August, 2005, Version 0.0) 49 AMIC Technology, Corp. A82DL32x4T(U) Series Capacitance (TA = 25°C, f = 1.0MHz) Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. 6 8 Unit pF pF Conditions VIN = 0V VI/O = 0V * These parameters are sampled and not 100% tested. PRELIMINARY (August, 2005, Version 0.0) 50 AMIC Technology, Corp. A82DL32x4T(U) Series AC Characteristics Symbol (TA = -40°C to +85°C, VCC_S = 2.7V to 3.6V) Parameter Min. Read Cycle tRC tAA tACE1 tACE2 tOE tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tOHZ tOH Write Cycle tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 70 60 0 60 50 0 0 30 0 5 25 ns ns ns ns ns ns ns ns ns ns Output Disable to Output in High Z Output Hold from Address Change Output Enable to Output in Low Z Chip Disable to Output in High Z Output Enable to Output Valid Chip Enable to Output in Low Z Read Cycle Time Address Access Time Chip Enable Access Time 70 70 70 70 35 25 25 25 ns ns ns ns ns ns ns ns ns ns ns ns -70 ns Max. Unit CE1_S CE2_S - CE1_S CE2_S 10 10 5 CE1_S CE2_S 0 0 0 10 Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. PRELIMINARY (August, 2005, Version 0.0) 51 AMIC Technology, Corp. A82DL32x4T(U) Series Timing Waveforms Read Cycle 1 (1, 2, 4) tRC Address tAA tOH tOH DOUT Read Cycle 2 (1, 3, 4, 6) CE1_S tACE1 tCLZ15 tCHZ15 DOUT Read Cycle 3 (1, 4, 7, 8) CE2_S tACE2 tCLZ25 tCHZ25 DOUT PRELIMINARY (August, 2005, Version 0.0) 52 AMIC Technology, Corp. A82DL32x4T(U) Series Timing Waveforms (continued) Read Cycle 4 (1) tRC Address tAA OE tOE tOH tOLZ5 CE1_S tACE1 tCLZ15 tCHZ15 CE2_S tACE2 tCLZ25 tOHZ5 tCHZ25 DOUT Notes: 1. W E is high for Read Cycle. 2. Device is continuously enabled CE1_S = VIL and CE2_S = VIH. 3. Address valid prior to or coincident with CE1_S transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. 6. CE2_S is high. 7. CE1_S is low. 8. Address valid prior to or coincident with CE2_S transition high. Write Cycle 1 (6) (Write Enable Controlled) t WC Address tAW t CW 5 t WR3 CE1_S (4) CE2_S t AS1 (4) tWP 2 WE tD W tDH DIN tWHZ tO W DOUT PRELIMINARY (August, 2005, Version 0.0) 53 AMIC Technology, Corp. A82DL32x4T(U) Series Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address tAW tCW 5 tWR3 CE1_S tAS 1 (4) CE2_S (4) tCW 5 tWP2 WE tDW tDH DIN tWHZ 7 DOUT Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (tWP) of a low CE1_S , a high CE2_S and a low W E . 3. tWR is measured from the earliest of CE1_S or W E going high or CE2_S going low to the end of the Write cycle. 4. If the CE1_S low transition or the CE2_S high transition occurs simultaneously with the W E low transition or after the W E transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE1_S going low or CE2_S going high to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (August, 2005, Version 0.0) 54 AMIC Technology, Corp. A82DL32x4T(U) Series SRAM Data Retention Characteristics (TA = -40°C to 85°C) Symbol VDR1 VCC for Data Retention VDR2 2.0 3.6 V CE2_S ≤ 0.2V, VCC_S = 2V, ICCDR1_S Data Retention Current Chip Disable to Data Retention Time Operation Recovery Time 1µA at TA = 0°C to + 40°C 0 5 1* µA Parameter Min. 2.0 Max. 3.6 Unit V Conditions CE1_S ≥ VCC - 0.2V - 1* µA CE1_S ≥ VCC_S - 0.2V, VIN ≥ 0V VCC_S = 2V, CE2_S ≤ 0.2V, VIN ≥ 0V See Retention Waveform ICCDR2_S tCDR tR * ns ms ICCDR_S: max. Low VCC_S Data Retention Waveform (1) ( CE1_S Controlled) DATA RETENTION MODE VCC_S 3.0V tCDR VDR _Σ ≥ 2V 3.0V tR CE1_S VIH CE1_S ≥ VDR - 0.2V VIH Low VCC Data Retention Waveform (2) (CE2_S Controlled) DATA RETENTION MODE VCC_S 3.0V tCDR VDR_S ≥ 2.0V 3.0V tR CE2_S VIL CE2_S ≤ 0.2V VIL PRELIMINARY (August, 2005, Version 0.0) 55 AMIC Technology, Corp. A82DL32x4T(U) Series ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Accelerated Word/Byte Programming Time Chip Programming Time (Note 3) Byte Mode Word Mode Typ. (Note 1) 0.7 27 5 7 4 9 6 150 210 120 27 18 Max. (Note 2) 15 Unit sec sec µs µs µs Comments Excludes 00h programming prior to erasure (Note 4) Excludes system-level overhead (Note 5) sec sec Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC_F, 10,000 cycles. Additionally, programming typically assumes checkerboard pattern. 2. Under worst case conditions of 90°C, VCC_F = 2.7V, 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 12 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 10,000 cycles. FLASH LATCH-UP CHARACTERISTICS Description Input Voltage with respect to VSS on all I/O pins VCC_F Current Input voltage with respect to VSS on all pins except I/O pins (including A9, OE and RESET ) Includes all pins except VCC_F. Test conditions: VCC_F = 3.0V, one pin at time. Min. -1.0V -100 mA -1.0V Max. VCC_F+1.0V +100 mA 12.5V DATA RETENTION Parameter Minimum Pattern Data Retention Time Test Conditions 150°C 125°C Min 10 20 Unit Years Years PRELIMINARY (August, 2005, Version 0.0) 56 AMIC Technology, Corp. A82DL32x4T(U) Series Ordering Information Top Boot Sector Flash & SRAM Part No. A82DL3224TG-70 A82DL3224TG-70F A82DL3224TG-70I 70 A82DL3224TG-70IF A82DL3224TG-70U A82DL3224TG-70UF A82DL3234TG-70 A82DL3234TG-70F A82DL3234TG-70I 70 A82DL3234TG-70IF A82DL3234TG-70U A82DL3234TG-70UF A82DL3244TG-70 A82DL3244TG-70F A82DL3244TG-70I 70 A82DL3244TG-70IF A82DL3244TG-70U A82DL3244TG-70UF Note: Industrial operating temperature range: -40°C to 85°C for –U; -25°C to 85°C for –I 16M 16M 69-ball Pb-Free TFBGA 69-ball TFBGA 69-ball Pb-Free TFBGA 8M 24M 69-ball Pb-Free TFBGA 69-ball TFBGA 69-ball Pb-Free TFBGA 69-ball TFBGA 69-ball Pb-Free TFBGA 69-ball TFBGA 4M 28M 69-ball Pb-Free TFBGA 69-ball TFBGA 69-ball Pb-Free TFBGA 69-ball TFBGA 69-ball Pb-Free TFBGA 69-ball TFBGA Access Time (ns) Bank 1 Bank 2 Package 69-ball TFBGA 69-ball Pb-Free TFBGA 69-ball TFBGA PRELIMINARY (August, 2005, Version 0.0) 57 AMIC Technology, Corp. A82DL32x4T(U) Series Bottom Boot Sector Flash & SRAM Part No. A82DL3224UG-70 A82DL3224UG-70F A82DL3224UG-70I 70 A82DL3224UG-70IF A82DL3224UG-70U A82DL3224UG-70UF A82DL3234UG-70 A82DL3234UG-70F A82DL3234UG-70I 70 A82DL3234UG-70IF A82DL3234UG-70U A82DL3234UG-70UF A82DL3244UG-70 A82DL3244UG-70F A82DL3244UG-70I 70 A82DL3244UG-70IF A82DL3244UG-70U A82DL3244UG-70UF Note: Industrial operating temperature range: -40°C to 85°C for –U; -25°C to 85°C for –I 16M 16M 69-ball Pb-Free TFBGA 69-ball TFBGA 69-ball Pb-Free TFBGA 8M 24M 69-ball Pb-Free TFBGA 69-ball TFBGA 69-ball Pb-Free TFBGA 69-ball TFBGA 69-ball Pb-Free TFBGA 69-ball TFBGA 4M 28M 69-ball Pb-Free TFBGA 69-ball TFBGA 69-ball Pb-Free TFBGA 69-ball TFBGA 69-ball Pb-Free TFBGA 69-ball TFBGA Access Time (ns) Bank 1 Bank 2 Package 69-ball TFBGA 69-ball Pb-Free TFBGA 69-ball TFBGA PRELIMINARY (August, 2005, Version 0.0) 58 AMIC Technology, Corp. A82DL32x4T(U) Series Package Information 69LD STF BGA (8 x 11mm) Outline Dimensions Pin #1 -AD aaa -BD1 e unit: mm K J H G F E D C B A aaa 1 2 3 4 5 6 7 8 9 10 See Detail B ddd M C eee M C A B See Detail A CAVITY // bbb C A2 C B A c A b -Cccc C SOLDER BALL SEATING PLANE Detail A A1 1 2 3 Detail B Symbol A A1 A2 c D E D1 E1 e b aaa bbb ccc ddd eee MD/ME Dimensions in mm Min Nom Max 1.40 0.25 0.30 0.35 0.91 0.96 1.01 0.22 0.26 0.30 7.90 8.00 8.10 10.90 11.00 11.10 7.20 7.20 0.80 0.35 0.40 0.45 0.15 0.20 0.12 0.15 0.08 10/10 Dimensions in inches Min Nom Max 0.055 0.010 0.012 0.014 0.036 0.038 0.040 0.009 0.010 0.012 0.311 0.315 0.319 0.429 0.433 0.437 0.283 0.283 0.031 0.14 0.16 0.18 0.006 0.008 0.005 0.006 0.003 10/10 Notes: 1. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 2. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C. 3. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. 4. REFERENCE DOCUMENT: JEDEC MO-219 5. THE PATTERN OF PIN 1 FIDUCIAL IS FOR REFERENCE ONLY. PRELIMINARY (August, 2005, Version 0.0) 59 AMIC Technology, Corp. E1 E