LP61L1024V-15

LP61L1024 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM Document Title 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM Revision History Rev. No. 2.0 2.1 History Add product family and 32-pin TSSOP package Add 36 ball BGA package type Issue Date May 9, 2002 August 22, 2002 Remark Final (August, 2002, Version 2.1) AMIC Technology, Inc. LP61L1024 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM Features n Single +3.3V power supply n Access times: 12/15 ns (max.) n Current: Operating: 170mA (max.) Standby: 10mA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL compatible n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2.0V (min.) n Available in 32-pin SOJ 300 mil, 32-pin TSOP and 32pin TSSOP and 36-pin CSP packages General Description The LP61L1024 is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2.0V. Product Family Product Family Operating Temperature VCC Range Power Dissipation Speed Data Retention (ICCDR, Typ.) Standby (ISB1, Typ.) Operating (ICC1, Typ.) Package Type 32L SOJ LP61L1024 0°C ~ 70°C 32L TSOP 3V ~ 3.6V 12/15 ns 0.4mA 0.5mA 130mA 32L TSSOP 36B µBGA 1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested. 2. Data retention current VCC = 2.0V. (August, 2002, Version 2.1) 1 AMIC Technology, Inc. LP61L1024 Pin Configurations n SOJ n TSOP / TSSOP n CSP (Chip Size Package) 36-pin Top View NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 Pin No. Pin Name Pin No. Pin Name 1 A11 17 A3 2 A9 18 A2 3 A8 19 A1 4 A13 20 A0 16 1 1 A B C D E F G H A0 I/O4 I/O5 GND VCC I/O6 I/O7 A9 OE A10 NC CE1 A11 NC A16 A12 A15 A13 2 A1 A2 3 NC WE NC 4 A3 A4 A5 5 A6 A7 6 A8 I/O0 I/O1 VCC GND I/O2 I/O3 A14 LP61L1024V(X) Block Diagram VCC GND A0 LP61L1024S 17 32 5 WE 21 I/O1 6 CE2 22 I/O2 7 A15 23 I/O3 8 VCC 24 GND 9 NC 25 I/O4 10 A16 26 I/O5 11 A14 27 I/O6 12 A12 28 I/O7 13 A7 29 I/O8 14 A6 30 CE1 15 A5 31 A10 16 A4 32 OE Pin Description Pin No. 2 - 12, 23, 25 - 28, 31 256 X 4096 DECODER MEMORY ARRAY Symbol A0 - A16 Description Address Inputs 29 24 22 WE OE CE1 CE2 NC I/O1 - I/O8 VCC GND Write Enable Output Enable Chip Enable Chip Enable No Connection Data Input/Outputs Power Supply Ground A14 A15 A16 I/O1 INPUT DATA CIRCUIT I/O8 30 COLUMN I/O 1 13 - 15, 17 - 21 32 CE2 CE1 OE WE CONTROL CIRCUIT 16 (August, 2002, Version 2.1) 2 AMIC Technology, Inc. LP61L1024 Recommended DC Operating Conditions (TA = 0°C to + 70°C) Symbol VCC GND VIH VIL CL TTL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Output Load Output Load Min. 3.0 0 2.2 -0.3 Typ. 3.3 0 0 Max. 3.6 0 VCC + 0.3 +0.8 30 1 Unit V V V V pF - Absolute Maximum Ratings* VCC to GND .............................................. -0.5V to +7.0V IN, IN/OUT Volt to GND .....................-0.5V to VCC +0.5V Operating Temperature, Topr ...................... 0°C to +70°C Storage Temperature, Tstg..................... -55°C to +125°C Temperature Under Bias, Tbias................ -10°C to +85°C Power Dissipation, Pt................................................1.0W Soldering Temp. & Time .............................260°C, 10 sec *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Symbol ILI ILO Parameter (TA = 0°C to + 70°C, VCC = 3.3V + 10%, GND = 0V) LP61L1024-12/15 Min. Max. 2 2 µA µA VIN = GND to VCC CE1 = VIH or CE2 = VIL or OE = VIH or W E = VIL VI/O = GND to VCC CE1 = VIL, CE2 = VIH II/O = 0 mA CE1 = VIH or CE2 = VIL CE1 ≥ VCC - 0.2V, CE2 ≥ VCC - 0.2V, VIN ≤ 0.2V or VIN ≥ VCC - 0.2V CE1 ≤ 0.2V, CE2 ≤ 0.2V VIN ≤ 0.2V or VIN ≥ VCC - 0.2V IOL = 8 mA IOH = -4 mA Unit Conditions Input Leakage Current Output Leakage Current - ICC1 (1) ISB ISB1 Dynamic Operating Current - 170 30 10 mA mA mA Standby Power Supply Current ISB2 VOL VOH Output Low Voltage Output High Voltage 2.4 10 0.4 mA V V Note: 1. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns (August, 2002, Version 2.1) 3 AMIC Technology, Inc. LP61L1024 Truth Table Mode Standby CE1 H X Output Disable Read Write Note: X = H or L L L L CE2 X L H H H OE X X H L X WE X X H H L I/O Operation High Z High Z High Z DOUT DIN Supply Current ISB, ISB1 ISB, ISB2 ICC1 ICC1 ICC1 Capacitance (TA = 25°C, f = 1.0MHz) Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. 8 10 Unit pF pF Conditions VIN = 0V VI/O = 0V * These parameters are sampled and not 100% tested. AC Characteristics (TA = 0°C to +70°C, VCC = 3.3V + 10, GND = 0V) Symbol Parameter LP61L1024-12 Min. Read Cycle tRC tAA tACE1 tACE2 tOE tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tOHZ tOH Output Disable to Output in High Z Output Hold from Address Change Output Enable to Output in Low Z Chip Disable to Output in High Z CE1 CE2 Output Enable to Output Valid Chip Enable to Output in Low Z CE1 CE2 Read Cycle Time Address Access Time Chip Enable Access Time CE1 CE2 12 3 3 2 2 3 12 12 12 7 7 7 7 15 5 5 2 2 5 15 15 15 9 10 10 9 ns ns ns ns ns ns ns ns ns ns ns ns Max. LP61L1024-15 Min. Max. Unit (August, 2002, Version 2.1) 4 AMIC Technology, Inc. LP61L1024 AC Characteristics (continued) Symbol Parameter LP61L1024-12 Min. Write Cycle tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW Write Cycle Time Chip Enable to End of Write Address Setup Time of Write Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 12 10 0 10 8 0 0 8 0 5 7 15 12 0 12 10 0 0 10 0 5 8 ns ns ns ns ns ns ns ns ns ns Max. LP61L1024-15 Min. Max. Unit Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. Timing Waveforms Read Cycle 1 (1, 2, 4) tRC Address tAA tOH tOH DOUT (August, 2002, Version 2.1) 5 AMIC Technology, Inc. LP61L1024 Read Cycle 2 (1, 3, 4, 6) CE1 tACE1 tCLZ15 tCHZ15 DOUT Read Cycle 3 (1, 4, 7, 8) CE2 tACE2 tCLZ25 tCHZ25 DOUT (August, 2002, Version 2.1) 6 AMIC Technology, Inc. LP61L1024 Timing Waveforms (continued) Read Cycle 4 (1) tRC Address tAA OE tOE tOLZ5 CE1 tOH tACE1 tCLZ25 tCHZ15 CE2 tACE2 tCLZ25 DOUT tOHZ5 tCHZ25 Notes: 1. 2. 3. 4. 5. 6. 7. 8. W E is high for Read Cycle. Device is continuously enabled CE1 = VIL and CE2 = VIH. Address valid prior to or coincident with CE1 transition low. OE = VIL. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. CE2 is high. CE1 is low. Address valid prior to or coincident with CE2 transition high. (August, 2002, Version 2.1) 7 AMIC Technology, Inc. LP61L1024 Timing Waveforms (continued) Write Cycle 1 (Write Enable Controlled) tWC Address tAW tCW5 CE1 (4) tWR 3 (6) CE2 (4) tAS1 tWP 2 WE tDW DIN tWHZ tDH tOW DOUT (August, 2002, Version 2.1) 8 AMIC Technology, Inc. LP61L1024 Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address tAW tCW5 CE1 tAS1 (4) tWR 3 CE2 (4) tCW5 tWP 2 WE tDW tDH DIN tWHZ7 DOUT Notes: 1. 2. 3. 4. tAS is measured from the address valid to the beginning of Write. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low W E . tWR is measured from the earliest of CE1 or W E going high or CE2 going low to the end of the Write cycle. If the CE1 low transition or the CE2 high transition occurs simultaneously with the W E low transition or after the W E transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE going low or CE2 going high to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. (August, 2002, Version 2.1) 9 AMIC Technology, Inc. LP61L1024 AC Test Conditions Input Pulse Levels Input Rise and Fall Time Input and Output Timing Reference Levels Output Load 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 +3.3V 320Ω I/O I/O +3.3V 320Ω 350Ω 30pF* 350Ω 5pF* * Including scope and jig. * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tCLZ1, tCLZ2, tOHZ, tOLZ, tCHZ1, tCHZ2, tWHZ, and tOW Data Retention Characteristics (TA = 0°C to 70°C) Symbol VDR1 VCC for Data Retention Parameter Min. 2 Max. 3.6 Unit V Conditions CE1 ≥ VCC - 0.2V CE2 ≥ VCC - 0.2V or CE2 ≤ 0.2V CE2 ≤ 0.2V CE1 ≥ VCC - 0.2V or CE1 ≤ 0.2V VCC = 3.0V CE1 ≥ VCC - 0.2V CE2 ≥ VCC - 0.2V VIN ≥ VCC - 0.2V or VIN ≤ 0.2V VCC = 3.0V CE2 ≤ 0.2V CE1 ≤ 0.2V VIN ≥ VCC - 0.2V or VIN ≤ 0.2V See Retention Waveform tR Operation Recovery Time 5 ms VDR2 2 3.6 V ICCDR1 Data Retention Current - 5 mA ICCDR2 - 5 mA tCDR Chip Disable to Data Retention Time 0 - ns (August, 2002, Version 2.1) 10 AMIC Technology, Inc. LP61L1024 Low VCC Data Retention Waveform (1) ( CE1 Controlled) DATA RETENTION MODE VCC 3.0V tCDR VDR ≥ 2V 3.0V tR CE1 VIH CE1 ≥ VDR - 0.2V VIH Low VCC Data Retention Waveform (2) (CE2 Controlled) DATA RETENTION MODE VCC 3.0V tCDR VDR ≥ 2V 3.0V tR CE2 VIL CE2 ≤ 0.2V VIL Ordering Information Part No. LP61L1024S-12 LP61L1024V-12 LP61L1024X-12 LP61L1024U-12 LP61L1024S-15 LP61L1024V-15 LP61L1024X-15 LP61L1024U-15 Access Time (ns) 12 12 12 12 15 15 15 15 Operating Current Max. (mA) 170 170 170 170 170 170 170 170 Standby Current Max. (mA) 10 10 10 10 10 10 10 10 Package 32L SOJ (300 mil) 32L TSOP 32L TSSOP 36L CSP 32L SOJ (300 mil) 32L TSOP 32L TSSOP 36L CSP (August, 2002, Version 2.1) 11 AMIC Technology, Inc. LP61L1024 Package Information SOJ 32/32LD (300mil BODY) Outline Dimensions D 32 17 b unit: inches/mm F F DETAIL "A" BASE METAL WITH PLATING SECTION F-F 1 16 E DETAIL "A" HE b1 A2 A s SEATING PLANE b e MIN 0.026" y y e1 0.004 y Symbol A A1 A2 b b1 c D HE E e1 e s y Dimensions in inches Min. 0128 0.052 0.095 0.016 0.026 0.006 0.820 0.330 0.295 0.260 Nom. 0.132 0.100 0.018 0.028 0.008 0.825 0.335 0.300 0.267 0.050 Max. 0.140 0.105 0.020 0.032 0.012 0.830 0.340 0.305 0.274 0.048 0.004 D A1 Dimensions in mm Min. 3.25 2.08 2.41 0.41 0.66 0.15 20.83 8.39 7.49 6.61 Nom. 3.35 2.54 0.46 0.71 0.20 20.96 8.51 7.62 6.78 1.27 Max. 3.56 2.67 0.51 0.81 0.30 21.08 8.63 7.75 6.96 1.22 0.10 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E doesn't include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (August, 2002, Version 2.1) 12 AMIC Technology, Inc. c LP61L1024 Package Information TSOP 32L TYPE I (8 X 20mm) Outline Dimensions D unit: inches/mm e A2 12.0° c A GAUGE PLANE E A1 θ 0.25 BSC L LE HD Detail "A" Detail "A" y D S b 0.10(0.004) M Symbol A A1 A2 b c D E e HD L LE S Y θ Dimensions in inches 0.047 Max. 0.004±0.002 0.039±0.002 0.008±0.001 0.006±0.001 0.724±0.004 0.315±0.004 0.020 TYP. 0.787±0.007 0.020±0.004 0.031 TYP. 0.0167 TYP. 0.004 Max. 0° ~ 6° Dimensions in mm 1.20 Max. 0.10±0.05 1.00±0.05 0.20±0.03 0.15±0.02 18.40±0.10 8.00±0.10 0.50 TYP. 20.00±0.20 0.50±0.10 0.80 TYP. 0.425 TYP. 0.10 Max. 0° ~ 6° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (August, 2002, Version 2.1) 13 AMIC Technology, Inc. LP61L1024 Package Information TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm e A2 E A1 c θ L LE Detail "A" D1 D Detail "A" D 0.076MM S SEATING PLANE b Dimensions in inches Symbol A A1 A2 b c E e D D1 L LE S θ 0° 0.520 0.461 0.012 0.0275 Min 0.002 0.037 0.007 0.0056 0.311 Nom 0.039 0.008 0.0059 0.315 0.020 TYP 0.528 0.465 0.020 0.0315 0.0109 TYP 3° 5° 0.535 0.469 0.028 0.0355 Max 0.049 0.041 0.009 0.0062 0.319 Dimensions in mm Min 0.05 0.95 0.17 0.142 7.90 Nom 1.00 0.20 0.150 8.00 0.50 TYP 13.20 11.70 0.30 0.700 0° 13.40 11.80 0.50 0.800 0.278 TYP 3° 5° 13.60 11.90 0.70 0.900 Max 1.25 1.05 0.23 0.158 8.10 Notes: 1. The maximum value of dimension D1 includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. (August, 2002, Version 2.1) 14 AMIC Technology, Inc. A LP61L1024 Package Information 36LD CSP (6 x 8 mm) Outline Dimensions TOP VIEW BOTTOM VIEW Ball#A1 CORNER 0.10 S C 0.25 S C A B Ball*A1 CORNER 123456 b (36X) 654321 unit: mm A B C D E F G H e A B C D E F G H B A 0.10 C 0.20(4X) E1 E e D1 D SIDE VIEW // 0.25 C A2 C (0.36) SEATING PLANE A1 A Symbol A A1 A2 D E D1 E1 e b Dimensions in mm MIN. 1.00 0.16 0.48 5.80 7.80 ------0.25 NOM. 1.10 0.21 0.53 6.00 8.00 3.75 5.25 0.75 0.30 MAX. 1.20 0.26 0.58 6.20 8.20 ------0.35 Note: 1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM. 4. THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. (August, 2002, Version 2.1) 15 AMIC Technology, Inc.