LP61L256BS-12

LP61L256B Series 32K X 8 Bit High SPEED LOW VCC CMOS SRAM Features n Single +3.3 volt power supply n Access times: 12 ns (max.) n Current: Operating: 100mA (max.) Standby: 10mA (max.) n Full static operation, no clock or refreshing required n n n n All inputs and outputs directly TTL compatible Common I/O using three-state output Data retention voltage: 2V (min.) Available in 28-pin SOJ and TSOP packages General Description The LP61L256B is a high-speed, low-power 262,144-bit static random access memory organized as 32,768 words by 8 bits that operates on a single 3.3V power supply. Input and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Minimum standby power is drawn by this device when CE is at a high level, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 2V. Pin Configurations n SOJ n TSOP A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 14 1 LP61L256BV A9 A11 OE A10 CE I/O8 I/O7 I/O6 I/O5 I/O4 15 LP61L256B 28 Pin No. Pin Name Pin No. Pin Name 1 OE 15 A2 2 A11 16 A1 3 A9 17 A0 4 A8 18 I/O 1 5 A13 19 I/O 2 6 WE 20 7 VCC 21 8 A14 22 I/O 4 9 A12 23 I/O 5 10 A7 24 I/O 6 11 A6 25 I/O 7 12 A5 26 I/O 8 13 A4 27 CE 14 A3 28 A10 I/O 3 GND (August, 2001, Version 1.0) 1 AMIC Technology, Inc. LP61L256B Series Block Diagram A0 A5 A7 A9 A12 ROW DECODER 256 X 1024 MEMORY ARRAY VCC GND I/O1 COLUMN I/O INPUT DATA CIRCUIT COLUMN DECODER I/O8 A1 A4 A8 A13 A14 CE OE WE CONTROL CIRCUIT Pin Descriptions -SOJ Pin No. 1 - 10, 21, 23 - 26 11 - 13, 15 - 19 14 20 22 27 Symbol A0 - A14 I/O1 - I/O8 GND CE OE WE VCC Description Address Inputs Data Inputs/Outputs Ground Chip Enable Output Enable Write Enable Pin Description - TSOP Pin No. 1 2 - 5, 8 - 17, 28 6 7 18 - 20, 22 - 26 21 27 Symbol OE A0 - A14 WE VCC I/O1 - I/O8 GND CE Description Output Enable Address Inputs Write Enable Power Supply Data Inputs/Outputs Ground Chip Enable 28 Power Supply (+3.3V) (August, 2001, Version 1.0) 2 AMIC Technology, Inc. LP61L256B Series Recommended DC Operating Conditions (TA = 0°C to + 70°C) Symbol VCC GND VIH VIL CL TTL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Output Load Output Load Min. 3.0 0 2.2 -0.3 Typ. 3.3 0 0 Max. 3.6 0 VCC + 0.3 0.8 30 1 Unit V V V V pF - Absolute Maximum Ratings* VCC to GND . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V IN, IN/OUT Volt to GND . . . . . . . . . . -0.3V to VCC +0.3V Operating Temperature, Topr . . . . . . . . . . . 0°C to +70°C Storage Temperature, Tstg . . . . . . . . . . -55°C to +125°C Power Dissipation, Pt . . . . . . . . . . . . . . . . . . . . . . . . 1.0W *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (TA = 0°C to 70°C, VCC = 3.3V ± 10%, GND = 0V) LP61L256B-12 Symbol ILI ILO ICC1 (1) ISB Standby Power Supply Current Parameter Min. Input Leakage Current Output Leakage Current Dynamic Operating Current Max. 2 2 100 20 µA µA mA mA VIN = GND to VCC CE = VIH or OE = VIH VI/O = GND to VCC CE = VIL, II/O = 0 mA CE = VIH CE ≥ VCC - 0.2V VIN ≥ VCC - 0.2V or VIN ≤ 0.2V IOL = 8 mA IOH = -4 mA Unit Conditions ISB1 - 10 mA VOL VOH Output Low Voltage Output High Voltage 2.4 0.4 - V V Notes: 1. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns. (August, 2001, Version 1.0) 3 AMIC Technology, Inc. LP61L256B Series Truth Table Mode Standby Output Disable Read Write CE H L L L OE X H L X WE X H H L I/O Operation High Z High Z DOUT DIN Supply Current ISB, ISB1 ICC1 ICC1 ICC1 Capacitance (TA = 25°C, f = 1.0 MHz) Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. 10 10 Unit pF pF Conditions VIN = 0 V VI/O = 0 V * These parameters are sampled and not 100% tested. AC Characteristics (TA = 0°C to + 70°C, VCC = 3.3V ± 10%) LP61L256B-12 Symbol Parameter Min. Read Cycle tRC tAA tACE tOE tCLZ tOLZ tCHZ tOHZ tOH Read Cycle Time Address Access Time Chip Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change 12 2 2 0 2 2 12 12 7 7 6 ns ns ns ns ns ns ns ns ns Max. Unit (August, 2001, Version 1.0) 4 AMIC Technology, Inc. LP61L256B Series AC Characteristics (continued) LP61L256B-12 Symbol Parameter Min. Write Cycle tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW Write Cycle Time Chip Enable to End of Write Address Setup Time of Write Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 12 10 0 10 8 0 0 8 0 5 7 ns ns ns ns ns ns ns ns ns ns Max. Unit Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. Timing Waveforms Read Cycle 1 (1, 2, 4) tRC Address tAA tOH tOH DOUT (August, 2001, Version 1.0) 5 AMIC Technology, Inc. LP61L256B Series Timing Waveforms (continued) Read Cycle 2 (1, 3, 4) CE tACE tCLZ 5 tCHZ 5 DOUT Read Cycle 3 (1) tRC Address tAA OE tOE tOLZ 5 CE tACE tCLZ 5 DOUT tOH tOHZ 5 tCHZ 5 Note: 1. 2. 3. 4. 5. W E is high for Read cycle. Device is continuously enabled, CE = VIL. Address valid prior to or coincident with CE transition low. OE = VIL. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested. (August, 2001, Version 1.0) 6 AMIC Technology, Inc. LP61L256B Series Timing Waveforms (continued) Write Cycle (Write Enable Controlled) tWC Address tAW tCW5 CE tAS1 (4) tWP2 (6) tWR3 WE tDW tDH DIN tWHZ 7 tOW7 DOUT Write Cycle 2 (Chip Enable Controlled) tWC Address tAW tAS1 CE (4) tCW5 tWR3 tWP2 WE tDW DIN tDH tWHZ 7 DOUT Notes: 1. 2. 3. 4. tAS is measured from address valid to the beginning of Write. A Write occurs during the overlap (tWP) of a low CE and a low W E . tWR is measured from CE or W E going high to the end of the Write cycle. If the CE low transition occurs simultaneously with the W E low transition or after the W E transition, outputs remain in a high impedance state. 5. tCW is measured from CE going low to the end of Write. 6. OE is continuously low ( OE = VIL). 7. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested. (August, 2001, Version 1.0) 7 AMIC Technology, Inc. LP61L256B Series AC Test Conditions Input Pulse Levels Input Rise and Fall Times Input and Current Timing Reference Levels Output Load 0V - 3V 3 ns 1.5V See Figures 1, 2 and 3 +3.3V 320Ω I/O I/O 350Ω 30pF* +3.3V 320Ω OUTPUT ZO=50Ω 350Ω 5pF* VT=1.5V RL=50Ω * Including scope and jig. * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW Figure 3. Output Load Data Retention Characteristics (TA = 0°C to 70°C) Symbol VDR Parameter VCC for Data Retention Min. 2.0 Max. 3.6 Unit V Conditions CE ≥ VCC - 0.2V VCC = 2V, CE ≥ VCC - 0.2V VIN ≥ VCC - 0.2V or VIN ≤ 0.2V See Retention Waveform ICCDR Data Retention Current - 0.5 mA tCDR tR Chip Disable to Data Retention Time Operation Recovery Time 0 5 - ns ms (August, 2001, Version 1.0) 8 AMIC Technology, Inc. LP61L256B Series Low VCC Data Retention Waveform DATA RETENTION MODE VCC 3.3V tCDR VDR ≥ 2V 3.3V tR CE VIH CE ≥ VDR - 0.2V VIH Ordering Information Part No. LP61L256BS-12 LP61L256BV-12 Access Time (ns) 12 12 Operating Current Max. (mA) 100 100 Standby Current Max. (mA) 10 10 Package 28L SOJ 28L TSOP (August, 2001, Version 1.0) 9 AMIC Technology, Inc. LP61L256B Series Package Information SOJ 28L Outline Dimensions unit: inches/mm 28 15 1 14 D C A2 A A1 S Seating Plane b b1 HE E e L e1 y Symbol A A1 A2 b1 b C D E e e1 HE L S y Dimensions in inches 0.140 Max. 0.027 Min. 0.100±0.005 0.028 Typ. 0.018 Typ. 0.010 Typ. 0.710 Typ. (0.730 Max.) 0.300±0.005 0.050 Typ. 0.265±0.010 0.337±0.008 0.087±0.10 0.045 Max. 0.004 Max. D Dimensions in mm 3.56 Max. 0.69 Min. 2.54±0.13 0.71 Typ. 0.46 Typ. 0.25 Typ. 18.03 Typ. (18.54 Max.) 7.62±0.13 1.27 Typ. 6.73±0.25 8.56±0.20 2.21±0.25 1.14 Max. 0.10 Max. Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (August, 2001, Version 1.0) 10 AMIC Technology, Inc. LP61L256B Series Package Information TSOP 28L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm D RD A2 12.0° c A GAUGE PLANE E A1 θ 0.25 BSC e L LE HD Detail "A" Detail "A" y D S b Symbol A A1 A2 b c D E e HD L LE S y θ Dimensions in inches 0.049 Max. 0.002 Min. 0.039±0.002 0.0079±0.0012 0.006±0.0003 0.465±0.004 0.315±0.004 0.0217 TYP. 0.528±0.008 0.02±0.008 0.0266 TYP. 0.0167 TYP. 0.004 Max. 0° ~ 6° Dimensions in mm 1.25 Max. 0.05 Min. 1.00±0.05 0.20±0.03 0.15±0.008 11.80±0.10 8.00±0.10 0.55 TYP. 13.40±0.20 0.50±0.20 0.675 TYP. 0.425 TYP. 0.10 Max. 0° ~ 6° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (August, 2001, Version 1.0) 11 AMIC Technology, Inc.