LP61L256CS-12

LP61L256C Preliminary Document Title 32K X 8 BIT HIGH SPEED CMOS SRAM Revision History Rev. No. 0.0 32K X 8 BIT HIGH SPEED CMOS SRAM History Initial issue Issue Date November 9, 2001 Remark Preliminary PRELIMINARY (November, 2001, Version 0.0) AMIC Technology, Inc. LP61L256C Preliminary Features n Single +3.3V power supply n Access times: 12/15 ns (max.) n Current: Operating: 120mA (max.) Standby: 5mA (max.) n Full static operation, no clock or refreshing required n n n n All inputs and outputs are directly TTL compatible Common I/O using three-state output Data retention voltage: 2V (min.) Available in 28-pin SOJ package 32K X 8 BIT HIGH SPEED CMOS SRAM General Description The LP61L256C is a high-speed, low-power 262,144-bit static random access memory organized as 32,768 words by 8 bits and operates on a single 3.3V power supply. It is built using high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Minimum standby power is drawn by this device when CE is at a high level, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 2V. Pin Configurations n SOJ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 28 27 26 25 24 23 22 21 20 19 18 17 16 15 LP61L256C PRELIMINARY (November, 2001, Version 0.0) 1 AMIC Technology, Inc. LP61L256C Series Block Diagram A0 A5 A6 A7 A9 A10 A11 A12 ROW DECODER 256 X 1024 MEMORY ARRAY VCC GND I/O0 COLUMN I/O INPUT DATA CIRCUIT COLUMN DECODER I/O7 A1 A2 A3 A4 A8 A13 A14 CE OE WE CONTROL CIRCUIT Pin Descriptions - SOJ Pin No. 1 - 10, 21, 23 - 26 11 - 13, 15 - 19 14 28 20 22 27 Symbol A0 - A14 I/O0 - I/O7 GND VCC CE OE WE Description Address Inputs Data Inputs/Outputs Ground Power Supply Chip Enable Output Enable Write Enable PRELIMINARY (November, 2001, Version 0.0) 2 AMIC Technology, Inc. LP61L256C Series Recommended DC Operating Conditions (TA = 0°C to + 70°C) Symbol VCC GND VIH VIL CL Parameter Supply Voltage Ground Input High Voltage Input Low (1) Voltage Output Load Min. 3.0 0 2.2 -0.5 Typ. 3.3 0 0 Max. 3.6 0 VCC + 0.3 +0.8 30 Unit V V V V pF Absolute Maximum Ratings* VCC to GND . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V IN, IN/OUT Volt to GND . . . . . . . . . . -0.5V to VCC +0.5V Operating Temperature, Topr . . . . . . . . . . . 0°C to +70°C Storage Temperature, Tstg . . . . . . . . . . -55°C to +125°C Temperature Under Bias, Tbias . . . . . . . . -10°C to +85°C Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . . 1.0W *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Symbol Parameter (TA = 0°C to + 70°C, VCC = 3.3V ± 10%, GND = 0V) LP61L256C-12/15 Min. Max. 2 2 µA µA VIN = GND to VCC CE = VIH or OE = VIH VI/O = GND to VCC CE = VIL, II/O = 0 mA Min. Cycle, Duty = 100% CE = VIH CE ≥ VCC - 0.2V VIN ≥ VCC -0.2V or VIN ≤ 0.2V IOL = 8 mA IOH = -4 mA Unit Conditions ILI ILO Input Leakage Output Leakage - ICC1 (2) ISB Dynamic Operating Current - 120 30 mA mA ISB1 Standby Power Supply Current - 5 mA VOL VOH Output Low Voltage Output High Voltage 2.4 0.4 - V V Notes: 1. VIL = -3.0V for pulses less than 20 ns. 2. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns. PRELIMINARY (November, 2001, Version 0.0) 3 AMIC Technology, Inc. LP61L256C Series Truth Table Mode Standby Output Disable Read Write Note: X = H or L CE H L L L OE X H L X WE X H H L I/O Operation High Z High Z DOUT DIN Supply Current ISB, ISB1 ICC1 ICC1 ICC1 Capacitance (TA = 25°C, f = 1.0MHz) Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. 10 10 Unit pF pF Conditions VIN = 0V VI/O = 0V * These parameters are sampled and not 100% tested. AC Characteristics (TA = 0°C to +70°C, VCC = 3.3V ± 10%) Symbol Parameter LP61L256C-12 Min. Read Cycle tRC tAA tACE tOE tCLZ tOLZ tCHZ tOHZ tOH Read Cycle Time Address Access Time Chip Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable Output in High Z Output Disable to Output in High Z Output Hold from Address Change 12 3 0 0 0 3 12 12 6 6 6 15 3 0 0 3 15 15 8 8 8 ns ns ns ns ns ns ns ns ns Max. LP61L256C-15 Min. Max. Unit PRELIMINARY (November, 2001, Version 0.0) 4 AMIC Technology, Inc. LP61L256C Series AC Characteristics (continued) Symbol Parameter LP61L256C-12 Min. Write Cycle tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW Write Cycle Time Chip Enable to End of Write Address Setup Time of Write Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 12 10 0 10 10 0 0 6 0 3 6 15 12 0 12 12 0 0 7 0 3 8 ns ns ns ns ns ns ns ns ns ns Max. LP61L256C-15 Min. Max Unit Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levles. Timing Waveforms Read Cycle 1 (1) tRC Address tAA OE tOE tOLZ5 CE tACE tCLZ5 DOUT tOH tOHZ5 tCHZ5 PRELIMINARY (November, 2001, Version 0.0) 5 AMIC Technology, Inc. LP61L256C Series Timing Waveforms (continued) Read Cycle 2 (1, 2, 4) tRC Address tAA tOH tOH DOUT Read Cycle 3 (1, 3, 4,) CE tACE tCLZ 5 tCHZ 5 DOUT Notes: 1. 2. 3. 4. 5. W E is high for Read Cycle. Device is continuously enabled, CE = VIL. Address valid prior to or coincident with CE transition low. OE = VIL. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (November, 2001, Version 0.0) 6 AMIC Technology, Inc. LP61L256C Series Timing Waveforms (continued) Write Cycle 1 (Write Enable Controlled) tWC Address tAW tCW5 CE tAS1 (4) tWP 2 (6) tWR 3 WE tDW tDH DIN tWHZ7 tOW 7 DOUT Write Cycle 2 (Chip Enable Controlled) tWC Address tAW tAS1 CE (4) tCW5 tWR 3 tWP 2 WE tDW DIN tDH tWHZ7 DOUT Notes: 1. 2. 3. 4. tAS is measured from the address valid to the beginning of Write. A Write occurs during the overlap (tWP) of a low CE and a low W E . tWR is measured from the earliest of CE or W E going high to the end of the Write cycle If the CE low transition occurs simultaneously with the W E low transition or after the W E transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE going low to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (November, 2001, Version 0.0) 7 AMIC Technology, Inc. LP61L256C Series AC Test Conditions Input Pulse Levels Input Rise and Fall Time Input and Output Timing Reference Levels Output Load 0V to 3.0V 2 ns 1.5V See Figures 1 and 2 +3.3V 317Ω I/O OUTPUT ZO=50Ω RL=50Ω VT=1.5V * Including scope and jig. 351Ω 5pF* Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW Data Retention Characteristics (TA = 0°C to 70°C) Symbol VDR Parameter VCC for Data Retention Min. 2 Max. 3.6 Unit V Conditions CE ≥ VCC - 0.2V VCC = 2.0V CE ≥ VCC - 0.2V VIN ≥ VCC - 0.2V or VIN ≤ 0.2V ICCDR Data Retention Current - 2 mA tCDR tR Chip Disable to Data Retention Time Operation Recovery Time 0 tRC* - ns See Retention Waveform ns tRC = Read Cycle Time PRELIMINARY (November, 2001, Version 0.0) 8 AMIC Technology, Inc. LP61L256C Series Low VCC Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR VDR ≥ 2.0V 3.0V tR CE VIH CE ≥ VDR - 0.2V VIH Ordering Information Part No. LP61L256CS-12 LP61L256CS-15 Access Time (ns) 12 15 Operating Current Max. (mA) 120 120 Standby Current Max. (mA) 5 5 Package 28L SOJ 28L SOJ PRELIMINARY (November, 2001, Version 0.0) 9 AMIC Technology, Inc. LP61L256C Series Package Information SOJ 28L Outline Dimensions unit: inches/mm 28 15 1 14 D C A2 A A1 S Seating Plane b b1 HE E e L e1 y Symbol A A1 A2 b1 b C D E e e1 HE L S y Dimensions in inches Min 0.027 0.095 Nom 0.100 0.028 TYP 0.018 TYP 0.010 TYP 0.295 0.255 0.329 0.077 0.710 0.300 0.050 BSC 0.265 0.337 0.087 0.275 0.345 0.097 0.045 0.004 0.730 0.305 Max 0.140 0.105 D Dimensions in mm Min 0.69 2.41 Nom 2.54 0.71 TYP 0.46 TYP 0.25 TYP 7.49 6.48 8.36 1.96 18.03 7.62 1.27 BSC 6.73 8.56 2.21 6.99 8.76 2.46 1.14 0.10 18.54 7.75 Max 3.56 2.67 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. PRELIMINARY (November, 2001, Version 0.0) 10 AMIC Technology, Inc.