LP62P16128CV-12LLT

LP62P16128C-T Series Preliminary Document Title 128K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 128K X 16 BIT LOW VOLTAGE CMOS SRAM History Initial issue Issue Date March 11, 2002 Remark Preliminary PRELIMINARY (March, 2002, Version 0.0) AMIC Technology, Inc. LP62P16128C-T Series Preliminary Features n Operating voltage: 2.3V to 2.7V n Access times: 120 ns (max.) n Current: Very low power version: Operating: 20mA (max.) Standby: 100µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 1.2V (min.) n Available in 44-pin TSOP and 48-ball CSP (6 x 8 mm) packages 128K X 16 BIT LOW VOLTAGE CMOS SRAM General Description The LP62P16128C-T is a low operating current 2,097,152-bit static random access memory organized as 131,072 words by 16 bits and operates on low power voltage from 2.3V to 2.7V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The chip enable input is provided for POWER-DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 1.2V. Pin Configurations n TSOP A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC GND I/O5 I/O6 I/O7 I/O8 WE A16 A15 A14 A13 A12 1 2 3 4 44 43 42 41 A5 A6 A7 OE HB LB I/O16 I/O15 I/O14 I/O13 GND VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC n CSP (Chip Size Package) 48-pin Top View 1 A B C D E F G H LB I/O9 I/O10 GND VCC I/O15 I/O16 NC 2 OE HB I/O11 I/O12 I/O13 I/O14 NC A8 3 A0 A3 A5 NC NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O2 I/O4 I/O5 I/O6 WE A11 6 NC I/O1 I/O3 VCC GND I/O7 I/O8 NC LP62P16128BV-T 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 PRELIMINARY (March, 2002, Version 0.0) 1 AMIC Technology, Inc. LP62P16128C-T Series Block Diagram A0 VCC GND DECODER A15 512 X 4096 MEMORY ARRAY A16 I/O1 COLUMN I/O INPUT DATA CIRCUIT I/O9 INPUT DATA CIRCUIT I/O8 I/O16 CE LB HB OE WE CONTROL CIRCUIT Pin Descriptions -- TSOP Pin No. 1 - 5, 18 – 22, 24 – 27, 42 - 44 6 7 - 10, 13 - 16, 29 - 32, 35 - 38 17 39 40 41 11, 33 12, 34 23, 28 Symbol A0 - A16 CE I/O1 - I/O16 WE LB HB OE VCC GND NC Description Address Inputs Chip Enable Input Data Inputs/Outputs Write Enable Input Lower Byte Enable Input (I/O1 to I/O8) Higher Byte Enable Input (I/O9 to I/O16) Output Enable Input Power Ground No Connection PRELIMINARY (March, 2002, Version 0.0) 2 AMIC Technology, Inc. LP62P16128C-T Series Pin Description - CSP Symbol A0 - A16 Description Address Inputs Symbol HB Description Higher Byte Enable Input (I/O9 - I/O16) Output Enable Power Supply Ground No Connection CE I/O1 - I/O16 WE LB Chip Enable Data Input/Output Write Enable Input Byte Enable Input (I/O1 - I/O8) OE VCC GND NC Recommended DC Operating Conditions (TA = -25°C to + 85°C) Symbol VCC GND VIH VIL CL TTL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Output Load Output Load Min. 2.3 0 2.0 -0.3 Typ. 2.5 0 Max. 2.7 0 VCC + 0.3 +0.4 30 1 Unit V V V V pF - PRELIMINARY (March, 2002, Version 0.0) 3 AMIC Technology, Inc. LP62P16128C-T Series Absolute Maximum Ratings* VCC to GND ...............................................-0.5V to +4.6V IN, IN/OUT Volt to GND .................... -0.5V to VCC + 0.5V Operating Temperature, Topr ....................-25°C to +85°C Storage Temperature, Tstg......................-55°C to +125°C Power Dissipation, PT ............................................... 0.7W *Comments Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (TA = -25°C to + 85°C, VCC = 2.3V to 2.7V, GND = 0V) Symbol Parameter LP62P16128C-12LLT Min. ILI ILO Input Leakage Current Output Leakage Current 1 µA Max. 1 µA VIN = GND to VCC CE = VIH or LB = HB = VIH VI/O = GND to VCC ICC Active Power Supply Current 3 mA CE = VIL , LB = VIL or HB = VIL , II/O = 0 mA Min. Cycle, Duty = 100% ICC1 Dynamic Operating Current ICC2 4 mA 20 mA CE = VIL, LB = VIL or HB = VIL, II/O = 0 mA CE ≤ 0.2V , LB ≤ 0.2V or HB ≤ 0.2V, f = 1MHz , II/O = 0 mA ISB Standby Power ISB1 Supply Current 100 µA 0.3 mA CE = VIH or LB = HB = VIH CE ≥ VCC – 0.2V or LB = HB ≥ VCC – 0.2V, VIN ≥ VCC – 0.2V or VIN ≤ 0.2V VOL VOH Output Low Voltage Output High Voltage 1.8 0.4 V V IOL = 2.1 mA IOH = -1.0 mA Unit Conditions PRELIMINARY (March, 2002, Version 0.0) 4 AMIC Technology, Inc. LP62P16128C-T Series Truth Table CE H X OE X X WE X X LB X H L L L H L H L L X L L H L L H H H H L X HB X H L H L L H L X L I/O1 to I/O8 Mode Not selected High-Z Read Read High - Z Write Write High - Z High - Z High - Z I/O9 to I/O16 Mode Not selected High-Z Read High - Z Read Write High - Z Write High - Z High - Z VCC Current ISB1, ISB ISB1, ISB ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. 6 8 Unit pF pF Conditions VIN = 0V VI/O = 0V * These parameters are sampled and not 100% tested. PRELIMINARY (March, 2002, Version 0.0) 5 AMIC Technology, Inc. LP62P16128C-T Series AC Characteristics (TA = -25°C to +85°C, VCC = 2.3V to 2.7V) Symbol Parameter LP62P16128C-12LLT Min. Read Cycle tRC tAA tACE tBE tOE tCLZ tBLZ tOLZ tCHZ tBHZ tOHZ tOH Write Cycle tWC tCW tBW tAS tAW tWP tWR tWHZ tDW tDH tOW Write Cycle Time Chip Enable to End of Write Byte Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 120 100 100 0 100 85 0 60 0 10 35 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address Access Time Chip Enable Access Time Byte Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Byte Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Byte Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change 120 10 10 5 10 120 120 120 80 45 45 45 ns ns ns ns ns ns ns ns ns ns ns ns Max. Unit Note: tBLZ, tOLZ, tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. PRELIMINARY (March, 2002, Version 0.0) 6 AMIC Technology, Inc. LP62P16128C-T Series Timing Waveforms Read Cycle 1 (1, 2, 4) tRC Address tAA tOH tOH DOUT Read Cycle 2 (1, 2, 3) tRC Address tAA CE tACE tCLZ 5 tBE tCHZ 5 HB, LB tBLZ 5 tBHZ 5 OE tOHZ 5 tOE tOLZ 5 DOUT Notes: 1. W E is high for Read Cycle. 2. Device is continuously enabled CE = VIL , HB = VIL and, or LB = VIL. 3. Address valid prior to or coincident with CE and ( HB and, or LB ) transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (March, 2002, Version 0.0) 7 AMIC Technology, Inc. LP62P16128C-T Series Timing Waveforms (continued) Write Cycle 1 (Write Enable Controlled) tWC Address tAW tCW CE tWR3 tBW HB, LB tAS1 tWP2 WE tDW DATA IN tWHZ 4 tDH tOW DATA OUT PRELIMINARY (March, 2002, Version 0.0) 8 AMIC Technology, Inc. LP62P16128C-T Series Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address tAW tAS1 CE tCW2 tWR3 tBW HB, LB tWP WE tDW DATA IN tWHZ 4 tDH tOW DATA OUT PRELIMINARY (March, 2002, Version 0.0) 9 AMIC Technology, Inc. LP62P16128C-T Series Timing Waveforms (continued) Write Cycle 3 (Byte Enable Controlled) tWC Address tAW tCW CE tWR3 tAS1 tBW2 HB, LB tWP WE tDW tDH DATA IN tWHZ 4 tOW DATA OUT Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and ( HB and , or LB ). 3. tWR is measured from the earliest of CE or W E or ( HB and , or LB ) going high to the end of the Write cycle. 4. OE level is high or low. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (March, 2002, Version 0.0) 10 AMIC Technology, Inc. LP62P16128C-T Series AC Test Conditions Input Pulse Levels Input Rise And Fall Time Input and Output Timing Reference Levels Output Load 0.4V to 2.2V 5 ns 1.1V See Figures 1 and 2 TTL TTL CL 30pF CL 5pF * Including scope and jig. * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ, tBHZ, tBLZ, tCHZ, tOHZ, tWHZ, and tOW Data Retention Characteristics (TA = -25°C to 85°C) Symbol VDR Parameter VCC for Data Retention Min. 1.2 Max. 2.7 Unit V Conditions CE ≥ VCC - 0.2V or LB = HB ≥ VCC-0.2V VCC = 1.5V, CE ≥ VCC - 0.2V or LB = HB ≥ VCC-0.2V VIN ≥ VCC - 0.2V or VIN ≤ 0.2V tCDR tR tVR Chip Disable to Data Retention Time Operation Recovery Time VCC Rising Time from Data Retention Voltage to Operating Voltage 0 tRC 5 ns ns ms See Retention Waveform ICCDR Data Retention Current - 100* µA * LP62P16128C-12LLT ICCDR: max. 1µA at TA = 0°C to + 40°C PRELIMINARY (March, 2002, Version 0.0) 11 AMIC Technology, Inc. LP62P16128C-T Series Low VCC Data Retention Waveform DATA RETENTION MODE VCC 2.0V tCDR VDR ≥ 1.2V tVR CE VIH CE ≥ VDR - 0.2V VIH 2.0V tR Ordering Information Part No. Access Time (ns) Operating Current Max. (mA) 20 120 LP62P16128CU-12LLT 20 100 48L CSP Standby Current Max. (µA) 100 Package LP62P16128CV-12LLT 44L TSOP PRELIMINARY (March, 2002, Version 0.0) 12 AMIC Technology, Inc. LP62P16128C-T Series Package Information TSOP 44L TYPE II Outline Dimensions 44 23 unit: inches/mm HE E 0.254 L L1 1 D 22 A2 A S B e y Symbol A A1 A2 B c D E e HE L L1 S y θ Dimension in inch Min. 0.002 0.037 0.010 0.721 0.396 0.455 0.016 0° Nom. 0.039 0.014 0.006 0.725 0.400 0.031 0.463 0.020 0.031 Max. 0.047 0.041 0.018 0.729 0.404 0.471 0.024 0.036 0.004 5° A1 D L L1 Dimension in mm Min. 0.05 0.95 0.25 18.31 10.06 11.56 0.40 0° Nom. 1.00 0.35 0.15 18.41 10.16 0.80 11.76 0.50 0.80 Max. 1.20 1.05 0.45 18.51 10.26 11.96 0.60 0.93 0.10 5° Notes: 1. Dimension D&E do not include interlead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Dimension S includes end flash. PRELIMINARY (March, 2002, Version 0.0) 13 AMIC Technology, Inc. c LP62P16128C-T Series 48LD CSP ( 6 x 8 mm ) Outline Dimensions (48TFBGA) TOP VIEW BOTTOM VIEW Ball#A1 CORNER 0.10 S C 0.25 S C A B Ball*A1 CORNER 123456 b (48X) 654321 unit: mm A B C D E F G H e A B C D E F G H B A 0.10 C 0.20(4X) E1 E e D1 D SIDE VIEW // 0.25 C A2 C (0.36) SEATING PLANE A1 A Symbol A A1 A2 D E D1 E1 e b Note: Dimensions in mm MIN. 1.00 0.20 --5.90 7.90 ------0.30 NOM. ----0.53 6.00 8.00 3.75 5.25 0.75 0.35 MAX. 1.20 0.30 --6.10 8.10 ------0.40 1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. 4. BALL PAD OPENING OF SUBSTRATE IS Φ 0.3mm (SMD) SUGGEST TO DESIGN THE PCB LAND SIZE AS Φ 0.3mm (NSMD) PRELIMINARY (March, 2002, Version 0.0) 14 AMIC Technology, Inc.