LP62S16512U-55LLT

LP62S16512-T Series Preliminary Document Title 512K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.2 512K X 16 BIT LOW VOLTAGE CMOS SRAM History Add Product Family and 55ns specification Issue Date March 20, 2002 Remark Preliminary PRELIMINARY (March, 2002, Version 0.2) AMIC Technology, Inc. LP62S16512-T Series Preliminary Features n Operating voltage: 2.7V to 3.6V n Access times: 55/70 ns (max.) n Current: Very low power version: Operating: 50mA (max.) Standby: 20µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 2.0V (min.) n Available in 48-ball CSP (8×10mm) packages 512K X 16 BIT LOW VOLTAGE CMOS SRAM General Description The LP62S16512-T is a low operating current 8,388,608bit static random access memory organized as 524,288 words by 16 bits and operates on low power voltage from 2.7V to 3.6V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable input is provided for POWER-DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2.0V. Product Family Product Family LP62S16512 Operating Temperature -40°C ~ +85°C VCC Range 2.7V~3.6V Power Dissipation Speed 55ns / 70ns Data Retention (ICCDR, Typ.) 0.3µA Standby (ISB1, Typ.) 0.5µA Operating (ICC2, Typ.) 4mA Package Type 48 CSP 1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested. 2. Data retention current VCC = 2.0V. Pin Configurations n CSP (Chip Size Package) 48-pin Top View 1 A B C D E F G H LB I/O9 I/O10 GND VCC I/O15 I/O16 A18 2 OE HB I/O11 I/O12 I/O13 I/O14 NC A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CS1 I/O2 I/O4 I/O5 I/O6 WE A11 6 CS2 I/O1 I/O3 VCC GND I/O7 I/O8 NC PRELIMINARY (March, 2002, Version 0.2) 1 AMIC Technology, Inc. LP62S16512-T Series Block Diagram A0 VCC GND 1024 X 8192 DECODER A17 MEMORY ARRAY A18 I/O1 COLUMN I/O INPUT DATA CIRCUIT I/O9 INPUT DATA CIRCUIT I/O8 I/O16 LB CS1 CS2 LB HB OE WE CONTROL CIRCUIT PRELIMINARY (March, 2002, Version 0.2) 2 AMIC Technology, Inc. LP62S16512-T Series Pin Description - CSP Symbol A0 - A18 Description Address Inputs Chip Enable Data Input/Output Write Enable Input Byte Enable Input (I/O1 - I/O8) Symbol Description Higher Byte Enable Input (I/O9 - I/O16) Output Enable Power Supply Ground No Connection HB OE VCC GND NC CS1 , CS2 I/O1 - I/O16 WE LB Recommended DC Operating Conditions (TA = -25°C to + 85°C) Symbol VCC GND VIH VIL CL TTL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Output Load Output Load Min. 2.7 0 2.0 -0.3 Typ. 3 0 Max. 3.6 0 VCC + 0.3 +0.6 30 1 Unit V V V V pF - PRELIMINARY (March, 2002, Version 0.2) 3 AMIC Technology, Inc. LP62S16512-T Series Absolute Maximum Ratings* VCC to GND ..............................................-0.5V to +4.0V IN, IN/OUT Volt to GND ................... -0.5V to VCC + 0.5V Operating Temperature, Topr ...................-25°C to +85°C Storage Temperature, Tstg.....................-55°C to +125°C Power Dissipation, PT ...................................................................... 0.7W *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (TA = -25°C to + 85°C, VCC = 2.7V to 3.6V, GND = 0V) Symbol Parameter LP62S16512-55/70LLT Min. ILI Input Leakage Current Max. 1 µA VIN = GND to VCC CS1 = VIH or CS2 = VIL or ILO Output Leakage Current 1 µA LB = HB = VIH VI/O = GND to VCC Active Power Supply Current CS1 = VIL , CS2 = VIH , 5 mA LB = VIL or HB = VIL , II/O = 0mA Min. Cycle, Duty = 100%, CS1 = VIL , CS2 = VIH , LB = VIL or HB = VIL Dynamic Operating Current ICC2 15 mA II/O = 0mA CS1 ≤ 0.2V, CS2 ≥ VCC-0.2V , LB ≤ 0.2V or HB ≤ 0.2V f = 1MHz , II/O = 0mA ISB Standby Current ISB1 20 µA 1 mA CS1 = VIH or CS2 = VIL or LB = HB = VIH CS1 ≥ VCC - 0.2V or CS2 ≤ 0.2V or LB = HB ≥ VCC-0.2V VIN ≥ VCC-0.2V or VIN ≤ 0.2V VOL VOH Output Low Voltage Output High Voltage 2.2 0.4 V V IOL = 2.1 mA IOH = -1.0 mA Unit Conditions ICC ICC1 - 50 mA PRELIMINARY (March, 2002, Version 0.2) 4 AMIC Technology, Inc. LP62S16512-T Series Truth Table CS1 H X X CS2 X L X OE X X X WE X X X LB X X H L L H L H L H L L H X L L H L L H H H H H H L X HB X X H L H L L H L X L I/O1 to I/O8 Mode High - Z High - Z High - Z Read Read High - Z Write Write High - Z High - Z High - Z I/O9 to I/O16 Mode High - Z High - Z High - Z Read High - Z Read Write High - Z Write High - Z High - Z VCC Current ISB1, ISB ISB1, ISB ISB1, ISB ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. 6 8 Unit pF pF Conditions VIN = 0V VI/O = 0V * These parameters are sampled and not 100% tested. PRELIMINARY (March, 2002, Version 0.2) 5 AMIC Technology, Inc. LP62S16512-T Series AC Characteristics (TA = -25°C to +85°C, VCC = 2.7V to 3.6V) Symbol Parameter LP62S16512-55LLT Min. Read Cycle tRC tAA tAcs1 , tAcs2 tBE tOE tCLZ1 , tCLZ2 tBLZ tOLZ tCHZ1 , tCHZ2 tBHZ tOHZ tOH Write Cycle tWC tCW1 , tCW2 tBW tAS tAW tWP tWR tWHZ tDW tDH tOW Write Cycle Time Chip Enable to End of Write Byte Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 55 50 50 0 50 40 0 25 0 5 25 70 60 60 0 60 50 0 30 0 5 25 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address Access Time Chip Enable Access Time Byte Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Byte Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Byte Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change 55 10 10 5 5 55 55 55 25 20 20 20 70 10 10 5 5 70 70 70 35 25 25 25 ns ns ns ns ns ns ns ns ns ns ns ns Max. LP62S16512-70LLT Min. Max. Unit Note: tCLZ1 , tCLZ2 , tBLZ , tOLZ , tCHZ1, tCHZ2 , tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. PRELIMINARY (March, 2002, Version 0.2) 6 AMIC Technology, Inc. LP62S16512-T Series Timing Waveforms Read Cycle 1 (1, 2, 4) tRC Address tAA tOH tOH DOUT Read Cycle 2 (1, 2, 3) tRC Address tAA CS1 CS2 tACS1 , tACS2 tCLZ1 , tCLZ2 tBE tCHZ1 , tCHZ2 HB, LB tBLZ 5 tBHZ 5 OE tOHZ 5 tOE tOLZ 5 DOUT Notes: 1. W E is high for Read Cycle. 2. Device is continuously enabled CS1 = VIL, or CS2 = VIH , HB = VIL and, or LB = VIL. 3. Address valid prior to or coincident with CS1 and ( HB and, or LB ) transition low or CS2 transition High. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (March, 2002, Version 0.2) 7 AMIC Technology, Inc. LP62S16512-T Series Timing Waveforms (continued) Write Cycle 1 (Write Enable Controlled) tWC Address tAW tCW CS1 tWR3 CS2 tBW HB, LB tAS1 tWP2 WE tDW DATA IN tWHZ 4 tDH tOW DATA OUT PRELIMINARY (March, 2002, Version 0.2) 8 AMIC Technology, Inc. LP62S16512-T Series Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address tAW tAS1 CS1 tCW1 , tCW 2 tWR3 CS2 tBW HB, LB tWP WE tDW DATA IN tWHZ 4 tDH tOW DATA OUT PRELIMINARY (March, 2002, Version 0.2) 9 AMIC Technology, Inc. LP62S16512-T Series Timing Waveforms (continued) Write Cycle 3 (Byte Enable Controlled) tWC Address tAW tCW1 , tCW2 CS1 tWR3 tAS1 tBW2 CS2 HB, LB tWP WE tDW tDH DATA IN tWHZ 4 tOW DATA OUT Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (tWP, tBW) of a low CS1 , WE and ( HB and , or LB ) or a high CS2. 3. tWR is measured from the earliest of CS1 or W E or ( HB and , or LB ) going high or CS2 going Low to the end of the Write cycle. 4. OE level is high or low. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (March, 2002, Version 0.2) 10 AMIC Technology, Inc. LP62S16512-T Series AC Test Conditions Input Pulse Levels Input Rise And Fall Time Input and Output Timing Reference Levels Output Load 0.4V to 2.4V 5 ns 1.5V See Figures 1 and 2 TTL TTL CL 30pF CL 5pF * Including scope and jig. * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tCLZ1, tCLZ2 , tBHZ , tBLZ , tOLZ, tCHZ1, tCHZ2 , tOHZ, tWHZ, and tOW Data Retention Characteristics (TA = -25°C to 85°C) Symbol Parameter Min. Max. Unit Conditions CS1 ≥ VCC - 0.2V or CS2 ≤ 0.2V or LB = HB ≥ VCC-0.2V VCC = 2.0V, ICCDR Data Retention Current 6* µA CS1 ≥ VCC - 0.2V or CS2 ≤ 0.2V or LB = HB ≥ VCC-0.2V VIN ≥ VCC-0.2V or VIN ≤ 0.2V VDR VCC for Data Retention 2.0 3.6 V tCDR tR tVR Chip Disable to Data Retention Time Operation Recovery Time VCC Rising Time from Data Retention Voltage to Operating Voltage ICCDR: max. 0 tRC 5 - ns ns ms See Retention Waveform * LP62S16512-55/70LLT 1µA at TA = 25°C (3µA at TA = 0°C to + 40°C ) PRELIMINARY (March, 2002, Version 0.2) 11 AMIC Technology, Inc. LP62S16512-T Series Low VCC Data Retention Waveform (1) ( CS1 Controlled) DATA RETENTION MODE VCC 2.7V tCDR VDR ≥ 2.0V tVR CS1 VIH CS1 ≥ VDR - 0.2V VIH 2.7V tR Low VCC Data Retention Waveform (2) (CS2 Controlled) DATA RETENTION MODE VCC 2.7V tCDR VDR ≥ 2.0V tVR CS2 2.7V tR VIL CS2 ≤ 0.2V VIL Ordering Information Part No. LP62S16512U-55LLT LP62S16512U-70LLT Access Time(ns) 55 70 Operating Current Max.(mA) 50 50 Standby Current Max.(uA) 20 20 Package 48L CSP 48L CSP PRELIMINARY (March, 2002, Version 0.2) 12 AMIC Technology, Inc. LP62S16512-T Series Package Information 48LD CSP ( 8 x 10 mm ) Outline Dimensions (48TFBGA) TOP VIEW 0.10 0.25 Ball #A1 CORNER 123456 S S unit: mm BOTTOM VIEW C CAB Ball#A1 CORNER b (48X) 654321 A B C D E F G H A B C D E F G H B SIDE VIEW // 0.25 C 0.10 C A 0.20(4X) E1 E e e D1 D A2 (0.36) C SEATING PLANE A1 A Symbol A A1 A2 D E D1 E1 e b Notes: Dimensions in mm MIN. 1.04 0.20 0.48 7.90 9.90 ------0.30 NOM. 1.14 0.25 0.53 8.00 10.00 3.75 5.25 0.75 0.35 MAX. 1.24 0.30 0.58 8.10 10.10 ------0.40 1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM. 4. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. 5. BALL PAD OPENING OF SUBSTRATE IS Φ 0.3mm (SMD) SUGGEST TO DESIGN THE PCB LAND SIZE AS Φ 0.3mm (NSMD) PRELIMINARY (March, 2002, Version 0.2) 13 AMIC Technology, Inc.