LP62S1664CV-55LLT

LP62S1664C Series Preliminary Document Title 64K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 64K X 16 BIT LOW VOLTAGE CMOS SRAM History Initial issue Issue Date February 19, 2002 Remark Preliminary PRELIMINARY (February, 2002, Version 0.0) AMIC Technology, Inc. LP62S1664C Series Preliminary Features n Operating voltage: 2.7V to 3.6V n Access times: 55/70 ns (max.) n Current: LP62S1664C-55 series: Operating: 50mA (max.) Standby: 5µA (max.) LP62S1664C-70 series: Operating: 40mA (max.) Standby: 5µA (max.) n Extended operating temperature range : -40°C to 85°C for -LLI series n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 2V (min.) n Available in 44-pin TSOP and 48-ball Mini BGA (6X8) packages. 64K X 16 BIT LOW VOLTAGE CMOS SRAM General Description The LP62S1664C is a low operating current 1,048,576bit static random access memory organized as 65,536 words by 16 bits and operates on low power supply voltage from 2.7V to 3.6V. It is built using AMIC’s high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The chip enable input is provided for POWER-DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V. Product Family Product Family LP62S1664C Operating Temperature -40°C ~ +85°C VCC Range 2.7V~3.6V Power Dissipation Speed 55ns / 70ns Data Retention (ICCDR, Typ.) 0.2µA Standby (ISB1, Typ.) 0.3µA Operating (ICC2, Typ.) 3mA Package Type 44L TSOP 48B MBGA 1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested. 2. Data retention current VCC = 2.0V. Pin Configuration n TSOP (Type II) A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE HB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC n Mini BGA (6X8) Top View 1 A B C D E F G H LB I/O8 I/O9 VSS VCC I/O14 I/O15 NC 2 OE 3 A0 A3 A5 NC NC A14 A12 A9 4 A1 A4 A6 A7 NC A15 A13 A10 5 A2 6 NC I/O0 I/O2 VCC VSS I/O6 I/O7 NC HB I/O10 I/O11 I/O12 I/O13 NC A8 CS I/O1 I/O3 I/O4 I/O5 WE A11 LP62S1664CV LP62S1664CU PRELIMINARY (February, 2002, Version 0.0) 1 AMIC Technology, Inc. LP62S1664C Series Block Diagram A0 VCC GND 512 X 2048 DECODER A14 MEMORY ARRAY A15 I/O0 COLUMN I/O INPUT DATA CIRCUIT I/O8 INPUT DATA CIRCUIT I/O7 I/O15 CE LB HB OE WE CONTROL CIRCUIT PRELIMINARY (February, 2002, Version 0.0) 2 AMIC Technology, Inc. LP62S1664C Series Pin Description - TSOP Pin No. 1 - 5, 18 - 21, 24 - 27,42 - 44 6 7 - 10, 13 - 16, 29 - 32, 35 - 38 17 39 40 41 11, 33 12, 34 22 , 23, 28 Symbol A0 - A15 CE I/O0 - I/O15 WE LB HB OE VCC GND NC Description Address Inputs Chip Enable Input Data Input/Outputs Write Enable Input Byte Enable Input (I/O0 to I/O7) Byte Enable Input (I/O8 to I/O15) Output Enable Input Power Ground No Connection Recommended DC Operating Conditions (TA = -25°C to + 85°C for –LLT or -40°C to 85°C for -LLI) Symbol VCC GND VIH VIL CL TTL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Output Load Output Load Min. 2.7 0 2.2 -0.3 Typ. 3.0 0 Max. 3.6 0 VCC + 0.3 +0.6 30 1 Unit V V V V pF - PRELIMINARY (February, 2002, Version 0.0) 3 AMIC Technology, Inc. LP62S1664C Series Absolute Maximum Ratings* VCC to GND . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V IN, IN/OUT Volt to GND . . . . . . . . -0.5V to VCC + 0.5V Operating Temperature, Topr . . . . . . . . -40°C to +85°C Storage Temperature, Tstg . . . . . . . . . -55°C to +125°C Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . 0.7W Soldering Temp. & Time . . . . . . . . . . . . 260°C, 10 sec *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (TA = -25°C to + 85°C for -LLT or -40°C to + 85°C for -LLI, VCC = 2.7V to 3.6V, GND = 0V) Symbol Parameter LP62S1664C-55LLT/LLI Min. ILI Input Leakage Current Output Leakage Current Max. 1 LP62S1664C-70LLT/LLI Min. Max. 1 µA VIN = GND to VCC CE = VIH or OE = VIH or LB = HB = VIH or W E = VIL VI/O = GND to VCC CE = VIL, II/O = 0mA Min. Cycle, Duty = 100% CE = VIL, II/O = 0mA CE = VIL, VIH = VCC, VIL = 0V, f = 1MHz, II/O = 0 mA CE = VIH CE ≥ VCC - 0.2V VIN ≥ 0V IOL = 2.1mA IOH = -1.0mA Unit Conditions ILO - 1 - 1 µA ICC ICC1 Active Power Supply Current - 5 - 5 mA ICC2 Dynamic Operating Current - 50 - 40 mA - 5 - 5 mA ISB ISB1 Standby Power Supply Current Output Low Voltage Output High Voltage - 0.3 5 - 0.3 5 mA µA V V VOL VOH 2.2 0.4 - 2.2 0.4 - PRELIMINARY (February, 2002, Version 0.0) 4 AMIC Technology, Inc. LP62S1664C Series Truth Table CE H OE X WE X LB X L L L H L H L L X L L H L L H H X X X X H L H High - Z Not selected High - Z Not selected ICC1, ICC2, ICC ISB1, ISB HB X L H L L H L X I/O0 to I/O7 Mode Not selected Read Read High - Z Write Write Not Write/Hi - Z High - Z I/O8 to I/O15 Mode Not selected Read High - Z Read Write Not Write/Hi - Z Write High - Z VCC Current ISB1, ISB ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. 6 8 Unit pF pF Conditions VIN = 0V VI/O = 0V * These parameters are sampled and not 100% tested. PRELIMINARY (February, 2002, Version 0.0) 5 AMIC Technology, Inc. LP62S1664C Series AC Characteristics (TA = -25°C to +85°C for -LLT or -40°C to +85°C for -LLI, VCC = 2.7V to 3.6V) Symbol Parameter LP62S1664C-55LLT/LLI Min. Read Cycle tRC tAA tACE tBE tOE tCLZ tBLZ tOLZ tCHZ tBHZ tOHZ tOH Write Cycle tWC tCW tBW tAS tAW tWP tWR tWHZ tDW tDH tOW Write Cycle Time Chip Enable to End of Write Byte Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 55 50 50 0 50 40 0 25 0 5 25 70 60 60 0 60 50 0 30 0 5 30 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address Access Time Chip Enable Access Time Byte Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Byte Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Byte Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change 55 10 5 5 5 55 55 55 30 20 20 20 70 10 5 5 10 70 70 70 35 25 25 25 ns ns ns ns ns ns ns ns ns ns ns ns Max. LP62S1664C-70LLT/LLI Min. Max. Unit Note: tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. PRELIMINARY (February, 2002, Version 0.0) 6 AMIC Technology, Inc. LP62S1664C Series Timing Waveforms Read Cycle 1 (1, 2, 4) tRC Address tAA tOH tOH DOUT Read Cycle 2 (1, 2, 3) tRC Address tAA CE tACE tCLZ 5 tBE tCHZ 5 HB, LB tBLZ 5 tBHZ 5 OE tOHZ 5 tOE tOLZ 5 DOUT Notes: 1. W E is high for Read Cycle. 2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL. 3. Address valid prior to or coincident with CE and ( HB and, or LB ) transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (February, 2002, Version 0.0) 7 AMIC Technology, Inc. LP62S1664C Series Timing Waveforms (continued) Write Cycle 1 (Write Enable Controlled) tWC Address tAW tCW CE tWR3 tBW HB, LB tAS1 tWP2 WE tDW DATA IN tWHZ 4 tDH tOW DATA OUT PRELIMINARY (February, 2002, Version 0.0) 8 AMIC Technology, Inc. LP62S1664C Series Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address tAW tAS1 CE tCW2 tWR3 tBW HB, LB tWP WE tDW DATA IN tWHZ 4 tDH tOW DATA OUT PRELIMINARY (February, 2002, Version 0.0) 9 AMIC Technology, Inc. LP62S1664C Series Timing Waveforms (continued) Write Cycle 3 (Byte Enable Controlled) tWC Address tAW tCW CE tWR3 tAS1 tBW2 HB, LB tWP WE tDW tDH DATA IN tWHZ 4 tOW DATA OUT Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and ( HB and, or LB ). 3. tWR is measured from the earliest of CE or W E or ( HB and, or LB ) going high to the end of the Write cycle. 4. OE level is high or low. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (February, 2002, Version 0.0) 10 AMIC Technology, Inc. LP62S1664C Series AC Test Conditions Input Pulse Levels Input Rise And Fall Time Input and Output Timing Reference Levels Output Load 0V to 2.4V 5 ns 1.5V See Figures 1 and 2 TTL TTL CL 30pF CL 5pF * Including scope and jig. * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW Data Retention Characteristics (TA = -25°C to 85°C for –LLT or -40°C to 85°C for -LLI) Symbol VDR Parameter VCC for Data Retention Min. 2.0 Max. 3.6 Unit V Conditions CE ≥ VCC - 0.2V VCC = 2.0V, CE ≥ VCC - 0.2V VIN ≥ 0V ICCDR Data Retention Current - 3* µA tCDR tR tVR Chip Disable to Data Retention Time Operation Recovery Time VCC Rise Time from Data Retention Voltage to Operating Voltage ICCDR: max. 0 tRC 5 - ns ns ms See Retention Waveform * LP62S1664C-55/70(LLT/LLI) 1µA at TA = 0°C to + 40°C PRELIMINARY (February, 2002, Version 0.0) 11 AMIC Technology, Inc. LP62S1664C Series Low VCC Data Retention Waveform DATA RETENTION MODE VCC 2.7V tCDR VDR ≥ 2V tVR CE VIH CE ≥ VDR - 0.2V VIH 2.7V tR Ordering Information Part No. LP62S1664CV-55LLT LP62S1664CV-55LLI 55 LP62S1664CU-55LLT LP62S1664CU-55LLI LP62S1664CV-70LLT LP62S1664CV-70LLI 70 LP62S1664CU-70LLT LP62S1664CU-70LLI LLT : for -25°C ~ 85°C LLI : for -40°C ~ 85°C 40 5 48B Mini BGA 48B Mini BGA 50 5 48B Mini BGA 48B Mini BGA 44L TSOP 44L TSOP Access Time (ns) Operating Current Max. (mA) Standby Current Max. (µA) Package 44L TSOP 44L TSOP PRELIMINARY (February, 2002, Version 0.0) 12 AMIC Technology, Inc. LP62S1664C Series Package Information TSOP 44L (Type II) Outline Dimensions unit: inches/mm 44 E1 E θ L L1 1 D A2 b ZD Dimensions in inches D e A y A1 L L1 Dimensions in mm Min 0.05 0.95 0.30 0.12 18.28 11.56 10.03 0.49 Nom 1.00 18.41 0.805 REF 11.76 10.16 0.59 0.80 REF 0.80 BSC Max 1.20 0.15 1.05 0.45 0.21 18.54 11.96 10.29 0.69 Symbol A A1 A2 b c D ZD E E1 L L1 e y θ Min 0.002 0.037 0.012 0.005 0.720 0.455 0.395 0.019 Nom 0.039 0.725 0.032 REF 0.463 0.400 0.023 0.031 REF 0.031 BSC Max 0.047 0.006 0.041 0.018 0.008 0.730 0.471 0.405 0.027 0° - 0.004 5° 0° - 0.10 5° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension ZD includes end flash. PRELIMINARY (February, 2002, Version 0.0) 13 AMIC Technology, Inc. c LP62S1664C Series Package Information Mini BGA 6X8 (48 BALLS) Outline Dimensions unit : millimeter(mm) Bottom View Pin A1 Index 654 321 Pin A1 Index Top View C1 E F G H A A B1 Diameter D Solder Ball B D Symbol A B B1 C C1 D E E1 E2 Min 5.90 7.90 0.30 1.00 - Typ 0.75 6.00 3.75 8.00 5.25 0.35 1.10 0.36 0.25 Max 6.10 8.10 0.40 1.20 - PRELIMINARY (February, 2002, Version 0.0) 14 AMIC Technology, Inc. C E2 E A B C D 0.10 E1