LP62S2048X-70LLT

LP62S2048-T Series 256K X 8 BIT LOW VOLTAGE CMOS SRAM Features n Power supply range: 2.7V to 3.3V n Access times: 70/100 ns (max.) n Current: Low power version: Operating: 30mA (max.) Standby: 50µA (max.) Very low power version: Operating: 30mA (max.) Standby: 10µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2V (min.) n Available in 32-pin SOP, TSOP, TSSOP (8 X 13.4mm) and 36-pin CSP packages General Description The LP62S2048-T is a low operating current 2,097,152bit static random access memory organized as 262,144 words by 8 bits and operates on a low power supply range: 2.7V to 3.3V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V. Pin Configurations n SOP n TSOP/(TSSOP) n CSP (Chip Size Package) 36-pin Top View A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 32 31 30 29 28 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 17 32 H A9 A10 A11 A12 A13 A14 1 2 A1 A2 3 CE2 WE NC 4 A3 A4 A5 5 A6 A7 6 A8 I/O1 I/O2 VCC GND NC OE CE1 A17 A16 A15 I/O3 I/O4 16 1 LP62S2048V-T (LP62S2048X-T) 6 7 8 9 10 11 12 13 14 15 16 27 26 25 24 23 22 21 20 19 18 17 A B C D E F G A0 I/O5 I/O6 GND VCC I/O7 I/O8 (August, 2001, Version 1.0) LP62S2048M-T Pin No. Pin Name Pin No. Pin Name 1 A11 17 A3 2 A9 18 A2 3 A8 19 A1 4 A13 20 A0 5 WE 21 I/O1 6 CE2 22 I/O2 7 A15 23 I/O3 8 VCC 24 GND 9 A17 25 I/O4 10 A16 26 I/O5 11 A14 27 I/O6 12 A12 28 I/O7 13 A7 29 I/O8 14 A6 30 CE1 15 A5 31 A10 16 A4 32 OE 1 AMIC Technology, Inc. LP62S2048-T Series Block Diagram A0 VCC GND A15 A16 A17 ROW DECODER 1024 X 2048 MEMORY ARRAY I/O1 INPUT DATA CIRCUIT COLUMN I/O I/O8 CE2 CE1 OE WE CONTROL CIRCUIT Pin Description - SOP Pin No. 1 - 12, 23, 25 - 28, 31 13 - 15, 17 - 21 16 22 24 29 30 32 Symbol Description Pin Descriptions - TSOP/TSSOP Pin No. 1 - 4, 7, 9 - 20, 31 5 Symbol A0 - A17 WE CE2 VCC NC I/O1 - I/O8 GND CE1 OE Description Address Inputs Write Enable Chip Enable Power Supply No Connection Data Input/Outputs Ground Chip Enable Output Enable A0 - A17 Address Inputs I/O1 - I/O8 GND CE1 OE WE CE2 VCC Data Input/Outputs 6 Ground 8 Chip Enable Output Enable Write Enable Chip Enable Power Supply 9 21 - 23, 25 - 29 24 30 32 (August, 2001, Version 1.0) 2 AMIC Technology, Inc. LP62S2048-T Series Pin Description - CSP Symbol A0 - A17 WE OE CE1 CE2 Description Address Inputs Write Enable Output Enable Chip Enable Chip Enable Symbol NC I/O1 - I/O8 VCC GND -Description No Connection Data Input/Output Power Supply Ground -- Recommended DC Operating Conditions (TA = -25°C to + 85°C) Symbol VCC GND VIH VIL CL TTL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Output Load Output Load Min. 2.7 0 2.0 -0.3 Typ. 3.0 0 Max. 3.3 0 VCC + 0.3 +0.6 30 1 Unit V V V V pF - (August, 2001, Version 1.0) 3 AMIC Technology, Inc. LP62S2048-T Series Absolute Maximum Ratings* VCC to GND . . . . . . . . . . . . . . . . . . . . -0.5V to + 4.6V IN, IN/OUT Volt to GND . . . . . . . . . -0.5V to VCC + 0.5V Operating Temperature, Topr . . . . . . . . -25°C to + 85°C Storage Temperature, Tstg . . . . .. . . . . -55°C to + 125°C Temperature Under Bias, Tbias . . . . . . -10°C to + 85°C Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . 0.7W Soldering Temp. & Time . . . . . . . . . . . . . 260°C, 10 sec *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Symbol Parameter (TA = -25°C to + 85°C, VCC = 2.7V to 3.3V, GND = 0V) LP62S2048-70LLT/10LLT Min. Max. 1 µA VIN = GND to VCC CE1 = VIH or CE2 = VIL or OE = VIH or W E = VIL VI/O = GND to VCC CE1 = VIL, CE2 = VIH II/O = 0mA Min. Cycle, Duty = 100% CE1 = VIL, CE2 = VIH II/O = 0mA CE1 = VIL, CE2 = VIH VIH = VCC, VIL = 0V f = 1 MHZ, II/O = 0mA Unit Conditions LP62S2048-70LT/10LT Min. Max. 1 ILI Input Leakage Current - ILO Output Leakage Current Active Power Supply Current - 1 - 1 µA ICC - 3 - 3 mA ICC1 Dynamic Operating Current - 30 - 30 mA ICC2 - 5 - 5 mA (August, 2001, Version 1.0) 4 AMIC Technology, Inc. LP62S2048-T Series DC Electrical Characteristics (continued) Symbol Parameter LP62S2048-70LT/10LT Min. ISB Max. 0.5 LP62S2048-70LLT/10LLT Min. Max. 0.5 mA CE1 = VIH or CE2 =VIL CE1 ≥ VCC - 0.2V VIN ≥ 0V CE2 ≤ 0.2V VIN ≥ 0V IOL = 2.1mA Unit Conditions ISB1 Standby Power Supply Current - 50 - 10 µA ISB2 Output Low Voltage Output High Voltage - 50 - 10 µA VOL - 0.4 - 0.4 V VOH 2.2 - 2.2 - V IOH = -1.0mA Truth Table Mode Standby CE1 H X Output Disable Read Write Note: X = H or L L L L CE2 X L H H H OE X X H L X WE X X H H L I/O Operation High Z High Z High Z DOUT DIN Supply Current ISB, ISB1 ISB, ISB2 ICC, ICC1, ICC2 ICC, ICC1, ICC2 ICC, ICC1, ICC2 Capacitance (TA = 25°C, f = 1.0MHz) Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. 6 8 Unit pF pF Conditions VIN = 0V VI/O = 0V * These parameters are sampled and not 100% tested. (August, 2001, Version 1.0) 5 AMIC Technology, Inc. LP62S2048-T Series AC Characteristics Symbol (TA = -25°C to + 85°C, VCC = 2.7V to 3.3V) Parameter LP62S2048-70LT/LLT Min. Read Cycle tRC tAA tACE1 tACE2 tOE tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tOHZ tOH Write Cycle tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 70 60 0 60 50 0 0 30 0 5 25 100 80 0 80 60 0 0 40 0 5 35 ns ns ns ns ns ns ns ns ns ns Output Disable to Output in High Z Output Hold from Address Change Output Enable to Output in Low Z Chip Disable to Output in High Z CE1 CE2 Output Enable to Output Valid Chip Enable to Output in Low Z CE1 CE2 Read Cycle Time Address Access Time Chip Enable Access Time CE1 CE2 70 10 10 5 0 0 0 10 70 70 70 35 25 25 25 100 10 10 5 0 0 0 10 100 100 100 50 35 35 35 ns ns ns ns ns ns ns ns ns ns ns ns Max. LP62S2048-10LT/LLT Min. Max. Unit Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. (August, 2001, Version 1.0) 6 AMIC Technology, Inc. LP62S2048-T Series Timing Waveforms Read Cycle 1 (1, 2, 4) tRC Address tAA tOH tOH DOUT Read Cycle 2 (1, 3, 4, 6) CE1 tACE1 tCLZ15 tCHZ15 DOUT Read Cycle 3 (1, 4, 7, 8) CE2 tACE2 tCLZ25 tCHZ25 DOUT (August, 2001, Version 1.0) 7 AMIC Technology, Inc. LP62S2048-T Series Timing Waveforms (continued) Read Cycle 4 (1) tRC Address tAA OE tOE tOLZ5 tOH CE1 tACE1 tCLZ15 CE2 tACE2 tCLZ25 DOUT tCHZ25 tOHZ 5 tCHZ15 Notes: 1. 2. 3. 4. 5. 6. 7. 8. W E is high for Read Cycle. Device is continuously enabled CE1 = VIL and CE2 = VIH. Address valid prior to or coincident with CE1 transition low. OE = VIL. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. CE2 is high. CE1 is low. Address valid prior to or coincident with CE2 transition high. (August, 2001, Version 1.0) 8 AMIC Technology, Inc. LP62S2048-T Series Timing Waveforms (continued) Write Cycle 1 (Write Enable Controlled) (6) tWC Address tAW tCW CE1 (4) 5 tWR3 CE2 (4) tAS1 tWP2 WE tDW tDH DIN tWHZ tOW DOUT (August, 2001, Version 1.0) 9 AMIC Technology, Inc. LP62S2048-T Series Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address tAW tCW5 CE1 tAS1 (4) tWR3 CE2 (4) tCW5 tWP2 WE tDW DIN tDH tWHZ7 DOUT Notes: 1. 2. 3. 4. tAS is measured from the address valid to the beginning of Write. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low W E . tWR is measured from the earliest of CE1 or W E going high or CE2 going low to the end of the Write cycle. If the CE1 low transition or the CE2 high transition occurs simultaneously with the W E low transition or after the W E transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. (August, 2001, Version 1.0) 10 AMIC Technology, Inc. LP62S2048-T Series AC Test Conditions Input Pulse Levels Input Rise and Fall Time Input and Output Timing Reference Levels Output Load 0.4V to 2.4V 5 ns 1.5V See Figures 1 and 2 TTL TTL CL 30pF CL 5pF * Including scope and jig. * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tCLZ1, tCLZ2, tOHZ, tOLZ, tCHZ1, tCHZ2, tWHZ, and tOW Data Retention Characteristics (TA = -25°C to 85°C) Symbol VDR1 VDR2 ICCDR1 VCC for Data Retention L-Version LL-Version L-Version LL-Version tCDR tR tVR Chip Disable to Data Retention Time Operation Recovery Time VCC Rising Time from Data Retention Voltage to Operating Voltage ICCDR: max. ICCDR: max. Parameter Min. 2.0 2.0 0 tRC 5 Max. 3.3 3.3 20* 5** 20* 5** ns ns ms See Retention Waveform Unit V V Conditions CE1 ≥ VCC - 0.2V CE2 ≤ 0.2V, VCC = 2.0V, CE1 ≥ VCC - 0.2V, VIN ≥ 0V µA Data Retention Current ICCDR2 µA VCC = 2.0V, CE2 ≤ 0.2V, VIN ≥ 0V ** LP62S2048-70LLT/10LLT * LP62S2048-70LT/10LT 1µA at TA = 0°C to + 40°C 5µA at TA = 0°C to + 40°C (August, 2001, Version 1.0) 11 AMIC Technology, Inc. LP62S2048-T Series Low VCC Data Retention Waveform (1) ( CE1 Controlled) DATA RETENTION MODE VCC 2.7V tCDR VDR ≥ 2V tVR CE1 VIH CE1 ≥ VDR - 0.2V VIH 2.7V tR Low VCC Data Retention Waveform (2) (CE2 Controlled) DATA RETENTION MODE VCC 2.7V tCDR VDR ≥ 2V tVR CE2 2.7V tR VIL CE2 ≤ 0.2V VIL (August, 2001, Version 1.0) 12 AMIC Technology, Inc. LP62S2048-T Series Ordering Information Part No. Access Time (ns) Operating Current Max. (mA) 30 30 30 70 30 30 30 30 30 30 30 30 100 30 30 30 30 30 Standby Current Max. (µA) 50 10 50 10 50 10 50 10 50 10 50 10 50 10 50 10 Package LP62S2048M-70LT LP62S2048M-70LLT LP62S2048V-70LT LP62S2048V-70LLT LP62S2048X-70LT LP62S2048X-70LLT LP62S2048U-70LT LP62S2048U-70LLT LP62S2048M-10LT LP62S2048M-10LLT LP62S2048V-10LT LP62S2048V-10LLT LP62S2048X-10LT LP62S2048X-10LLT LP62S2048U-10LT LP62S2048U-10LLT 32L SOP 32L SOP 32L TSOP 32L TSOP 32L TSSOP 32L TSSOP 36L CSP 36L CSP 32L SOP 32L SOP 32L TSOP 32L TSOP 32L TSSOP 32L TSSOP 36L CSP 36L CSP (August, 2001, Version 1.0) 13 AMIC Technology, Inc. LP62S2048-T Series Package Information SOP (W.B.) 32L Outline Dimensions 32 17 e1 ~ ~ unit: inches/mm HE E L 1 b 16 Detail F e1 c A2 A D s Seating Plane y D e A1 LE See Detail F Symbol A A1 A2 b c D E e e1 HE L LE S y θ Dimensions in inches 0.118 Max. 0.004 Min. 0.106±0.005 0.016 +0.004 -0.002 0.008 +0.004 -0.002 0.805 Typ. (0.820 Max.) 0.445±0.010 0.050 ±0.006 0.525 NOM. 0.556±0.010 0.031±0.008 0.055±0.008 0.044 Max. 0.004 Max. 0° ~ 10° Dimensions in mm 3.00 Max. 0.10 Min. 2.69±0.13 0.41 +0.10 -0.05 0.20 +0.10 -0.05 20.45 Typ. (20.83 Max.) 11.30±0.25 1.27±0.15 13.34 NOM. 14.12±0.25 0.79±0.20 1.40±0.20 1.12 Max. 0.10 Max. 0° ~ 10° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (August, 2001, Version 1.0) 14 AMIC Technology, Inc. LP62S2048-T Series Package Information TSOP 32L TYPE I (8 X 20mm) Outline Dimensions D unit: inches/mm e A2 12.0° c A GAUGE PLANE E A1 θ 0.25 BSC L LE HD Detail "A" Detail "A" y D S b 0.10(0.004) M Symbol A A1 A2 b c D E e HD L LE S Y θ Dimensions in inches 0.047 Max. 0.004±0.002 0.039±0.002 0.008±0.001 0.006±0.001 0.724±0.004 0.315±0.004 0.020 TYP. 0.787±0.007 0.020±0.004 0.031 TYP. 0.0167 TYP. 0.004 Max. 0° ~ 6° Dimensions in mm 1.20 Max. 0.10±0.05 1.00±0.05 0.20±0.03 0.15±0.02 18.40±0.10 8.00±0.10 0.50 TYP. 20.00±0.20 0.50±0.10 0.80 TYP. 0.425 TYP. 0.10 Max. 0° ~ 6° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (August, 2001, Version 1.0) 15 AMIC Technology, Inc. LP62S2048-T Series Package Information TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm e 12.0° A2 E c A GAUGE PLANE A1 θ 0.25 BSC L LE D1 D Detail "A" Detail "A" D 0.10MM S SEATING PLANE b Symbol A A1 A2 b c E e D D1 L LE S y θ Dimensions in inches 0.049 Max. 0.002 Min. 0.039±0.002 0.008±0.001 0.006±0.0003 0.315±0.004 0.020 TYP. 0.528±0.008 0.465±0.004 0.02±0.008 0.0266 Min. 0.0109 TYP. 0.004 Max. 0° ~ 6° Dimensions in mm 1.25 Max. 0.05 Min. 1.00±0.05 0.20±0.03 0.15±0.008 8.00±0.10 0.50 TYP. 13.40±0.20 11.80±0.10 0.50±0.20 0.675 Min. 0.278 TYP. 0.10 Max. 0° ~ 6° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (August, 2001, Version 1.0) 16 AMIC Technology, Inc. LP62S2048-T Series Package Information 36LD CSP (6 x 8 mm) Outline Dimensions TOP VIEW BOTTOM VIEW Ball#A1 CORNER 0.10 S C 0.25 S C A B Ball*A1 CORNER 123456 b (36X) 654321 unit: mm A B C D E F G H e A B C D E F G H B A 0.10 C 0.20(4X) E1 E e D1 D SIDE VIEW // 0.25 C A2 C (0.36) SEATING PLANE A1 A Symbol A A1 A2 D E D1 E1 e b Dimensions in mm MIN. 1.00 0.16 0.48 5.80 7.80 ------0.25 NOM. 1.10 0.21 0.53 6.00 8.00 3.75 5.25 0.75 0.30 MAX. 1.20 0.26 0.58 6.20 8.20 ------0.35 Note: 1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM. THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. 4. BALL PAD OPENING OF SUBSTRATE IS Φ 0.25mm (SMD) SUGGEST TO DESIGN THE PCB LAND SIZE AS Φ 0.25mm (NSMD) (August, 2001, Version 1.0) 17 AMIC Technology, Inc.