A3525AC21O20R

AS3525-A/-B C22O22 Data Sheet, Confidential å Datasheet, Confidential AS3525 Advanced Audio Processor System 1 Description 2 2.1 Key Features Digital Core This highly flexible and fully integrated audio processor system (AS3525) combines strong calculating power, high performance audio features with system power management options for battery powered devices. Using advanced 0.13µm process technology and large on chip RAM leads to outstanding low power consumption of as low as 58mW for a complete flash-player during MP3 playback. Based on a powerful ARM9TDMI capable of performing up to 200MIPS it is suited to run MP3, AAC, WMA, OGG… decoders and encoders and, in addition, it can perform extensive user interfaces, motion graphics support, video playback and much more. The AS3525 SOC (system-on-a-Chip) features dedicated high speed interfaces for ATA IDE, USB2.0 HS-OTG and SDRAM ensuring maximum performance for download, upload, and playback. Furthermore interfaces for NAND flashes, MMC/SD cards and Memory Stick ensure most flexible system design possibilities. Hardware support for parallel interfaces lower the CPU load serving complex and/or colour user interfaces. Additional serial high-speed data and control interfaces guarantee the connection to other peripherals and or processors in the system. Two independently programmable PLLs generate the required frequencies for audio playback/recording, for the processor core and for the USB interface at the same time. An additional external clock input eliminates the use of external crystals when used in multi-processor systems like mobile phones. It has a variety of audio inputs and outputs to directly connect electret microphones, and auxiliary signal sources via a 10-channel mixer to a 16Ω/32Ω headset , 4Ω speaker or auxiliary audio peripherals. Further the device offers advanced power management functions. All necessary ICs and peripherals in a Digital Audio Player with flash or hard-disk memory are supplied by the AS3525. The different regulated supply voltages are fully programmable. The power management block generates 10 different supply voltages out of a single battery supply. CPU, NAND flash, SRAM, memory cards, LCD, LCD backlight and USB-OTG can be powered. When operating from a single cell (AA or AAA) battery the AS3525 can use a DCDC booster to generate the needed system supply. The AS3525 has an independent 32kHz real time clock (RTC) on chip, which allows a complete power down of the system CPU and peripherals. AS3525 also contains a charger for Li-Io battery supply The single supply voltage may vary from 1.0V to 5.5V. Embedded 32-Bit RISC Controller • A RM922TDMI RISC CPU • 2 .5Mbit on-chip RAM • 1 Mbit on chip ROM • C lock speed max. 250MHz (200MIPS) • S tandard JTAG interface USB 2.0 HS & OTG Interface • U p to 480Mbit/s transfer speed • U SB 2.0 HS/FS physical inlcuding OTG support • U SB 2.0 HS/FS digital core including OTG host • D edicated dual port buffer RAM • D MA bus master functionality IDE Host Controller • S upporting Ultra ATA 33/66/100/133 modes • P rogrammable IO and Multi-word DMA capability • D edicated dual port buffer RAM • D MA bus master functionality External Memory Controller • D ynamic memory interface • A synchronous static memory • D MA bus master functionality DMA Controller • S ingle Master DMA controller • 2 D MA channels possible at the same time • 1 6 DMA requests supported Interrupt Controller • S upport for 32 standard interrupts • S upport for 16 vectored IRQ interrupts Audio Subsystem Interface • D edicated 2 wire serial control master • I 2S input and output with dual port buffer RAM Nand Flash Interface • 8 a nd 16bit flash support • 3 , 4 & 5 byte address support • h ardware ECC MMC/SD Interface • • M MC/SD Card host for multiple card support 4 d ata line support for SD cards © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 1 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 2.3 MS / MS Pro Interface • D edicated dual port buffer RAM Display Interface • S erial and parallel controller supported • O n chip hardware acceleration Synchronous Serial Interface • M aster and slave operation • 8 a nd 16 bit support • S everal protocol standards supported I2S Interface • I nput multiplexed with audio subsystem • s electable SPDIF input conversion • D edicated dual port buffer RAM 2 Wire Serial Control Interface • M aster and slave operation • S tandard and fast mode support General Purpose IO Interface • 4 x 8-bit ports Power Management Voltage Generation • s tep up for system supply (3.0V-3.6V, 150mA) • c harge-pump for CPUcore (1.05V-1.2V, 50mA) • c harge pump for USB OTG (5V, 10mA) • L DO for digital supply (2.9V, 200mA) • L DO for analog supply (2.9V, 200mA) • L DO for IO supply (2.94 or 3.11V, 200mA) • L DO for peripherals (1.7V-3.3V, 200mA) • L DO for USB Transceiver (3.26V, 200mA) • L DO for RTC (1.0V-2.5V, 2mA) 15V Back-light step up converter • f or driving up to 6 white LEDs in series to achieve a uniform illumination • c urrent programmable up to 40mA (1.25mA steps) Li-Io Battery Charger • • • a utomatic 50mA trickle charging p rog. constant current charging (50 – 400mA) p rog. constant voltage charging (3.9 - 4.25V) 2.4 RTC System 2.2 Audio Multi-bit Sigma Delta Converters • D AC: 18bit with 94dB SNR (‘A’ weighted) • A DC: 14bit with 82dB SNR (‘A’ weighted) • S ampling Frequency: 8-48kHz • 3 2 gain steps @ 1.5dB and MUTE 2 Line Inputs • s tereo, 2x mono or mono differential inputs • 3 2 gain steps @ 1.5dB and MUTE 2 Microphone Inputs • d ifferential inputs • 3 g ain pre-sets (28/34/40 dB) and OFF with AGC • 3 2 gain steps @ 1.5dB and MUTE • m icrophone detection with about 50uA • s upply for electret microphone max 1mA • r emote control by switch Line Output • m ax 1Vp @ 10k Ω i n single ended stereo mode • > 32 Ω i n mono differential mode to drive ear-pieces • 3 2 gain steps @ 1.5dB and MUTE Stereo Headphone Audio Amplifier • 2 x 60mW @ 16 Ω d river capacity • 3 2 gain steps @ 1.5dB and MUTE • C lick- and pop-less start-up and power down • H eadphone and over-current detection • P hantom ground eliminates large capacitors Stereo Speaker Audio Amplifier • 2 x 500mW @ 4 Ω d river capacity • 3 2 gain steps @ 1.5dB and MUTE • C lick- and pop-less start-up and power down • O ver-current detection 10 Channel Audio Mixer • • • m ixes Line inputs, Mic inputs and DAC output s eparate selectable source for right and left channel p ossibility to select AGC to prevent clipping • u ltra low power 32kHz oscillator • 3 2bit RTC second counter • s electable alarm (seconds or minutes) • t rim able oscillator Oscillator • l ow power 12-24MHz Oscillator • g enerating main system clock Supervisor • a utomatic battery monitoring with interrupt generation and selectable warning level • a utomatic temperature supervision with interrupt generation and selectable warning and shutdown levels General Purpose ADC • 1 0bit resolution • 1 6 inputs analog multiplexer UID • U nique Identification Number in OTP ROM for DRM support General • R eset pin, watchdog • 1 0sec emergency shut-down • W ide battery supply range 1V – 5.5V • M P3 playback with 58mW Packages: • • A S3525-A: CTBGA224 13x13mm, 0.8mm pitch A S3525-B: CTBGA144 10x10mm, 0.8mm pitch 3 • • • • Application P ortable Digital Audio Player and Recorder P ortable Digital Media Player P DA S martphone © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 2 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 4 Figure 1 Block Diagram AS3525 Block Diagram © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 3 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table of Contents 1 2 2.1 2.2 2.3 2.4 DESCRIPTION KEY FEATURES Digital Core Audio Power Management System 1 1 1 2 2 2 3 4 5 5.1 5.2 APPLICATION BLOCK DIAGRAM TYPICAL APPLICATIONS Flash-Player Hard-Disk-Player 2 3 9 9 10 6 6.1 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings 11 11 12 12 12 13 14 14 15 6.2 Operating Conditions 6.2.1 Supply Voltages 6.2.2 Internal Supply Voltages 6.2.3 Power Management Output Voltages 6.2.4 Operating Currents 6.2.5 Temperature Range 6.2.6 Audio Specification 7 DETAILED FUNCTIONAL DESCRIPTIONS 17 17 17 18 19 19 21 22 24 24 25 25 27 29 7.1 ARM922-T Processor Core 7.1.1 General 7.1.2 Block Diagrams 7.1.3 ARM922T Details 7.1.4 ARM V4T Architecture 7.1.5 JTAG Interface 7.1.6 Boot Concept 7.2 AHB Peripheral Blocks 7.2.1 2.5 MBIT RAM Main Memory 7.2.2 On-Chip ROM 7.2.3 VIC – Vectored Interrupt Controller 7.2.4 SMDMAC - Single master DMAC 7.2.5 Multi Port Memory Controller (MPMC) © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 4 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.2.6 7.2.7 7.2.8 IDE Interface USB 2.0 HS OTG interface Memory Stick / Memory Stick Pro Interface 30 33 38 40 40 44 47 49 56 57 58 59 65 66 72 83 93 100 114 119 119 121 123 126 129 131 134 138 141 143 147 148 150 151 152 154 156 157 162 164 167 168 7.3 APB Peripheral Block 7.3.1 Timers 7.3.2 Watchdog Unit 7.3.3 SSP – Synchronous Serial Port 7.3.4 GPIO - General purpose input/output ports 7.3.5 MCI – SD / MMC Card Interface 7.3.6 I2cAudMas - I2C audio master interface 7.3.7 I2CMSI - I2C master/slave interface 7.3.8 I2SIN - I2S input interface 7.3.9 SPDIF interface 7.3.10 I2SOUT - I2S output interface 7.3.11 NAND Flash Interface 7.3.12 DBOP - Data Block Output Port 7.3.13 UART – Universal Asynchronous Receiver/Transmitter 7.3.14 CGU - Clock generation unit 7.3.15 CCU - Chip Control Unit 7.4 Audio and Power Management functions 7.4.1 SYSTEM 7.4.2 3V Step-Up Converter 7.4.3 Low Drop Out Regulators 7.4.4 Charge-Pump Step-Down Converter 7.4.5 Audio Line Output 7.4.6 Headphone Output 7.4.7 Speaker Output 7.4.8 Microphone Inputs (2x) 7.4.9 Audio Line Inputs (2x) 7.4.10 I2S Digital Audio Interface 7.4.11 Audio Output Mixer 7.4.12 Audio Settings 7.4.13 VBUS CP & Comparator 7.4.14 Auxiliary Oscillator 7.4.15 Charger 7.4.16 15V Step-Up Converter 7.4.17 Supervisor 7.4.18 Interrupt Generation 7.4.19 Real Time Clock 7.4.20 10-Bit ADC 7.4.21 128 bit OTP ROM 7.4.22 2-Wire-Serial Control Interface 8 8.1 PINOUT AND PACKAGING Package Variants 172 172 172 172 173 173 182 182 183 8.2 CTBGA224 Package Drawings 8.2.1 Marking 8.2.2 CTBGA224 Package Ball-out 8.2.3 CTBGA224 Ball List 8.3 CTBGA144 Package Drawings 8.3.1 CTBGA144 Package Ball-out 8.3.2 CTBGA144 Ball List © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 5 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 8.4 Pad Cell Description 8.4.1 Digital Pads 189 189 9 9.1 APPENDIX Memory MAP 190 190 191 192 9.2 Register definitions 9.2.1 Base Address definitions 10 11 12 13 ORDERING INFORMATION COPYRIGHT DISCLAIMER CONTACT INFORMATION 193 194 194 194 © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 6 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Document Revisions Revision 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .6 0 .7 0 .7 0 .7 0 .8 0 .8 0 .8 Chapter all 4,6.6 7.6, 7.7 6.2 6.4.14 6.2, 7.4 7.7 6.7 – 6.28 5.1.2. 6.15 7.4, 7.7 5 5.0, 5.1 Date 9.12.2004 Owner mma first preliminary version Description 19.12.2004 mma 28.1.2005 7.3.2005 24.3.2005 1.4.2005 1.4.2005 2.5.2005 2.5.2005 5.5.2005 21.6.2005 28.7.2005 5.8.2005 mma mma mma mma mma mma mma mma mma mma wsg application figures, register base address CTBGA144 ball-out added changes in boot-concept CGU frequency settings updated correct IntBootSel Package Code and Marking added Parameters updated Supply Currents added Audio Specification added tmsel PAD-type is pull down Lead temperature corrected for lead-free package Added conditions for absolute max rating of vdd_peri, vdd_mem, vdd_core, usb_vdda_33t, usb_vdda_33c. Changed operating condition for vdd_core max limit. added pad cell description correct pin list pad types (JTAG_trst_n, jtag_tdi, mpmc_fbclkin, naf_bsy_n, ide_ha[0..2], ide_reset_n, id_dig) Added Note on VDD_CORE supply voltage scaling Major revision added description for modified C22 bootloader added UART description corrected NAFmode register description added C22O22 version in order information corrected header in table “CGU frequency settings” updated ESD and soldering conditions, change ADC_10 source for C22O22 from BVDD to CHG_OUT update of PINOUT for AS3525A: test pins at K2, K4 and L2 are only used during production test and must stay unconnected for normal operation mode. Pins are now marked with NC. Added Note for AS3525B package that CVDD and vdd_core have to be connected externally! added application circuit with schottky diodes for speaker output protection. deleted description of C21O20 bootloader (this chip version is not available any more) Added definition of Power Management Output Voltages 0 .82 0 .82 0 .83 1 .00 1 .1 7.8 7 5.1.1 all 6.10.2005 pkm 13.10.2005 pkm 22.10.2005 wsg wsg/pkm 25.9.2006 1 6.2.2007 wsg wsg 2 2.3.2007 1 .11 17.4.2007 pkm wsg 1 .12 7.4.7.2 7 .1.6 6.7.2007 6.7.2007 24.2.2009 wsg wsg wsg 1 .13 6.2.3 © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 7 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Related Documents ARM922T Technical Reference Manual ARM9TDMI Technical Reference Manual PrimeCell™ MultiPort Memory Controller; PL172 Technical Reference Manual AMBA Specification (Rev 2.0) PrimeCell™ Synchronous Serial Port; PL022 Technical Reference Manual PrimeCell™ General Purpose Input/Output; PL061 Technical Reference Manual PrimeCell™ Single Master DMA Controller; PL081 Technical Reference Manual PrimeCell™ Multimedia Card Interface; PL180 Technical Reference Manual PrimeCell™ Vectored Interrupt Controller; PL190 Technical Reference Manual CWda03 - SPDIF-AES/EBU TO I2S CONVERTER TSMC TPZ013G3 Standard I/O Library Databook DesignWare USB 2.0 HI-SPEED ON-THE-GO Controller Subsystem DesignWare USB 2 PHY Hardmacro SMS2IP mem stick host controller ICON mem stick host con interface IDE host controller BK3710S IHI0011A_AMBA_SPEC.pdf DDI0184B_922T_TRM.pdf DDI0180A_9tdmi_trm.pdf http://www.arm.com http://www.arm.com http://www.arm.com http://www.arm.com http://www.arm.com http://www.arm.com http://www.arm.com http://www.arm.com http://www.arm.com http://www.coreworks.pt http://www.tsmc.com http://www.synopsys.com http://www.synopsys.com http://www.sony.com http://www.sony.com http://www.palmchip.com © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 8 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 5 Typical Applications AS3525 is an advanced audio system-on-a-chip for flash-players, hard-disk players, mobile phones and PDAs powered by single Li+, AA or AAA batteries. AS3525-A is the package variant with 224 balls intended for full-featured harddisk players, AS3524-B is the package variant with 144 balls for flash players with reduced feature set and no need for an external SDRAM. Two versions are available for the chips: C22O22 which is the newest version with additional boot loader features, and C21O20 which is outdated and must not be used for new design starts. 5.1 Flash-Player The following schematic shows a typical flash-player application of the AS3525-B in the CTBGA144 package. A single AAA or AA battery powers the complete system. The on-chip DC/DC converter generates a supply voltage of 3.25V (BVDD) with a maximum output load current of 150mA. Linear regulators, which are connected to this BVDD, provide the supply voltages for the analog functions, the USB-2.0-Phy, the digital periphery and external components. A highly efficient Charge-Pump Step-Down-Converter supplies the digital core. All analog features are available in this package variant. Also, the digital interfaces to NAND-flash, MMC/SD card, Memory-Stick-Pro, USB-2.0 HS&OTG, Synchronous Serial Interface, General Purpose IOs and different displays are provided. Figure 2 Flash Player Application © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 9 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 5.2 Hard-Disk-Player The following schematic shows a typical hard-disk-player application of the AS3525-A using the CTBGA224 package. A single Li+ battery powers the complete system. The Li+ cell can be charged either from a DC-supply or the USB connector. Linear regulators, which are connected to this battery voltage (BVDD), provide the supply voltages for the analog functions, the USB-2.0-Phy, the digital periphery and the SDRAM interface. A highly efficient Charge-Pump Step-Down-Converter supplies the digital core. All chip functions are available in this package variant. For lowest power consumption, it is recommended to use low voltage external SDRAMs (PVDD=1.8V). Figure 3 Hard Disk Player © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 10 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 6 6.1 Electrical Specifications Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings“ may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The device should be operated under recommended operating conditions. Table 1 Absolute Maximum Ratings Parameter d igital supply pins Min -0.5 Max 3.7 Unit V Note Applicable for pins vdd_peri, vdd_mem, usb_vdda33t1, usb_vdda33t2, usb_vdda33t3, usb_vdda33c Applicable for pins vdd_core Applicable for pin VBAT_1V Applicable for pins BVDD, CHG_IN, VBUS Applicable for pins SW15 Applicable for pins VSS3,VSS15, VSSCP, BVSS, BVSS2, AVSS, DVSS, vss_core, vss_peri, vss_mem, usb_vssa33t, usb_vssa33c A pplicabel for pins MCLK, LRCK, SCLK, SDI, P_PVDD, BATTEMP, ISINK, XIN_32K, XOUT_32K, XIN_24M, XOUT_24M, INTRQ, XRES, CP_1V, CN_1V, CN_5V Applicable for pins CSCL, CSDA, PWR_UP, CP_5V A pplicable for pins BGND, HPH_CM, HPGD, LOUTL/R, VREF, AGND, LIN1L/R, LIN2L/R, MIC1_P/N, MIC2_P/N, MSUP1, MSUP2 A pplicable for pins AVDD, QLDO2, DVDD, PVDD, CPVDD, CVDD, UVDD A pplicable for pins RVDD A pplicable for pins LSPR/L, HPR/L, CHG_OUT, SW3 Norm: JEDEC 17 Norm: JEDEC JESD22-A114C (1) Norm: JEDEC JESD22-A114C (Pins: usb_dp, usb_dm, usb_vbus) V alid for CTBGA144 package Symbol V IN_SUP V IN_CORE V IN_VB1V V IN_5V V IN_SW15 V IN_VSS d igital core supply pins s ingle cell supply voltage 5 V pins 1 5V pin V oltage difference at VSS terminals -0.5 -0.5 -0.5 -0.5 -0.5 1.68 5.0 7.0 17 0.5 V V V V V V IN_DVDD 3 .3V pins with diode to DVDD -0.5 5.0 DVDD+0.5 V V IN_xDVDD V IN_AVDD p ins with no diode to DVDD 3 .3V pins with diode to AVDD -0.5 -0.5 7.0V 5.0 AVDD+0.5 V V V IN_REG V IN_RVDD V IN_BVDD I scr E SD E SD_USB Pt H (1) v oltage regulator pins with diodes to BVDD v oltage regulator pin with diode to BVDD p ins with diode to BVDD I nput Current (latchup immunity) Electrostatic Discharge HBM Electrostatic Discharge HBM for USB Pins T otal Power Dissipation (all supplies and outputs) H umidity non-condensing -0.5 -0.5 -0.5 -100 5.0 BVDD+0.5 3.6 BVDD+0.5 7.0 BVDD+0.5 100 +/-1 +/-2 1000 V V V mA kV kV mW % 5 85 Electrostatic discharge of XIN24 and XOUT24 pin is +/-600V for C21O20 © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 11 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 2 Soldering Conditions Parameter P ackage Body Temperature 2 35 S older Profile* 30 Min Max 260 245 45 Unit °C °C s above 217 °C Note Norm IPC/JEDEC J-STD-020C, reflects moisture sensitivity level only Symbol T body T peak D well * austriamicrosystems AG strongly recommends to use underfill. 6.2 Table 3 Operating Conditions Operating conditions for supply input voltages Parameter DCDC Supply Voltage Battery Supply Voltage USB VBUS Voltage Charger Supply Voltage D ifference of Negative Supplies VSS3, VSS1, VSS15, BVSS, BVSS2, AVSS, DVSS, VSSCP Min 1.0 3.2 4.0 4.5 -0.1 Max 3.6 5.5 5.5 5.5 0.1 Unit V V V V V To achieve good performance, the negative supply terminals should be connected to low impedance ground plane. Note 6.2.1 Supply Voltages Symbol V B1V B VDD V BUS C HGIN 6.2.2 Internal Supply Voltages Following supply voltages for the digital system are generated by the integrated power management Table 4 Operating conditions for internal internal supply voltages Parameter Min 3 .0 1 .7 1 .08 3 .15 3 .15 Digital Supply Voltage Analogue Supply Voltage D ifference of Negative Supplies vss_peri, vss_core, vss_mem, usb_vssa33c, usb_vssa33t N ote(s) 2.8 2.8 -0.1 Max 3.6 3.6 1.26 3.45 3.45 3.6 3.6 0.1 Unit V V V V V V V V Note digital periphery supply voltage to be connected to IOVDD digital IO supply for MPMC PADs to be connected to PVDD digital core supply voltage to be connected to CVDD; s ee Note (1) USB analog supply transmit block to be connected to UVDD USB analog supply common block to be connected to UVDD Digital Audio Supply Voltage (LDO2) Analog Audio Supply Voltage (LDO1) To achieve good performance, the negative supply terminals should be connected to low impedance ground plane. Symbol V DD peri V DD mem V DD core U SBVDDA33 T U SBVDDA33 C D VDD A VDD (1) For the VDD_CORE supply, voltage scaling should be applied to optimize power consumption and CPU speed performance. For normal operation with fclk (CPU ARM-922T clock) frequencies below 200 MHz, CVDD (supply of VDD_CORE) can be set to a lower value of 1.10 V. Only for setting fclk of the CPU to clock frequencies above 200 MHz, the VDD_CORE supply voltage must be set to 1.20 V typical conditions. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 12 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 6.2.3 Power Management Output Voltages Following voltages are generated by the integrated power management blocks. Table 5 Power Management – Output Voltages Symbol CVDD Regulator Parameter Condition min. typ. max. Unit bits CVDDp[1:0]=00 bits CVDDp[1:0]=01 CVDDP Core Supply Voltage bits CVDDp[1:0]=10 see Note (1) bits CVDDp[1:0]=11 see Note (1) Low Dropout Regulators AVDD DVDD Output Voltage LDO1 Output Voltage LDO2 bit PVDDp=0 bit PVDDp=1 bit PVDDp=0 PVDDP Output Voltage LDO3 bit PVDDp=1 bit PVDDp=0 bit PVDDp=1 bit PVDDp=0 bit PVDDp=1 IOVDD Output Voltage LDO4 bit IOVDDp=0 bit IOVDDp=1 1.16 1.10 1.06 1.01 1.20 1.15 1.10 1.05 1.24 1.30 1.14 1.09 V V V V 2.85 2.85 1.65 1.75 2.69 2.84 3.10 3.27 2.45 2.30 3.06 2.89 2.90 2.90 1.70 1.80 2.74 2.90 3.15 3.30 2.50 2.36 3.11 2.94 2.95 2.95 1.75 1.85 2.80 2.96 3.20 3.39 2.55 2.42 3.16 2.99 V V V V V V V V V V V V 3V Step-Up Converter bits DCDC3p=11 BVDD Output Voltage of DCDC Step Up Converter bits DCDC3p=10 bits DCDC3p=01 bits DCDC3p=00 Notes: (1) This setting must not be used for AS3525 core supply because the lower voltage limit is out of core supply specification limits. 1.95 3.05 3.15 3.55 3.00 3.10 3.20 3.60 3.05 3.15 3.25 3.65 V V V V © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 13 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 6.2.4 Operating Currents Table 6 Supply currents Parameter Total current consumption at BVDD Peripheral current External memory interface current Digital core current Typ 22 2 20 Max 340 20 20 145 30 30 2 8 40 15 Unit mA (1), (2), (3) mA mA mA mA mA mA mA (3) (1), (3) (2) (1), (2), (3) Note Symbol I _BVDD I DD_PERI_OP I DD_MEM_OP I DD_CORE_OP I DD_USBA33T_OP USB transmitter current I DD_USBA33C_OP USB common blocks current I _Headphone I _Audio Headphone current from BVDD Analog audio frontend current from DVDD (2.9V) and AVDD (2.9V) N otes (1) Typical condition for playback of MP3 music with 44.1 KHz / 128 kbit with 32 Ω h eadphones. The internal charge pump generates VDD_CORE. No external SDRAM connected. USB2.0 in standby. (2) Maximum condition for ARM running at 250 MHz, AHB/APB bus and memory at 64 MHz, USB 2.0 in HS operation. For high current mode, the charge pump is disabled and IDD_CORE_OP is added to the total current consumption at BVDD. (3) For maximum value: assuming maximum output power of 2x40 mW sine-wave into headphones (16 Ω ). Internal loss of headphone AB amplifier is included. In the case of standby mode or in the case of configuring the device to stopped clock, following current consumption is measured. Table 7 Leakage currents Parameter Typ Max 1500 500 1000 Unit μA μA μA Note Including USBA33T, USBA33C Symbol I DD_PERI_LEAK I DD_MEM_LEAK I DD_CORE_LEAK 6.2.5 Temperature Range Table 8 Temperature Range Parameter O perating temperature range J unction temperature range T hermal Resistance Min 0 0 29 Typ 25 Max 85 110 Unit °C °C °C/W F or CTBGA144 package Note Symbol T op Tj R th © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 14 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 6.2.6 Audio Specification Table 9 Audio Parameters Parameter Notes 1kHz FS input A-weighted, no load, silence input A-weighted, no load, -60dB FS 1kHz input 1kHz FS input 1kHz 1V RMS ( FS) input A-weighted, no load, silence input 1kHz 1V RMS ( FS) input Min Typ 0.985 92 89 -90 0.95 93 -85 89 0 .950 0 .944 94 90 -90 -73 -66 73 66 0.930 0.936 96 95 - 86 -75 -69 70 62 1.708 1.690 1.524 94 -86 70 -60 Max Unit V RMS dB dB dB V RMS dB dB dB V RMS V RMS dB dB dB dB dB dB dB V RMS V RMS dB dB dB dB dB dB dB V RMS V RMS V RMS dB dB dB Symbol DAC Input to Line Output FS Full Scale Output S NR Signal to Noise Ratio DR Dynamic Range T HD Total Harmonic Distortion L ine Input to Line Output FS Full Scale Output S NR Signal to Noise Ratio T HD Total Harmonic Distortion CS Channel Separation D AC Input to HP Output FS Full Scale Output S NR DR T HD Signal to Noise Ratio Dynamic Range Total Harmonic Distortion R L = 32 Ω R L = 16 Ω A-weighted, no load, silence input A-weighted, no load, -60dB FS 1kHz input no load, 1kHz FS input P out=20mW, R L = 32 Ω , f=1kHz FS input P out=40mW, R L = 16 Ω , f=1kHz FS input RL = 32Ω RL = 16Ω R L = 32 Ω , 1kHz 1V RMS (FS) i nput R L = 16 Ω , 1kHz 1V RMS ( FS) input A-weighted, no load, silence input A-weighted, no load, -60dB FS 1kHz (FS) input no load, 1kHz 1V RMS input P out=20mW, R=32 Ω , 1kHz 1V RMS ( FS) input P out=40mW, R=16 Ω , 1kHz 1V RMS ( FS) input RL = 32Ω RL = 16Ω R L = 32 Ω , 1kHz 1V RMS ( FS) input R L = 16 Ω , 1kHz 1V RMS ( FS) input R L = 4 Ω , 1kHz 1V RMS ( FS) input A-weighted, no load, silence input no load, 1kHz 1V RMS ( FS) input RL = 32Ω CS Channel Separation L ine Input to HP Output FS Full Scale Output S NR DR T HD Signal to Noise Ratio Dynamic Range Total Harmonic Distortion CS Channel Separation L ine Input to SP Output FS Full Scale Output S NR T HD CS Signal to Noise Ratio Total Harmonic Distortion Channel Separation © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 15 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Symbol Parameter Notes A-weighted, no load, silence input A-weighted, no load, -60dB FS 1kHz input 1kHz 53mV RMS ( FS) input A-weighted, no load, silence input A-weighted, no load, -60dB FS 1kHz input 1kHz, 1V RMS , -3dB FS input Min Typ 74 73 -61 83 82 -62 Max Unit dB dB dB dB dB dB MIC Input to ADC Output S NR Signal to Noise Ratio DR Dynamic Range T HD Total Harmonic Distortion L ine Input to ADC Output S NR Signal to Noise Ratio DR Dynamic Range T HD Total Harmonic Distortion BVDD = 3.3V, TA= 25oC, fs=48kHz, RL= 10kΩ unless otherwise mentioned © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 16 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7 Detailed Functional Descriptions This chapter contains detailed functional descriptions of all modules of the chip. Central microcontroller is an ARM-9, all peripherals are connected to the AMBA bus which is divided into a AHB (advanced high speed bus) and APB (advanced peripheral bus) part. All audio, power management and system monitoring functions are controlled via an I2C interface (I2C audio master). This chapter includes also all detailed desciptions and performance values for these parts. 7.1 ARM922-T Processor Core 7.1.1 General The ARM922T macrocell is a high-performance 32-bit RISC integer processor combining an ARM9TDMI™ processor core with: • • • • 8KB instruction cache and 8 KB data cache Instruction and data Memory Management Unit (MMU) Write buffer with 16 data words and 4 addresses Advanced Microprocessor Bus Architecture (AMBA™) AHB interface The ARM922T provides a high-performance processor solution for open systems requiring full virtual memory management and sophisticated memory protection. The ARM922T processor core is capable of running at 250 MHz. The ARM922T hard macrocell has a very low power consumption. The integrated cache helps to significantly reduce memory bandwith demands, improving performance and minimizing power consumption. At 250 MHz the ARM922T comsumes as little as 65 mW, making it ideal for high-performance battery operated audio or video applications. The ARM core and associated bus structures are configured for little endian byte order (compatible with Windows CE™ and Symbian™ OS). Table 10 ARM 922T characteristics C ache (I/D) 8 KB / 8KB M MU yes A HB yes T humb yes m W/MHz 0.25 @ 1.2 V M Hz 250 Features • • • • • • • • • 3 2-bit RISC architecture (ARMv4T) H arvard architecture with separated instruction (I) and data (D) caches with 8 KB each and 8-word line length F ive stage pipeline (fetch, decode, execute, memory, write back) enabling high master clock speeds 3 2-bit ARM instruction set for maximum performance and flexibility 1 6-bit Thumb instruction set for increased code density E nhanced ARM architecture V4 MMU to provide translation and access permission checks for instruction and data addresses. With this MMU different operating systems (Windows CE, Symbian …) can be implemented. I ndustry standard AMBA bus interface (AHB and APB) H ard-macro implementation T he processor core clock frequency (FCLK) is programmable up to 250MHz and the ARM922 power consumption is directly proportional to this clock frequency FCLK © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 17 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.1.2 Block Diagrams Figure 4 ARM 922T Functional Block Diagram Figure 5 ARM9TDMI Functional Block Diagram © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 18 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.1.3 ARM922T Details The ARM922T macrocell is based on the ARM9TDMI Harvard architecture processor core with an efficient five-stage pipeline. To reduce the effect of memory bandwidth and latency on performance, the ARM922T macrocell includes separate cachs and MMUs for both instructions and data. It also has a write buffer and physical address TAG RAM. Control Coprocessor (CP15) The control coprocessor is provided for configuration of the caches, the write buffer, and other ARM922T options. Eleven registers are available for program control: • • • • • • • R egister 1 controls system operation parameters including endianness, cache, and MMU enable R egister 2 and 3 configure and control MMU functions R egister 5 and 6 provide MMU status information R egister 7 and 9 are used for cache maintenance operations R egister 8 and 10 are used for MMU maintenance operations R egister 13 is used for fast context switching R egister 15 is used for test. Caches Two 8KB caches are implemented, one for instructions, the other for data, both with an 8-word line size. Separate buses connect each cache to the ARM9TDMI core permitting a 32 bit instruction to be fetched and fed into the Decode stage of the pipeline at the same time as a 32 bit data access for the memory stage of the pipeline. Cache lock-down is provided to permit critical code sequences to be locked into the cache to ensure predictability for real-time code. The cache replacement algorithm can be selected by the operating system as either pseudo-random or round-robin. Both caches are 64-way set-associative. Lock-down operates on a per-way basis. Debug Features The ARM9TDMI processor core incorporates an EmbeddedICE unit and EmbeddedICE-RT logic permitting both software tasks and external debug hardware to • S et hardware and software breakpoints • P erform single-stepping • E nable access to registers and memory This functionality is implemented as a coprocessor and is accessible from hardware through the JTAG port. Full-speed, real-time execution of the processor is maintained until a breakpoint is hit. At this point control is passed either to a software handler or to JTAG control. Write Buffer The ARM922T macrocell also incorporates a 16-data, 4address write buffer to avoid stalling the processor when writes to external memory are performed. PA TAG RAM The ARM922T macrocell implements a physical address TAG RAM (PA TAG RAM) to perform write-backs from the data cache. The physical addresses of all the lines held in the data cache are stored by the PA TAG memory, removing the requirement for address translation when evicting a line from the cache. 7.1.4 ARM V4T Architecture The ARM9TDMI processor core implements the ARMv4T Instruction Set Architecture (ISA). The ARMv4T ISA is a superset of the ARMv4 ISA with additional support for the Thumb 16-bit compressed instruction set. MMU The ARM922T macrocell implements an enhanced ARMv4 MMU to provide translation and access permission checks for the instruction and data address ports of the ARM9TDMI core. The MMU features are: • • • • • • • • • S tandard ARMv4 MMU mapping sizes, domains, and access protection scheme M apping sizes are 1 MB sections, 64 KB large pages, 4 KB small pages, and new 1KB tiny pages A ccess permissions for sections A ccess permissions for large pages and small pages can be specified separately for each quarter of the page (subpages) A ccess permissions for tiny pages 1 6 domains implemented in hardware 6 4-entry instruction Translation-Lookaside-Buffer (TLB) and 64-entry data TLB H ardware page table walks R ound-robin replacement algorithm (also called cyclic) Performance and Code Density The ARM9TDMI core executes two instruction sets • 3 2-bit ARM instruction set • 1 6-bit Thumb instruction set The ARM instruction set is designed so that a program can achieve maximum performance with the minimum number of instructions. Most ARM9TDMI instructions are executed in a single cycle. The simpler Thumb instruction set offers much increased code density deducing code size and memory requirement. Code can switch between the ARM and Thumb instruction sets on any procedure call. ARM9TDMI Integer Pipeline Stages The integer pipeline consists of five stages to maximize instruction throughput in the ARM9TDMI core: • • • • • F etch D ecode and register read E xecute shift and ALU operation, or address calculate, or multiply M emory access and multiply W rite register © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 19 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential By using a five-stage pipeline, the ARM922T delivers a throughput approaching one instruction per cycle. Classes of Instructions The ARM and Thumb instruction sets can be divided into four broad classes of instruction: • • • • D ata processing instructions L oad and store instructions B ranch instructions C oprocessor instructions Registers The ARM9TDMI processor core consists of a 32-bit datapath and associated conrol logic. This datapath contains 31 generalpurpose registers, coupled to a full shifter, Arithmetic Logic Unit, and a multiplier. At any one time 16 registers are visible to the user. The remainder are mode-specific replacement registers (banked registers) used to speed up execution processing, and make nested exceptions possible. Register 15 is the Program Counter (PC) that can be used in all instructions to reference data relative to the current instruction. R14 holds the return address after a subroutine call. R13 is used (by software convention) as a stack pointer. Data Processing Instructions The data processing instructions operate on data held in generalpurpose registers. Of the two source operands, one is always a register. The other has two basic forms: • A n immediate value • A r egister value optionally shifted If the operand is a shifted register, the shift can be an immediate value or the value of another register. Four types of shift can be specified. Most data processing instructions can perform a shift followed by a logical or arithmetic operation. There are two classes of multiply instructions: • N ormal, 32 bit result • L ong, 64 bi resut variants. Both types of multiply instruction can optionally perform an accumulate operation Exeption Types/Modes The ARM9TDMI core supports five types of exception, and a privileged processing mode for each type. The types of exceptions are: • • • F ast interrupt (FIQ) N ormal interrupt (IRQ) M emory aborts (used to implement memory protection or virtual memory) • A ttempted execution of an undefined instruction • S oftware interrupts (SWIs) All exceptions have banked registers for R14 and R13. After an exception, R14 holds the return address for exception processing. This address is used both to return after the exception is processed and to address the instruction that caused the exception. R13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without the need to save or restore these registers. A seventh processing mode, System mode, uses the User mode registers. System mode runs tasks that require a privileged processor mode and enables them to invoke all classes of exceptions. Load and Store Instructions There are two main types of laod and store instructions: • L oad or store the value of a single register • L oad or store multiple register values Load and store single register instructions can transfer a 32-bit word, a 16-bit halfword, or an 8-bit byte between memory and a register. Byte and halfword loads can be automatically zero extended or sign extended as they are loaded. These instructions have three primary addressing modes: • O ffset • P re-indexed • P ost-indexed The address is formed by adding an immediate, or register-based, positive, or negative offset to a base register. Register-based offsets can also be scaled with shift operations. Pre-indexed and post-indexed addressing modes update the base registers with the base plus offset calculation. As the PC is a general-purpose register, a 32-bit balue can be loaded directly into the PC to perform a jump to any address in the 4GB memory space. Load and store multiple instructions perform a block transfer of any number of the general purpose registers to, or from, memory. Four addressing modes are provided: • P re-increment addressing • P ost-increment addressing • P re-decrement addressing • P ost-decrement addressing The base address is specified by a register value (that can be optionally updated after the transfer). As the subroutine return address and the PC values are in general-purpose registers, very efficient subroutine calls can be constructed. Status Registers All other processor states are held in status registers. The current operating processor status is in the Current Program Status Register (CPSR). The CPSR holds: • • F our ALU flags (Negative, Zero, Carry, Overflow) A n interrupt disable bit for each of the IRQ and FIQ interrupts • A b it to indicate ARM or Thumb execution state • F ive bits to encode the current processor mode All five exception modes also have a Saved Program Status Register (SPSR) that holds the CPSR of the task immediately before the exception occurred. Conditional Execution All ARM instructions can be executed conditionally and can optionally update the four condition code flags (Negative, Zero, Carry, and Overflow) according to their result. Fifteen conditions are implemented. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 20 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Branch Instructions As well as letting data processing or load instructions change control flow (by writing the PC) a standard branch instruction is provided with 24-bit signed offset, providing for forward and backward branches of up to 32 MB. A branch with link (BL) instruction enables efficient subroutine calls. BL preserves the address of the instruction after the branch in R14 (Link register or LR). This lets a move instruction put the LR in to the PC and return to the instruction after the branch. The branch and exchange (BX) instruction switches between ARM and Thumb instruction sets with the return address optionally preserving the operating mode of the calling subroutine. Coprocessor Instructions There are three types of coprocessor instructions: • • • C oprocessor data processing instructions C oprocessor register transfer instructions C oprocessor data transfer instructions 7.1.5 JTAG Interface The ARM933T debug interface is based on IEEE Std. 1149.1- 1990, standard test access port. The ARM922T contains hardware extensions for advanced debugging features. These are intended to ease the development of application software. The debug extensions allow the core to be stopped by one of the following: • • • A given instruction fetch (breakpoint) A data access (watchpoint) Asynchronously by a debug request When this happens, the ARM922T is said to be in debug state. At this point, you can examine the internal state of the core and the external state of the system. When examination is complete, you can restore the core and system state and resume program execution. Normally, all control for debugging is done by running a debugger software (ARM AXD or ARM Realview Debugger) on a debug host PC. Connection to the chip is done by an ARM Multi-ICE interface, which connects either to the parallel port or the USB port of the debug host PC. The connection to the multi-ICE interface is done via a 20 way connector and ribbon cable. Following diagram shows the signals connections of the AS3525 to this ICE connector. Figure 6 Interface connector to multi-ICE © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 21 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.1.6 Boot Concept It can be selected if the system should boot either using the internal ROM (internal boot loader) or an external ROM/Flash (connected to the MPMC interface). XPC[0] is read within global chip reset to do the selection of either internal or external boot. Table 11 Boot definitions for internal/external boot selection X PC[0] 1 0 B ooting Option I nternal ROM E xternal ROM/Flash 7.1.6.1 • • • • • • Internal Bootloader Version C22 Within the internal ROM boot loader several options for booting can be selected: S SP IF - SPI master for ST serial flash types S SP IF - SPI slave N andFlash D ebug UART diagnostics I DE boot: direct boot from harddisk U SB boot promer. In the case that a USB connection is present and either an update button is pressed or there is no bootable device, the USB promer is started (see Figure 7 Boot decision between normal boot and USB boot promer” for details). The USB boot promer allows update of the firmware by using an USB mass storage class device. This update can be used either for initial programming (factory programming) or as mechanism for an in-field firmware update. All boot loader options of the internal bootloader are configured by XPC[3:1] pins. External pull-up or pull-down resistors should be used to configure the boot options. Table 12 Boot definitions Chip version C22 X PC[3:1] 0 1 2 3 4 5 6 7 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 B oot Device SPI master ST M25Pxx serial Nor Flash SPI master Atmel AT45DB011B serial Nor Flash SPI slave NandFlash IDE reserved for developers mode UART / Command Line Interface without diagnostics UART / Command Line Interface with diagnostics The update button is located between xpa[4] and xpa[0]. Within the key scan routine, xpa[4] is driven shortly to each logic level “0” and “1” and the value of xpa[0] is read back to sense a keypress of the update button. For the USB promer, it is necessary that frequency settings defining the quarz crystal frequency are defined by the pins xpa[6:4]. For details refer to “Table 13 USB promer frequency settings”. These settings are read at the beginning in the initialisation routine of the bootloader. Table 13 USB promer frequency settings X PA[6:4] 0 00 0 01 0 10 0 11 1 00 o thers U SB promer frequency settings 24 MHz 20 MHz 13 MHz 12 MHz 10 MHz reserved / defaults to 24 MHz © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 22 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Figure 7 Boot decision between normal boot and USB boot promer © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 23 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.2 AHB Peripheral Blocks ARM AHB ("advanced high-performance bus") is the new generation of AMBA bus, which is intended to address the requirements of highperformance synthesizable designs. AMBA AHB implements the features required for high performance, high clock frequency systems including: • • • • • • b urst transfers s plit transactions s ingle cycle bus master handover n on-tristate implementation 3 2 bit bus width t he clock frequency of the AHB can set by software up to 65MHz 7.2.1 2.5 MBIT RAM Main Memory The memory subsystem consists of a RAM part and a ROM part. Within the RAM memory subsystem, following functions are included: • • 1 -TRAM controller with AHB bus slave interface 1 -TRAM memory macros 7.2.1.1 1-TRAM Controller The 1T RAM Controller is a slave interface connected to the AMBA AHB bus. • • • • slave AHB interface supports byte(8 bit), half-word(16 bit) and word(32 bit) read/write accesses 128-bit Line Buffer as temporary storage to reduce the number of memory accesses and optimise power consumption controls 5TSMC 1T-RAM instances 7.2.1.2 On-Chip 1T-RAM macro blocks TSMC Emb1tRAM™ technology is a special kind of DRAM, which is implemented in a logic CMOS process. This innovative concept and design guarantees lowest power, high density, high performance and high yield advantages. ECC (Error Correction Code) technique is applied in the macro to dynamically correct errors caused by hard defects or soft errors. No fuses are needed because the conventional redundancy scheme is replaced with ECC design in the macro. The macro can be operated at clock rate from 20 MHz up to maximum AHB bus clock frequency in flow through random access mode. In the product, one idle cycle for refresh is needed in every 32 clock cycles. Total 5 macros with organisation of 4Kx128 = 64 KByte each are implemented. For the refresh, one master macro is generating the refresh clock (T1F4Kx128_PIFE) and four macros are connected serially in slave mode to the refresh clock (T1F4Kx128PIFES). Features • • • • • • • 20 Mhz to 65 Mhz operation speed Flow through random access Built-in error correction (ECC) 128-bit wide data bus Separated data in/out bus SRAM-style interface operation Built-in refresh controller with refresh clock generator © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 24 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.2.2 On-Chip ROM 7.2.2.1 ROM Controller The ROM controller implements the AHB slave interface for accessing the ROM. The ROM controller generates OK response for all reads and error response for all writes. Access width is always 32 bits. 7.2.2.2 1MBIT ROM 128 KByte of on-chip mask-programmable ROM are included. The ROM is metal mask programmable by a single mask change (VIA2). The ROM contains the following firmware package • B oot loader 7.2.3 VIC – Vectored Interrupt Controller The ARM PrimeCell™ PL190 “vectored interrupt controller” is included in the AHB system. 7.2.3.1 • • • • • • • • • • • • Features A MBA specification Rev 2.0 compliant s upport for 32 standard interrupts s upport for 16 vectored interrupts h ardware interrupt priority I RQ and FIQ generation A HB mapped for fast interrupt response s oftware interrupt generation t est registers r aw interrupt status i nterrupt request status i nterrupt masking p rivileged mode supportBlock Diagram Figure 8 VIC Block Diagram © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 25 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.2.3.2 I RQ S ource 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VIC Interrupt Sources M odule W atchdog T imer 1 T imer 2 U SB D MAC N and Flash I DE M CI INTR0 M CI INTR1 A UDIO IRQ SSP I2C MS I2C Audio I2SIN I2SOUT UART I RQ S ource 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 M odule GPIO4 (XPD) CGU Memory Stick DBOP GPIO1 (XPA) GPIO2 (XPB) GPIO3 (XPC) Table 14 VIC Interrupt Sources © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 26 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.2.4 SMDMAC - Single master DMAC The ARM PrimeCell™ PL081 “SMDMAC single master DMA controller” is included in the AHB system. • • • • • • • • • A MBA specification Rev 2.0 compliant t wo DMA channels. Each channel can support a unidirectional transfer p rovides 16 peripheral DMA request lines s ingle DMA and burst DMA request signals. Each peripheral connected to the PrimeCell™ SMDMAC can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the PrimeCell™ SMDMAC M emory-to-Memory, memory-to-peripheral, peripheral-to-memory and peripheral-to-peripheral transfers. S catter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not need to occupy contiguous areas of memory H ardware DMA channel priority. Each DMA channel has a specific hardware priority. DMA channel 0 has the highest priority and channel 1 has the lowest priority. If requests from two channels become active at the same time the channel with the highest priority is serviced first. A HB slave DMA programming interface. The PrimeCell™ SMDMAC is programmed by writing to the DMA control registers over the AHB slave interface O ne AHB bus master for transferring data. This interface is used to transfer data when a DMA request goes active. Figure 9 SMDMAC Block Diagram © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 27 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.2.4.1 Table 15 DMAC Registers DMAC Registers Base Address AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x020 0x024 0x028 0x02C 0x030 0x034 0x100 0x104 0x108 0x10C 0x110 0x120 0x124 0x128 0x12C 0x130 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC Note Interrupt status register Interrupt terminal count status register Interrupt terminal count clear register Interrupt error status register Interrupt error clear register Raw interrupt terminal count status register Raw interrupt error status register Software burst request register Software single request register Software last burst request register Software last single request register Configuration register Synchronisation register Channel 0 source address Channel 0 destination address Channel 0 linked list item register Channel 0 control register Channel 0 configuration register Channel 1 source address Channel 1 destination address Channel 1 linked list item register Channel 1 control register Channel 1 configuration register peripheral ID0 register peripheral ID1 register peripheral ID2 register peripheral ID3 register peripheral cell ID0 register peripheral cell ID1 register peripheral cell ID2 register peripheral cell ID3 register Register Name D MAC_IntStatus D MAC_IntTCStatus D MAC_IntTCClear D MAC_IntErrorStatus D MAC_IntErrorClear D MAC_RawIntTCStatus D MAC_RawIntErrorStatus D MAC_SoftBReq D MAC_SoftSReq D MAC_SoftLBReq D MAC_SoftSBReq D MAC_Configuration D MAC_Sync D MAC_C0SrcAddr D MAC_C0DestAddr D MAC_C0LLI D MAC_C0Control D MAC_C0Configuration D MAC_C1SrcAddr D MAC_C1DestAddr D MAC_C1LLI D MAC_C1Control D MAC_C1Configuration D MAC_PeripheralId0 D MAC_PeripheralId1 D MAC_PeripheralId2 D MAC_PeripheralId3 D MAC_CellId0 D MAC_CellId1 D MAC_CellId2 D MAC_CellId3 © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 28 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.2.5 Multi Port Memory Controller (MPMC) The MPMC block is integrated into the AMBA system through AHB slave port. The PrimeCell™ MPMC offers: • AMBA 32-bit AHB compliance. • Dynamic memory interface support including SDRAM and JEDEC low-power SDRAM • Asynchronous static memory device support including RAM, ROM, and Flash, with or without asynchronous page mode. • Low transaction latency. • Read and write buffers to reduce latency and to improve performance. • Single AHB interface for accessing external memory. • 8-bit and 16-bit wide static memory support. • 16-bit wide chip select SDRAM memory support. • Static memory features include: • asynchronous page mode read • programmable wait states • bus turnaround delay • output enable, and write enable delays • extended wait • Two chip selects for synchronous memory and two chip selects for static memory devices. • Software controllable HCLK to MPMCCLKOUT ratio. • Power-saving modes dynamically control SDRAM MPMCCKEOUT and MPMCCLKOUT. • Dynamic memory self-refresh mode supported by software. • Controller supports 2K, 4K, and 8K row address synchronous memory parts. That is typical 512MB, 256MB, 128MB, and 16Mb parts, with 8, 16 bits per device. • Two reset domains enable dynamic memory contents to be preserved over a soft reset. • A separate AHB interface to program the MPMC. This enables the PrimeCell™ MPMC registers to be situated in memory with other system peripheral registers. • Locked AHB transactions supported. • Support for all AHB burst types. Figure 10 Multi Port Memory Controller Block Diagram © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 29 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.2.6 IDE Interface Note: The IDE interface is only available on AS3525-A, not for AS3525-B because some of the IDE PINs are not bonded within the AS3525-B package variant. The IDE host interface core provides an efficient and easy-to-use interface to IDE and ATAPI devices. The core implements programmable I/O, Multi-word DMA, and Ultra ATA-33, -66, -100 and -133 modes of operation and supports up to two devices. The core interface to the system-on-chip provides PIO access and DMA capability to optimise data transfers to and from the IDE devices. For ease of integration, this interface includes a register set compatible with the Intel chip set, including a descriptor-based scatter-gather DMA core. This core is compatible with ATA-4 with Ultra ATA33, -66, -100 and -133 extensions. Single-word DMA is not supported. The licensed SpeedSelectTM technology allows the core to be reconfigured to support any timing mode for PIO, MultiWord DMA, and Ultra ATA transfers (-33, -66, -100 or -133) while running at any clock frequency. Interface to the host processor is the AMBA AHB bus architecture. There are two AHB interfaces on the core: an AHB master and an AHB slave. 7.2.6.1 AHB Master Interface The AHB Master implements a subset of the AHB protocol. The following features are supported: • Single transfer, unspecified-length, 4-beat incrementing and optionally 8-beat incrementing bursts (HBURST will be ‘000’, ‘001’, ‘011’, or optionally ‘101’) • Accesses that cross a 1kB boundary will be unspecified-length incrementing (HBURST will be ‘001’) • 16-bit and 32-bit transfers only (HSIZE will only be ‘001’ or ‘010’) • BUSY cycles are not issued (HTRANS will not be ‘01’) • HPROT is not implemented • OKAY, SPLIT and RETRY responses accepted (HRESP may be ‘00’, ‘10’ or ’11’) • HLOCK asserted during fixed-length bursts • The AHB master may be granted by default 7.2.6.2 AHB Slave Interface The AHB Slave implements a subset of the AHB protocol. The following features are supported: • Non-burst only (HBURST must be ‘000’) • 8-, 16-, or 32-bit transfers only (HSIZE must be ‘000’, ‘001’ or ‘010’) • No advantage is gained by issuing a SEQ cycle over a NONSEQ cycle (HTRANS values of ‘10’ and ‘11’ are interpreted identically) • HPROT is ignored • HRESP is ‘00’ (OKAY) • HREADY is issued no sooner than 2 clock cycles after a valid SEQ or NONSEQ cycle • The AHB slave may be selected by default © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 30 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.2.6.3 IDE Block diagram Figure 11 IDE Block Diagram © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 31 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.2.6.4 IDE Interface Registers Table 16 IDE Interface Registers Register Name I deReg_BMICP I deReg_BMISP I deReg_BMIDTPP_LO I deReg_BMIDTPP_HI I deReg_IDETIMP_LO I deReg_IDETIMP_HI I deReg_IDETIMS_LO I deReg_IDETIMS_HI I deReg_SIDETIM I deReg_SLEWCTL_LO I deReg_SLEWCTL_HI I deReg_IDESTAT I deReg_UDMACTL I deReg_UDMATIM_LO I deReg_UDMATIM_HI I deReg_MISCCTL I deReg_REGSTB I deReg_REGRCVR I deReg_DATSTB I deReg_DATRCVR I deReg_DMASTB I deReg_DMARCVR I deReg_UDMASTB I deReg_UDMATRP I deReg_UDMATENV I deReg_IORDYTMP I deReg_IORDYTMS I deTaskF_DATA I deTaskF_ERR_FEAT I deTaskF_SECT_CNT I deTaskF_SECT_NUM I deTaskF_CYL_LO I deTaskF_CYL_HI I deTaskF_DEV_HEAD I deTaskF_STAT_CMD I deTaskF_ALT_STAT_DEV_CTRL I deTaskF_DEV_ADDR Base Address AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE Offset 0x00 0x02 0x04 0x06 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x4A 0x4B 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C 0x1F0 0x1F1 0x1F2 0x1F3 0x1F4 0x1F5 0x1F6 0x1F7 0x3F6 0x3F7 Note primary channel bus master command primary channel bus master status primary channel bus master table pointer primary channel timing register secondary channel timing register slave IDE timing register slew rate control register IDE status register ultra DMA control register ultra DMA timing register miscellaneous control register task file register strobe timing register task file register recovery timing register data register PIO strobe timing register data register PIO recovery timing register DMA strobe timing register DMA recovery timing register ultra DMA strobe timing register ultra DMA ready-to-stop timing register ultra DMA timing envelope register primary IO ready timer configuration reg secondary IO ready timer configuration reg © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 32 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.2.7 USB 2.0 HS OTG interface The USB 2.0 on-chip interface includes the USB 2.0 On-The-Go Physical Interface and the HS OTG controller. Figure 12 USB 2.0 Interface 7.2.7.1 HS OTG controller subsystem The Synopsys HS OTG subsystem is a configurable design. The HS OTG subsystem is fully compliant with the On-TheGo supplement to the USB 2.0 specification, Revision 1.0a. The subsystem supports high speed (480-Mbps) and fullspeed transfers. It is designed to interface to the AMBA AHB bus, shielding the application from the complexities of the HS OTG subsystem-native protocols and simplifying the system interface. The OTG subsystem can be configured using application software as follows: • • • • • • • • • • • • • • • • • • OTG dual-role device (DRD) OTG device only OTG mini host only • • • USB High-Speed (HS) device USB HS mini host USB Full-Speed (FS) device The HS OTG subsystem has the following interfaces the UTMI+, which connect the on-chip PHY to the HS OTG core the AHB slave interface, which provides the microcontroller with read and write access to the core's control and status register (CSRs) the AHB master interface, which enables the core to act as a master on the AHB to transfer data to and from the core's DMA controller the descriptor prefetch buffer RAM interface, which connects to an single-port RAM for DMA descriptor prefetch buffer storage the data RAM interface, which connects to and dual-port RAM (FIFO memory) for transaction data storage • • • General features handles all clock synchronisation within the core uses a descriptor prefetch buffer for optimal AHB use in host mode supports adaptive buffering for dynamic FIFO memory allocation, avoiding gaps in RAM utilisation SOFs are supported in high/full speed modes includes built-in DMA includes hardware transaction scheduling for enhanced performance supports memory mapped address space for the CSRs USB 2.0 supported features supports up to 15 configurations in Device mode • each configuration supports 15 interfaces • each interface handles up to 15 alternate settings supports session request protocol (SRP) supports session request protocol (SRP) supports Host Negotiation Protocol (HNP) r ecovers clock and data from the USB • • • s upports a generic root hub i ncludes auto ping/split completion capabilities c omplies with UTMI+ level 3 interface Implemented Controller configurations are: configured with 4 host channels and 3 bidirectional- plus 1 in-endpoints in device mode dynamic alternate configuration selection (for different bandwidths of isochronous endpoints) © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 33 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Figure 13 USB 2.0 OTG Controller Block Diagram © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 34 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.2.7.2 • • • • • • • USB 2.0 OTG PHY • Complete PHY for USB2.0 On-The-Go USB 2.0 UTMI+ specification compliant Supports high speed (480 Mbit/s), full speed (12 Mbit/s) and low speed (1.5 Mbit/s) data transmission Supports OT supplement features: VBUS state detecting SRP request by “data-line pulsing” method Low jitter clock from either on-chip PLL (48MHz) or optional additional crystal (12MHz, 24MHz or 48MHz) which is available with the 224 pin package, only 16 bit parallel datain/out interface Typical current consumption on vdda33c and vdd33t: • 12 mA in FS RX mode • 30 mA in FS TX mode • 30 mA in HS RX mode • 40 mA in HS TX mode • < 100 uA in suspend mode Rext = 3.4kOhm (+/- 1%) must be connected between pads “rext” and “vssa33c” to set the bias current. 7.2.7.3 USB 2.0 OTG Interface Registers Table 17 USB Interface Registers Register Name USB_IEP0_CTRL USB_IEP0_STS USB_IEP0_TXFSIZE USB_IEP0_MPS USB_IEP0_DESC_PTR USB_IEP0_STS_MASK USB_IEP1_CTRL USB_IEP1_STS USB_IEP1_TXFSIZE USB_IEP1_MPS USB_IEP1_DESC_PTR USB_IEP1_STS_MASK USB_IEP2_CTRL USB_IEP2_STS USB_IEP2_TXFSIZE USB_IEP2_MPS USB_IEP2_DESC_PTR USB_IEP2_STS_MASK USB_IEP3_CTRL USB_IEP3_STS USB_IEP3_TXFSIZE USB_IEP3_MPS USB_IEP3_DESC_PTR USB_IEP3_STS_MASK USB_OEP0_CTRL USB_OEP0_STS USB_OEP0_RXFR USB_OEP0_MPS USB_OEP0_SUP_PTR USB_OEP0_DESC_PTR USB_OEP0_STS_MASK USB_OEP1_CTRL USB_OEP1_STS USB_OEP1_RXFR Base Address AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE Offset 0x00000 0x00004 0x00008 0x0000c 0x00014 0x00018 0x00020 0x00024 0x00028 0x0002c 0x00034 0x00038 0x00040 0x00044 0x00048 0x0004c 0x00054 0x00058 0x00060 0x00064 0x00068 0x0006c 0x00074 0x00078 0x00200 0x00204 0x00208 0x0020c 0x00210 0x00214 0x00218 0x00220 0x00224 0x00228 Note Control Register Status Register TxFIFO Size Maximum Packet Size Data Descriptor Pointer Status Mask Register Control Register Status Register TxFIFO Size Maximum Packet Size Data Descriptor Pointer Status Mask Register Control Register Status Register TxFIFO Size Maximum Packet Size Data Descriptor Pointer Status Mask Register Control Register Status Register TxFIFO Size Maximum Packet Size Data Descriptor Pointer Status Mask Register Control Status Register Rx Packet Frame Number Register RxFIFO Size/Maximum Packet Size Setup buffer Pointer Register Data Descriptor Pointer Status Mask Register Control Register Status Register Rx Packet Frame Number Register © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 35 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Register Name USB_OEP1_MPS USB_OEP1_SUP_PTR USB_OEP1_DESC_PTR USB_OEP1_STS_MASK USB_OEP2_CTRL USB_OEP2_STS USB_OEP2_RXFR USB_OEP2_MPS USB_OEP2_SUP_PTR USB_OEP2_DESC_PTR USB_OEP2_STS_MASK USB_OEP3_CTRL USB_OEP3_STS USB_OEP3_RXFR USB_OEP3_MPS USB_OEP3_SUP_PTR USB_OEP3_DESC_PTR USB_OEP3_STS_MASK USB_DEV_CFG USB_DEV_CTRL USB_DEV_STS USB_DEV_INTR USB_DEV_INTR_MASK USB_DEV_EP_INTR USB_DEV_EP_INTR_MASK USB_PHY_EP0_INFO USB_PHY_EP1_INFO USB_PHY_EP2_INFO USB_PHY_EP3_INFO USB_PHY_EP4_INFO USB_PHY_EP5_INFO USB_HOST_CH0_SPLT USB_HOST_CH0_STS USB_HOST_CH0_TXFSIZE USB_HOST_CH0_REQ USB_HOST_CH0_PER_INFO USB_HOST_CH0_DESC_PTR USB_HOST_CH0_STS_MASK USB_HOST_CH1_SPLT USB_HOST_CH1_STS USB_HOST_CH1_TXFSIZE USB_HOST_CH1_REQ USB_HOST_CH1_PER_INFO USB_HOST_CH1_DESC_PTR USB_HOST_CH1_STS_MASK USB_HOST_CH2_SPLT USB_HOST_CH2_STS USB_HOST_CH2_TXFSIZE USB_HOST_CH2_REQ USB_HOST_CH2_PER_INFO Base Address AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE Offset 0x0022c 0x00230 0x00234 0x00238 0x00240 0x00244 0x00248 0x0024c 0x00250 0x00254 0x00258 0x00260 0x00264 0x00268 0x0026c 0x00270 0x00274 0x00278 0x00400 0x00404 0x00408 0x0040c 0x00410 0x00414 0x00418 0x00504 0x00508 0x0050c 0x00510 0x00514 0x00518 0x01000 0x01004 0x01008 0x0100c 0x01010 0x01014 0x01018 0x01020 0x01024 0x01028 0x0102c 0x01030 0x01034 0x01038 0x01040 0x01044 0x01048 0x0104c 0x01050 Note RxFIFO Size/Maximum Packet Size Setup buffer Pointer Register Data Descriptor Pointer Status Mask Register Control Register Status Register Rx Packet Frame Number Register RxFIFO Size/Maximum Packet Size Setup buffer Pointer Register Data Descriptor Pointer Status Mask Register Control Register Status Register Rx Packet Frame Number Register RxFIFO Size/Maximum Packet Size Setup buffer Pointer Register Data Descriptor Pointer Status Mask Register Device Configuration Register Device Control Register Device Status Register Device Interrupt Register Device Interrupt Mask Register Device Endpoint Interrupt Device Endpoint Interrupt Mask Information Register Information Register Information Register Information Register Information Register Information Register Split Information Register Status Register TxFIFO Register Request Register Periodic/Split Transaction Information Register Data Descriptor Pointer Status Mask Register Split Information Register Status Register TxFIFO Register Request Register Periodic/Split Transaction Information Register Data Descriptor Pointer Status Mask Register Split Information Register Status Register TxFIFO Register Request Register Periodic/Split Transaction Information © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 36 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Register Name USB_HOST_CH2_DESC_PTR USB_HOST_CH2_STS_MASK USB_HOST_CH3_SPLT USB_HOST_CH3_STS USB_HOST_CH3_TXFSIZE USB_HOST_CH3_REQ USB_HOST_CH3_PER_INFO USB_HOST_CH3_DESC_PTR USB_HOST_CH3_STS_MASK USB_HOST_CFG USB_HOST_CTRL USB_HOST_INTR USB_HOST_INTR_MASK USB_HOST_CH_INTR USB_HOST_CH_INTR_MASK USB_HOST_FRAME_INT USB_HOST_FRAME_REM USB_HOST_FRAME_NUM USB_HOST_PORT0_CTRL_STS USB_OTG_CSR USB_I2C_CSR USB_GPIO_CSR USB_SNPSID_CSR USB_USERID_CSR USB_USER_CONF1 USB_USER_CONF2 USB_USER_CONF3 USB_USER_CONF4 USB_USER_CONF5 Base Address AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE Offset 0x01054 0x01058 0x01060 0x01064 0x01068 0x0106c 0x01070 0x01074 0x01078 0x01400 0x01404 0x0140c 0x01410 0x01414 0x01418 0x0141c 0x01420 0x01424 0x01500 0x02000 0x02004 0x02008 0x0200c 0x02010 0x02014 0x02018 0x0201c 0x02020 0x02024 Note Register Data Descriptor Pointer Status Mask Register Split Information Register Status Register TxFIFO Register Request Register Periodic/Split Transaction Information Register Data Descriptor Pointer Status Mask Register Host Configuration Register Host Control Register Host Interrupt Register Host Interrupt Mask Register Host Channel Interrupt Register Host Channel Interrupt Mask Register Host Frame Interval Register Host Frame Remaining Register Host Frame Number Register Host Port and Status Register OTG Control and Status Register I2C Access Register General Purpose Input/Output Register Synopsys ID Register User ID Register User Config1 Register User Config2 Register User Config3 Register User Config4 Register User Config5 Register © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 37 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.2.8 Memory Stick / Memory Stick Pro Interface The Sony memory stick interface is an AHB bus slave device. This interface conforms to following standards: • • Memory Stick Standard Format Specifications version 1.4-00 Memory Stick PRO Format Specifications version 1.00-01 7.2.8.1 Block Diagram The memory stick interface contains two main blocks, the ICON and the host controller. Figure 14 SONY memory stick interface block diagram 7.2.8.2 I-CON This IP is Memory Stick / Memory Stick PRO Host Controller automatic control IP with a 32-bit CPU interface. This IP automatically controls the series of TPC-based communication with the Memory Stick in place of the CPU, and aims to reduce the burden on the Host CPU. The contents of communication with the Memory Stick are designated in this IP by micro codes. Features • • • • • • 3 2-bit CPU interface I nside controller specified by microcodes B uffer for two-way data transmission loaded (256 byte x 2) 3 2/16 bit access available D MA support G eneral-purpose data transmit/receive FIFO (12 Bytes) 7.2.8.3 Features • • • • • • Host Controller M emory Stick and Memory Stick PRO support F iFo memory (64 bits × 4 ) for two-way data transmission B uilt-in CRC circuit M emory Stick serial clock (Serial: 20 MHz (max.), Parallel: 40 MHz (max.)) D MA support 1 6/32/64-bit access possible © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 38 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.2.8.4 Functional description Communication with the Memory Stick The communication protocol with the Memory Stick is started by write from the CPU to the command register. When the protocol finishes, the CPU is notified that the protocol has ended by an interrupt request. Data transfer request When the protocol is started and enters the data transfer state, data is requested by issuing a DMA transfer request or an interrupt request to the CPU. Data can also be requested to an external memory. Memory Stick communication time out The RDY time out time when the handshake state (read protocol: BS2, write protocol: BS3) is established in communication with the Memory Stick can be designated as the number of Memory Stick transfer clocks. When a time out occurs, the CPU is notified that the protocol has ended due to a time out error by an interrupt request. CRC off CRC off can be set as a test mode. When CRC off is set, CRC is not added to the data transmitted to the Memory Stick. PAD cells The connections to the MemoryStick Interface are shared with the General Purpose I/O port-D (GPIO xpd[0:7]). Figure 15 external memory stick connection © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 39 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3 APB Peripheral Block 7.3.1 Timers The Dual Input Timers module is an APB slave that provides access to two interrupt-generating, programmable 32-bit free-running decrementing counters (FRCs). The system clock (PCLK) is used to control the programmable registers, and the second clock input is used to drive the counter, enabling the counters to run from a much slower clock than the system clock. This input clock of the counters (TIMCLK) is connected to a clock derived (divided by 16) from the main clock (clk_main) signal. That clock clk_main is always running and is coming from the internal or external oscillator (set by clk_sel pad). 7.3.1.1 Timer modes • • • Free-running mode: the counter wraps after zero and continues at the maximum value. This is the default mode. Periodic mode: reload of original value after wrapping past zero. One-shot mode - interrupt is generated once, counter halts after reaching zero Figure 16 Timer Block Diagram Each timer has an identical set of registers shown in table Table 18. The operation of each timer is identical. The timer is loaded by writing to the load register and, if enabled, counts down to zero. When a counter is already running, writing to the load register will cause the counter to immediately restart at the new value. Writing to the background load value has no effect on the current count. The counter continues to decrement to zero, and then recommences from the new load value (if in periodic mode, and one shot mode is not selected). When zero is reached, an interrupt is generated. The interrupt can be cleared by writing to the clear register. If One Shot Mode is selected, the counter halts on reaching zero One Shot Mode is deselected, or a new load value is written. Otherwise, after reaching a zero count, if the timer is operating in free-running mode it continues to decrement from its maximum value. If periodic timer mode is selected, the timer reloads the count value from the load register and continues to decrement. In this mode the counter effectively generates a periodic interrupt. The mode is selected by a bit in the timer control register. At any point, the current counter value can be read from the value register. The counter is enabled by a bit in the control register. At reset, the counter is disabled, the interrupt is cleared, and the load register is set to zero. The mode and prescale values are set to free-running, and clock divide of 1 respectively. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 40 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential The timer clock enable is generated by a prescale unit. The enable is then used by the counter to create a clock with a timing of one of the following. • • • T he system clock T he system clock divided by 16, generated by 4 bits of prescale T he system clock divided by 256, generated by a total of 8 bits of prescale Figure 17 - timer prescaler 7.3.1.2 Interrupt generation An interrupt is generated when the full 32-bit counter reaches zero, and is only cleared when the TimerXClear location is written to. A register holds the value until the interrupt is cleared. The most significant carry bit of the counter detects the counter reaching zero. Interrupts can be masked by writing 0 to the interrupt enable bit in the control register. Both the raw interrupt satus (prior to masking) and the final interrupt status (after masking) can be read from status registers. Timer 1 interrupt output is connected to interrupt input line irq1 (VIC input) and Timer 2 interrupt output is connected to interrupt line irq2. 7.3.1.3 Timer Register Descriptions Table 18 – Timer 1 and 2 registers Register Name T imer1Load T imer1Value T imer1Control T imer1IntClr T imer1RIS T imer1MIS T imer1BGLoad T imer2Load T imer2Value T imer2Control T imer2IntClr T imer2RIS T imer2MIS T imer2BGLoad P eriheral ID register bits 7:0 P eriheral ID register bits 15:8 P eriheral ID register bits 23:16 P eriheral ID register bits 31:24 P rimecell ID register bits 7:0 P rimecell ID register bits 15:8 P rimecell ID register bits 23:16 P rimecell ID register bits 31:24 Base Address AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC Note load value for Timer 1 current value for Timer 1 Timer 1 control register Timer 1 interrupt clear Timer 1 raw interrupt status Timer 1 masked interrupt status Timer 1 background load value load value for Timer 2 current value for Timer 2 Timer 2 control register Timer 2 interrupt clear Timer 2 raw interrupt status Timer 2 masked interrupt status Timer 2 background load value Peripheral ID register bits 7:0 Peripheral ID register bits 15:8 Peripheral ID register bits 23:16 Peripheral ID register bits 31:24 Primecell ID register bits 7:0 Primecell ID register bits 15:8 Primecell ID register bits 23:16 Primecell ID register bits 31:24 © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 41 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Load register, Timer1Load, Timer2Load This is a 32-bit register containing the value from which the counter is to decrement. This is the value used to reload the counter when periodic mode is enabled, and the current count reaches zero. When this register is written to directly, the current count is immediately reset to the new value at the next rising edge of TIMCLK which is enabled by TIMCLKEN. The value in this register is also overwritten if the TimerXBGLoad register is written to, but the current count is not immediately affected. If values are written to both the timerXLoad and TimerXBGLoad registers before an enabled rising edge on TIMCLK, the following occurs: • O n the next enabled TIMCLK edge the value written to the TimerXLoad value replaces the current count value • F ollowing this, eacht time the counter reaches zero, the current count value is reset to the value written to TimerXBGLoad. Reading from the TimerXLoad register at any time after the two writes have occurred will retrieve the value written to TimerXBGLoad. That is, the value read from TimerXLoad is always the value which will take effect for periodic mode after the next time the counter reaches zero. Current value register, Timer1Value, Timer2Value This register gives the current value of the decrementing counter. Timer control register Table 19 Timer control register Name Timer1Control, Timer2Control Offset: 0x08, 0x28 Bit 7 Bit Name T imer Enable Base AS3525_TIMER_BASE Default 0x20 Timer Control Register C ontains control bits of the PLLA register. Default 0 Access R/W Bit Description Enable bit: 0: timer disabled (default) 1: timer enabled Mode bit 0: timer is in free-running mode (default) 1: timer is in periodic mode Interrupt enable bit 0: timer interrupt disabled 1: timer interrupt enabled (default) Reserved bit, do not modify, and ignore on read Prescale bits: 00: no prescale, clock is divided by 1 (default) 01: 4 stages of prescale, clock is divided by 16 10: 8 stages of prescale, clock is divided by 256 11: undefined, do not use Selects 16/32 bit counter operation 0: 16 bit counter (default) 1: 32 bit counter Selects one-shot or wrapping counter mode 0: wrapping mode (default) 1: one-shot mode 6 T imer Mode 0 R/W 5 I nterrupt Enable 1 R/W 4 3 :2 R ESERVED TimerPre 00 R/W 1 T imer Size 0 R/W 0 O neShotCount 0 R/W Interrupt clear register, Timer1IntClr, Timer2IntClr Any write to this register will clear the interrupt output from the counter © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 42 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Raw Interrupt status register, Timer1RIS, Timer2RIS This register indicates the raw interrupt status from the counter. This value is ANDed with the timer interrupt enable bit from the control register to create the masked interrupt, which is passed to the interrupt output pin. Table 20 raw interrupt status register Name Timer1RIS, Timer2RIS Offset: 0x10, 0x30 Bit 0 Bit Name R aw Timer Interrupt Base AS3525_TIMER_BASE Default Timer raw interrupt status register C ontains control bits of the PLLA register. Default Access R Bit Description Raw interrupt status from the counter Interrupt status register, TIMERXMIS This register indicates the masked interrupt status from the counter. This value is the logical AND of the raw interrupt status with the timer interrupt enable bit from the control register, and is the same value which is passed to the interrupt output pin. Table 21 interrupt status register Name Timer1MIS, Timer2MIS Offset: 0x10, 0x30 Bit 0 Bit Name R aw Timer Interrupt Base AS3525_TIMER_BASE Default Timer raw interrupt status register C ontains control bits of the PLLA register. Default Access R Bit Description Raw interrupt status from the counter Background load register, TimerXBGLoad This is a 32 bit register containing the value from which the counter is to decrement. This is the value used to reload the counter when periodic mode is enabled, and the current count reaches zero. This register privides an alternative method of accessing the TimerXLoad register. The difference is that writes to TimerXBGLoad will not cause the counter immediately to restart from the new value. Reading from this register returns the same value returned from TimerXLoad. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 43 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.2 Watchdog Unit The watchdog unit provides a way of recovering from software crashes. The watchdog clock is used to generate a regular interrupt (WDOGINT), depending on a programmed value. The watchdog monitors the interrupt and asserts a reset signal (WDOGRES) if the interrupt remains unserviced for the entire programmed period. You can enable or disable the watchdog unit as required. Clock reference for the watchdog is PCLK divided by 256. Figure 18 watchdog unit 7.3.2.1 Watchdog register descriptions Table 22 Watchdog Registers Register Name W DT_LOAD W DT_VALUE W DT_CONTROL W DT_INTCLR W DT_RIS W DT_MIS W DT_LOCK W DT_PERIPHID0 W DT_PERIPHID1 W DT_PERIPHID2 W DT_PERIPHID3 W DT_PCELLID0 W DT_PCELLID1 W DT_PCELLID2 WDT_PCELLID3 Base Address AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0xC00 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC Note load register counter current value control register Interrupt clear register Raw interrupt status register Masked interrupt status register Lock register Watchdog peripheral ID 0 register Watchdog peripheral ID 1 register Watchdog peripheral ID 2 register Watchdog peripheral ID 3 register Watchdog primecell ID 0 register Watchdog primecell ID 1 register Watchdog primecell ID 2 register Watchdog primecell ID 3 register Watchdog load register, WdogLoad This is a 32-bit register containing the value from which the counter is to decrement. When this register is written to, the count is immediately restarted from the new value. The minimum valid value for WdogLoad is one. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 44 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Watchdog control register, WdogControl This is a read/write register that enables the software to control the watchdog unit. Table 23 watchdog control register Name WdogControl Offset: 0x08 Bit 1 Bit Name R ESEN Default 0 Access R/W Base AS3525_WDT_BASE Watchdog Control Register Bit Description Enable Watchdog reset output (WDOGRES). Acts as a mask for the reset output. 0: disable the reset 1: enable the reset Enable the interrupt event (WDOGINT). 0: disable the counter and interrupt 1: enable the counter and interrupt Default 0x04 0 I NTEN 0 R/W Watchdog clear interrupt register, WdogIntClr A write of any value to this location clears the watchdog interrupt, and reloads the counter from the value in WdogLoad. Raw interrupt status register, WdogRIS This register indicates the raw interrupt status from the counter. This value is ANDed with the inerrupt enable bit from the control register to create the masked interrupt, which is passed to the interrupt output pin. Table 24 watchdog raw interrupt status register Name WdogRIS Offset: 0x10 Bit 0 Bit Name W atchdog Interrupt Default Access R Base AS3525_WDT_BASE Watchdog interrupt status register Bit Description Enabled interrupt status from the counter Default Interrupt status register, WdogMIS This register indicates the masked interrupt status from the counter. This value is the logical AND of the raw interrupt status with the INTEN bit from the control register, and is the same value which is passed to the interrupt output pin. Name WdogMIS Offset: 0x14 Bit 0 Bit Name R aw Watchdog Interrupt Default Access R Base AS3525_WDT_BASE Watchdog raw interrupt status register Bit Description Raw interrupt status from the counter Default Table 25 watchdog interrupt status register © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 45 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Watchdog lock register, WdogLock Use of this register allows write-access to all other registers to be disabled. This is to prenent rogue software from disabling the watchdog functionality. Writing a value of 0x1ACCE551 will enable write access to all other registers. Writing any other value will disable write accesses. A read from this register will return only the bottom bit: • • 0 i ndicates that write access is enabled (not locked) 1 i ndicates that write access is disabled (locked) Table 26 watchdog lock register Name WdogLock Offset: 0xC00 Bit 3 1:0 0 Bit Name Enable register writes R egister write enable status Default Access W R Base AS3525_WDT_BASE Default 0x00 Watchdog raw interrupt status register Bit Description Enable write access to all other registers by writing 0x1ACCE551. Disable write access by writing any other value. 0: write access to all other registers is enabled (default) 1: write access to all other registers is disabled 0 © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 46 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.3 SSP – Synchronous Serial Port The SSP is a master or slave interface that enables synchronous serial communication with slave or master peripherals having one of the following: • a Motorola SPI-compatible interface • a TI synchronous serial interface • a National Semiconductor MicroWire interface In both master and slave configurations the SSP performs • parallel-to-serial conversion on data written to an internal 16-bit wide, 8-location deep transmit FIFO • serial-to-parallel conversion on received data, buffering it in a similar 16-bit wide, 8 location-deep receive FIFO Interrupts are generated to: • request servicing of the transmit and receive FIFO • inform the system that a receive FIFO overrun has occurred • inform the system that data is present in the receive FIFO after an idle period has expired SSP Features: • compliant to AMBA Rev 2.0 • master or slave operation • programmable clock bit rate and prescale • separate receive and transmit memory buffers each 16 bits wide and 8 bits deep • programmable data frame size from 4 to 16 bit • independent masking of receive FIFO, transmit FIFO and receive overrun interrupts • internal loopback testmode available • support for DMA • identification register uniquely identifying the PrimeCell™ itself (support for OS) SPI features: • full-duplex, four wire synchronous transfer • programmable clock polarity and phase MicroWire features: • half duplex transfer using 8 bit control message Texas Instruments SSI features: • full-duplex, four wire synchronous transfer • transmit data PIN tristateable when not transmitting Programmable parameters: • master or slave mode • enabling of operation • frame format • communication baud rate • clock phase and polarity • data width from 4 to 16 bit • interrupt masking © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 47 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Figure 19 Serial Synchronous Port Block Diagram Table 27 SSP Registers Register Name S PI_SSPCR0 S PI_SSPCR1 S PI_SSPRXD S PI_SSPTXD S PI_SSPSR S PI_SSPCPSR S PI_SSPIMSC S PI_SSPIRS S PI_SSPMIS S PI_SSPICR S PI_SSPDMACR Base Address SSP_BASE SSP_BASE SSP_BASE SSP_BASE SSP_BASE SSP_BASE SSP_BASE SSP_BASE SSP_BASE SSP_BASE SSP_BASE Offset 0x00 0x04 0x08 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 Note CR0 control register CR1 control register Read Data Register Write Data register SSP status register SSP Pre-scaler register SSP Interrupt Mask and clear register SSP Raw interrupt status register SSP Masked interrupt status register SSP interrupt clear register SSP DMA control register © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 48 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.4 GPIO - General purpose input/output ports The ARM PrimeCell™ PL061 “General Purpose Input/Output” is included in the APB system. • • • • • • compliant to AMBA Rev 2.0 each port has eight individually programmable input/output pins, default to input at reset four ports A, B, C, D are included programmable interrupt generation capability, from a transition or level condition, on any number of PINs hardware control capability of GPIO’s for different system configurations. bit masking in both read and write operations through address lines Figure 20 GPIO Block Diagram © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 49 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.4.1 GPIO register descriptions Table 28: GPIO Registers Register Name G PIO1_DATA G PIO1_DIR G PIO1_IS G PIO1_IBE G PIO1_IEV G PIO1_IE G PIO1_RIS G PIO1_MIS G PIO1_IC G PIO1_AFSEL G PIO2_DATA G PIO2_DIR G PIO2_IS G PIO2_IBE G PIO2_IEV G PIO2_IE G PIO2_RIS G PIO2_MIS G PIO2_IC G PIO2_AFSEL G PIO3_DATA G PIO3_DIR G PIO3_IS G PIO3_IBE G PIO3_IEV G PIO3_IE G PIO3_RIS G PIO3_MIS G PIO3_IC G PIO3_AFSEL G PIO4_DATA G PIO4_DIR G PIO4_IS G PIO4_IBE G PIO4_IEV G PIO4_IE G PIO4_RIS G PIO4_MIS G PIO4_IC G PIO4_AFSEL Base Address AS3525_GPIO1_BASE AS3525_GPIO1_BASE AS3525_GPIO1_BASE AS3525_GPIO1_BASE AS3525_GPIO1_BASE AS3525_GPIO1_BASE AS3525_GPIO1_BASE AS3525_GPIO1_BASE AS3525_GPIO1_BASE AS3525_GPIO1_BASE AS3525_GPIO2_BASE AS3525_GPIO2_BASE AS3525_GPIO2_BASE AS3525_GPIO2_BASE AS3525_GPIO2_BASE AS3525_GPIO2_BASE AS3525_GPIO2_BASE AS3525_GPIO2_BASE AS3525_GPIO2_BASE AS3525_GPIO2_BASE AS3525_GPIO3_BASE AS3525_GPIO3_BASE AS3525_GPIO3_BASE AS3525_GPIO3_BASE AS3525_GPIO3_BASE AS3525_GPIO3_BASE AS3525_GPIO3_BASE AS3525_GPIO3_BASE AS3525_GPIO3_BASE AS3525_GPIO3_BASE AS3525_GPIO4_BASE AS3525_GPIO4_BASE AS3525_GPIO4_BASE AS3525_GPIO4_BASE AS3525_GPIO4_BASE AS3525_GPIO4_BASE AS3525_GPIO4_BASE AS3525_GPIO4_BASE AS3525_GPIO4_BASE AS3525_GPIO4_BASE Offset 0x000 0x400 0x404 0x408 0x40C 0x410 0x414 0x418 0x41C 0x420 0x000 0x400 0x404 0x408 0x40C 0x410 0x414 0x418 0x41C 0x420 0x000 0x400 0x404 0x408 0x40C 0x410 0x414 0x418 0x41C 0x420 0x000 0x400 0x404 0x408 0x40C 0x410 0x414 0x418 0x41C 0x420 Note data register data direction register interrupt sense register interrupt both edges register interrupt event register interrupt mask register raw interrupt status masked interrupt status interrupt clear mode control select data register data direction register interrupt sense register interrupt both edges register interrupt event register interrupt mask register raw interrupt status masked interrupt status interrupt clear mode control select data register data direction register interrupt sense register interrupt both edges register interrupt event register interrupt mask register raw interrupt status masked interrupt status interrupt clear mode control select data register data direction register interrupt sense register interrupt both edges register interrupt event register interrupt mask register raw interrupt status masked interrupt status interrupt clear mode control select GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 50 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential GPIO data register Table 29 GPIO data register Name GPIO1_DATA GPIO2_DATA GPIO3_DATA GPIO4_DATA Base AS3525_GPIO1_BASE AS3525_GPIO2_BASE AS3525_GPIO3_BASE AS3525_GPIO4_BASE Default 0xC80B0000 0xC80C0000 0xC80D0000 0xC80E0000 Offset: 0x000 GPIO data register I n software control mode (GPIO1_AFSEL,...), values written in this register are transferred onto the GPOUT pins if the respective pins have been configured as outputs through the GPIO1_DIR, .. . So that GPIO bits can be set without affect to other pins in a single write operation, the address bus is used as a mask on read/write operation. The data register covers 256 locations in the address space. The eight address lines used are PADDR[9:2]. During a write, only GPIO1_DATA,... bits corresponding to HIGH address bits are updated. During a read all data bits corresponding to HIGH address bits are read, the other bits are zero. A read from this register returns the last bit value written if the respective pins are configured as output, or it returns the value on the corresponding input GPIN bit when these are configured as inputs. All bits are cleared by a reset. Default 00000000 Access RW Bit Description Input data, output data. Bit 7 :0 Bit Name GPIO data register GPIO data direction register Table 30 GPIO data direction register Name GPIO1_DIR GPIO2_DIR GPIO3_DIR GPIO4_DIR Offset: 0x400 Bit 7 :0 Bit Name GPIO data direction register Base AS3525_GPIO1_BASE AS3525_GPIO2_BASE AS3525_GPIO3_BASE AS3525_GPIO4_BASE Default 0xC80B0000 0xC80C0000 0xC80D0000 0xC80E0000 GPIO data direction register B its set to HIGH configure corresponding pin to be an output. Clearing a bit configures the pin to be input. All bits are cleared by a reset. Default 00000000 Access RW Bit Description 0: pins input 1: pins output © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 51 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential GPIO interrupt sense register Table 31 GPIO interrupt sense register Name GPIO1_IS GPIO2_IS GPIO3_IS GPIO4_IS Offset: 0x404 Bit 7 :0 Bit Name GPIO interrupt sense register Base AS3525_GPIO1_BASE AS3525_GPIO2_BASE AS3525_GPIO3_BASE AS3525_GPIO4_BASE Default 0xC80B0000 0xC80C0000 0xC80D0000 0xC80E0000 GPIO interrupt sense register B its set to HIGH configure the corresponding pins to detect levels. Clearing a bit configures the pin to detect edges. All bits are cleared by a reset. Default 00000000 Access RW Bit Description 0: edge on corresponding pin is detected 1: level on corresponding pin is detected GPIO interrupt both edges register Table 32 GPIO interrupt both edges register Name GPIO1_IBE GPIO2_IBE GPIO3_IBE GPIO4_IBE Base AS3525_GPIO1_BASE AS3525_GPIO2_BASE AS3525_GPIO3_BASE AS3525_GPIO4_BASE Default 0xC80B0000 0xC80C0000 0xC80D0000 0xC80E0000 Offset: 0x408 GPIO interrupt both edges register W hen the corresponding bit in GPIO interrupt sense register (GPIO1_IS, …) is set to detect edges, bits set to HIGH in GPIO interrupt both edges register (GPIO1_IBE, … ) configure the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the GPIO interrupt event register (GPIO1_IEV, …). Clearing a bit configures the pin to be controlled by GPIO interrupt event register (GPIO1_IEV, …). All bits are cleared by a reset. Default 00000000 Access RW Bit Description 0: on corresponding pin interrupt generation event is controlled by GPIO interrupt event register (GPIO1_IEV, …). 1: both edges on corresponding pin trigger an interrupt. Single edge determined by corresponding bit in GPIO interrupt event register (GPIO1_IEV, …). Bit 7 :0 Bit Name GPIO interrupt event register © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 52 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential GPIO interrupt event register Table 33 GPIO interrupt event register Name GPIO1_IEV GPIO2_IEV GPIO3_IEV GPIO4_IEV Base AS3525_GPIO1_BASE AS3525_GPIO2_BASE AS3525_GPIO3_BASE AS3525_GPIO4_BASE Default 0xC80B0000 0xC80C0000 0xC80D0000 0xC80E0000 Offset: 0x40C GPIO interrupt event register B its set to HIGH configure the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in GPIO interrupt sense register (GPIO1_IS, …). Clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in GPIO interrupt sense register (GPIO1_IS, …). All bits are cleared by a reset. Default 00000000 Access RW Bit Description 0: falling edges, or low levels on corresponding pin trigger interrupts. 1: rising edges, or high levels on corresponding pin trigger interrupts. Bit 7 :0 Bit Name GPIO interrupt event register GPIO interrupt mask register Table 34 GPIO interrupt mask register Name GPIO1_IE GPIO2_IE GPIO3_IE GPIO4_IE Base AS3525_GPIO1_BASE AS3525_GPIO2_BASE AS3525_GPIO3_BASE AS3525_GPIO4_BASE Default 0xC80B0000 0xC80C0000 0xC80D0000 0xC80E0000 Offset: 0x410 GPIO interrupt mask register B its set to HIGH allow the corresponding pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables interrupt triggering on that pin. All bits are cleared by a reset. Default 00000000 Access RW Bit Description 0: corresponding pin interrupt is masked. 1: corresponding pin interrupt is not masked. Bit 7 :0 Bit Name GPIO interrupt mask register © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 53 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential GPIO raw interrupt status register Table 35 GPIO raw interrupt status register Name GPIO1_RIS GPIO2_RIS GPIO3_RIS GPIO4_RIS Base AS3525_GPIO1_BASE AS3525_GPIO2_BASE AS3525_GPIO3_BASE AS3525_GPIO4_BASE Default 0xC80B0000 0xC80C0000 0xC80D0000 0xC80E0000 Offset: 0x414 GPIO raw interrupt status register B its read HIGH reflect the status of interrupts trigger conditions detected (raw, prior to masking), indicating that all the requirements have been met, before they are finally allowed to trigger by GPIO interrupt mask register (GPIO1_IE, ...). Bits read as LOW indicate that corresponding input pins have not initiated an interrupt. This register is read only, its bits are cleared by a reset. Default 00000000 Access R Bit Description Reflect the status of interrupts trigger conditions detection on pins (raw, prior to masking). 0: requirements not met on corresponding pins. 1: requirements met by corresponding pins. Bit 7 :0 Bit Name GPIO raw interrupt status register GPIO masked interrupt status register Table 36 GPIO masked interrupt status register Name GPIO1_MIS GPIO2_MIS GPIO3_MIS GPIO4_MIS Base AS3525_GPIO1_BASE AS3525_GPIO2_BASE AS3525_GPIO3_BASE AS3525_GPIO4_BASE Default 0xC80B0000 0xC80C0000 0xC80D0000 0xC80E0000 Offset: 0x418 GPIO masked interrupt status register B its read HIGH reflect the status of input lines triggering an interrupt. Bits read as LOW indicate that either no interrupt has been generated, or the interrupt is masked. This register shows the state of the interrupt after masking. This register is read-only. All bits are cleared by a reset. The contents of this register are made available externally through the intra-chip (or on-chip) GPIO1_MIS, ... signals. Default 00000000 Access R Bit Description Masked value of interrupt due to corresponding pin. 0: PrimeCell GPIO line interrupt not active. 1: PrimeCell GPIO line asserting interrupt. Bit 7 :0 Bit Name GPIO masked interrupt status register © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 54 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential GPIO interrupt clear register Table 37 GPIO interrupt clear register Name GPIO1_IC GPIO2_IC GPIO3_IC GPIO4_IC Base AS3525_GPIO1_BASE AS3525_GPIO2_BASE AS3525_GPIO3_BASE AS3525_GPIO4_BASE Default 0xC80B0000 0xC80C0000 0xC80D0000 0xC80E0000 Offset: 0x41C GPIO interrupt clear register S etting a bit to HIGH in this register clears the corresponding interrupt edge detection logic register. Setting a bit to LOW in this register has no effect. This register is writeonly. All bits are cleared by a reset. Default 00000000 Access W Bit Description 0: has no effect. 1: clears edge detection logic. Bit 7 :0 Bit Name GPIO interrupt clear register GPIO mode control select register Table 38 GPIO2, GPIO3 mode control select register Name GPIO2_AFSEL GPIO3_AFSEL Offset: 0x420 Bit 7 :0 Bit Name GPIO mode control select register Base AS3525_GPIO2_BASE AS3525_GPIO3_BASE Default 0xC80C0000 0xC80D0000 GPIO mode control select register S etting a bit to HIGH in this register selects DBOP control for the corresponding PrimeCell GPIO line. All bits are cleared by a reset. Default 00000000 Access RW Bit Description 0: enables software control mode on corresponding pin. Bits 1: enables DBOP control mode on corresponding pin. Table 39 GPIO1, GPIO4 mode control select register Name GPIO1_AFSEL GPIO4_AFSEL Offset: 0x420 Bit 7 :0 Bit Name GPIO mode control select register Base AS3525_GPIO1_BASE AS3525_GPIO4_BASE Default 0xC80B0000 0xC80E0000 GPIO mode control select register N ot used. If bit set to HIGH, the corresponding pin will be set to 1. Default 00000000 Access RW Bit Description Bits 0: enables software control mode on corresponding pin. Bits 1: corresponding pins set to 1. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 55 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.5 MCI – SD / MMC Card Interface Features • • • C onformance to Multimedia Card Specification v2.11 C onformance to Secure Digital Memory Card Physical Layer Specification, v0.96 u ses multimedia card bus or SD card bus. The PrimeCell™ MCI provides an interface between the APB system bus and multimedia and/or secure digital memory cards. It consists of two parts: • • T he PrimeCell™ MCI adapter block includes the clock generation unit, the power management control, command and data transfer t he APB interface provides access to the MCI adapter registers, and generates interrupt and DMA request signals. Figure 21 Multimedia Card Interface Block Diagram The connections to the Multimedia Card Interface are shared with the General Purpose I/O port-D (GPIO xpd[0:7]). Following diagram shows the external circuit elements for connection to a SD card adapter. Note that a feedback clock must be routed back to xpd[6]/mci_fbclk. Figure 22 Connecting SD / MC to GPIO-D © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 56 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.6 I2cAudMas - I2C audio master interface This is the control interface between the digital and the audio-part. The corresponding signal lines are connected inside of the MCM on the BGA substrate. For test purposes of the audio chip only, the signals are available at dedicated balls. • • • • • • • • • • • T he key features of this interface block are: s erial 2-wire I2C bus master s upports standard (100 kbps) and fast speed (400kbps) 7 -bit addressing s ub-addressing p rogrammable clock divider p rogrammable transfer count s oft reset bit i nterrupt generation (on RX Full, TX Empty, RX Overrun, no acknowledge received) s tatus register t est register Figure 23 I2C Audio Master Interface Block Diagram Table 40 I2C Audio Master Registers Register Name I 2C2_DATA I 2C2_SLAD0 I 2C2_CNTRL I 2C2_DACNT I 2C2_CPSR0 I 2C2_CPSR1 I 2C2_IMR I 2C2_RIS I 2C2_MIS I 2C2_SR I 2C2_INT_CLR I 2C2_SADDR I 2C2_TESTIN I 2C2_TESTOUT1 I 2C2_TESTOUT2 Base Address AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE Offset 0x00 0x04 0x0C 0x10 0x1C 0x20 0x24 0x28 0x2C 0x30 0x40 0x44 0x50 0x54 0x58 Note transmit/receive FIFO data register slave ID register control register master data count register clock prescale register 0 clock prescale register 1 interrupt mask register raw interrupt status register masked interrupt status register I2C status register interrupt clear register sub-address register test register (monitors state of SCL and SDA) test mode register for driving output interrupt test mode register for driving SCLout, SCLOEn, SDAOUT and SDAOEN signals © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 57 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.7 I2CMSI - I2C master/slave interface This is a general control interface for chip-to-chip communication. The corresponding IOs are either used by the general purpose port C (xpc[6:7]) or by this I2C interface. The features of this interface block are: • • • • • • • • • • s erial 2-wire I2C bus master s upports standard (100 kbps) and fast speed (400kbps) s upports multi-master system architecture p rogrammable clock divider p rogrammable transfer count p rogrammable slave wait enable (for slave mode of operation, insertion of wait on the bus) s oft reset bit i nterrupt generation (on RX Full, TX Empty, RX Overrun, no acknowledge received) s tatus register t est register Figure 24: I2C Interface Table 41 I2C Interface Registers Register Name I 2C1_DATA I 2C1_SLAD0 I 2C1_SLAD1 I 2C1_CNTRL I 2C1_DACNT I 2C1_SEAD0 I 2C1_SEAD1 I 2C1_CPSR0 I 2C1_CPSR1 I 2C1_IMR I 2C1_RIS I 2C1_MIS I 2C1_SR I 2C1_TXCNT I 2C1_RXCNT I 2C1_TX_FLUSH I 2C1_INT_CLR I 2C1_TESTIN I 2C1_TESTOUT1 I 2C1_TESTOUT2 Base Address AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x50 0x54 0x58 Note transmit/receive FIFO data register slave ID register 0 slave ID register 1 control register master data count register self ID of slave 0 self ID of slave 1 clock prescale register 0 clock prescale register 1 interrupt mask register raw interrupt status register masked interrupt status register I2C status register transmit Fifo data count register receive Fifo data count register TX Fifo flush register interrupt clear register test register (monitors state of SCL and SDA) test mode register for driving output interrupt test mode register for driving SCLout, SCLOEn, SDAOUT and SDAOEN signals 58 - 194 © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.8 I2SIN - I2S input interface The I2S input interface module (called I2SINIF module hereafter) is used to connect an external audio source to the processor system. The communication is based on the standardized I2S interface. The interface module connects to the processor system using the AMBA APB bus. All the input left & right channel data are mapped to either 14 or 24 bit format, selectable within the control register. If the data word length is less than 24 bit, the unused lower bits are set to zero. To reduce the interrupt frequency for the processor, a FIFO buffer is provided. The buffer can hold up to 32 words of 48 bit length (left plus right channel). Generation of interrupt request signal with several maskable interrupt sources (Pop Full, Pop Empty, Pop Error, Push Error, …etc) The I2SINIF provides the following features: • • • • • t wo independent clock domains: AMBA APB clock PCLK, I2S input clock i2si_sclk F IFO (32 words/48 bit) separating clock domains s upport of several oversampling rates: 128x, 256x, 512x i nterrupt support for FIFO data read D MA support for FIFO data transfer The I2SINIF provides five different modes: • • • • • i nput from on-chip audio ADC i nput from external audio ADC in master mode (SCLK, LRCK generated by external ADC) i nput from external audio ADC in slave mode (SCLK, LRCK, MCLK generated internally and fed to external ADC) i nput from SPDIF (SPDIF to I2S converter) f eedback mode with input from I2S output interface: used for test purposes Figure 25 I2S Input Interface © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 59 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.8.1 I2S Input Register Mapping I2S Input Interface Registers Table 42 I2S Input Interface Registers Base Address AS3525_I2SIN_BASE AS3525_I2SIN_BASE AS3525_I2SIN_BASE AS3525_I2SIN_BASE AS3525_I2SIN_BASE AS3525_I2SIN_BASE AS3525_I2SIN_BASE Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 Control register Interrupt mask register Raw status register Status register Interrupt clear register Audio data register SPDIF status signals register Note Register Name I2SIN_CONTROL I2SIN_MASK I2SIN_RAW_STATUS I2SIN_STATUS I2SIN_CLEAR I2SIN_DATA I2SIN_SPDIF_STATUS Table 43 I2S Input Control Register Name I2SIN_CONTROL Offset: 0x0000 Bit 11 Bit Name DMA_req_en Base AS3525_I2SIN_BASE Default 0x04 Control register 1 2 bit wide read/write register containing the control bits of the I2SINIF. Default 0 Access R/W Bit Description DMA request enable 0: disable 1: enable Invert MCLK 0: disable (SCLK changes at MCLK’s falling edge) 1: enable (SCLK changes at MCLK’s rising edge) Define the source of SCLK and LRCK for I2SINIF 00: SCLK and LRCK from I2SOUTIF (used if AFE sends data) 01: SCLK and LRCK from external ADC device (outside AS3525) 10: SCLK and LRCK from SPDIF converter 11: SCLK and LRCK from I2SINIF’s clock controller Define the source of SDATA for I2SINIF 00: SDATA from AFE 01: SDATA from external ADC device (outside AS3525) 10: SDATA from SPDIF converter 11: loopback SDATA from I2SOUTIF (test purpose) 0: ADC data from FIFO transferred in two 32-bit words to I2SIN_DATA (first left and then right data as indicated by the stereo24_status bit) 1: ADC data from FIFO transferred in one 32-bit word to I2SIN_DATA Enable/disable SCLK for I2SINIF 0: SCLK enabled 1: SCLK disabled 0: SDATA ignored at first SCLK edge (I2S standard) 1: valid SDATA at first SCLK edge 0: data valid at negative edge of SCLK 1: data valid at positive edge of SCLK Oversampling rate (needed for generating sclk and lrck) 00: 128x 01: 256x 10: 512x 11: 128x 10 mclk_invert 0 R/W 9 ,8 i2s_clk_source 00 R/W 7 ,6 sdata_source 00 R/W 5 1 4bit_mode 0 R/W 4 s clk_idle 0 R/W 3 2 1 ,0 S DATA_valid s clk_edge osr 0 1 00 R/W R/W R/W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 60 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential The following table shows the valid combinations for sdata_source (bit 7 and 6) and i2s_clk_source (bit 9 and 8) of the I2SIN_CONTROL register. sdata_source 00 01 01 10 11 00 00 11 10 00 i2s_clk_source Description default mode (AFE with AS3525) external data, external clock external data, internal clock data and clock from SPDIF converter loopback, internal data and clock Table 44 I2S Input mask register Name I2SIN_MASK Offset: 0x0004 Bit 7 6 5 4 3 2 1 0 Bit Name r eserved I 2SIN_MASK_PUER I 2SIN_MASK_POE I 2SIN_MASK_POAE I 2SIN_MASK_POHF I 2SIN_MASK_POAF I 2SIN_MASK_POF I 2SIN_MASK_POER Base AS3525_I2SIN_BASE Default 0x00 Interrupt mask register T he interrupt mask register determines which status flags generate an interrupt by setting the corresponding bit to 1. Default 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit Description stereo24_status cannot assert interrupt request 1 enables the FIFO PUSH error interrupt 1 enables the FIFO POP is empty interrupt 1 enables the FIFO POP is almost empty interrupt 1 enables the FIFO POP is half full interrupt 1 enables the FIFO POP is almost full interrupt 1 enables the FIFO POP is full interrupt 1 enables the FIFO POP error interrupt Table 45 I2S Input raw status register Name I2SIN_RAW_STATUS Base AS3525_I2SIN_BASE Default 0x00 Offset: 0x0008 Raw status register T he read-only raw status register contains the actual bit values as reflected by the FIFO controller status signals. I2SIN_PUER and I2SIN_POER are static bits, since FIFO controller gives the PUSH/POP error bit only for one clock. This means that these two bits remain asserted until they are cleared in the I2SIN_CLEAR register. All other bits change state depending on the underlying logic, i.e. state of FIFO controller. Default 0 Access R Bit Description Status of write interface for 24 bit stereo mode 0: left audio sample will be transferred next 1: right audio sample will be transferred next 1 if FIFO PUSH error 1 if FIFO POP is empty 1 if FIFO POP is almost empty 1 if FIFO POP is half full 1 if FIFO POP is almost full 1 if FIFO POP is full 1 if FIFO POP error Bit 7 Bit Name s tereo24_status 6 5 4 3 2 1 0 I 2SIN_PUER I 2SIN_POE I 2SIN_POAE I 2SIN_POHF I 2SIN_POAF I 2SIN_POF I 2SIN_POER 0 0 0 0 0 0 0 R R R R R R R © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 61 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 46 I2S input status register Name I2SIN_STATUS Base AS3525_I2SIN_BASE Default 0x00 Offset: 0x000C Status register T he status register is a read-only register. A read to this register returns the value of the raw status bits AND’ed with the corresponding mask of enable bits set in the mask register. Default 0 Access R Bit Description Status of write interface for 24 bit stereo mode 0: left audio sample will be transferred next 1: right audio sample will be transferred next 1 if FIFO PUSH error 1 if FIFO POP is empty 1 if FIFO POP is almost empty 1 if FIFO POP is half full 1 if FIFO POP is almost full 1 if FIFO POP is full 1 if FIFO POP error Bit 7 Bit Name s tereo24_status 6 5 4 3 2 1 0 I 2SIN_PUER I 2SIN_POE I 2SIN_POAE I 2SIN_POHF I 2SIN_POAF I 2SIN_POF I 2SIN_POER 0 0 0 0 0 0 0 R R R R R R R Table 47 I2S Input interrupt clear register Name I2SIN_CLEAR Base AS3525_I2SIN_BASE Default 0x00 Offset: 0x0010 Interrupt clear register T he interrupt clear register is a write-only register. The corresponding static status bit can be cleared by writing a 1 to the corresponding bit in the clear register. All other interrupt flags are level interrupts depending on the status of the FIFO. The bits are de-asserted depending on the FIFO controller. Default Access W W W W Bit Description Clear PUSH error interrupt flag Clear POP error interrupt flag Bit 7 6 5 :1 0 Bit Name r eserved I 2SIN_clear_puer reserved I 2SIN_clear_poer I2SIN_DATA The I2SINIF provides a single 32 bit wide data register. The register is used to read the audio samples from FIFO. If 14 bit mode is selected, both the left and right data are made available in the same register. Otherwise in the 24 bit mode the left and right data are provided through the same register alternatively. The stereo24_status bit in the I2SIN_STATUS register provides information which channel’s data will be provided next. The 14bit_mode bit in the I2SIN_CONTROL register defines how the values are read from the FIFO. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 62 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.8.2 I2S Input Signals The following specifications signals are given: • • D ata are valid at rising/falling edge of SCLK (depending on I2SI_CONTROL’s setting). T he left and right channels are indicated by the LRCK signal. The timing diagram of the standard I2S interface signals from the ADC is shown below (Figure 29). Figure 26 - I2S standard timing diagram Tperiod(fsaudio) / 2 Tperiod(fsaudio) / 2 LRCK SCLK SDATA 24 bit Left Channel Right Channel X 23 2 1 0 X 23 2 1 0 While the I2S standard states that the LRCK line changes one clock cycle before the MSB is transmitted. If the ADC sends the MSB directly after LRCK line changes, the SDATA_valid bit in the I2SI_CONTROL register must be set. Figure 27 - I2S standard timing diagram with SDATA valid directly after LRC changes Tperiod(fsaudio) / 2 Tperiod(fsaudio) / 2 LRCK SCLK SDATA 24 bit Left Channel Right Channel 23 22 2 1 0 23 22 2 1 0 Assumption: The LRCK toggles every 32 clocks of SCLK. 7.3.8.3 Power Modes The I2SINIF contains two clock domains. The PCLK domain can be turned off in the clock controller. The SCLK clock domain can be turned off locally using the SCLK_idle bit in the I2SIN_CONTROL register. Note that the SCLK’s clock gating signal has to be synchronized with the SCLK clock in order to guarantee correct operation. If PCLK is turned off, no interrupt must be triggered by the I2SINIF module. The I2SI_MCLK clock can be turned on/off in the clock generation unit. 7.3.8.4 Loopback Feature On the AS3525 are two I2S interfaces: • I 2SOUTIF is responsible to send values to the DAC of the audio chip via I2SO_SDATA • I 2SINIF is responsible to receive audio values from ADC of the audio chip via I2SI_SDATA In the AS3525 both SDATA signals are provided as loopback signals (I2SO_FSDATA, I2SI_FSDATA): • I 2SO_SDATA to I2SINIF: This loopback is mainly for testing the transmit and receive paths of both I2S interfaces. The loopback signal is called I2SO_FSDATA. • I 2SI_SDATA to I2SOUTIF: This loopback feature allows the application to echo the input audio samples directly to a loudspeaker. The signal provided by the I2SINIF is called I2SI_FSDATA. In normal mode the I2SINIF pushes audio values into the FIFO based on the I2SI_SDATA signal. If the loopback feature is enabled, the sdata_source bit in the control register must be set to 3. The FIFO content is filled with audio values send by the I2SOUTIF (signal I2SO_FSDATA). NOTE: This feature will only be available if SCLK is the same for I2S input and output interface. For implementation the I2SO_FSDATA signal is simply routed through a multiplexer to the I2SI_SDATA interface. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 63 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.8.5 DMA Interface The I2SINIF supports DMA transfers. The DMA controller supports incrementing and non-incrementing (single address) addressing for source and destination. For I2SINIF the single-address mode is used. The address of the I2SI_DATA register is used as DMA source address. 7.3.8.6 The 24 bit Stereo DMA Mode In 24 bit stereo mode, right and left audio samples must be read separately from the FIFO. In single-address DMA-mode both data must be read from the same address. The I2SINIF is responsible to split up the 48 bit FIFO entries into two 24 bit samples. The 24 bit value can then be transferred via the 32 bit wide AMBA bus. The I2SINIF provides the data in a specific order: first the left value is sent, and afterwards the right value is provided. Then a left value follows, and so on. In the destination memory the words are stored incrementally as shown below. Address addr 0 addr 1 addr 2 addr 3 … addr n*2 addr n*2+1 LDATA 0 RDATA 0 LDATA 1 RDATA 1 … LDATA n RDATA n Value © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 64 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.9 SPDIF interface As part of the I2SIN module also a SPDIF receiver interface is included. This SPDIF interface works as converter from SPDIF-AES/EBU to I2S. The SPDIF-AES/EBU standard is a serial audio interface that conveys 2 time-multiplexed audio channels, the left and right channels, as is the case in audio stereo transmission. The two channels are encoded in a 64-bit frame. Each individual channel is encoded in a sub-frame that consists of a 4-bit preamble, followed by 24 bits of audio data and 4 control bits, in a total of 32 bits per sub-frame. The SPDIF-AES/EBU standard provides for LSB first, up to 24-bit audio samples, Samples of 20 bits or less may be used, in which case the 4 least significant bits may be used for a 12-bit monitoring channel, transmitted at 1/3 of the sample rate. Please refer to the SPDIF-AES/EBU, AES3 or IEC958 standard documentation for more information. Features • • • • • F eed-forward operation: extracts audio data from the SPDIF-AES/EBU input signal by sampling it with a fast clock signal which not necessarily related to the sample rate frequency P urely digital receiver solution, without need of an input PLL for synchronisation. T he audio samples are output serially in I2S format. P LL interface to filter out the jitter and generate a jitter-free I2S output. R ecognizes all common audio and video related sample frequencies and outputs a nibble code for each. 7.3.9.1 SPDIF register description Table 48 SPDIF status register Name I2SIN_SPDIF_STATUS Base AS3525_I2SIN_BASE Default 0x00 Offset: 0x0018 SPDIF status signals register T his read-only register contains status information of the SPDIF interface. The spdif_sample_freq and spdif_sync status bits are directly derived from the SPDIF converter. In order to provide valid status bits, these signals must be synchronized with pclk, i.e. clk_i2sin. Default Access R R Bit Description Incoming sample frequency Recognition of sub-frame preamble 0: first sub-frame preamble not recognized 1: successful recognition of the first sub-frame preamble Bit 4 :1 0 Bit Name spdif_sample_freq s pdif_sync The following table shows the input sample rate in KHz according to the sample_freq_code (bit 5 to 1) in the I2SIN_SPDIF register. sample_freq_code 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Input Sample Rate (KHz) 22.050 24.000 32.000 44.100 48.000 64.000 88.200 96.000 176.400 192.000 © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 65 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.10 I2SOUT - I2S output interface The I2S output interface module (called I2SOUTIF module hereafter) is used to connect the processor system to an audio DAC. The communication is based on the standardized I2S interface. The audio samples are transferred from the processor to the I2SOUTIF module using the AMBA APB bus. A FIFO for 128 dual-channel audio samples is provided as a data buffer. Furthermore, the module provides a set of data, control and status registers. The I2SOUTIF provides the following features: • • • • • • • t wo independent clock domains: AMBA APB clock PCLK, I2S output clock i2so_mclk F IFO (128 words with 36 bit) separating clock domains s upport of 16 and 18 bit audio samples c lock generator for I2S clocks (LCLK, I2SO_SCLK) s upport of several oversampling rates: 128x, 256x, 512x i nterrupt support for FIFO data write D MA support for FIFO data transfer For data output, following modes are implemented: • • • • t wo 18 bit audio samples, one for each channel (R,L). The values are written to I2SO_DATA. t wo 16 bit audio samples, one for each channel (R,L). Both values are written to the 32-bit wide I2SO_DATA register at the same time. This mode is highly efficient for 32-bit processor architectures. o ne 18 bit mono audio sample; the sample is used for both channels (R and L). The value is written to the I2SO_DATA. o ne 16 bit mono audio sample; the sample is used for both channels (R and L). The value is written to the I2SO_DATA. Figure 28 I2SO Block Diagram 7.3.10.1 I2S Output Interface Registers Table 49 I2S Output Interface Registers Base Address AS3525_I2SOUT_BASE AS3525_I2SOUT_BASE AS3525_I2SOUT_BASE AS3525_I2SOUT_BASE AS3525_I2SOUT_BASE AS3525_I2SOUT_BASE Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 Control register Interrupt mask register Raw status register Status register Interrupt clear register Audio data register Note Register Name I2SOUT_CONTROL I2SOUT_MASK I2SOUT_RAW_STATUS I2SOUT_STATUS I2SOUT_CLEAR I2SOUT_DATA © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 66 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 50 I2SOUT control register Name I2SOUT_CONTROL Offset: 0x0000 Bit 6 Bit Name D MA_req_en Base AS3525_I2SOUT_BASE Default 0x0C Control register 7 b it wide read/write register containing the control bits of the I2SOUTIF. Default 0 Access R/W Bit Description DMA request enable 0: disable 1: enable I2SDATA loopback from I2SINIF 0: I2SOUT_SDATA source is I2SOUTIF’s FIFO 1: I2SOUT_SDATA source is loopback value from I2SINIF (signal I2SIN_FDATA) Invert MCLK 0: disable (SCLK changes at MCLK’s falling edge) 1: enable (SCLK changes at MCLK’s rising edge) Audio samples provided by processor 0: mono 1: stereo Bit width of audio samples provided by processor 0: 16 bit 1: 18 bit Oversampling rate 00: 128x 01: 256x 10: 512x 11: 128x 5 s data_lb 0 R/W 4 m clk_invert 0 R/W 3 s tereo_mode 1 R/W 2 1 8bit_mode 1 R/W 1 ,0 osr 00 R/W CAUTION: The control bit sdata_lb can only be set, if the I2SIN_FSDATA is synchronous to I2SOUT_SCLK. This is the case if AFE is used together with the AS3525 (in this case the I2SINIF uses also I2SOUT_CLK). Table 51 I2S Output mask register Name I2SOUT_MASK Offset: 0x0004 Bit 7 6 5 4 3 2 1 0 Bit Name r eserved I 2SOUT_MASK_POER I 2SOUT_MASK_PUE I 2SOUT_MASK_PUAE I 2SOUT_MASK_PUHF I 2SOUT_MASK_PUAF I 2SOUT_MASK_PUF I 2SOUT_MASK_PUER Base AS3525_I2SOUT_BASE Default 0x00 Interrupt mask register T he interrupt mask register determines which status flags generate an interrupt by setting the corresponding bit to 1. Default 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit Description stereo18_status cannot assert interrupt request 1 enables the FIFO POP error interrupt 1 enables the FIFO PUSH is empty interrupt 1 enables the FIFO PUSH is almost empty interrupt 1 enables the FIFO PUSH is half full interrupt 1 enables the FIFO PUSH is almost full interrupt 1 enables the FIFO PUSH is full interrupt 1 enables the FIFO PUSH error interrupt © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 67 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 52 I2S output raw status register Name I2SOUT_RAW_STATUS Base AS3525_I2SOUT_BASE Default 0x00 Offset: 0x0008 Raw status register T he read-only raw status register contains the actual bit values as reflected by the FIFO controller status signals. I2SOUT_POER and I2SOUT_PUER are static bits, since FIFO controller gives the PUSH/POP error bit only for one clock. This means that these two bits remain asserted until they are cleared in the I2SOUT_CLEAR register. All other bits change state depending on the underlying logic, i.e. state of FIFO controller. Default 0 Access R Bit Description Status of write interface for 18 bit stereo mode 0: left audio sample is expected next 1: right audio sample is expected next 1 if FIFO POP error 1 if FIFO PUSH is empty 1 if FIFO PUSH is almost empty 1 if FIFO PUSH is half full 1 if FIFO PUSH is almost full 1 if FIFO PUSH is full 1 if FIFO PUSH error Bit 7 Bit Name s tereo18_status 6 5 4 3 2 1 0 I 2SOUT_POER I 2SOUT_PUE I 2SOUT_PUAE I 2SOUT_PUHF I 2SOUT_PUAF I 2SOUT_PUF I 2SOUT_PUER 0 0 0 0 0 0 0 R R R R R R R Table 53 I2S output status register Name I2SOUT_STATUS Base AS3525_I2SOUT_BASE Default 0x00 Offset: 0x000C Status register T he status register is a read-only register. A read to this register returns the value of the raw status bits AND’ed with the corresponding mask of enable bits set in the mask register. Default 0 Access R Bit Description Status of write interface for 18 bit stereo mode 0: left audio sample is expected next 1: right audio sample is expected next 1 if FIFO POP error 1 if FIFO PUSH is empty 1 if FIFO PUSH is almost empty 1 if FIFO PUSH is half full 1 if FIFO PUSH is almost full 1 if FIFO PUSH is full 1 if FIFO PUSH error Bit 7 Bit Name s tereo18_status 6 5 4 3 2 1 0 I 2SOUT_POER I 2SOUT_PUE I 2SOUT_PUAE I 2SOUT_PUHF I 2SOUT_PUAF I 2SOUT_PUF I 2SOUT_PUER 0 0 0 0 0 0 0 R R R R R R R © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 68 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 54 I2S output interrupt clear register Name I2SOUT_CLEAR Base AS3525_I2SOUT_BASE Default 0x00 Offset: 0x0010 Interrupt clear register T he interrupt clear register is a write-only register. The corresponding static status bit can be cleared by writing a 1 to the corresponding bit in the clear register. All other interrupt flags are level interrupts depending on the status of the FIFO. The bits are de-asserted depending on the FIFO controller. Default Access W W W W Bit Description Clear POP error interrupt flag Clear PUSH error interrupt flag Bit 7 6 5 :1 0 Bit Name r eserved I 2SOUT_clear_poer reserved I 2SOUT_clear_puer I2SOUT_DATA The I2SOUTIF provides two 32 bit wide data registers. The registers are used to store the audio samples before they are written to the FIFO. The registers can be used in different modes depending on the setting of the I2SOUT_CONTROL register. Basically, there are four ways to fill the FIFO. The processor can provide • • t wo 18 bit audio samples, one for each channel (R,L). The values are written to I2SOUT_DATA. t wo 16 bit audio samples, one for each channel (R,L). Both values are written to the 32-bit wide I2SOUT_DATA register at the same time. This mode is highly efficient for 32-bit processor architectures. • o ne 18 bit mono audio sample; the sample is used for both channels (R and L). The value is written to the I2SOUT_DATA. • o ne 16 bit mono audio sample; the sample is used for both channels (R and L). The value is written to the I2SOUT_DATA. In 18 bit stereo mode the data in I2SOUT_DATA is interpreted either as left or right audio value. The stereo18_status bit in the I2SOUT_STATUS register provides the information which channel’s audio sample is expected next. The I2S Output Signals The following specifications signals are given: • • D ata are valid at the rising edge of I2SO_SCLK. T he MSB is left justified to the I2S frame identification (I2SO_LRCK). According to standard I2S definition, a delay of one clock cycle between transition of I2SO_LRCK and the data MSB is used. The timing diagram of the I2S interface signals for 18bit and 16bit DAC is shown below. Tperiod(fsaudio) / 2 Tperiod(fsaudio) / 2 I2SO_MCLK I2SO_LRCK I2SO_SCLK I2SO_SDATA 16 bit Left Channel Right Channel 15 2 1 0 15 2 1 0 I2SO_SDATA 18 bit 17 2 1 0 17 2 1 0 Figure 29 - I2S output timing diagram © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 69 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential For the relationship of the clocks following constraints must be met: • • LRCK must change with the falling edge of MCLK while MCLK is low (constrained should be set to 40 % of the MCLK period, see figure below). SDATA must change at the falling edge of SCLK. It will be read with the rising edge of SCLK. Figure 30 Clock constraints I2SO_MCLK Lrck must change with falling edge, within 40 % of MCLK period I2SO_LRCK I2SO_SCLK Sampling of I2S data by Cello IF with rising edge of SCLK I2SO_SDATA L15 L14 R15 R14 7.3.10.2 Power Modes The I2SOUTIF contains two clock domains. Each clock domain can be turned off separately. The I2SO_MCLK must be turned off in the global clock controller register. This is necessary, as the audio chip requires I2SO_MCLK and I2SO_SCLK not only for I2S output, but also I2S input (see I2SINIF). PCLK Idle Mode If the PCLK is turned off (by the clock controller) the I2SOUT_STATUS register can hold invalid data. However, no interrupt should be triggered if the I2SOUTIF is in idle mode. I2SO_MCLK Idle Mode If I2SO_MCLK is disabled (by the clock controller) no audio samples are read from the FIFO. The output signals remain unchanged until the I2SO_MCLK is enabled again. 7.3.10.3 Loopback Feature On the AS3525 are two I2S interfaces: • • I 2SOUTIF is responsible to send values to the DAC of the audio chip via I2SO_SDATA I 2SINIF is responsible to receive audio values from ADC of the audio chip via I2SI_SDATA In the AS3525 both SDATA signals are provided as loopback signals (I2SO_FSDATA, I2SI_FSDATA): I 2SO_SDATA to I2SINIF: This loopback is mainly for testing the transmission and reception paths of both I2S interfaces. The loopback signal is called I2SO_FSDATA. • I 2SI_SDATA to I2SOUTIF: This loopback feature allows the application to echo the input audio samples directly to a loudspeaker. The signal provided by the I2SINIF is called I2SI_FSDATA. In normal mode the I2SOUTIF generates the I2SO_SDATA signal based on the contents of the FIFO. If the loop back feature is enabled, the SDATA_LB bit in the I2SOUT_CONTROL register must be set. NOTE: This feature will only be available if SCLK is the same for I2S input and output interface. For implementation the I2SI_FSDATA signal is simply routed through a multiplexer to the I2SO_SDATA interface. • © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 70 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.10.4 DMA Interface The I2SOUTIF supports DMA transfers. The DMA controller supports incrementing and non-incrementing (single address) addressing for source and destination. For I2SOUTIF the single-address mode is used. The address of the I2SOUT_DATA register is used as DMA destination address. Stereo 18 bit DMA Mode In 18 bit stereo mode, right and left audio samples must be transferred separately to the FIFO. In single-address DMA-mode both data must be written to the same address. The I2SOUTIF is responsible to put the two 18 bit samples together to a 36 bit word. This word is written into the 36 bit wide FIFO. The I2SOUTIF requires a specific ordering of the samples written to the I2SOUT_DATA register: first the left value must be written, and afterwards the DMA controller must write the right value. Then a left value can follow, a.s.o. The status bit stereo18_status shows which audio sample is expected. In order to set up a correct DMA transfer the values must be placed in the source memory as follows: Address addr 0 addr 1 addr 2 addr 3 … addr n*2 addr n*2+1 LDATA 0 RDATA 0 LDATA 1 RDATA 1 … LDATA n RDATA n Value © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 71 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.11 NAND Flash Interface The NAND FLASH interface module enables control of NAND flash devices. The design follows the hardware reference implementation described in SMIL (SmartMediaTM Interface Library), Hardware Edition 1.00, TOSHIBA Corporation, but has extensions to support the latest generation of NAND flash devices. Programming and Reading can be done either by direct access to/from data register (normal mode) or by using a FIFO (burst mode). NAF supports 8-bit and 16-bit transfers. Features • • • • • • • • • • • • • • • i nterface compliant to AMBA APB bus g eneration of interrupt request signal with several maskable interrupt sources (ready, empty, almost_empty…) h ardware error detection (2 detect, 1 correct per 256 bytes block) for up to 8 *256 bytes (up to 24 ECC bytes) 8 -bit and 16-bit transfer Mode fore X8/X16 devices b ig endian / little endian support D MA Mode N ormal Mode D ata/Mode/Status Register w rite/read on/from data register automatically generates read/write strobes B urst Transfer 3 6 x 32 bit FIFO for DMA/burst support r ead- & write controller for automatic data resizing (32bit 8/16bit) and read/write control c onfigurable strobe (low and high time) for higher PCLK clocks / lower speed NAND Flash devices l ittle endian/ big endian selectable l oad interrupts when FIFO is ‘almost_empty’ & ’almost_full’ to ensure continuous data flow Figure 31 Block Diagram of NAND Flash Interface © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 72 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Figure 32 Connecting a NAND Flash 7.3.11.1 NandFlash Interface Registers Table 55 NAF registers Register Name N AFCONFIG N AFCONTROL N AFECC N AFDATA N AFMODE N AFSTATUS N AFMASK N AFFIFODATA N AFWORDS N AFCLEAR N AFTEST Base Address AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 Configuration register Control register Error correction code reg Data register Mode register Status register Interrupt mask register buffered read/write data register Words register Interrupt clear register Test register Note © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 73 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 56 NAF configuration register Name NAFConfig Base AS3525_NAND_FLASH_BASE Default 0x00 Offset 0x0000 NAF Configuration Register T he register is used for basic setup. 8 or 16-bit data width, little or big endian can be selected. DMA and FIFO on/off can be controlled as well as duty cycle and duration of read & write signals. Default 0x00 Access R/W Bit Description low time (# of PCLK cycles + 1) of the output ‘naf_we_n’ (e.g. a value of 1 will keep naf_we_n at ‘0’ for 3 PCLK cycles during write) high time (# of PCLK cycles + 2) of the output ‘naf_we_n’ (e.g. a value of 0 will keep naf_we_n at ‘1’ for 2 PCLK cycles during write) low time (# of PCLK cycles + 1) of the output ‘naf_re_n’ (e.g. a value of 2 will keep naf_re_n at ‘0’ for 3 PCLK cycles during read) high time (# of PCLK cycles + 2) of the output ‘naf_re_n’ (e.g. a value of 0 will keep naf_re_n at ‘1’ for 2 PCLK cycles during read) 0: DMA is disabled and all DMA request signals are tied to 1: DMA is enabled 0: FIFO is reset 1: FIFO is enabled 0: little endian (FIFO data word will be processed in the order word(7:0), word(15:8), word(23:16) and word(31:24) when x16_device is 0; word(15:0) and word(31:16) when x16_device is 1 1: big endian (FIFO data word will be processed in the order word(31:24), word(23:16), word(15:8) and word(7:0) when x16_device is 0; word(31:16) and word(15:0) when x16_device is 1 Note: big_endian is only supported for r/w access through register NAFFifodata 0: X8 Device (for NAND flash with 8-bit data bus) 1: X16 Device (for NAND flash with 16-bit data bus) Bit 1 9:16 Bit Name write_strobe_low [3:0] 1 5:12 write_strobe_high [3:0] 0x00 R/W 1 1:8 read_strobe_low [3:0] 0x00 R/W 7 :4 read_strobe_high [3:0] 0x00 R/W 3 d ma_on 0x0 R/W 2 f ifo_staticreset_n 0x0 R/W 1 b ig_endian 0x0 R/W 0 x 16_device 0x0 R/W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 74 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 57 NAF control register Name NAFControl Offset 0x0004 Bit 1 Bit Name r ead_strobe Base AS3525_NAND_FLASH_BASE NAFControl Register T he NAFControl register controls read access and FIFO dynamic reset. Default 0x1 Access W Bit Description 1: triggers a FIFO reset pulse (when NAFConfig bit ‘fifo_staticreset_n’ is 1) The bit is cleared automatically in the next PCLK cycle. 1: triggers one single read cycle on output ‘naf_re_n’. The bit is cleared automatically in the next PCLK cycle. Default 0x2 0 f ifo_reset_strobe 0x1 W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 75 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 58 NAF error correction register Name NAFEcc Offset 0x0008 Bit Bit Name Base AS3525_NAND_FLASH_BASE NAF Error correction code register T he NAFEcc register offers access to the error correction code registers. Default Access Bit Description This register can be accessed up to 8 times and contains the following data: 1.access => Line Parity Block1 2.access => Column Parity Block1** 3.access => Line Parity Block2 4.access => Column Parity Block2** 5.access => Line Parity Block3 6.access => Column Parity Block3** 7.access => Line Parity Block4 8.access => Column Parity Block4** (9.access => same as 1.access) Default 0x2 3 2:0 Nafecc [32:0] 0x0001 R N ote: * Before access to NAFEcc registers is possible, NAFMode register has to be set to 0xd4 (after page write operation) or to 0x54 (after page read operation). NAFEcc register contents will be cleared if NAFMode register bits 6 and 5 are both ‘1’. ** Only bits 11 to 0 are relevant for column parity, other bits are ‘0’; The content of NAFEcc depends on the device type. X8 (8-bit data bus) devices: Line Parity Block1 : will contain the line Column Parity Block1 : will contain the column Line Parity Block2 : will contain the line Column Parity Block2 : will contain the column Line Parity Block3 : will contain the line Column Parity Block3 : will contain the column Line Parity Block4 : will contain the line Column Parity Block4 : will contain the column X16 (16-bit data bus) devices: Line Parity Block1 : will contain the line Column Parity Block1 : will contain the column Line Parity Block2 : will contain the line Column Parity Block2 : will contain the column Line Parity Block3 : will contain the line Column Parity Block3 : will contain the column Line Parity Block4 : will contain the line Column Parity Block4 : will contain the column parity of halfword(7:0) 1 to 512 (after 512 r/w cycles) parity of halfword(7:0) 1 to 512 (after 512 r/w cycles) parity of halfword(15:8) 1 to 512 (after 512 r/w cycles) parity of halfword(15:8) 1 to 512 (after 512 r/w cycles) parity of halfword(7:0) 513 to 1024 (after 1024 r/w cycles) parity of halfword(7:0) 513 to 1024 (after 1024 r/w cycles) parity of halfword(15:8) 513 to 1024 (after 1024 r/w cycles) parity of halfword(15:8) 513 to 1024 (after 1024 r/w cycles) parity of byte 1 to 512 (after 512 r/w cycles) parity of byte 1 to 512 (after 512 r/w cycles) parity of byte 513 to 1024 (after 1024 r/w cycles) parity of byte 513 to 1024 (after 1024 r/w cycles) parity of byte 1025 to 1536 (after 1536 r/w cycles) parity of byte 1025 to 1536 (after 1536 r/w cycles) parity of byte 1537 to 2048 (after 2048 r/w cycles) parity of byte 1537 to 2048 (after 2048 r/w cycles) Note: Read ECC is not performed in unbuffered READ mode (this means when CPU accesses the Nand Flash through the NAF_DATA registers) © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 76 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 59 NAF data register Name NAFData Offset 0x000C Bit 1 5:0 Bit Name NAFData Base AS3525_NAND_FLASH_BASE Default 0x0000 Data Register T he NAFData register offers unbuffered access to the data bus of the NAND flash device. Default 0x01 Access R/W Bit Description For X8 devices (8-bit data bus) only bits 7:0 are relevant, other bits are ignored For X16 devices (16-bit data bus) all are relevant Table 60 NAF mode register Name NAFMode Offset 0x0010 Bit 7 Bit Name w rite protection Base AS3525_NAND_FLASH_BASE Mode register T he NAFMode register controls NAND flash read/write/erase procedures. Default 0x0 Access R/W Bit Description 0: write protection is on 1: write protection is off (when ‘power_on’ is 1) 0: error code correction disabled 1: error code correction enabled (when ‘ce’ is 1) 2: stop error code correction, disable read/write strobes and disable ‘naf_do’ (when ‘ce’ is 1). Use this mode when reading the NAFEcc register 3: Reset NAFEcc register contents, ‘ecc’ changes to value 1 (enable mode) automatically after the next PCLK cycle controls ‘chip enable’ 0: output ‘naf_ce_n’ is set to ‘1’ (device is disabled) 1: output ‘naf_ce_n’ is set to ‘0’ (device is enabled) always ‘0’ Default 0x00 6 :5 ecc [1:0] 0x0 R/W 4 ce 0x0 R/W 3 - 0 x0 R 2 p ower_on 0x0 R/W 0: power off (all output enable signals are turned off) 1: power on controls ‘address latch enable’ 0: output ‘naf_ale’ is set to ‘0’ 1: output ‘naf_ale’ is set to ‘1’ (Address Latch Cycle) controls ‘command latch enable’ 0: output ‘naf_cle’ is set to ‘0’ 1: output ‘naf_cle’ is set to ‘1’ (Command Latch Cycle) 1 a le 0x0 R/W 0 c le 0x0 R/W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 77 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 61 NAF status register Name NAFStatus Offset 0x0014 Bit Bit Name Base AS3525_NAND_FLASH_BASE Status Register T he NAFStatus register contains information on the internal status. Defau lt Access Bit Description FIFO error signal 0: if FIFO is reset 1: if FIFO contains 36 words and FIFO push(write) has occurred or when FIFO contains 0 words and a FIFO pop(read) has occurred. The FIFO error will lock the FIFO and has to be reset by a reset of the FIFO (by setting NAFControl register bit 1 to ‘1’) FIFO full signal 0: if FIFO contains less than 36 words 1: if FIFO contains 36 words FIFO almost_full signal 0: if FIFO contains less than 32 words 1: if FIFO contains more than or equal 32 words FIFO almost_empty signal 0: if FIFO contains more than 4 words 1: if FIFO contains less than or equal 4 words FIFO empty signal 0: if FIFO contains more than 0 words 1: = when FIFO contains 0 words read/write strobe ready signal 0: if read/write strobe ‘0’ (strobe active) 1: if read/write strobe ‘1’ (strobe inactive) synchronised NAND flash ready signal 0: if synchronised input ‘naf_busy_in_n’ is ‘0’ (busy) 1: if synchronised input ‘naf_busy_in_n’ is ‘1’ (ready) FIFO error indication (edge triggered) 0: if bit 6 of NAFClear register is set to ‘1’ 1: if FIFO contains 36 words and FIFO push(write) occurs or when FIFO contains 0 words and a FIFO pop(read) occurs. FIFO full indication (edge triggered) 0: if bit 5 of NAFClear register is set to ‘1’ 1: if FIFO contains 36. FIFO high indication (edge triggered) 0: if bit 4 of NAFClear register is set to ‘1’ 1: if FIFO gets full (36 words) or changes from 31 to 32 words (and when the NAFWords register is greater than 32). Note: When this bit gets ‘1’ during ‘Page Read’ mode, a new FIFO burst read of up to 32 words is possible. FIFO low indication (edge triggered) 0: if bit 3 of NAFClear register is set to ‘1’ 1: if FIFO gets empty or changes from 5 to 4 words (and when the NAND Flash requires more than 32 bytes/halfwords). Note: When this bit gets ‘1’ during ‘Page Programming’ mode, a new FIFO burst write of up to 32 words is possible Default - 13 fifo_error 0x0 R 12 fifo_full 0x0 R 11 fifo_almost_full 0x0 R 10 fifo_almost_empty 0x0 R 9 f ifo_empty 0x0 R 8 s trobe_ready 0x0 R 7 f lash_ready 0x0 R 6 g ot_fifo_error 0x0 R 5 g ot_fifo_full 0x0 R 4 g ot_fifo_high 0x0 R 3 g ot_fifo_low 0x0 R © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 78 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Name NAFStatus Offset 0x0014 Bit Bit Name Base AS3525_NAND_FLASH_BASE Status Register T he NAFStatus register contains information on the internal status. Defau lt Access Bit Description NAFWords empty and Controller ready indication (edge triggered) 0: when bit 2 of NAFClear register is set to ‘1’ 1: when read/write strobe changes from ‘0’ to ‘1’ (end of strobe) and NAFWords register has become empty. Note: This bit is used to detect the end of a multiple read/write burst transaction Read/write strobe ready indication (edge triggered) 0: when bit 1 of NAFClear register is set to ‘1’ 1: when read/write strobe changes from ‘0’ to ‘1’ (end of strobe) Note: read/write strobes can last from 3 to 33 PCLK cycles depending on NAFConfig settings. NAFWords empty and Controller ready indication (edge triggered) 0: when bit 2 of NAFClear register is set to ‘1’ 1: when read/write strobe changes from ‘0’ to ‘1’ (end of strobe) and NAFWords register has become empty. Note: This bit is used to detect the end of a multiple read/write burst transaction Default - 2 g ot_empty_and_rdy 0x0 R 1 g ot_strobe_ready 0x0 R 0 g ot_flash_ready 0x0 R © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 79 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 62 NAF interrupt mask register Name NAFMask Offset 0x0018 Bit 6 Bit Name m ask6 Base AS3525_NAND_FLASH_BASE Interrupt Mask Register T he NAFMask register is used to mask/enable the internal interrupt requests. Default 0x1 Access R/W Bit Description Mask ‘FIFO error indication’ interrupt request 0: enable 1: masked Mask ‘FIFO full indication’ interrupt request 0: enable 1: masked Mask ‘FIFO high indication’ interrupt request 0: enable 1: masked Mask ‘FIFO low indication’ interrupt request 0: enable 1: masked Mask ‘NAFWords empty and Controller ready indication’ interrupt request 0: enable 1: masked Mask ‘Read/write strobe ready indication’ interrupt request 0: enable 1: masked Mask ‘NAND flash ready indication’ interrupt request 0: enable 1: masked Default 0x0018 5 m ask5 0x1 R/W 4 m ask4 0x1 R/W 3 m ask3 0x1 R/W 2 m ask2 0x1 R/W 1 m ask1 0x1 R/W 0 m ask0 0x1 R/W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 80 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 63 NAF FiFo Data register Name NAFFifodata Offset 0x001c Bit Bit Name Base AS3525_NAND_FLASH_BASE FIFO Data Register T he NAFFifodata register offers access to the internal FIFO. Default Access Bit Description Writing this register will push a word on the FIFO and the write address will be incremented by 1. When the FIFO is full (36 words) then a write access on the register is ignored and the FIFO ERROR status bit is set. Reading on this register will pop a word from the FIFO and the read address will be incremented by 1. When the FIFO is empty then a read access on the register is ignored and the FIFO ERROR status bit is set. Default 0x0000 3 2:0 Fifodata [32:0] - R/W Table 64 NAF interrupt mask register Name NAFWords Offset 0x0020 Bit 3 2:0 Bit Name Words [32:0] Base AS3525_NAND_FLASH_BASE Default 0x0000 Interrupt Mask Register T he NAFWords register informs the controller about the maximum words to be transferred and controls the FIFO transfer both in interrupt and DMA mode. Default 0x0000 Access R/W Bit Description 0: FIFO based data transfer is disabled not 0: FIFO transfer is in progress Note: For page transfers (program or read) the initial number of words depends on the NAND flash device. For a page size of 512 bytes, an initial word value of 512/4 = 128 has to be written. For a page size of 2k bytes, an initial word value of 512 has to be used. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 81 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 65 NAF interrupt clear register Name NAFClear Offset 0x0024 Bit 6 Bit Name c lear6 Base AS3525_NAND_FLASH_BASE Default 0x0018 Clear Register T he NAFClear register clears interrupt status information and re-enables interrupt detection. Default Access W Bit Description Reset of ‘FIFO error indication’ status bit 0: no action 1: bit 6 of NAFStatus is reset and interrupt 6 detection is enabled Reset of ‘FIFO full indication’ status bit 0: no action 1: bit 5 of NAFStatus is reset and interrupt 5 detection is enabled Reset of ‘FIFO high indication’ status bit 0: no action 1: bit 4 of NAFStatus is reset and interrupt 4 detection is enabled Reset of ‘FIFO low indication’ status bit 0:no action 1:bit 3 of NAFStatus is reset and interrupt 3 detection is enabled Reset of ‘NAFWords empty and Controller ready indication’ status bit 0:no action 1:bit 2 of NAFStatus is reset and interrupt 2 detection is enabled Reset of ‘Read/write strobe ready indication’ status bit 0: no action 1: bit 1 of NAFStatus is reset and interrupt 1 detection is enabled Reset of ‘Read/write strobe ready indication’ status bit 0:no action 1: bit 0 of NAFStatus is reset and interrupt 0 detection is enabled 5 c lear5 - W 4 c lear4 - W 3 c lear3 - W 2 c lear2 - W 1 c lear1 - W 0 c lear0 - W Table 66 NAF test register Name NAFTest Base AS3525_NAND_FLASH_BASE Test Register T he NAFTest register is used for functional tests of the FIFO. Default Access W Bit Description 0: default mode 1: disables FIFO access by the internal controller => FIFO is accessed by APB interface only 0: default mode 1: data word both on FIFO input and output is inverted Default 0x0000 Offset 0x0028 Bit 1 Bit Name d atainvert 0 f ifotest - W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 82 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.12 DBOP - Data Block Output Port Purpose of this ARM APB peripheral module is a high-speed data output port that can support data transfer to various display controllers based on synchronous control interfaces. Programmability of polarity and timing of the generated control signals makes it possible to support various kinds of displays. Example of a supported display controller is the Hitachi HD77766R LCDE controller. From the programmers point of view the DBOP module can be serviced by DMA accesses. With the large size of the data FIFO and the programmable interrupt request conditions the overhead for SW is minimised. Simple read instructions to read for example a status register of the LCD controller are also supported. The usage of this cell results in a great performance boost compared to the standard ARM GPIO PrimeCell™ architecture. Features • • • • • • • • • • • A PB bus interface s upport for direct memory access (DMA) d ata output FIFO with 128 words (32 bit wide) 8 o r 16 bit parallel data output (configurable) 4 c ontrol outputs - flexible programming of the signal waveforms with respect to polarity and timing p rogrammable even/odd control output generation 8 o r 16 bit parallel data input register with programmable read strobe p rogrammable conditions for interrupt generation based on FIFO flags u sage of FIFO for simple division of APB clock domain and output clock domain p rogrammable data output rate in range of 0.05 to 4 MHz A PB Clock & DBOP Clocks are synchronous. Figure 33 DBOP Block Diagram DBOP FiFo 128x32 Dual ported RAM 128x32 PRESETn PSEL PENABLE PWRITE PADDR[11:2] PWDATA[31:0] PRDATA[7:0] PCLK 32 32 Amba APB Interface Dout register lb_select, hb_select dbop_d[7:0] / xpc[7:0] dbop_d[11:8] / xpb[7:4] push FiFo push status pop symetric FiFo Controller dbop_d[15:12] FiFo pop status c0 / xpb[0] Control Signal Generator c1 / xpb[1] c2 / xpb[2] c3 / xpb[3] Register Block dinStrobe dataValid 8 Din register din[7:0] DBOPDMASREQ DBOPDMABREQ DBOPDMACLR DMA Interface Interrupt Generator DBOPIRQ dbop_clk © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 83 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.12.1 DBOP register definitions Table 67 DBOP Registers Register Name D BOP_TIMPOL_01 D BOP_TIMPOL_23 D BOP_CTRL_REG D BOP_STAT_REG D BOP_DOUT_REG D BOP_DIN_REG Base Address AS3525_DBOP_BASE AS3525_DBOP_BASE AS3525_DBOP_BASE AS3525_DBOP_BASE AS3525_DBOP_BASE AS3525_DBOP_BASE Offset 0x00 0x04 0x08 0x0C 0x10 0x14 Note Timing and polarity for control 0 and 1 Timing and polarity for control 1 and 2 Control Register Status Register Data output register Data input register Timing & Polarity Control register TPC01 This register contains all information necessary for definition of control signals C0 and C1. Table 68 DBOP control registers C0 and C1 Register bits 31 30 29 2 8:24 2 3:19 18 17 16 15 14 13 1 2:8 7 :3 2 1 0 Name c1_p0 c1_p1 c1_p2 c1_t1 c1_t2 c1_ev c1_od c1_qs c0_p0 c0_p1 c0_p2 c0_t1 c0_t2 c 0_ev c 0_od c 0_qs type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function polarity 1 polarity 2 polarity 3 Time 1 Time 2 even enable odd enable quiescent state polarity 1 polarity 2 polarity 3 Time 1 Time 2 even enable odd enable quiescent state default value 0 1 0 0xA 0x14 1 1 0 0 1 0 0xA 0x14 1 1 0 Timing & Polarity Control register TPC23 This register contains all information necessary for definition of control signals C2 and C3. Table 69 DBOP control registers C2 and C3 Register bits 31 30 29 2 8:24 2 3:19 18 17 16 15 14 13 1 2:8 7 :3 2 1 Name c3_p0 c3_p1 c3_p2 c3_t1 c3_t2 c3_ev c3_od c3_qs c2_p0 c2_p1 c2_p2 c2_t1 c2_t2 c 2_ev c 2_od type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function polarity 1 polarity 2 polarity 3 Time 1 Time 2 even enable odd enable quiescent state polarity 1 polarity 2 polarity 3 Time 1 Time 2 even enable odd enable default value 0 1 0 0xA 0x14 1 1 0 0 1 0 0xA 0x14 1 1 © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 84 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 0 c 2_qs r/w quiescent state 0 Table 70 DBOP control register Register bits 3 1:22 21 20 Name type function r eserved I nterrupt clear signal for pop error interrupt I nterrupt clear signal for push error interrupt T ri-state enable for dout bus s hort count bit reset to even cycle enable write start read output serial mode default value 0 0 W riting 1 to this bit will clear the pop error interrupt. Writing 0 has no effect. W riting 1 to this bit will clear the push error interrupt. Writing 0 has no effect . W hen set, dout bus is tri-stated when there is no active write on the bus. when set, next output cycle is even 0: write disabled 1: write enabled 0: 1: 2: 0: 1: 0: 1: single word out 2 serial words out 4 serial words out 8 bit data width 16 bit data width all IR disabled IR enabled clr_pop_err clr_push_err W W 19 18 17 16 15 1 4:13 en_data sdc res_even enw strd osm r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 12 11 10 9 8 7 6 5 4 :0 ow ir_enable ir_po_err i r_pu_err i r_e_en i r_ae_en i r_af_en i r_f_en rs_t r/w r/w r/w r/w r/w r/w r/w r/w r/w output data width IR enable IR enable on pop error IR enable on push error IR enable set on push empty IR enable set on push almost empty IR enabbe set on push almost full IR enable set on push full read strobe time 0 0 0 0 0 0 0 0x1F Notes: If the start read bit is issued by setting the strd bit to 1, a single read cycle is generated. After this read cycle the strd bit is set to 0 again by HW. If write is enabled by setting enw=1, no read is possible (strd does not cause any action). res_even is a reset bit that defines the start of even/odd generated signals. With res_even bit set, the next output cycle is a even cycle. Within this first even output cycle the res_even bit is set to 0 by the SW. sdc selects the counter length for the timing generator. Default is end value of 31. With sdc set to 1, the count end value is 15. en_data is used as a tri-state enable for the dout bus . When set as 1, dout is tri-stated if there is no active write on the bus . When this bit is set as 0, dout is bus is tri-stated only during the read cycle. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 85 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 71: DBOP status register Register bits 3 1:17 16 1 5:12 11 10 9 8 7 6 5 4 3 2 1 0 Name type function r eserved read data valid push error push fifo empty push fifo almost empty push fifo half full push fifo almost full push fifo full pop error pop fifo empty pop fifo almost empty pop fifo half full pop fifo almost full pop fifo full default value rd_d_valid Reserved fi_pu_err fi_pu_e f i_pu_ae f i_pu_hf f i_pu_af f i_pu_f f i_po_err f i_po_e f i_po_ae f i_po_hf f i_po_af f i_po_f r f r r r r r r r r r r r The read data valid flag is cleared with every start read and set after read data strobe is issued (at read data valid 1 the data can be readout by SW). Data Output Register 32 bit register for data output - the data written to this register are directly written to the FiFo. Depending on the serial output mode and the output data width, the effective register width of this register is 8, 16 or 32 bits. Following table shows the effective data width for this register: o sm=0 8 (byte0) 16 (HW0) o sm=1 16 (byte0, byte1) 32 (HW0, HW1) o sm=2 32 (byte0, byte1, byte2, byte3) 32 (HW0, HW1) o dw = 0 o dw = 1 Depending on odw, • either one, two or four bytes are transmitted serially for odw=0 • or one or two half words (HW = 16 bits) are transmitted serially for odw=1. Note that for the 8 or 16 bit width only a part of the FiFo memory is used (to keep HW design simple). Data Input Register 16 bit data input register that holds the value of the last read cycle. It is only valid if the data valid flag is set in the status register. No interrupt support is given, for data input the read data valid flag must be polled. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 86 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Dbop Integration Test Registers The Dbop module is programmed to integration test mode using test control register. The integration test mode enables the user to access all the input/output pins through the APB bus interface. Name D BOPITC D BOPITIP1 DBOPITOP1 Offset 0x18 0x1C 0x20 R/W R/W R/W R Reset Value 0x00000000 0x00 0x0 Description DBOP integration test control register DBOP integration test input register DBOP integration test output register Table 72 DBOPITC test register Register bits 3 1:1 0 Name type function r eserved Integration test enable default value 1 will enable the integration test mode i ten r/w Table 73 DBOPITIP1 test register Register bits 3 1:5 4 3 2 1 0 Name type function r eserved Test value for out_enControl_n Test value for out_enData_n Test value for DMASREQ Test value for DMABREQ Test value for interrupt default value 0 0 0 0 0 T he value on this bit will be reflected in out_enControl_n T he value on this bit will be reflected in out_enData_n T he value on this bit will be reflected in DBOPDMACSREQ T he value on this bit will be reflected in DBOPDMACBREQ The value on this bit will be reflected in DBOPIRQ T estctrloen T estdataoen T estdmasreq T estdmabreq t estirq r/w r/w r/w r/w r/w Table 74 DBOPITOP1 test register Register bits 3 1:1 0 Name type function r eserved D BOPDMACCLR test register. default value 0 R ead of this register will return the value on the DBOPDMACCLR input. T estdmaclr r 7.3.12.2 DBOP DMA Interface This block generates all necessary interface signals with the DMAC primecell for DMA transfer. Following table gives a description of these signals. DBOPDMASREQ DBOPDMABREQ DBOPDMACLR single word request, asserted by DBOP. This signal is asserted when there is at least one empty location in the FiFo burst DMA transfer request, asserted by DBOP. This signal is asserted when there are at least four empty locations in the FiFo DMA request clear, asserted by DMA controller to clear the DMA request signals. If DMA burst transfer is requested, the clear signal is asserted during the transfer of the last data in the burst Symmetric FiFo The FiFo buffer has two main purposes: • data buffering: the FiFo contains 128 locations with 32 bits for data storage: with according DMA transfer, the data can be transferred in short time without need for any SW control © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 87 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential • clock domain crossing: the FiFo is at the boarder of clock domain PCLK and DBOPCLK. All necessary synchronisation is done internally. All flags are available as push flags (synchronised to the push clock PCLK) and pop flags (synchronised to the POP clk, which is synchronous to DBOPCLK. The FiFo controller gives empty, almost empty, half full, almost full and full flags which are available in two fashions: synchronous to the push or the pop side (pop_empty, push_empty, …). 7.3.12.3 Control Signal Generator Four independent control signals can be generated: typical application for such signals is a 80xx interface with RS, RD*, WR* and E or a 68xx interface with RS, E, RWN. The idea of this control signal generator is a general-purpose block, which generates any signal timing/waveform that is necessary to transfer the data to any specific display. Polarity Parameters For each of the control signals c0 - c3 following polarity parameters are defined: • • • p 0 … polarity 0 at start of cycle p 1 … polarity 1 following polarity 0 p 2 … polarity 2 following polarity 1 Following figure shows an example for timing waveforms defined with these control parameters. Figure 34 DBOP timing waveform Tperiod T1 D1 P0, P1, P2 = 000 T2 T1 D2 T2 Static 0 P0, P1, P2 = 001 NRZ 1 P0, P1, P2 = 010 P0, P1, P2 = 011 RZ 1 NRZ 1 P0, P1, P2 = 100 P0, P1, P2 = 101 RZ 1 RO 1 P0, P1, P2 = 110 RZ 1 P0, P1, P2 = 111 Static 1 Quiescent State The control signals are only generated with each data output cycle (data output cycles are generated as long as the FiFo is not empty). With FiFo empty and in the absence of a read cycle, all control signals are set to a quiescent state. For each control signal, this quiescent state can be programmed either to 1 or 0. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 88 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Timing Parameters Also the time points for change from p0-p1 (t1) and p1-p2 (t2) can be programmed. For these programmable timing parameters each data output cycle is divided into 32 steps. Both T1 and T2 can be in the range of 0 to 31. For short count bit set (sdc bit in control register), T1 and T2 must be in the range of 0 to 15. Figure 35 DBOP timing parameters dout Tperiod D0 0 10 20 30 P0, P1, P2 = 0,1,0; T1=6, T2=10 P0, P1, P2 = 1,0,1; T1=14, T2=28 P0, P1, P2 = 0,0,1; T1 FCLK. Default 0x00 Access R/W Bit Description post divider division ratio => post_div = 1/(fclk_postdiv_sel + 1) pre divider (fractional) division ratio 00: pre_div = 1/1 01: pre_div = 7/8 10: pre_div = 6/8 11: pre_div = 5/8 clkin select 00: clk_main 01: plla_fout 10: pllb_fout 11: reserved (clk_main) 3 :2 FCLK_PREDIV_SEL [1:0] 0x00 R/W 1 :0 FCLK_SEL[1:0] 0x00 R/W N OTE: f(fclk) := f(clkin) * pred_div * post_div; © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 107 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 26 Peripheral Clock Controller Register Name CGU_PERI Offset0x14 Bit 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Bit Name MBIST_EN EXTMEM_EN EXTMEMIF_EN 1TRAM_EN ROM_EN VIC_EN DMAC_EN USB_EN I2SO_APB_EN I2SI_APB_EN I2C_EN I2C_AUDIO_EN GPIO_EN SDMCI_EN NANDFLASH_EN UART_EN WDOCNT_EN WDOIF_EN SSP_EN T IMER1_EN T IMER2_EN T IMERIF_EN P CLK_DIV1_SEL 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Base AS3525_CGU_BASE T his register allows setting the peripheral clocks. Default Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Description memory bist manager clock enable external memory clock enable external memory AHB IF clock enable 1TRAM controller AHB IF clock enable ROM AHB IF clock enable vectored interrupt controller AHB IF clock enable DMA controller AHB IF clock enable USB controller AHB IF clock enable I2Sout APB IF clock enable I2Sin APB IF clock enable I2C master/slave APB IF clock enable I2C audio APB IF clock enable general purpose IO APB IF clock enable secure digital/multimedia APB IF clock enable NAND flash/Smart Media APB IF clock enable UART APB IF clock enable watchdog counter clock enable watchdog timer module APB IF clock enable synchronous serial port APB IF clock enable timer module timer1 clock enable timer module timer2 clock enable timer module APB IF clock enable Default 0x0F800000 Peripheral clock controller register division ratio div1 (AHB/APB clock) => div1 = 1/(pclk_div1_sel + 1) PCLK_DIV0_SEL division ratio div0 (ext. memory clock) => div0 = 5 :2 0x0 R/W [3:0] 1/(pclk_div0_sel + 1) clkin select b’00: clk_main 1 :0 PCLK_SEL[1:0] 0x0 R/W b’01: plla_fout b’10: pllb_fout b’11: fclk C AUTION : Clock gating takes effect immediately! Software must assure that all transactions to/from the module are finished before the clock is disabled. C AUTION : The peripheral clock must not exceed 65 MHz. The software must assure that requirement. Note: f(clk_extmem) := f(clkin) * div0; f(pclk) := f(clkin) * div0 * div1; © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 108 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 27 Audio Clock Controller Register Name CGU_AUDIO Offset0x18 Bit 24 23 2 2:14 Bit Name I2SI_MCLK2PAD_EN I2SI_MCLK_EN I2SI_MCLK_DIV_SEL [8:0] Base AS3525_CGU_BASE Audio Clock Controller Register T his register allows setting the audio clock to I2S input and output interface. Default 0 0 0x0 Access R/W R/W R/W Bit Description I2S audio input clock (I2SI_MCLK) to PAD connection enable I2S audio input clock (I2SI_MCLK) enable I 2Sin audio IF clock 1/(i2si_mclk_div_sel + 1) division ratio => div_i = Default 0x00 1 3:12 ISI_MCLK_SEL[1:0] 0x0 R/W I2SI_MCLK clkin select 00: clk_main 01: plla_fout 10: pllb_fout 11: reserved (clk_main) I2S audio output clock (I2SO_MCLK) enable I 2Sout audio IF clock 1/(i2so_mclk_div_sel + 1) division ratio => div_o = 11 1 0:2 I2SO_MCLK_EN I2SO_MCLK_DIV_SEL [8:0] 0 0x0 R/W R/W 1 :0 ISO_MCLK_SEL[1:0] 0x0 R/W I2SO_MCLK clkin select 00: clk_main 01: plla_fout 10: pllb_fout 11: reserved (clk_main) N ote: The clock gating bits in this register apply only to the audio clocks. To enable/disable the APB parts of the corresponding I2S IF CGU_PERI has to be configured. f(i2si_mclk) := f(I2SI_mclk clkin) * div_i; f(i2so_mclk) := f(I2SO_mclk clkin) * div_o; © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 109 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 28 Processor USB Clock Controller Register Name CGU_USB Offset0x1c Bit 5 Bit Name U SB_CLK_EN Default 0x00 Access R/W Base AS3525_CGU_BASE USB Clock ControllerRegister This register allows setting the USB PHY interface clock. Bit Description USB PHY clock enable => clk_usb division ratio 0: div = 1/1 > 0: div = 1/(2*n); (even division factors only) clkin select 00: clk_main 01: plla_fout 10: pllb_fout 11: reserved (clk_main) Default 0x00 4 :2 USB_DIV_SEL [2:0] 0x00 R/W 1 :0 USB_SEL[1:0] 0x00 R/W N ote: The clock gating bit applies only to the USB PHY clock. To enable/disable the clock to the AHB part (USB CORE) CGU_PERI has to be configured. f(clk_usb) = f(clk_core_48m) = f(clkin) * div; Table 29 Interrupt Mask and PLL Lock Status Register Name CGU_INTCTRL Offset: 0x20 Bit 3 2 1 0 Bit Name I NT_EN_PLLB_LOCK I NT_EN_PLLA_LOCK P LLB_LOCK P LLA_LOCK Default 0x00 0x00 0x00 Base AS3525_CGU_BASE Default 0x00 Interrupt Mask and PLL Lock Status Register Access R/W R/W R R Bit Description interrupt on PLLB lock enable (R/W) interrupt on PLLA lock enable (R/W) PLLB lock status, locked if SET (not cleared on read) PLLA lock status, locked if SET (not cleared on read) Table 30 Interrupt Clear Register Name CGU_IRQ Offset: 0x24 Bit 1 0 Bit Name P LLB_LOCK P LLA_LOCK Default 0x00 0x00 Access R R Base AS3525_CGU_BASE Interrupt Clear Register Default 0x00 Bit Description PLLB lock status, locked if SET (not cleared on read) PLLA lock status, locked if SET (not cleared on read) © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 110 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 31 PLL A Lock Counter Register Name CGU_COUNTA Offset: 0x28 Bit 7 :0 Bit Name COUNTA[7:0] Default 0x00 Access R/W Base AS3525_CGU_BASE PLL A Lock Counter Register Default 0x20 Bit Description number of PLL A’s fout-clock cycles until the LOCKA bit is set Table 32 PLL B Lock Counter Register Name CGU_COUNTB Offset: 0x2c Bit 7 :0 Bit Name COUNTB[7:0] Default 0x00 Access R/W Base AS3525_CGU_BASE PLL B Lock Counter Register Default 0x20 Bit Description number of PLL B’s fout-clock cycles until the LOCKB bit is set Table 33 IDE Clock Controller Register Name CGU_IDE Offset: 0x30 Bit 7 6 5 :2 Bit Name I DEIF_CLK_EN I DE_CLK_EN IDE_DIV_SEL [2:0] 0 0 0x0 Base AS3525_CGU_BASE IDE Clock Controller Register T his register allows setting the IDE interface clocks. Default Access R/W R/W R/W Bit Description IDE AHB IF clock enable IDE IF clock enable (90MHz domain) => clk_ide division ratio => div = 1/(ide_div_sel + 1) clkin select (clk_ide) 00: clk_main 01: plla_fout 10: pllb_fout 11: reserved (clk_main) Default 0x20 1 :0 IDE_SEL[1:0] 0x0 R/W N ote: f(clk_ide) := f(clkin) * div; © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 111 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 34 Memory Stick (MS) Clock Controller Register Name CGU_MS Offset: 0x34 Bit 8 7 6 :2 Bit Name M SIF_CLK_EN M S_CLK_EN MS_DIV_SEL [2:0] 0 0 0x0 Base AS3525_CGU_BASE MS Clock Controller Register T his register allows setting the MS interface clocks. Default Access R/W R/W R/W Bit Description MS APB IF clock enable MS IF clock enable (20/40MHz domain) => clk_ms division ratio => div = 1/(ms_div_sel + 1) clkin select (clk_ms) 00: clk_main 01: plla_fout 10: pllb_fout 11: reserved (clk_main) Default 0x00 1 :0 MS_SEL[1:0] 0x0 R/W N ote: f(clk_ms) = f(clkin) * div; Table 35 Data Block Output Port (DBOP) Clock Controller Register Name CGU_DBOP Offset: 0x38 Bit 3 2 :0 Note: Bit Name D BOP_EN DBOP_PREDIV_SEL [2:0] 0 0x0 Base AS3525_CGU_BASE DBOP Clock Controller Register T his register allows setting the DBOP interface clocks. Default Access R/W R/W Bit Description DBOP APB IF clock enable division ratio => div = 1/(dbop_prediv_sel + 1) Default 0x00 Setting DBOP_EN will enable both clocks (push/APB and pop) immediately. clk_dbop clock (pop clock) generation uses DBOP APB IF clock as input clock. f(clk_dbop) = f(PCLKDBOP) * div; © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 112 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Figure 43 Table with verified CGU frequency settings for Audio and USB applications with 24MHz crystal PLL PLL PLL fref fvco _F _R _OD [MHz] [MHz] Target: 48.000 Hz 48 24 41 23 6 3 8 5 1 3 2 3 4,000 8,000 3,000 4,800 384,000 384,000 246,000 220,800 plla_fout fclk_ fclk_ fclk [MHz] pre post [MHz] pclk_ pclk_ pclk div0 div1 [MHz] mclk mclk _div [Hz] faudio fsaudio error usb_ fusbphy [Hz] [%] div [Hz] fusb fsaudio CPU error target clock [%] [Hz] mode 384,000 96,000 123,000 55,200 0,00 0,00 0,00 0,00 5,00 1,00 1,00 0,00 64,000 48,000 61,500 55,200 0 0 0 0 0 0 0 0 64,000 48,000 61,500 55,200 61 15 19 8 6.193.548 6.000.000 6.150.000 6.133.333 48.387 0,806 46.875 -2,344 48.047 0,098 47.917 -0,174 3 48.000.000 0,000 1 48.000.000 0,000 48000 48000 48000 48000 fastbus fastbus fastbus fastbus Target: 44.100 Hz 48 24 47 79 47 6 3 10 12 10 1 3 2 3 3 4,000 8,000 2,400 2,000 2,400 384,000 384,000 225,600 316,000 225,600 384,000 96,000 112,800 79,000 56,400 0 0 0 0 0 5 1 1 1 1 64,000 48,000 56,400 39,500 28,200 0 0 0 0 0 0 0 0 0 0 64,000 48,000 56,400 39,500 28,200 67 16 19 13 9 5.647.059 5.647.059 5.640.000 5.642.857 5.640.000 44.118 0,040 44.118 0,040 44.063 -0,085 44.085 -0,034 44.063 -0,085 3 48.000.000 0,000 1 48.000.000 0,000 44100 44100 44100 44100 44100 fastbus fastbus fastbus fastbus fastbus Target: 32.000 Hz 48 24 41 31 6 3 6 7 1 3 3 3 4,000 8,000 4,000 3,429 384,000 384,000 328,000 212,571 384,000 96,000 82,000 53,143 0 0 0 0 5 1 1 1 64,000 48,000 41,000 26,571 0 0 0 0 0 0 0 0 64,000 48,000 41,000 26,571 93 22 19 12 4.085.106 4.173.913 4.100.000 4.087.912 31.915 -0,266 32.609 1,902 32.031 0,098 31.937 -0,197 3 48.000.000 0,000 1 48.000.000 0,000 32000 32000 32000 32000 fastbus fastbus fastbus fastbus Target: 24.000 Hz 48 24 41 6 3 8 1 3 2 4,000 384,000 8,000 384,000 3,000 246,000 384,000 96,000 123,000 0 0 0 5 1 1 64,000 48,000 61,500 0 0 0 0 64,000 0 48,000 0 61,500 124 3.072.000 30 3.096.774 39 3.075.000 24.000 24.194 24.023 0,000 0,806 0,098 3 48.000.000 0,000 1 48.000.000 0,000 24000 fastbus 24000 fastbus 24000 fastbus Target: 22.050 Hz 48 24 47 6 3 10 1 3 2 4,000 384,000 8,000 384,000 2,400 225,600 384,000 96,000 112,800 0 0 0 5 1 1 64,000 48,000 56,400 0 0 0 0 64,000 0 48,000 0 56,400 135 2.823.529 33 2.823.529 39 2.820.000 22.059 0,040 22.059 0,040 22.031 -0,085 3 48.000.000 0,000 1 48.000.000 0,000 22050 fastbus 22050 fastbus 22050 fastbus Target: 16.000 Hz 48 24 41 6 3 6 1 3 3 4,000 384,000 8,000 384,000 4,000 328,000 384,000 96,000 82,000 0 0 0 5 1 1 64,000 48,000 41,000 0 0 0 0 64,000 0 48,000 0 41,000 187 2.042.553 46 2.042.553 39 2.050.000 15.957 -0,266 15.957 -0,266 16.016 0,098 3 48.000.000 0,000 1 48.000.000 0,000 16000 fastbus 16000 fastbus 16000 fastbus Target: 12.000 Hz 48 24 41 6 3 6 1 3 3 4,000 384,000 8,000 384,000 4,000 328,000 384,000 96,000 82,000 0 0 0 5 1 1 64,000 48,000 41,000 0 0 0 0 64,000 0 48,000 0 41,000 249 1.536.000 62 1.523.810 52 1.547.170 12.000 0,000 11.905 -0,794 12.087 0,727 3 48.000.000 0,000 1 48.000.000 0,000 12000 fastbus 12000 fastbus 12000 fastbus Target: 11.025 Hz 48 24 41 6 3 6 1 3 3 4,000 384,000 8,000 384,000 4,000 328,000 384,000 96,000 82,000 0 0 0 5 1 1 64,000 48,000 41,000 0 0 0 0 64,000 0 48,000 0 41,000 271 1.411.765 67 1.411.765 57 1.413.793 11.029 11.029 11.045 0,040 0,040 0,184 3 48.000.000 0,000 1 48.000.000 0,000 11025 fastbus 11025 fastbus 11025 fastbus Target: 8.000 Hz 48 24 41 6 3 6 1 3 3 4,000 384,000 8,000 384,000 4,000 328,000 384,000 96,000 82,000 0 0 0 5 1 1 64,000 48,000 41,000 0 0 0 0 64,000 0 48,000 0 41,000 374 1.024.000 93 1.021.277 79 1.025.000 8.000 0,000 7.979 -0,266 8.008 0,098 3 48.000.000 0,000 1 48.000.000 0,000 8000 fastbus 8000 fastbus 8000 fastbus © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 113 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.15 CCU - Chip Control Unit Following chapters describe the functions of the CCU. Table 88 CCU Registers Register Name CCU_SRC CCU_SRL CCU_MEMMAP CCU_IO CCU_SCON CCU_VERS CCU_SPARE1 CCU_SPARE2 Base Address AS3525_CCU_BASE AS3525_CCU_BASE AS3525_CCU_BASE AS3525_CCU_BASE AS3525_CCU_BASE AS3525_CCU_BASE AS3525_CCU_BASE AS3525_CCU_BASE Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C Note Software reset control register Software reset lock register Memory map register IO configuration register System configuration register Chip version register spare register 1 (for future use) spare register 2 (for future use) 7.3.15.1 Reset Controller • Generation of the internal reset: the external reset pin XRES is used to generate the internal global reset. This internal reset is synchronised to clk_main and the active reset time is enlarged. This is necessary to wait for the startup of the DC/DC converter and LDO's that are generating the supplies of the digital chip. The time assumed for this startup is 10 ms, therefore 2^18 cycles of clk_main are counted before the internal reset is released. This mechanism is also used for the WATCHDOG reset. Softreset: for each module, the reset can also be generated by SW control. For this purpose, the SW can write to the software reset control register (CCU_SRC). To avoid unintended SW resets, the access to this control register is locked by the SW reset lock register (CCU_SRL). So the correct usage is: • • • write CCU_SRC write CCU_SRL (magic number 0x1A720212) to CCU_LOCK to activate resets write CCU_SRL (0x00000000) to deactivate resets • Table 89 Software Reset Control Register Name CCU_SRC Offset: 0x0000h Bit 24 23 22 21 20 19 18 17 Bit Name DBOP_EN MBIST_EN SPDIF_EN TIMER_EN SSP_EN WDO_EN IDE_EN IDE_AHB_EN Base AS3525_CCU_BASE Default 0x00 Software Reset Control Register W riting a logic 1 to the single bits in the read/write register enables resets to each module. Default 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: Bit Description enable DBOP reset disable DBOP reset enable MBIST manager reset disable MBIST manager reset enable SPDIF reset disable SPDIF reset enable timer module reset disable timer module reset enable synchronous serial port reset disable synchronous serial port reset enable watchdog timer module reset disable watchdog timer module reset enable compact flash/IDE reset (except AHB part) disable compact flash/IDE reset (except AHB part) enable compact flash/IDE’s AHB interface reset disable compact flash/IDE’s AHB interface reset © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 114 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Name CCU_SRC Offset: 0x0000h Bit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name UART_EN NAF_EN SDMCI_EN GPIO_EN I2C_AUDIO_EN I2C_EN MMS_EN I 2SI_APB_EN I 2SO_APB_EN U SB_AHB_EN U SB_PHY_EN D MAC_EN V IC_EN R AMC_EN 1 TRAM_EN M PMC_EN B RIDGE_EN Base AS3525_CCU_BASE Default 0x00 Software Reset Control Register W riting a logic 1 to the single bits in the read/write register enables resets to each module. Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: Bit Description enable UART interface reset disable UART interface reset enable NAND flash/Smart Media interface reset disable NAND flash/Smart Media interface reset enable secure digital/multimedia interface reset disable secure digital/multimedia interface reset enable general purpose IO reset disable general purpose IO reset enable audio I2C interface reset disable audio I2C interface reset enable master/slave I2C interface reset disable master/slave I2C interface reset enable memory stick interface reset disable memory stick interface reset enable I2S input interface reset for APB part disable I2S input interface reset for APB part enable I2S output interface reset for APB part disable I2S output interface reset for APB part enable USB AHB reset disable USB AHB reset enable USB PHY reset disable USB PHY reset enable DMA controller reset disable DMA controller reset enable vectored interrupt cell reset disable vectored interrupt cell reset enable RAMC reset disable RAMC reset enable 1TRAM reset disable 1TRAM reset enable external memory AHB reset disable external memory AHB reset enable bridge reset disable bridge reset Table 90 Software Reset Lock Register Name CCU_SRL Base AS3525_CCU_BASE Default 0x00 Offset: 0x0004h Software Reset Lock Register U se of this register enables the software reset selected with Software Reset Control Register. Writing a value of 0 x1A720212 w ill enable the selected reset; writing any other value will not enable software reset. Default 0 Access R/W Bit Description 0x1A720212: enables selected reset Other values: no effect Bit 0 :31 Bit Name software_reset_lock © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 115 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.15.2 IO_PADRING functions Within the IO_PADRING module all multiplexing for selecting alternative functions is implemented. The selection of active functions is chosen within the IO_configuration_register. Following table gives a description of the IO configurations: Table 91 IO_PADRING Configurations Name CCU_IO Offset: 0x000Ch Bit 8 :7 Bit Name naf_ce_sel[1:0] Base AS3525_CCU_BASE Default 0x00 IO Configuration Registers W ith this read/write registers the functionality of IOs are controlled which provides several different functions Default 0 Access R/W Bit Description these bits select which output is used for NAF ce_n. 0: naf_ce0_n 1: naf_ce1_n 2: naf_ce2_n 3: naf_ce3_n test mode: 1: pll output clock is available at a GPIO Pin 1: the IDE input/output configuration is set SPI used in master mode: 1: pin SSP_FSSOUT always 0 0 : pin SSP_FSSOUT generated by SSP hardware block SPI used in slave mode: spi_flash_mode hast to be switched to 0 00: XPD works as general purpose IO 01: SD-MCI interface 10: the XPD[5:0] are configured to support MS, XPD[7:6} are general IO pins 11: reserved (XPD works as general IO) 1: the I2C master/slave IO configuration is set 1: the uart IO configuration is set 6 5 4 p ll_probe_en i de_sel s pi_flash_mode 0 0 0 R/W R/W R/W 3 :2 xpd_func_sel(1:0) 0 R/W 1 0 i 2c_ms_sel u art_sel 0 0 R/W R/W 7.3.15.3 Other CCU functions With the CCU_MEMMAP register, the remap(r/w) and int_boot_sel (read only) bits are accessible. Table 92 Memory Map Register Name CCU_MEMMAP Offset: 0x0008h Bit 1 Bit Name I NT_BOOT_SEL Base AS3525_CCU_BASE Default N/A Memory Map Register W ith the register the remap(r/w) and int_boot_sel (r only) bits are accessible. Default external pin XPC[0] 0 Access R Bit Description Boot selection 1: internal ROM 0: external memory interface Defines memory mapping 1: RAM 0: ROM 0 R EMAP R/W If the INIT_BOOT_SEL is 0 (boot from external memory interface), following pins will be latched at startup to define the MPMC interface settings: • • mpmc_stcs1mw[0] mpmc_stcs1pol • • mpmc_stcs1pb mpmc_rel1config © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 116 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.3.15.4 Additional Chip Control Unit Registers Table 93 System Configuration Register Name CCU_SCON Offset: 0x0010h Bit 0 Bit Name p riority_config Base AS3525_CCU_BASE System Configuration Register T his read/write register controls system parameters. Default 0 Access R/W Bit Description AHB master’s priority configuration: 0: Configuration A (default) Highest priority: TIC (Test Interface Controller) – for production test only 2 nd h ighest priority: ARM922T 3 rd h ighest priority: DMA 4 th h ighest priority: USB lowest priority: IDE 1: Configuration B Highest priority: TIC (Test Interface Controller) – for production test only 2 nd h ighest priority: DMA 3 rd h ighest priority: USB 4 th h ighest priority: IDE lowest priority: ARM922T Default 0x00 Table 94 Chip Version Register Name CCU_VERS Offset: 0x0014h Bit 3 1:12 1 1:0 Bit Name main_version_id(19 :0) sub_version_id(11: 0) Base AS3525_CCU_BASE Chip Version Register V ersion information can be read from this register. Default 0x2 0x1 Access R R Bit Description main version ID sub version ID Default 0x09 Table 95 Spare Register 1 Name CCU_SPARE1 Offset: 0x0018h Bit 3 1:9 8 7 6 5 4 3 :2 1 :0 Bit Name spare d ma_sreq_SSPRX_off d ma_sreq_SSPTX_off d ma_sreq_DBOP_off d ma_sreq_I2Sin_off d ma_sreq_I2Sout_off spare mpmc_clk_inv Base AS3525_CCU_BASE Default 0x00 Metal ECO Spare Register T his register implements 32bit spare FF’s. Use for metal ECO redesign. Defau lt 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit Description spare bits to be used for metal ECO redesign if SET disableDMA single request of SSPRX module if SET disable DMA single request of SSPTX module if SET disable DMA single request of DBOP module if SET disable DMA single request of I2Sin module if SET disable DMA single request of I2Sout module if SET spare bits to be used for metal ECO redesign if SET spare bits used to invert output clocks mpmc_clk(1:0) if SET 117 - 194 © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 AS3525-A/-B C22O22 Data Sheet, Confidential Table 96 Spare Register 2 Name CCU_SPARE2 Offset: 0x001Ch Bit 3 1:3 2 :0 Bit Name spare bist_idle_cycle_ctrl Base AS3525_CCU_BASE Default 0x00 Metal ECO Spare Register T his register implements 32bit spare FF’s. Use for metal ECO redesign. Defau lt 0x00 0x00 Access R/W R/W Bit Description spare bits to be used for metal ECO redesign if SET internal RAM refresh cycle control bits of BIST_MGR module 000: idle every 32nd cycle (default) 100: idle every 16th cycle 110: idle every 8th cycle 111: idle every 4th cycle © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 118 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4 7.4.1 7.4.1.1 Audio and Power Management functions SYSTEM General The system block handles the power up, power down and regulator voltage settings of the AFE. 7.4.1.2 Power Up The chip powers up when on of the following condition is true: • H igh signal on the PWR_UP pin (>80ms, >1V & >1/3 BVDD) • I nput voltage on the UVDD pin (USB plug in: >80ms, BVDD>1.5V, UVDD>4.5V) • I nput voltage on the CHG_IN pin (charger plug in: >80ms, BVDD>1.5V, CHG_IN>4.0V) • I nput voltage on BVDD pin (battery change: >1.35V) To hold the chip in power up mode the PwrUpHld bit in the SYSTEM register (0x20h) is set. 7.4.1.3 Power Down The chip automatically shuts off if one of the following conditions arises: 1. C learing the PwrUpHld bit in SYSTEM register (0x20h) 2. I 2C watchdog power down if enabled (no serial reading for >1s, has to be enabled) 3. B VDD drops below the minimum threshold voltage (6s, >1V & >1/3 BVDD). Figure 44 Power Up Timing Power up from PwrUp, CHG_IN, VBUS or RTCSUP pin BVDD rising with VBAT1 supply (DCDC3V) VREF, IREF rising with vdd_bandgap QLDO1 & 2 AVDD & DVDD for internal supply EN LDO2 + DCDC QLDO2=ok Enable CP Sequence start sequencer with 1.2 MHz clock VREF=ok Enable PVDD +2ms Enable IOVDD +4ms start up with length regulator (200mA) Enable CVDD +6ms +10ms charge pump (50mA) enable unlock, enable via I2C setting PowerGood = XRES +8ms © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 119 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.1.4 Parameter Table 97 Supply Regulator Block Characteristics Symbol Parameter Notes Min Typ 2.15 2.0 100 4.1 50 8 Max Unit V V mV kHz us D VDD_POR_OFF D VDD_POR_ON P OR_ON/OFF_HYST L RCK WATCHDOG F (LRCK)_WD_OFF O N_Delay DVDD=2.9V; Tamb=25ºC; unless otherwise specified 7.4.1.5 Register Description Table 98 System Register Name System Offset: 0x20 Bit 7 :4 3 Bit Name Version P VDDp Base I2C audio master System Settings Register T his register is reset at a DVDD-POR. Default 0010 0 Access R R/W Bit Description AFE number to identify the design version 0 010: revision 2 PVDD trimming: 0 : Vnom 1 : Vnom *17/18 IOVDD trimming: 0 : IOVDD = 3.11V (nominal) 1 : IOVDD = 2.94V 0 : forced power down through watchdog is disabled 1 : forced power down through watchdog is enabled (no serial interface reading within 1s) 0: power up hold is cleared and supply is switched off 1 : set to on after power on Default 0x21 2 I OVDDp 0 R/W 1 E nWDogPwdn 0 R/W 0 P wrUpHld 1 R/W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 120 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.2 7.4.2.1 • • • • • • • • • • • • 3V Step-Up Converter General O utput voltage 3V to 3.6V (BVDD) programmable in 4 steps via DCDC3p bit to save power I nput voltage 1V (1.2V) to 3V, voltages higher than that can be connected to BVDD directly M aximum output current to BVDD: 150mA C urrent mode operation O n-chip compensation and feedback network O n chip 300m Ω N MOS switch P WM mode with 1.2MHz switching frequency I nductor current limitation 850mA P ulse skipping capability L ow quiescent current: 40 μ A in PFM-mode, 300 μ A in PWM mode ≤ 1 μ A shutdown current u ses external coil (6.8 μ H) and Schottky diode (500mA) Figure 45 DCDC 3V Block Diagram 7.4.2.2 Parameter Table 99 DCDC Boost Parameter Symbol I VDD2.9 Parameter S upply Current Notes P ower down mode P FM mode operation PWM mode (low output load) R Load >220 Ω I OUT =1mA, VBAT falling from 1.5 to 0V Start-up, X3VOK=1 P WM mode operation, X3VOK=0 Min Typ 40 300 1 .0 0.5 100 250 1.2 100 100 85 87 0.85 3 00 500 Max 5 Unit μA μA μA V V mΩ kHz MHz ns ns % % A mA V STARTUP V HOLD R SW_on f SW t ON_min t OFF_min η eff I SW_LIM I OUT S tartup Voltage H old-on Voltage I nternal Switch R DS_ON S witching Frequency M inimum On-time M inimum Off-time E fficiency C urrent Limit L oad Current I OUT =20mA, Vin=1.35 I OUT =50mA, Vin=1.5 1.0V ≤ V B1V ≤ 3 .0V VB1V=1.0V 0.60 1.10 150 Vin=1.0..2.0V, C(VBAT_1V) = 2.2μF ceramic || 2000μF Elko, C(BVDD) = 3 x 2.2μF ceramic, L=DS1608 6.8μH, Temp = 25deg © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 121 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Figure 46 DCDC Boost Typical Performance Characteristics 90,0 85,0 80,0 1,5V 1,35V 1,25V 1,1V 0,9V Eff. [%] 75,0 70,0 65,0 60,0 1 10 Iout [mA] 100 1000 BVDD=3.1V, L=DS1608 6.8μH, Temp = 25deg 7.4.2.3 Register Description Table 100 CVDD / DCDC3 Register Name CVDD / DCDC 3 Offset: 0x21 Bit 7 Bit Name C P_SW Base I2C audio master Default 0x00 Charge Pump and 3V DCDC Register T his register is reset at a DVDD-POR. Default 0 Access R/W Bit Description c harge pump / length regulator switch margin reduction 0 : margin set to 200/300 mV 1 : margin reduced to 150/225 mV (automatic switching to length regulator is done “later”, at a lower input voltage) 0 : normal operation 1 : keeps Mode 3 charge pump always on Please note that bit 2 = “0”, overrides bit 6. C ore voltage generation mode 0 : CP is working 1 : LREG is working F or production testing purpose only, in normal application mode this bit must always be written with “0”. D CDC3 Vout programming (BVDD) 0 0: 3.6V 0 1: 3.2V 10: 3.1V 11: 3.0V 0 : keeps Mode2 (length regulator always on) 1 : normal operation C VDD trimming: 0 0: 1.2V 0 1: 1.15V 10: 1.10V 11: 1.05V 6 C P_on 0 R/W 5 L REG_CPnot 0 R W 4 :3 DCDC3p 00 R/W 2 1 :0 L REG_off CVDDp 0 00 R/W R/W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 122 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.3 7.4.3.1 Low Drop Out Regulators General These LDO’s are designed to supply sensitive analogue circuits, audio devices, AD and DA converters, micro-controller and other peripheral devices. The design is optimised to deliver the best compromise between quiescent current and regulator performance for battery powered devices. Stability is guaranteed with ceramic output capacitors of 1μF +/-20% (X5R) or 2.2μF +100/-50% (Z5U). The low ESR of these caps ensures low output impedance at high frequencies. Regulation performance is excellent even under low dropout conditions, when the power transistor has to operate in linear mode. Power supply rejection is high enough to suppress high ripple on the battery at the output. The low noise performance allows direct connection of noise sensitive circuits without additional filtering networks. The low impedance of the power device enables the device to deliver up to 150mA even at nearly discharged batteries without any decrease of performance. Figure 47 LDO Block Diagram 7.4.3.2 • • LDO1 This LDO generates the analog supply voltage used for the AFE itself. I nput voltage is BVDD O utput voltage is AVDD (typ. 2.9V) 7.4.3.3 • • • LDO2 This LDO generates the digital supply voltage used for the AFE itself. I nput Voltage is BVDD O utput Voltage is DVDD (typ. 2.9V) D river strength: 200mA 7.4.3.4 • • • • LDO3 This LDO can used to generate the periphery voltage for the digital processor (e.g. vdd_mem for MPMC interface) I nput Voltage BVDD O utput Voltage is PVDD 1.7 to 3.3V D river strength: 200mA P rogrammable via P_PVDD pin and PVDDp bit in 8 steps Table 101 PVDD programming P_PVDD V SS 1 50k to VSS O pen 1 50k to DVDD D VDD PVDDp=0 OFF 2.50V 3.33V 2.90V 1.80V PVDDp=1 OFF 2.36V 3.15V 2.74V 1.70V © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 123 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.3.5 LDO4 This LDO will be used to supply the digital processor periphery (vdd_peri). Default value is 3.11V, but it can be manually programmed to 2.94V if needed. • • • • I nput Voltage BVDD O utput Voltage is IOVDD (3.11 or 2.94) P rogrammable via IOVDDp bit. D river strength: 200mA 7.4.3.6 • • • • LDO6 This LDO will be used to supply the USB 2.0 OTG interface block. I nput Voltage BVDD O utput Voltage is UVDD (3.26V) s eparate enable bit in USB_UTIL register (0x17) D river strength: 200mA 7.4.3.7 Parameter Table 102 LDOs Block Characteristics Symbol R ON P SRR I OFF I VDD N oise t start V out Parameter O n resistance Power supply rejection ratio S hut down current S upply current Output noise S tartup time O utput voltage f =1kHz f=100kHz without load 10Hz < f < 100kHz V bat>3.0V f ull prog. range LDO1, LDO2 L DO1, LDO1, L DO1, LDO1, LDO1, Static Transient; Slope: t r =10 μ s Static Transient; Slope: t r =10 μ s LDO2, LDO3, LDO4 1.7 1.7 2.9 -50 -1 -10 -1 -10 400 50 1 10 1 10 Notes Min 70 40 100 50 50 200 2.85 3.56 Typ Max 1 Unit Ω dB nA μA μ V rms μs V V V mV mV mV mA V out_tol V LineReg V LoadReg I LIMIT O utput voltage tolerance L ine regulation L oad regulation C urrent limitation BVDD=4V; ILOAD=150mA; Tamb=25ºC; CLOAD =2.2μF (Ceramic); unless otherwise specified © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 124 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.3.8 Register Description Table 103 System Register Name System Offset: 0x20 Bit 7 :4 3 Bit Name Version P VDDp Base I2C audio master System Settings Register T his register is reset at a DVDD-POR. Default 0010 0 Access R R/W Bit Description AFE number to identify the design version 0 010: revision 2 PVDD trimming: 0 : Vnom 1 : Vnom *17/18 IOVDD trimming: 0 : IOVDD = 3.11V (nominal) 1 : IOVDD = 2.94V 0 : forced power down through watchdog is disabled 1 : forced power down through watchdog is enabled (no serial interface reading within 1s) 0: power up hold is cleared and supply is switched off 1 : set to on after power on Default 0x21 2 I OVDDp 0 R/W 1 E nWDogPwdn 0 R/W 0 P wrUpHld 1 R/W Table 104 USB_UTIL Register Name USB_UTIL Offset: 0x17 Bit 7 ..5 4 3 :2 Bit Name L DO6_on COMP_TH Base I2C audio master USB Utility Register T his register is reset at a DVDD-POR. Default 000 0 0 Access n/a R/W R/W Bit Description 0 : UVDD generation disabled 1 : LDO6 for generating UVDD enabled. Sets the threshold for the VBUS comparator 0 0: 4.5V 0 1: 3.18V 10: 1.5V 11: 0.6V 0 : normal operation 1 : enables the skip mode for the VBUS 1:2 charge pump. This is increasing the efficiency for smaller loads, but increasing the VBUS ripple. 0 : disables VBUS charge pump 1 : enables VBUS charge pump Default 0x00 1 S KIP_ENAB 0 R/W 0 C P_5V_on 0 R/W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 125 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.4 7.4.4.1 • • • • • • • Charge-Pump Step-Down Converter General This converter will be used to supply the core voltage for a microprocessor. I nput Voltage CPVDD O utput Voltage 1.05 to 1.2 V V oltage setting via CVDDp bits in 4 steps r egulated 2:1 charge pump with pulse skipping s caleable switches according to BVDD B ypass LDO for higher currents or lower battery voltages respectively D river strength: 50mA / 200mA with bypass LDO Figure 48 CP Block Diagram 7.4.4.2 Mode Description Three different functional parts generate core supply voltage CVDD. The switching between the modes is generally done automatically, but can also be manually overwritten by register settings. Please observe that the charge pump block starts up in Mode 2(IOVDD length regulator mode) to avoid a current limitation and has to be switched to automatic operation by register settings. Direct length regulation from VBAT Mode1=true IF ((1.2V+Vmargin1) < VBAT_1V < (VTH1)) && (NoUSB) • • • • V margin1=50mV/150mV (100mV hysteretic) V TH1=1.7V/1.8V (100mV hysteretic) V BAT LDO is used when [1.8V > VBAT_1V > 1.25V] V BAT LDO is not used when there is high supply present from USB even when VBAT is in range. Direct length regulation from IOVDD Mode2=true IF ((Not Mode1) && (IOVDD/2 < (1.2+Vmargin2))) • • • V margin2=200mV/300mV (100mV hysteretic) I OVDD LDO is used when VBAT LDO Mode1 is not entered and I OVDD is not high enough to do 2:1 charge-pump regulation. Charge-Pump IOVDD division by 2 active plus length regulation Mode3=true IF ((Not Mode1) && (Not Mode2)) © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 126 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.4.3 Parameter Table 105 CP Typical Performance Parameter CVDD Charge Pump Regulation to 1.2V 1,3 1,25 V_CVDD [V ] 1,2 1,15 h 1,1 1,05 0 50 100 150 200 250 BVDD= 2.8V BVDD= 3.0V BVDD= 3.2V BVDD= 3.6V BVDD= 3.4V I_CVDD [mA] CVDD Lengh Regulation to 1.2V 1,25 1,2 BVDD= 3.6V BVDD= 3.4V V_CVDD [V] 1,15 1,1 BVDD= 3.0V 1,05 BVDD= 3.2V 1 0 50 100 150 200 250 300 350 400 I_CVDD [mA] © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 127 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.4.4 Register Settings Table 106 CVDD / DCDC3 Register Name CVDD / DCDC 3 Offset: 0x21 Bit 7 Bit Name C P_SW Base I2C audio master Default 0x00 Charge Pump and 3V DCDC Register T his register is reset at a DVDD-POR. Default 0 Access R/W Bit Description c harge pump / length regulator switch margin reduction 0 : margin set to 200/300 mV 1 : margin reduced to 150/225 mV (automatic switching to length regulator is done “later”, at a lower input voltage) 0 : normal operation 1 : keeps Mode 3 charge pump always on Please note that bit 2 = “0”, overrides bit 6. C ore voltage generation mode 0 : CP is working 1 : LREG is working F or production testing purpose only, in normal application mode this bit must always be written with “0”. D CDC3 Vout programming (BVDD) 0 0: 3.6V 0 1: 3.2V 10: 3.1V 11: 3.0V 0 : keeps Mode2 (length regulator always on) 1 : normal operation C VDD trimming: 0 0: 1.2V 0 1: 1.15V 10: 1.10V 11: 1.05V 6 C P_on 0 R/W 5 L REG_CPnot 0 R W 4 :3 DCDC3p 00 R/W 2 1 :0 L REG_off CVDDp 0 00 R/W R/W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 128 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.5 7.4.5.1 Audio Line Output General The line output is designed to provide the audio signal with typical 1Vp at a load of minimum 10kΩ, which is a minimum value for line inputs. Additional this output amplifier is capable to drive a 32Ω load (e.g. an earpiece of a mobile phone). To achieve this operation mode can be switched from single ended stereo to mono differential. This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from -40.5dB to +6dB. Changing of volume and mute control can only be done after enabling the output. If using the output in mono differential mode, the volume setting for the right channel should be set to 0dB. Figure 49 Line Output S tereo Mode Mono Differential Mode (please observe that gain of right channel amplifier has to best to 0dB) 7.4.5.2 Parameter Table 107 Line Output Characteristics Symbol RL Parameter O utput Load stereo mode differential mode A0 Ax S NR Gain Gain Step-Size Signal to Noise Ratio M ute Attenuation BVDD = 3.3V, TA= 25oC unless otherwise mentioned stereo mode 90 120 programmable gain Notes Min 10k 32 -40.5 1.5 6 Typ Max Unit Ohm Ohm dB dB dB dB © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 129 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.5.3 Register Description Table 108 Line Output Related Register Name A udioSet_1 Base I2C audio master Offset 0x14 Description Enable/disable driver stage Table 109 LINE_OUT_R Register Name LINE_OUT_R Offset: 0x00 Bit 7 :5 4 :0 Bit Name LOR_VOL Base I2C audio master Default 0x00 Right Line Output Register T his register is reset when the block is disabled in AudioSet1 register (0x14) or at a DVDD-POR. The register cannot be written when the block is disabled. Default 000 00000 Access n/a R/W Bit Description do not change volume settings for right line output, adjustable in 32 steps @ 1.5dB 11111: 6 dB gain 11110: 4.5 dB gain .. 00001: -39 dB gain 0 0000: -40.5 dB gain Table 110 LINE_OUT_L Register Name LINE_OUT_L Offset: 0x01 Bit 7 :6 Bit Name LO_SES_DM Base I2C audio master Default 0x00 Left Line Output Register T his register is reset when the stage is disabled in AudioSet1 register (0x14) or at a DVDD-POR. The register cannot be written when the block is disabled. Default 00 Access R/W Bit Description Single ended stereo or differential mono selection 11: do not use 10: output switched to single ended stereo 01: output switched to differential mono 0 0: output switched to mute do not change volume settings for right line output, adjustable in 32 steps @ 1.5dB 11111: 6 dB gain 11110: 4.5 dB gain .. 00001: -39 dB gain 0 0000: -40.5 dB gain 5 4 :0 LOL_VOL 0 00000 n /a R/W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 130 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.6 7.4.6.1 Headphone Output General The headphone output is designed to provide the audio signal with 2x40mW @ 16Ω or 2x20mW @32Ω, which are typical values for headphones. This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –43.43dB to +1.07dB. The maximum output power of 40mW @ 16Ω is achieved, by setting the mixer output to 1Vp and using the gain of 1.07dB. Figure 50 Headphone Output H eadphones connected via decoupling capacitors Headphones connected to Phantom Ground (Common Mode) 7.4.6.2 Phantom Ground HPCM pin is the buffered HPGND output. It can be used to drive the loads without external blocking capacitors between HPL / HPR and HPCM. If the load is between HPR / HPL and BVSS, 100uF of de-coupling capacitors are needed. The phantom ground can be switched off to save power if not needed. 7.4.6.3 No-Pop Function To avoiding click and pop noise during power-up and shutdown, the output is automatically set to mute when the output stage is disabled. HPGND pin, which needs a 100nF capacitor outside, gets charged on power-up with 2uA to AGND=1.45V. After start-up the DC level of the following pins are the same: HPR=HPL=HPCM=HPGND=AGND=1.45V. The Start-up time before releasing mute is about 90ms. To avoid popnoise 150ms discharging time of HPGND after a shutdown, have to be waited before starting up again. 7.4.6.4 Over-current Protection This output stage has an over-current protection, which disables the output for 256ms or 512ms. This value can be set in the headphone registers. The over-current protection limit of HPR and HPL pin is typical 145mA while HPCM pin has a 210mA threshold. If needed, the over-current condition can also be signalled via an interrupt to the controlling microprocessor. 7.4.6.5 Headphone Detection With a control bit the headphone detection can be enabled. The detection is only working as long as the headphone stage is in power down mode and the load is applied between HPR / HPL and HPCM. The headphone detection can also trigger a corresponding interrupt. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 131 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.6.6 Power Save Options To save power, especially when driving 32 Ohm loads, a reduction of the bias current can be selected. Together with switching off the phantom ground this gives 4 possible operating modes. Table 111 Headphone Power-Save Options HPCM_OFF 0 1 0 1 IBR_HPH 0 0 1 1 IDD_HPH (typ.) 2.2mA 1.5mA 1.5mA 1.0mA Load 16 Ohm 16 Ohm 32 Ohm 32 Ohm BVDD = 3.3V, TA= 25oC unless otherwise mentioned 7.4.6.7 Parameter Table 112 Power Amplifier Block Characteristics Symbol Parameter RL O utput Load P out Maximum Output Power A0 Ax P SRR I OUT_pd T power_up S NR Notes stereo mode R L = 32 Ω R L = 16 Ω programmable gain Min 16 Typ 20 40 -43.43 60 -20 90 Signal to Noise Ratio M ute Attenuation 90 120 1.5 90 145 20 1.07 Max Unit Ohm mW mW dB dB dB mA uA ms dB dB Gain Gain Step-Size Power Supply Rejection Ratio 200Hz-20kHz, 720mVpp, R L = 16 Ω S hort Current Protection Level I OUT p ower down BVDD = 3.3V, TA= 25oC unless otherwise mentioned © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 132 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.6.8 Register Description Table 113 Headphone Related Register Name A udioSet_3 I RQ_ENRD_1 Base I2C audio master I2C audio master Offset 0x16 0x26 Description Power save options, common mode buffer Interrupt settings for over current and HP detection Table 114 HPH_OUT_R Register Name HPH_OUT_R Offset: 0x02 Bit 7 :6 Bit Name HP_OVC_TO Base I2C audio master Right Headphone Output Register T his register is reset at a DVDD-POR. Default 00 Access R/W Bit Description headphone over current time out: 11: 0 ms 10: 512 ms 01: 128 ms 0 0: 256 ms do not change volume settings for right headphone output, adjustable in 32 steps @ 1.5dB 11111: 1.07 dB gain 11110: -0.43 dB gain .. 00001: -43.93 dB gain 0 0000: -45.43 dB gain Default 0x00 5 4 :0 HPR_VOL 0 00000 n /a R/W Table 115 HPH_OUT_L Register Name HPH_OUT_L Offset: 0x03 Bit 7 6 5 4 :0 Bit Name H P_Mute_on H P_on H Pdet_on HPL_VOL Base I2C audio master Left Headphone Output Register T his register is reset at a DVDD-POR. Default 0 0 0 00000 Access R/W R/W R/W R/W Bit Description 0 : normal operation 1 : headphone output set to mute (mute is on during power-up) 0 : headphone stage not powered 1 : power up headphone stage 0 : no headphone detection 1 : enable headphone detection volume settings for left headphone output, adjustable in 32 steps @ 1.5dB 11111: 1.07 dB gain 11110: -0.43 dB gain .. 00001: -43.93 dB gain 0 0000: -45.43 dB gain Default 0x00 © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 133 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.7 7.4.7.1 Speaker Output General The speaker output is designed to provide the stereo audio signal with 2x500mW @ 4Ω. This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from −40.5dB to +6dB. The maximum output power of 500mW @ 4Ω is achieved, by setting the mixer output to 1Vp and using the gain of +6dB. Figure 51 Speaker Output S peaker connected via decoupling capacitors 7.4.7.2 Latchup Protection For latchup protection of pins LSPL and LSPR, external schottky diodes must be implemented from LSPL to BVDD and LSPR to BVDD as drawn in the above diagram. These diodes protect pins LSPL and LSPR against the back-voltage induced by the inductance of the speaker in case of switching off the speaker. These diodes must be schottky type diodes with low forward voltages to prevent high current through the internal LSPR/LSPL ESD protection diodes that potentially would cause latchup for currents exceeding the maximum input current specifications given in chapter 6.1 Absolute Maximum Ratings. These schottky diodes must be capable of surging maximum peak currents of up to 600 mA. 7.4.7.3 No-Pop Function BGND pin, which needs a 100nF capacitor outside, gets charged on power-up to BVDD/2.To avoiding click and pop noise during power-up and shutdown, the output is automatically set to mute when the output stage is disabled. The Start-up time before releasing mute is about 100ms. To avoid pop-noise the 150ms discharging time of SPR / SPL after a shutdown (220µF capacitor in stereo single ended mode assumed), have to be waited before starting up again. 7.4.7.4 Over-current Protection This output stage has an over-current protection, which disables the output for 0 to 512ms. This value can be set in the speaker registers. The overcurrent protection limit of SPR and SPL pin is typical 700mA. To get an interrupt on an over-current event, the corresponding bit in the IRQ_ENRD1 register (0x26h) has to be set. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 134 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.7.5 Power Save Options When driving > 4Ω, two power save options can be chosen. The output driver stage can be set to only 25% drive capacity, which will reduce the maximum output power. Additionally the bias currents can be reduced to 50% in 3 steps. Table 116 Speaker Power-Save Options LSP_LP 0 1 1 1 1 IBR_LSP 00 00 01 10 11 IDD_LSP (typ.) 8mA 2.8mA 2.4mA 1.9mA 1.5mA Load 4 Ohm 16-32 Ohm 16-32 Ohm 16-32 Ohm 16-32 Ohm BVDD = 3.3V, TA= 25oC unless otherwise mentioned 7.4.7.6 Parameter Table 117 Speaker Amplifier Parameter Symbol Parameter RL O utput Load P out A0 Ax P SRR I OUT_pd T power_up S NR Notes s tereo mode mono differential mode Min 4 8 -40.5 70 -20 1 00 Signal to Noise Ratio M ute Attenuation 90 120 1.5 75 700 20 Typ Max Unit Ohm Ohm W dB dB dB mA uA ms dB dB Maximum Output Power RL= 8Ω Gain programmable gain Gain Step-Size Power Supply Rejection Ratio 200Hz-20kHz, 720mVpp, no load S hort Current Protection Level I OUT p ower down 1 6 BVDD = 5V, TA= 25oC unless otherwise mentioned © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 135 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.7.7 Register Description Table 118 Speaker Related Register Name A udioSet_2 I RQ_ENRD_1 Base I2C audio master I2C audio master Offset 0x15 0x26 Description Power save options Interrupt settings for over current detection Right Speaker Register (04h) Table 119 LSP_OUT_R Register Name LSP_OUT_R Offset: 0x04 Bit 7 :6 Bit Name SP_OVC_TO Base I2C audio master Right Speaker Output Register T his register is reset at a DVDD-POR. Default 00 Access R/W Bit Description speaker over current time out: 11: 0 ms 10: 512 ms 01: 128 ms 0 0: 256 ms do not change volume settings for right speaker output, adjustable in 32 steps @ 1.5dB 11111: 6 dB gain 11110: 4.5 dB gain .. 00001: -39 dB gain 0 0000: -40.5 dB gain Default 0x00 5 4 :0 SPR_VOL 0 00000 n /a R/W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 136 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 120 LSP_OUT_L Register Name SPH_OUT_L Offset: 0x05 Bit 7 6 5 4 :0 Bit Name S P_Mute_on S P_on Base I2C audio master Left Speaker Output Register T his register is reset at a DVDD-POR. Default 0 0 0 00000 Access R/W R/W n /a R/W Bit Description 0 : normal operation 1 : speaker output set to mute (mute is on during power-up) 0 : speaker stage not powered 1 : power up speaker stage do not change volume settings for left speaker output, adjustable in 32 steps @ 1.5dB 11111: 6 dB gain 11110: 4.5 dB gain .. 00001: -39 dB gain 0 0000: -40.5 dB gain Default 0x00 SPL_VOL © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 137 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.8 7.4.8.1 Microphone Inputs (2x) General The chip features two identical microphone inputs. The blocks have differential inputs to a microphone amplifier with adjustable gain. This stage also includes an AGC. The following volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from – 40.5dB to +6dB. The stage is set to mute by default. If the microphone input is not enabled, the volume settings are set to their default values. Changing of volume and mute control can only be done after enabling the input. Figure 52 Microphone Input M icrophone Preamplifier and Gain Stage 7.4.8.2 AGC The microphone amplifier includes an AGC, which is limiting the signal to 1Vp. The AGC has 15 steps with a dynamic range of about 29dB. The AGC is ON by default but can be disabled by a microphone register bit. 7.4.8.3 Supply & Detection Each microphone input generates a supply voltage of 1.5V above HPHCM. The supply is designed for ≤2mA and has a 10mA current limit. In OFF mode the MICSUP terminal is pulled to AVDD with 30kohm. A current of typically 50uA generates an interrupt to inform the CPU, that a circuit is connected. When using HPHCM as headset ground the HPH–stage gives the interrupt. After enabling the HPH-stage through the CPU the microphone detection interrupt will follow. 7.4.8.4 Remote Control Fast changes of the supply current of typically 500uA are detected as a remote button press, and an interrupt is generated. Then the CPU can start the measurement of the microphone supply current with the internal 10-bit ADC to distinguish which button was pressed. As the current measurement is done via an internal resistor, only two buttons generating a current of about 0.5mA and 1mA can be detected. With this 1mA as microphone bias is still available. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 138 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.8.5 Parameter Table 121 Microphone Inputs Parameter Symbol A0 Ax R inMIC A MIC 0 A MIC 1 A MIC 2 Parameter Notes programmable gain differential Min -40.5 1.5 15 28 34 40 15*2.0 60 120 40 20 10 90 120 0-4mA 2.95 10 50 500 5.7 Typ Max 6 Unit dB dB kOhm dB dB dB dB us ms mVp mVp mVp dB dB V mA uA uA uV Gain Gain Step-Size I nput Resistance MicAmp_Gain0 MicAmp_Gain1 MicAmp_Gain2 S oftClip_AGC_Range A ttack_Time R elease_Time V Innom 0 Nominal_Input_Voltage0 V Innom 1 Nominal_Input_Voltage1 V Innom 2 Nominal_Input_Voltage2 S NR Signal to Noise Ratio M ute Attenuation M icrophone Supply V MICsup M icrophone Supply Voltage I MIClim M ic. Supply Current Limit I MICdet M ic. Detection Current I REMdet R emote Detection Current V noise V oltage Noise BVDD = 3.3V, TA= 25oC MicInGain = 0dB, MicAmp_Gain0 MicInGain = 0dB, MicAmp_Gain1 MicInGain = 0dB, MicAmp_Gain2 microphone supply current step unless otherwise mentioned © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 139 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.8.6 Register Description Table 122 Microphone Related Register Name A udioSet_1 I RQ_ENRD_1 I RQ_ENRD_2 Base I2C audio master I2C audio master I2C audio master Offset 0x14 0x26 0x27 Description Enable/disable driver stage Interrupt settings for microphone detection Interrupt settings for remote button press detection Table 123 MIC1_R & MIC2_R Register Name MIC1_R, MIC2_R Offset: 0x06, 0x08 Bit 7 6 :5 Bit Name M ic1_AGC_off Mic2_AGC_off Mic1_Gain Mic2_Gain Base I2C audio master Default 0x00 Right Microphone Input Registers T his register is reset when the block is disabled in AudioSet1 register (0x14) or at a DVDD-POR. The register cannot be written when the block is disabled. Default 0 00 Access R/W R/W Bit Description 0 : automatic gain control enabled 1 : automatic gain control disabled 0 0: gain set to 28 dB 0 1: gain set to 34 dB 10: gain set to 40 dB 11: reserved, do not use. volume settings for right microphone input, adjustable in 32 steps @ 1.5dB 11111: 6 dB gain 11110: 4.5 dB gain .. 00001: -39 dB gain 0 0000: -40.5 dB gain 4 :0 Mic1R_VOL Mic2R_VOL 00000 R/W Table 124 MIC1_L & MIC2_L Register Name MIC1_L, MIC2_L Offset: 0x07, 0x09 Bit 7 6 5 4 :0 Bit Name M ic1_Sup_off Mic2_Sup_off M ic1_Mute_off Mic2_Mute_off Mic1L_VOL Mic2L_VOL Base I2C audio master Default 0x00 Left Microphone Input Registers T his register is reset when the block is disabled in AudioSet1 register (0x14) or at a DVDD-POR. The register cannot be written when the block is disabled. Default 0 0 0 00000 Access R/W R/W n /a R/W Bit Description 0 : microphone supply enabled 1 : microphone supply disabled 0 : microphone input set to mute 1 : normal operation volume settings for left microphone input, adjustable in 32 steps @ 1.5dB 11111: 6 dB gain 11110: 4.5 dB gain .. 00001: -39 dB gain 0 0000: -40.5 dB gain © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 140 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.9 7.4.9.1 Audio Line Inputs (2x) General The chip features includes two identical line inputs. The blocks can work in mono differential, 2x mono single ended or in stereo single ended mode. The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –34.5dB to +12dB. The stage is set to mute by default. If the line input is not enabled, the volume settings are set to their default values. Changing the volume and mute control can only be done after enabling the input. Figure 53 Line Inputs S tereo Mode Mono Single Ended Mode M ono Differential Mode 7.4.9.2 Parameter Figure 54 Line Input Parameter Symbol A0 Ax R inLINE S NR Parameter Gain Gain Step-Size I nput Resistance Signal to Noise Ratio M ute Attenuation Notes programmable gain M ute Min Gain, single ended stereo 90 120 Min -34.5 1.5 49 100 Typ Max 12 Unit dB dB kOhm kOhm dB dB BVDD = 3.3V, TA= 25oC, fs=48kHz unless otherwise mentioned © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 141 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.9.3 Register Description Table 125 Line Input Related Register Name A udioSet1 Base I2C audio master Offset 0x14 Description Enable/disable driver stage Table 126 LINE_IN1_R & LINE_IN2_R Register Name LINE_IN1_R, LINE_IN2_R Offset: 0x0A, 0x0C Bit 7 :6 5 4 :0 Bit Name L I1R_Mute_off LI2R_Mute_off LI1R_VOL LI2R_VOL Base I2C audio master Default 0x00 Right Line Input Registers T his register is reset when the block is disabled in AudioSet1 register (0x14) or at a DVDD-POR. The register cannot be written when the block is disabled. Default 00 0 00000 Access n/a R/W R/W Bit Description do not change 0 : right line input is set to mute 1 : normal operation volume settings for right line input, adjustable in 32 steps @ 1.5dB 11111: 12 dB gain 11110: 10.5 dB gain .. 00001: -33 dB gain 0 0000: -34.5 dB gain Table 127 LINE_IN1_L & LINE_IN2_L Register Name LINE_IN1_L, LINE_IN2_L Offset: 0x0B, 0x0D Bit 7 :6 Bit Name LI1_Mode LI2_Mode Base I2C audio master Default 0x00 Right Line Input Registers T his register is reset when the block is disabled in AudioSet1 register (0x14) or at a DVDD-POR. The register cannot be written when the block is disabled. Default 00 Access R/W Bit Description Stereo or mono input selection 0 0: inputs switched to single ended stereo 0 1: inputs switched to differential mono 10: inputs switched to single ended mono 11: reserved, do not use. 0 : left line input is set to mute 1 : normal operation volume settings for right line input, adjustable in 32 steps @ 1.5dB 11111: 12 dB gain 11110: 10.5 dB gain .. 00001: -33 dB gain 0 0000: -34.5 dB gain 5 4 :0 L I1L_Mute_off LI2L_Mute_off LI1L_VOL LI2L_VOL 0 00000 R/W R/W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 142 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.10 I2S Digital Audio Interface 7.4.10.1 Input Digital audio data can be fed into the AS3515A via the I2S interface These input data are then used by the 18-bit DAC to generate the analog audio signal. The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –40.5dB to +6dB. The stage is set to mute by default. If the DAC input is not enabled, the volume settings are set to their default values. Changing the volume and mute control can only be done after enabling the input. 7.4.10.2 Output This block consists of an audio multiplexer where the signal, which should be recorded, can be selected. The output is then fed through a volume control to the 14 bit ADC. The digital output is done via an I2S interface. The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –34.5dB to +12dB. The stage is set to mute by default. If the ADC output is not enabled, the volume settings are set to their default values. Changing the volume and mute control can only be done after enabling the input. The I2S output uses the same clocks as the I2S input. The sampling rate therefore depends also on the input sampling rate. 7.4.10.3 Signal Description The digital audio interface uses the standard I2S format: • l eft justified • M SB first • o ne additional leading bit The first 18 bits are taken for DAC conversion. The on-chip synchronization circuit allows any bit-count up 32bit. When there are less than 18 bits sampled, the data sample is completed with “0”s. The ADC output is always 16 bit. If more SCLK pulses are provided, only the first 16 will be significant. All following bits will be “0”. SCLK has not to be necessarily synchronous to LRCK but the high going edge has to be separate from LRCK edges. The LRCK signal has to be derived from a jitter-free clock source, because the on-chip PLL is generating a clock for the digital filter, which has to be always in correct phase lock condition to the external LRCK. The digital part has to provide MCLK (master clock) with 128*fs (fs = audio sampling frequency) over-sampling to guarantee a proper DAC and ADC operation. Figure 55 I2S Left Justified Mode © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 143 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Figure 56 I2S Timing 7.4.10.4 Power Save Options The bias current of the DAC block can be reduced in three steps down to 50% to reduce the power consumption. 7.4.10.5 Clock Supervision The digital audio interface automatically checks the LRCK. An interrupt can be generated when the state of the LRCK input changes. A bit in the interrupt register represents the actual state (present or not present) of the LRCK. 7.4.10.6 Parameter Table 128 Audio Converter Parameter Symbol A0 Ax Gain Parameter Notes p rogrammable gain DAC input programmable gain ADC output Min -43.43 -34.5 1.5 120 S CLK, LRCK, SDI (30%DVDD/2) S CLK, LRCK, SDI (70%DVDD/2) S DO,IRQ @2mA S DO,IRQ @2mA 1.02 2.6 80 80 80 80 80 80 20 -20 0.42 DVDD 0.3 Typ Max 1.07 12 Unit dB dB dB dB V V V V ns ns ns ns ns ns ns ns ns Gain Step-Size M ute Attenuation I 2S inputs / outputs V IL V IH V OL V OH T SCLKH S CLK clock high time T SCLKL S CLK clock low time T SDSU D ata set-up time T SDHD D ata hold time T SDOD D ata Output Delay T LRSU C lock set up time T LRHD C lock hold time T S1, T S2 C lock separation time T JITTER c lock Jitter SDI versus rising edge of SCLK SDI versus rising edge of SCLK SDO versus falling edge of SCLK LRCK versus rising edge of SCLK LRCK versus rising edge of SCLK MCLCK rising edge versus LRCK LRCK 25 20 BVDD = 3.3V, DVDD = 2.9V, TA= 25oC unless otherwise mentioned © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 144 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.10.7 Register Description Table 129 Audio Converter Related Register Name A udioSet_1 A udioSet_2 I RQ_ENRD_1 Base I2C audio master I2C audio master I2C audio master Offset 0x14 0x15 0x25 Description Enable/disable DAC and ADC Power save options and dither control Interrupt settings for LRCK changes Table 130 DAC_R Register Name DAC_R Offset: 0x0E Bit 7 :5 4 :0 Bit Name DAR_VOL Base I2C audio master Default 0x00 Right DAC output Registers T his register is reset when the block is disabled in AudioSet1 register (0x14) or at a DVDD-POR. The register cannot be written when the block is disabled. Default 000 00000 Access n/a R/W Bit Description do not change volume settings for right DAC output, adjustable in 32 steps @ 1.5dB 11111: 6 dB gain 11110: 4.5 dB gain .. 00001: -39 dB gain 0 0000: -40.5 dB gain Table 131 DAC_L Register Name DAC_L Offset: 0x0F Bit 7 6 5 4 :0 Bit Name D AC_Mute_off 0 0 0 00000 Base I2C audio master Default 0x00 Left DAC output Registers T his register is reset when the block is disabled in AudioSet1 register (0x14) or at a DVDD-POR. The register cannot be written when the block is disabled. Default Access n /a R/W n /a R/W Bit Description 0 : DAC output is set to mute 1 : normal operation volume settings for left DAC output, adjustable in 32 steps @ 1.5dB 11111: 6 dB gain 11110: 4.5 dB gain .. 00001: -39 dB gain 0 0000: -40.5 dB gain DAL_VOL © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 145 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 132 ADC_R Register Name ADC_R Offset: 0x10 Bit 7 :6 Bit Name ADCmux Base I2C audio master Default 0x00 Right ADC input Registers T his register is reset when the block is disabled in AudioSet1 register (0x14) or at a DVDD-POR. The register cannot be written when the block is disabled. Default 00 Access R/W Bit Description 0 0: Stereo Microphone 0 1: Line_IN1 10: Line_IN2 11: Audio SUM volume settings for right ADC input, adjustable in 32 steps @ 1.5dB 11111: 12 dB gain 11110: 10.5 dB gain .. 00001: -33 dB gain 0 0000: -34.5 dB gain 5 4 :0 ADR_VOL 00000 R/W Table 133 ADC_L Register Name ADC_L Offset: 0x11 Bit 7 Bit Name A D_FS_4 Base I2C audio master Default 0x00 Left ADC input Registers T his register is reset when the block is disabled in AudioSet1 register (0x14) or at a DVDD-POR. The register cannot be written when the block is disabled. Default 0 Access R/W Bit Description Divider selection for ADC sampling clock 0 : ADC sample clock is I2S LRCK / 2 1 : ADC sample clock is I2S LRCK / 4 0 : ADC output is set to mute 1 : normal operation volume settings for left ADC input, adjustable in 32 steps @ 1.5dB 11111: 12 dB gain 11110: 10.5 dB gain .. 00001: -33 dB gain 0 0000: -34.5 dB gain 6 5 4 :0 A DC_Mute_off 0 0 00000 R/W n /a R/W ADL_VOL © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 146 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.11 Audio Output Mixer 7.4.11.1 General The mixer stage sums up the audio signals of the following stages • M icrophone Input 1 • M icrophone Input 2 • L ine Input 1 • L ine Input 2 • D igital Audio Input (DAC) The mixing ratios have to be with the volume registers of the corresponding input stages. Please be sure that the input signals of the mixer stage are not higher than 1Vp. If summing up several signals, each individual signal has of course to be accordingly lower. This shall insure that the output signal is also not higher than 1Vp to get a proper signal for the output amplifier. This stage features an automatic gain control (AGC), which automatically avoids clipping. 7.4.11.2 Register Description Audio Mixer Related Register Name A udioSet_1 A udioSet_2 Base I2C audio master I2C audio master Offset 0x14 0x15 Description Enable/disable mixer stage Enable/disable AGC The mixer stage has no dedicated registers. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 147 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.12 Audio Settings 7.4.12.1 Register Description Table 134 AudioSet_1 Register Name AudioSet_1 Offset: 0x14 Bit 7 6 5 4 3 2 1 0 Bit Name A DC_on S UM_on D AC_on L OUT_on L IN2_on L IN1_on M IC2_on M IC1_on Base I2C audio master First Audio Set Register T his register is reset at a DVDD-POR. Default 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit Description 0 : ADC disabled 1 : ADC for recording is enabled 0 : Summing / Mixing stage is disabled (no audio output) 1 : Summing / Mixing stage is enabled 0 : DAC disabled 1 : DAC enabled 0 : Line output disabled 1 : Line output enabled 0 : Line input 2 disabled 1 : Line input 2 enabled 0 : Line input 1 disabled 1 : Line input 1 enabled 0 : Microphone input 2 disabled 1 : Microphone input 2 enabled 0 : Microphone input 1 disabled 1 : Microphone input 1 enabled Default 0x00 Table 135 AudioSet_2 Register Name AudioSet_2 Offset: 0x15 Bit 7 6 5 4 :3 Bit Name B IAS_off D ITH_off A GC_off IBR_DAC Base I2C audio master Second Audio Set Register T his register is reset at a DVDD-POR. Default 0 0 0 00 Access R/W R/W R/W R/W Bit Description 0 : bias enabled 1 : bias disabled, for power saving in non audio mode 0 : add dither to the DAC audio stream 1 : no dither added 0 : automatic gain control for summing stage enabled 1 : automatic gain control for summing stage disabled Bias current reduction settings for DAC: 0 0: 0% 0 1: 25% 10: 40% 11: 50% Low power mode for speaker output: 0 : speaker output driver set for 4Ohm to 16Ohm loads 1 : speaker output driver set for 16Ohm or larger loads Bias current reduction settings for speaker output: 0 0: 0% 0 1: 17% 10: 34% 11: 50% Default 0x00 2 L SP_LP 0 R/W 1 :0 IBR_LSP 00 R/W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 148 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 136 AudioSet_3 Register Name AudioSet_3 Offset: 0x16 Bit 7 :3 2 Bit Name Z CU_off Base I2C audio master Third Audio Set Register T his register is reset at a DVDD-POR. Default 00000 0 Access n/a R/W Bit Description do not change Zero cross gain update of audio outputs 0 : zero cross update enabled 1 : zero cross update disabled should be disabled for C21O20 Bias current reduction settings for headphone output: 0 : headphone output driver set for 16Ohm load 1 : headphone output driver set for 32Ohm load or more Headphone common mode buffer settings: 0 : headphone CM buffer is switched on 1 : headphone CM buffer is switched off Default 0x00 1 I BR_HPH 0 R/W 0 H PCM_off 00 R/W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 149 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.13 VBUS CP & Comparator 7.4.13.1 General This block will be used to generate VBUS for USB OTG host operation and to read back VBUS voltage levels to support USB OTG protocols. • • • • I nput Voltage DVDD O utput Voltage 5V (VBUS) r egulated 1:2 charge pump with pulse skipping D river strength: 10mA 7.4.13.2 Register Description Table 137 USB_UTIL Register Name USB_UTIL Offset: 0x17 Bit 7 ..5 4 3 :2 Bit Name L DO6_on COMP_TH Base I2C audio master USB Utility Register T his register is reset at a DVDD-POR. Default 000 0 0 Access n/a R/W R/W Bit Description 0 : UVDD generation disabled 1 : LDO6 for generating UVDD enabled. Sets the threshold for the VBUS comparator 0 0: 4.5V 0 1: 3.18V 10: 1.5V 11: 0.6V 0 : normal operation 1 : enables the skip mode for the VBUS 1:2 charge pump. This is increasing the efficiency for smaller loads, but increasing the VBUS ripple. 0 : disables VBUS charge pump 1 : enables VBUS charge pump Default 0x00 1 S KIP_ENAB 0 R/W 0 C P_5V_on 0 R/W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 150 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.14 Auxiliary Oscillator 7.4.14.1 General This block is a low power oscillator, which can provide a clock to the digital core. CLK_OUT pad of the AFE is connected to clk_int pad of the digital die. 7.4.14.2 Register Description Table 138 CLOCK_OUT Register Name CLOCK_OUT Offset: 0x1D Bit 7 ..5 4 :3 Bit Name CLKOUT_mode Base I2C audio master Clock Output Register T his register is reset at a DVDD-POR. Default 000 00 Access n/a R/W Bit Description CLKOUT pin frequency divider 0 0: oscillator frequency direct mode 0 1: osc freq. divide by 2 10: osc freq. divide by 4 11: OFF CLKOUT pin driver strength adjustment 0 0: 4mA PushPull 0 1: 2mA PushPull 10: 1mA PushPull 11: 0.5mA PushPull 0 : 24MHz oscillator enabled 1 : 24MHz oscillator in power down Default 0x00 2 :1 CLKOUT_drive 00 R/W 0 O SC_pd 0 R/W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 151 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.15 Charger 7.4.15.1 General This block can be used to charge a 4V Li-Io accumulator. It supports constant current and constant voltage charging modes with adjustable charging currents (50 to 400mA) and maximum charging voltage (3.9 to 4.25V). Figure 57 Charger States 7.4.15.2 Trickle Charge If the battery voltage is below 3V, the charger goes automatically in trickle charge mode with 50mA charging current and 3.9V endpoint voltage. In this mode charging current and voltage are not precise, but provide a charger function also for deep discharged batteries. The temperature supervision is not enabled in trickle charge mode. 7.4.15.3 Temperature Supervision This charger block also features a 15uA supply for an external 100k NTC resistor to measure the battery temperature while charging. If the temperature is too high, an interrupt can be generated. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 152 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.15.4 Parameter Table 139 Charger Parameter Symbol I CHG_trick V CHG_trick I CHG ( 0-7) Parameter C harging Current (trickle charge) Notes Min Typ Max Unit mA mA V mA V V mV mV mV mV mA nA B VDD3V BVDD >3V BVDD >3V BVDD = 5V, CHG_IN open V CHG ( 0-7) Charging Voltage V ON_ABS V ON_REL V OFF_REL V BATEMP_ON V BATEMP_OFF I CHG_OFF I REV_OFF C harger On Voltage IRQ C harger On Voltage IRQ C harger Off Voltage IRQ B attery Temp. high level (55°C) B attery Temp. low level (50°C) E nd Of Charge current level R everse current shut down 37 68 111 17 32 55 0.70* 0.72* 0.74* CHG_IN CHG_IN CHG_IN I NOM I NOM I NOM - 20% + 20% V NOM V NOM V NOM - 50mV + 30mV 3.1 4.0 170 240 40 77 380 400 420 480 500 520 1 0% 1 5% 5% I NOM I NOM I NOM 160 336 420 BVDD=3.6V; Tamb=25ºC; unless otherwise specified 7.4.15.5 Register Description Charger Related Register Name I RQ_ENRD_0 Base I2C audio master Offset 0x25 Description Enable/disable EOC and battery over-temperature interrupt Read out charger status Table 140 Charger Register Name Charger Offset: 0x22 Bit 7 6 :4 Bit Name T MPSup_off CHG_I Base I2C audio master Charger Register T his register is reset at a DVDD-POR. Default 0 000 Access R/W R/W Bit Description 0 : enables 15uA supply for external 100k NTC resistor 1 : disables supply set maximum charging current 111: 400 mA 110: 350 mA .. 001: 100 mA 0 00: 50 mA set maximum charger voltage 111: 4.25 V 110: 4.2 V .. 001: 3.95 V 0 00: 3.9 V 0 : enables Charger 1 : disables Charger Default 0x00 3 :1 CHG_V 000 R/W 0 C HG_OFF 0 R/W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 153 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.16 15V Step-Up Converter 7.4.16.1 General The integrated Step-Up DC/DC Converter is a high efficiency current-mode PWM regulator, providing an output voltage up to 15V. A constant switching-frequency results in a low noise on supply and output voltages. When using an additional transistor the output voltage can be up to 25V to drive 6 white LED in series. It has an adjustable sink current (1.25 to 38.75mA) to provide e.g. dimming function when driving white LEDs as back-light. 7.4.16.2 Parameter Table 141 15V Step-Up Converter Parameter Symbol V SW I VDD V FB V FB I SW_MAX R SW I LOAD V PULSESKIP Parameter H igh Voltage Pin Q uiescent Current F eedback Voltage, Transient F eedback Voltage, during Regulation C urrent Limit S witch Resistance L oad Current P ulse-skip Threshold Notes Pin SW15 Pulse Skipping mode Pin ISINK Pin ISINK V15_ON = 1 V15_ON = 0 @ 15V output voltage Voltage at pin ISINK, pulse skips are introduces w hen load current becomes too low. Ceramic Use inductors with small C PARASITIC ( 2 0mA I LOAD < 2 0mA M inimum On-Time Maximum Duty Cycle 0.5 17 8 90 88 0.55 1 22 10 91 0.6 27 27 180 94 MHz µF µH t MIN_ON M DC Guaranteed per design ns % BVDD=3.6V; Tamb=25ºC; unless otherwise specified © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 154 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Figure 58 15V Step-Up Performance Characteristics Efficiency vs Output Current 100 90 80 VIN=3.6V EFFICIENCY [%] 70 60 50 40 30 20 1 DCDC stepup Current controlled 0..15V OUTPUT CURRENT [mA] 10 100 7.4.16.3 Register Description Table 142 DCDC15 Register Name DCDC15 Offset: 0x23 Bit 7 :5 4 :0 Bit Name I_V15 Base I2C audio master 15V DCDC Register T his register is reset at a DVDD-POR. Default 000 00000 Access n/a R/W Bit Description defines the current through the LED = 1.25mA * I_V15 0 0000: DCDC15 switched off 0 0001: 1.25mA 00010: 2.5mA .. 11110: 37.5mA 11111: 38.75mA Default 0x00 © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 155 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.17 Supervisor 7.4.17.1 General This supervisor function can be used for automatic detection of BVDD brown out or junction over-temperature condition. 7.4.17.2 BVDD Supervision The supervision level can be set in 8 steps @ 60mV from 2.74 to 3.16V. If the level is reached an interrupt can be generated. If BVDD reaches 2.6V the AFE shuts down automatically. 7.4.17.3 Junction Temperature Supervision The temperature supervision level can also be set by 5 bits (120 to –15oC). If the temperature reaches this level, an interrupt can be generated. The over-temperature shutdown level is always 20oC higher. If the IRQ level is set to 120oC the shutdown is disabled. 7.4.17.4 Register Description Table 143 Supervisor Related Register Name I RQ_ENRD_0 I RQ_ENRD_1 Base I2C audio master I2C audio master Offset 0x25 0x26 Description Enable/disable battery brown out interrupt Enable/disable junction temperature interrupt Table 144 Supervisor Register Name Supervisor Offset: 0x24 Bit 7 :5 Bit Name BVDD_Sup Base I2C audio master Supervisor Register T his register is reset at a DVDD-POR. Default 000 Access R/W Bit Description supervision of BVDD brown out V_BrownOut=2.74+x*60mV 0 00: 2.74V 0 01: 2.80V … 110: 3.10V 111: 3.16V junction temperature supervision: Temp_ShutDown=140-x*5 ° C Temp_IRQ=120-x*5 ° C Default 0x00 4 :0 JT_Sup 00000 R/W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 156 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.18 Interrupt Generation 7.4.18.1 General All interrupt sources can get enabled or disabled by corresponding bits in the 3 IRQ-bytes. By default no IRQ source is enabled. The IRQ output can get configured to be PUSH/PULL or OPEN_DRAIN and ACTIVE_HIGH or ACTIVE LOW with 2 bits in IRQ_ENRD_2 register (0x27). Default state is open drain and active_low. 7.4.18.2 IRQ Source Interpretation There are 3 different modules to process interrupt sources: 7.4.18.3 LEVEL The IRQ output is kept active as long as the interrupt source is present and this IRQ-Bit is enabled 7.4.18.4 EDGE The IRQ gets active with a high going edge of this source. The IRQ stays active until the corresponding IRQ-Register gets read. 7.4.18.5 STATUS CHANGE The IRQ gets active when the source-state changes. The change bit and the status can be read to notice which interrupt was the source. The IRQ stays active until the corresponding interrupt register gets read. 7.4.18.6 De-bouncer There is a de-bounc function implemented for USB and CHARGER. Since these 2 signals can be unstable for the phase of plug-in or unplug, a debounce time of 512ms/256ms/128ms can be selected by 2 bits in the IRQ_ENRD2 register (0x27h). Table 145 First Interrupt Register Name IRQ_ENRD_0 Base I2C audio master Default 0x00 Offset: 0x25 First Interrupt Register P lease be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR. Default 0 Access W Bit Description b attery over-temperature interrupt setting 0 : disable 1 : enable The interrupt must not be enabled if the charger block and battery temperature supervision is disabled Battery over-temperature interrupt reading 0: battery temperature below 55°C 1: battery temperature was too high and the charger was turned off. The charger will be turned on again, when the temperature gets below 50°C B attery end of charge interrupt setting 0 : disable 1 : enable The interrupt must not be enabled if the charger block is disabled Battery end of charge interrupt reading 0: battery charging in progress 1: charging is complete, turn charger off To check end of charge again the charger has to be turned on. 0: no charger input source connected 1: charger input source connected, also valid if charger is connected during wakeup Bit 7 Bit Name C HG_tmphigh (level) x R 6 C HG_endofch (edge) 0 W x R 5 C HG_status x R © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 157 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Name IRQ_ENRD_0 Base I2C audio master Default 0x00 Offset: 0x25 First Interrupt Register P lease be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR. Default 0 Access W Bit Description C harger input status change interrupt setting 0 : disable 1 : enable enables an interrupt on a low to high or high to low change of CHG_IN pin. The thresholds are set in Charger input status change interrupt reading 0: charger input status not changed 1: charger input status changed, check CHG_status 0: no USB input connected 1: USB input connected, also valid if USB is connected during wakeup U SB input status change interrupt setting 0 : disable 1 : enables an interrupt on a low to high or high to low change of VBUS pin. The threshold can be set in the USB_UTIL register (0x17) USB input status change interrupt reading 0: USB input status not changed 1: USB input status changed, check USB_status R eal time clock supply interrupt setting 0 : disable 1 : enable Real time clock supply interrupt reading 0 : RTC supply o.k. 1 : RTC supply was low, RTC not longer valid The interrupt gets set during power-up even if the interrupt is not enabled. For a valid reading, the interrupt has to be enabled first. S upervisor BVDD interrupt setting 0 : disable 1 : enable Supervisor BVDD interrupt setting 0: BVDD is above brown out level 1:BVDD has reached brown out level The threshold can be set in the SUPERVISOR register (0x24) Bit 4 Bit Name C HG_changed (status change) x R 3 U SB_status x R 2 U SB_changed (status change) 0 W x R 1 R VDD_waslow (level) 0 W x R 0 B VDD_islow 0 W x R © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 158 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 146 Second Interrupt Register Name IRQ_ENRD_1 Base I2C audio master Default 0x00 Offset: 0x26 Second Interrupt Register P lease be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR. Default 0 Access W Bit Description S upervisor junction over-temperature interrupt setting 0 : disable 1 : enable Supervisor junction over-temperature interrupt reading 0: chip temperature below threshold 1: chip temperature has reached the threshold The threshold can be set in the SUPERVISOR register (0x24) S peaker over-current interrupt setting 0 : disable 1 : enable The interrupt must not be enabled if the speaker block is disabled Speaker over-current interrupt reading 0: no over-current detected 1: speaker over-current detected, speaker amplifier was shut down. The shut-down time can be set in LSP_OUT_R register (0x04) H eadphone over-current interrupt setting 0 : disable 1 : enable The interrupt must not be enabled if the headphone block is disabled Headphone over-current interrupt reading 0: no over-current detected 1: headphone over-current detected, headphone amplifier was shut down. The shut-down time can be set in HPH_OUT_R register (0x02) 0: no LRCK on I2S interface detected 1: LRCK on I2S interface present I 2S input status change interrupt setting 0 : disable 1 : enable I2S input status change interrupt reading 0: I2S input status not changed 1: I2S input status changed, check I2S_status M icrophone 2 connect detection interrupt setting 0 : disable 1 : enable Microphone 2 connect detection interrupt reading 0: no microphone connected to MIC2 input 1: microphone connected at MIC2 input. IRQ will be released after enabling the microphone stage. Detecting a microphone during operation has to be done by measuring the supply current. Bit 7 Bit Name J TEMP_high (level) x R 6 L SP_overcurr (level) 0 W x R 5 H PH_overcurr (level) 0 W x R 4 3 I 2S_status I 2S_changed (status change) x 0 R W x R 2 M IC2_connect (level) 0 W x R © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 159 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 1 M IC1_connect (level) 0 W x R 0 H PH_connect (level) 0 W x R M icrophone 1 connect detection interrupt setting 0 : disable 1 : enable Microphone 1 connect detection interrupt reading 0: no microphone connected to MIC1 input 1: microphone connected at MIC1 input. IRQ will be released after enabling the microphone stage. Detecting a microphone during operation has to be done by measuring the supply current. H eadphone connect detection interrupt setting 0 : disable 1 : enable Headphone connect detection interrupt reading 0: no headphone connected 1: headphone connected IRQ will be released after enabling the headphone stage. Detecting a headphone during operation is not possible. Table 147 Third Interrupt Register Name IRQ_ENRD_2 Base I2C audio master Default 0x00 Offset: 0x27 Third Interrupt Register P lease be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR. Default 00 Access R/W Bit Description Sets the USB and Charger connect de-bounce time: 0 0: 512ms 0 1: 256ms 10: 128ms 11: not defined Sets the active output state of the INTRQ line: 0 : IRQ is active low 1 : IRQ is active high Sets the INTRQ output buffer type: 0 : IRQ output is open drain 1 : IRQ output is push pull M icrophone 2 remote key press detection interrupt setting 0 : disable 1 : enable Microphone 2 remote key press detection interrupt reading 0 : no key press detected 1 : Microphone 2 supply current got increased, remote key press detected -> measure MSUP2 supply current M icrophone 1 remote key press detection interrupt setting 0 : disable 1 : enable Microphone 1 remote key press detection interrupt reading 0: no key press detected 1: Microphone 1 supply current got increased, remote key press detected -> measure MSUP1 supply current RTC timer interrupt setting 0 : disable 1 : enable Bit 7 :6 Bit Name T_deb 5 I RQ_Acthigh 0 R/W 4 I RQ_PushPull 0 R/W 3 R emote_Det2 (edge) 0 W x R 2 R emote_Det1 (edge) 0 W x R 1 R TC_update (edge) 0 W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 160 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Name IRQ_ENRD_2 Base I2C audio master Default 0x00 Offset: 0x27 Third Interrupt Register P lease be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR. Default x Access R Bit Description R TC timer interrupt reading 0: not RTC interrupt occurred 1: RTC timer interrupt occurred.Selecting minute or second interrupt can be done via RTCT register (0x29) A DC end of conversion interrupt setting 0 : disable 1 : enable ADC end of conversion interrupt reading 0: ADC conversion not finished 1: ADC conversion finished. Read out ADC_0 and ADC_1 register to get the result (0x2E & 0x2F) Bit Bit Name 0 A DC_EndCon (edge) 0 W x R © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 161 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.19 Real Time Clock 7.4.19.1 General The real time clock block is an independent block, which is still working even when the chip is shut down. The only condition for this operation is that BVDD has a voltage of above 1.0V. The block uses a standard 32kHz crystal that is connected to a low power oscillator. An internal 32bit second register stores the current time. The RTC block has special functions for trimming the time base and generating interrupts every second or minute. 7.4.19.2 RTC supply The internal RTC is supplied via the BVDD pin. The block has an internal LDO to generate the RTC supply voltage on RVDD pin. This voltage can be programmed via the RTCV register (0x28h). If the internal RTC is not used, RVDD can be used to supply an external RTC block. If the supply voltage on BVDD pin rises, the whole chip gets powered up. See also power-up conditions in chapter 7.4.1.2. 7.4.19.3 Register Description Table 148 RTC Related Register Name I RQ_ENRD_0 I RQ_ENRD_2 Base I2C audio master I2C audio master Offset 0x25 0x27 Description Interrupt settings for RVDD under-voltage detection Interrupt settings for getting a second or minute interrupt Table 149 RTCV Register Name RTCV Offset: 0x28 Bit 7 :4 Bit Name VRTC Base I2C audio master RTC Voltage Register T his register is reset at a RVDD-POR. (DVDD_POR for C21O20) Default 0010 Access R/W Bit Description Sets the RTC supply voltage, 16 steps @ 0.1V, default is 1.2V 0000: 1V 0001: 1.1V 0 010: 1.2V … 1 110: 2.4V 1111: 2.5V do not change RTC clock control: 0: Disable clock for RTC 1 : Enables clock for RTC RTC oscillator control: 0: Disables RTC oscillator 1 : Enables RTC oscillator Default 0x23 3 :2 1 R TC_ON 00 1 n/a R/W 0 O SC_ON 1 R/W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 162 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 150 RTCV Register Name RTCT Offset: 0x29 Bit 7 6 :0 Bit Name I RQ_MIN TRTC Base I2C audio master RTC Timing Register T his register is reset at a RVDD-POR. (DVDD_POR for C21O20) Default 0 1000000 Access R/W R/W Bit Description 0 : generates an interrupt every second 1 : generates an interrupt every minute Trimming register for RTC, 128 steps @ 7.6ppm 000000: 1 (7.6ppm) 000001: 2 (15.2ppm) … 1 00000: 64 (488ppm) … 1 11110: 126 (960.8ppm) 111111: 127 (968.4ppm) Default 0x40 Table 151 RTC_0 to RTC_3 Register Name RTC_0 to RTC_3 Offset: 0x2A to 0x2D Adr. 0 x2A 0 x2B 0 x2C 0 x2D Byte Name RTC_0 RTC_1 RTC_2 RTC_3 Base I2C audio master Default 0x00 00 00 00 Unique ID Register T his register is reset at a RVDD-POR. Default 0x00 0x00 0x00 0x00 Access R/W R/W R/W R/W Bit Description RTC; RTC seconds bits 0 to 7 RTC; RTC seconds bits 8 to 15 RTC; RTC seconds bits 9 to 23 RTC; RTC seconds bits 24 to 31 © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 163 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.20 10-Bit ADC 7.4.20.1 General This general purpose ADC can be used for measuring several voltages and currents to perform functions like battery monitor, temperature supervision, button press detection, etc.. . Please note that C21O20 is measuring BVDD instead of CHG_OUT 7.4.20.2 Input Sources Table 152 ADC10 Input Sources Nr. 0 1 2 3 4 5 6 7 8 9 10 11 12 1 3..15 Source C HG_OUT R TCSUP V BUS C HG_IN C VDD B atTemp M icSup1 M icSup2 V BE1 V BE2 I_MicSup1 I_MicSup2 VBAT Reserved Range 5.120V 5.120V 5.120V 5.120V 2.560V 2.560V 2.560V 2.560V 1.024 1.024 1.024mA typ. 1.024mA typ. 2.560V 1.024V LSB 5mV 5mV 5mV 5mV 2.5mV 2.5mV 2.5mV 2.5mV 1mV 1mV 1.0uA 1.0uA 2.5mV 1mV Description check battery voltage of 4V LiIo accumulator check RTC backup battery voltage (connected to BVDD inside the package) check USB host voltage check charger input voltage check charge pump output voltage check battery charging temperature check voltage on MicSup1 for remote control or external voltage measurement check voltage on MicSup2 for remote control or external voltage measurement measuring junction temperature measuring junction temperature check current of MicSup1 for remote control detection check current of MicSup2 for remote control detection check single cell battery voltage for testing purpose only CHG_OUT, RTCSUP, VBUS, CHG_IN These sources are fed into an 1/5 voltage divider (180kΩ typ.) and further amplified by 2.5. CVDD, BatTemp, MicSup1, MicSup2 These sources are fed directly to the ADC input multiplexer. VBE1, VBE2 These inputs are first amplified by 2.5 and than fed to the ADC input multiplexer. I_MicSup1, I_MicSup2 The measurement of the microphone supply LDOs is not very accurate, as the current-voltage conversion is only done by a single resistor which shows wide process and temperature variations. These measurements should be only used for remote function detection. VBAT This source is divided by 2.5 with a voltage divider (180kΩ typ.) and than amplified by 2.5. This has to be done, as VBAT can represent voltages up to 3.6V. Please note, that the maximum measurement rage will be still 2.560V 7.4.20.3 Reference AVDD=2.9V is used as reference to the ADC. AVDD is trimmed to +/-20mV with over all precision of +/-29mV. So the absolute accuracy is +/-1%. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 164 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.20.4 Parameter Table 153 ADC10 Parameter Symbol R DIV A DC FS R atio1 R atio2 G ain T CON I _MIC FS Parameter I nput Divider Resistance Notes CHG_OUT, RTCSUP, VBUS, CHG_IN, VBAT Min 138k 2.534 0.198 0.396 2.475 0.7 Typ 180k 2.56 0.2 0.4 2.5 34 1.0 Max 234k 2.586 0.202 0.404 2.525 50 1.4 Unit Ω V 1 1 V µs mA A DC Full Scale Range Divition Factor 1 CHG_OUT, RTCSUP, VBUS, CHG_IN Divition Factor 2 VBAT ADC Gain Stage C onversion Time I _MicSup1/2 Full Scale Range BVDD=3.6V; Tamb=25ºC; unless otherwise specified 7.4.20.5 Register Description Table 154 ADC10 Related Register Name I RQ_ENRD_2 Base I2C audio master Offset 0x27 Description Interrupt settings for end of conversion interrupt Table 155 ADC_0 Register Name ADC_0 Offset: 0x2E Bit 7 :4 Bit Name ADC_Source Base I2C audio master Default 0000 00xx First 10-bit ADC Register W riting to this register will start the measurement of the selected source. This register is reset at a DVDD-POR, exception are bit 8 and 9. Default 00000000 Access R/W Bit Description Selects ADC input source 0 000: CHG_OUT 0 001: RTCSUP 0010: VBUS 0011: CHG_IN 0100: CVDD 0101: BatTemp 0110: MicSup1 0111: MicSup2 1000: VBE_1uA 1001: VBE_2uA 1010: I_MicSup1 1011: I_MicSup2 1100: VBAT 1101: reserved 1110: reserved 1101: reserved do not change ADC result bit 9 to 8 3 :2 1 :0 ADC 00 xx n/a R/W © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 165 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Table 156 ADC_1 Register Name ADC_1 Offset: 0x2F Bit 7 :0 Bit Name ADC Base I2C audio master Second 10-bit ADC Register T his register is not reset. Default xxxx xxxx Access R/W Bit Description ADC result bit 7 to 0 Default xxxx xxxx © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 166 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.21 128 bit OTP ROM 7.4.21.1 General This fuse array is used to store a unique identification number, which can be used for DRM issues. The number is generated and programmed during the production process. 7.4.21.2 Register Description Table 157 UID_0 to UID_15 Register Name UID_0 to UID_15 Offset: 0x30 to 0x3F Adr. 0 x30 0 x31 0 x32 0 x33 0 x34 0 x35 0 x36 0 x37 0 x38 0 x39 0 x3A 0 x3B 0 x3C 0 x3D 0 x3E 0 x3F Byte Name UID_0 UID_1 UID_2 UID_3 UID_4 UID_5 UID_6 UID_7 UID_8 UID_9 UID_10 UID_11 UID_12 UID_13 UID_14 UID_15 Base I2C audio master Default n/a Unique ID Register T his register is read only and is not reset. Default 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 n/a n/a n/a n/a n/a n/a n/a n/a Access R R R R R R R R R R R R R R R R Bit Description Unique Unique Unique Unique Unique Unique Unique Unique Unique Unique Unique Unique Unique Unique Unique Unique ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 167 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.22 2-Wire-Serial Control Interface 7.4.22.1 General There is an I2C slave block implemented to have access to 64 byte of setting information. The I2C address is: Adr_Group8 - audio processors • • 8 Ch_write 8 Dh_read Figure 59 I2C timing 7.4.22.2 Parameter Table 158 I2C Operating Conditions Symbol V IL V IH H YST V OL T sp TH TL T SU T HD TS T PD Parameter I nput low voltage I nput high voltage Hysteretic O utput low voltage S pike insensitivity C lock high time C lock low time D ata setup time Notes CSCL, CSDA (max 30%DVDD) CSCL, CSDA (min 70%DVDD) CSCL, CSDA CSDA @3mA Min 0 2.03 200 50 500 500 100 0 200 24 50 80 Typ Max 0.87 5.5 800 0.4 Unit V V mV V ns ns ns ns ns ns ns 450 100 CSDA has to change T SU b efore rising edge of CSCL D ata hold time No hold time needed for CSDA relative t o rising edge of CSCL Clock start-condition hold time CSCL HIGH hold time relative to CSDA edge for start/stop/rep_start O utput delay CSDA propagation delay relative to low going edge of CSCL DVDD =2.9V, Tamb=25ºC; unless otherwise specified © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 168 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 7.4.22.3 Register Description Registers Overview (00h to 3Fh) Table 159 I2C Register Overview Addr 0 0h Name D D D D D D D D L INE_OUT_R r eserved 0 0 L INE_OUT_L L O_SES_DM 0 0 HPH_OUT_R H P_OVC_TO 0 0 H P_Mute_ HP_on on 0 0 S P_OVC_TO 0 0 S P_Mute_ S P_on on 0 M ic1_AGC _ off 0 M ic1_Sup _off 0 M ic2_AGC _ off 0 M ic2_Sup _ off 0 - 0 1h 0 2h 0 3h HPH_OUT_L 0 4h L SP_OUT_R 0 5h L SP_OUT_L L OR_Vol G ain from Mixer_Out 0 0 0 L OL_Vol G ain from Mixer_Out 0 0 0 HPR_Vol Gain from Mixer_Out 0 0 0 HPdet_on H PL_Vol Gain from Mixer_Out 0 0 0 S PR_Vol G ain from Mixer_Out 0 0 0 S PL_Vol G ain from Mixer_Out to Line_Out= (-40.5dB … +6dB) 0 0 0 to Line_Out= (-40.5dB … +6dB) 0 0 0 to HPH_Out= (-45.43dB … +1.07dB) 0 0 0 to HPH_Out= (-45.43dB … +1.07dB) 0 0 0 to LSP_Out= (-40.5dB … +6.0dB) 0 0 0 to LSP_Out= (-40.5dB … +6.0dB) 0 6h MIC1_R 0 7h MIC1_L 0 8h M IC2_R 0 9h M IC2_L 0 Ah Line_IN1_R 0 Bh Line_IN1_L 0 Ch L ine_IN2_R 0 Dh L ine_IN2_L 0 Eh DAC_R 0 0 0 0 0 Mic1R_Vol Gain from MicAmp_Out to Mixer_In= (-40.5dB … +6.0dB) 0 0 0 0 0 0 0 Mic1_Mute Mic1L_Vol _ off Gain from MicAmp_Out to Mixer_In= (-40.5dB … +6.0dB) 0 0 0 0 0 0 0 M ic2_Gain M ic2R_Vol G ain from MicAmp_Out to Mixer_In= (-40.5dB … +6.0dB) 0 0 0 0 0 0 0 M ic2_Mute M ic2L_Vol _ off G ain from MicAmp_Out to Mixer_In= (-40.5dB … +6.0dB) 0 0 0 0 0 0 0 L I1R_Mut LI1R_Vol e Gain from LineIn_Pin to Mixer_In=-34.5dB+LI1R_VOL*1.5dB _off (-34.5dB … +12dB) 0 0 0 0 0 0 0 0 L I1_Mode LI1L_Mut LI1L_Vol e Gain from LineIn_Pin to Mixer_In= (-34.5dB … +12dB) _off 0 0 0 0 0 0 0 0 L I2R_Mut L I2R_Vol e_off G ain from LineIn_Pin to Mixer_In= (-34.5dB … +12dB) 0 0 0 0 0 0 0 0 L I2_Mode L I2L_Mut L I2L_Vol e_off G ain from LineIn_Pin to Mixer_In= (-34.5dB … +12dB) 0 0 0 0 0 0 0 0 D AR_Vol Gain from DAC_Out to Mixer_In= (-40.5dB … +6dB) 0 0 0 0 0 0 0 0 0 0 Mic1_Gain © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 169 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Addr 0 Fh Name DAC_L - D D D D D D D D 1 0h 1 1h 1 4h 1 5h 1 6h 1 7h 1 Dh 2 0h 2 1h 2 2h 2 3h 2 4h 2 5h 2 6h 2 7h 2 8h 2 9h 2 Ah 2 Bh 2 Ch 2 Dh 2 Eh DAL_Vol Gain from DAC_Out to Mixer_In= (-40.5dB … +6dB) 0 0 0 0 0 A DC_R A DR_Vol G ain from ADCMux_Out to ADC_In= (-34.5dB … +12dB) 0 0 0 0 0 0 0 0 A DC_L A D_FS2 A DC_Mute A DL_Vol _ off G ain from ADCMux_Out to ADC_In= (-34.5dB … +12dB) 0 0 0 0 0 0 0 0 AudioSet1 A DC_on SUM_on DAC_on LOUT_on LIN2_on LIN1_on MIC2_on MIC1_on 0 0 0 0 0 0 0 0 AudioSet2 B IAS_off DITH_off AGC_off IBR_DAC LSP_LP IBR_LSP 0 0 0 0 0 0 0 0 AudioSet3 Z CU_OFF IBR_HPH HPCM_off 0 0 0 0 0 0 0 0 U SB_UTIL L DO6_on C OMP_TH S KIP_ENAB C P_5V_on 0 0 0 0 0 0 0 0 CLOCK_OUT C LK_OUT_mode CLKOUT_drive OSC_pd 0 0 0 0 0 0 0 0 S YSTEM D esign_Version P VDDp I OVDDp E nWDogPw P wrUPHld dn 0 0 1 0 0 0 0 1 CVDD/DCDC3 C P_SW CP_on LREG_C DCDC3p LREG_off CVDDp P_not 0 0 0 0 0 0 0 0 C HARGER T mpSup_ C HGI C HGV C HG_off off 0 0 0 0 0 0 0 0 DCDC15 I _V15 0 0 0 0 0 0 0 0 S UPERVISOR B VDD_Sup J T_Sup 0 0 0 0 0 0 0 0 IRQ_ENRD0 C HG CHG CHG CHG USB USB RVDD BVDD tmphigh endofch status changed status changed was low Is low 0 0 0 0 0 0 0 0 IRQ_ENRD1 J TEMP LSP HPH I2S I2S Mic2 Mic1 HeadPh high overcurr overcurr status changed connect connect Connect 0 0 0 0 0 0 0 0 IRQ_ENRD2 T _deb IRQ_ActH IRQ_PushP Remote_Det Remote_D RTC_Updat ADC_EndCo igh ull 2 et1 e n 0 0 0 0 0 0 0 0 R TCV V RTC R TC_ON O SC_ON 0 0 1 0 0 0 1 1 R TCT I RQ_MIN T RTC 0 1 0 0 0 0 0 0 R TC_0 R TC 0 0 0 0 0 0 0 0 R TC_1 R TC 0 0 0 0 0 0 0 0 R TC_2 R TC 0 0 0 0 0 0 0 0 R TC_3 R TC 0 0 0 0 0 0 0 0 ADC_0 A DC_Source ADC 0 0 0 0 0 0 X X D AC_Mute _ off 0 0 0 A DCmux - © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 170 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Addr 2 Fh 3 0-3F Name ADC_1 U ID_0 .. 15 D D X D X D X D X D X D X D A DC X X I D … I D © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 171 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 8 8.1 Pinout and Packaging Package Variants CTBGA (Thin ChipArray BGA) package technology is used for multi-chip-module (MCM) packaging. The following package variants are available for the product: Table 160 Package Options Product Code A S3525-A AS3525-B Package CTBGA CTBGA Balls 224 144 Ball Matrix 15x15, 7 Row 12x12, full Pitch [mm] 0.8 0.8 Height [mm] 1.2 1.2 Size [mm] 13x13 10x10 Application with external SDRAM interface w/o external SDRAM interface 8.2 CTBGA224 Package Drawings 8.2.1 Marking Figure 60 CTBGA224 Package Marking AS3525A C22O22 AYWWZZZ Package Code AYYWWZZZ A A … for PB free Y Year WW working week assembly/packaging ZZZ Free choice Figure 61 CTBGA224 Package Drawing © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 172 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 8.2.2 1 A B C D E F G H J K L M N P R CTBGA224 Package Ball-out 2 xpc_7 Figure 62 AS3525A Package Ball--out 3 xpc_3 4 xpa_2 5 6 7 8 9 10 11 12 ide_ha_0 13 naf_d_1 14 dbop_d14 15 vdd_peri jtag_tms mpmc_addr_3 mpmc_addr_9 mpmc_addr_17 mpmc_cas_n mpmc_bls_n_0 mpmc_data_5 mpmc_data_13 jtag_tdi jtag_tck xpc_5 xpa_0 mpmc_addr_1 mpmc_addr_11 mpmc_addr_19 vss_mem vdd_mem mpmc_data_7 mpmc_data_15 naf_d_7 naf_d_4 naf_d_2 vss_peri i2si_sdata_in jtag_trst_n xpc_6 xpc_1 xpa_6 mpmc_addr_7 mpmc_addr_15 vss_mem vdd_mem mpmc_data_9 ssp_fssout naf_d_5 naf_d_0 naf_d_8 dbop_d15 i2si_lrck_out tmsel jtag_tdo xpc_4 xpa_4 mpmc_addr_5 mpmc_addr_13 mpmc_dqm_0 mpmc_stcs_n_0 mpmc_oe_n ssp_rxd ide_ha_2 naf_d_3 naf_d_14 naf_d_11 clk_ext clk_sel i2si_sclk_out i2si_mclk xpc_0 mpmc_addr_8 mpmc_addr_14 mpmc_clk_0 mpmc_dycs_n_1 mpmc_data_1 mpmc_data_11 naf_d_9 naf_d_13 naf_d_15 naf_ce0_n id_dig usb_vdda33t VBUS xpc_2 xpa_7 mpmc_addr_6 mpmc_addr_16 mpmc_cke_0 mpmc_we_n mpmc_data_3 naf_d_10 naf_d_12 naf_ale naf_cle naf_bsy_n usb_dp usb_vssa33t dbop_d12 xpa_1 mpmc_addr_0 mpmc_addr_18 mpmc_clk_1 mpmc_data_10 mpmc_data_12 ide_reset_n naf_d_6 naf_wp_n naf_ce3_n naf_we_n xpd_3 usb_dm usb_vssa33t dbop_d13 xpa_3 mpmc_addr_10 mpmc_addr_20 mpmc_data_8 ssp_clkout ide_ha_1 naf_ce1_n naf_re_n xpd_0 xpd_4 xpd_7 usb_vssa33c usb_rkelvin_rext usb_vdda33c xpa_5 mpmc_addr_12 mpmc_cke_1 mpmc_ras_n mpmc_data_6 mpmc_data_14 ssp_txd naf_ce2_n xpd_1 xpd_2 xpd_5 xpd_6 vdd_core nc DVDD nc mpmc_addr_4 mpmc_dycs_n_0 mpmc_bls_n_1 mpmc_data_4 xpb_4 xpb_3 xpb_2 xpb_5 xpb_7 SW_15V SW_3V vss_core nc PwrUP mpmc_addr_2 mpmc_fbclkin mpmc_dqm_1 mpmc_stcs_n_1 mpmc_data_0 mpmc_data_2 xpb_0 xpb_1 xpb_6 CN_5V CP_5V VSS_3V CLK_OUT XRES CSDA CSCL MCLK SDI SDO VREF HPCM BATTEMP ISINK VSS_15V VBAT_1V QLDO2 VSS_1V INTRQ P_PVDD MSUP2 LOUTR LRCK SCLK LOUTL AVDD HPGND HPR BGND BVSS2 HPL CHG_IN CN_1V DVSS LIN2R LIN1R MIC2_N MIC1_N MSUP1 BVSS AGND BVDD BVDD BVDD IOVDD RVDD CHG_OUT CP_1V XIN_24M XOUT_24M LIN2L LIN1L MIC2_P MIC1_P AVSS BVSS LSPR LSPL UVDD PVDD XIN_32k XOUT_32k CVDD Note: PINs K2, L2 and K4 are reserved for production test purposes and must be left not connected for normal operation mode. 8.2.3 CTBGA224 Ball List Table 161 CTBGA224 Ball List Ball Nr. BGA224 M2 M1 E1 E2 D2 F1 Ball Name X RES r esetext_n C LK_OUT c lk_int clk_ext clk_sel tmsel id_dig PAD Type DO D I N ST DO D I N ST D IN ST PD D IN ST PD D IN ST PD D IN ST (PU) I I I/O O I O I I I Ball Description X RES i s generated by the PMU subsystem a nd connected to reset input (active low) on the BGA C LK_OUT is o utput of 20-24MHz crystal oscillator clock a nd connected to c lk_int o n the BGA external clock input (10-26MHz) clock select 0 (low): clock from internal oscillator is used 1 (high): clock from pad c lk_ext i s used test mode select For testing purpose only, has to be set to “0”. USB mini receptacle identifier Has to be connected to USB jack ID pin. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 173 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Ball Nr. BGA224 B4 G4 A4 H4 D5 J4 C5 F5 Ball Name Port A xpa[0] xpa[1] xpa[2] xpa[3] xpa[4] xpa[5] xpa[6] xpa[7] x pb[0] L 10 m pmc_stcs1mw[0 D IO ST PD LSR ]* dbop_c0 x pb[1] L 11 m pmc_stcs1pol* dbop_c1 x pb[2] D IO ST PD LSR O IO I K 11 m pmc_stcs1pb* D IO ST PD LSR O IO I D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR IO IO IO IO IO IO IO IO IO I GPIO IO, Port A GPIO IO, Port A GPIO IO, Port A GPIO IO, Port A GPIO IO, Port A GPIO IO, Port A GPIO IO, Port A GPIO IO, Port A GPIO IO, Port B static memory chip memory width setting for boot loader 0: 8 bit data bus 1: 16 bit data bus The value is latched at reset. DISPLAY control output GPIO IO, Port B static memory chip select polarity setting for boot loader 0: active LOW chip select 1: active high chip select The value is latched at reset. DISPLAY control output GPIO IO, Port B static memory byte lane polarity setting for boot loader 0: HIGH for reads, LOW for writes, used for we_n access 1: LOW for reads, LOW for writes, used for upper and lower byte access The value is latched at reset. DISPLAY control output GPIO IO, Port B test mode configuration (for testing purpose only !!!) The value is latched at reset. DISPLAY control output GPIO IO, Port B DISPLAY data input/output (high byte) GPIO IO, Port B DISPLAY data input/output (high byte) GPIO IO, Port B UART receive line DISPLAY data input/output (high byte) GPIO IO, Port B UART transmit line DISPLAY data input/output (high byte) GPIO IO, Port C BOOT LOADER source select input 1: internal ROM 0: external ROM/Flash DISPLAY data input/output (low byte) GPIO IO, Port C PAD Type I/O Ball Description Port B / DISPLAY / UART dbop_c2 x pb[3] K 10 m pmc_rel1config* D IO ST PD LSR dbop_c3 K9 K 12 x pb[4] dbop_d[8] x pb[5] dbop_d[9] x pb[6] L 12 u art_rxd dbop_d[10] x pb[7] K 13 u art_txd dbop_d[11] Port C / DISPLAY / 2-WIRE SERIAL x pc[0] E5 I ntBootSel* dbop_d[0] C4 xpc[1] D IO ST PD LSR D IO ST PD LSR D IO ST PU LSR D IO ST PU LSR D IO ST PD LSR D IO ST PD LSR O IO I O IO IO IO IO IO I IO IO O IO IO I IO IO © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 174 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Ball Nr. BGA224 Ball Name b oot_sel[0] d bop_d[1] x pc[2] F4 b oot_sel[1] dbop_d[2] x pc[3] A3 b oot_sel[2] dbop_d[3] D4 B3 x pc[4] dbop_d[4] x pc[5] dbop_d[5] x pc[6] C3 c md_ms_sck dbop_d[6] x pc[7] A2 c md_ms_sda dbop_d[7] Port D / SD Card / Memory Stick x pd[0] H 13 m ci_dat[0] ms_sdio[0] x pd[1] J 12 m ci_dat[1] ms_sdio[1] x pd[2] J 13 m ci_dat[2] ms_sdio[2] x pd[3] G 15 m ci_dat[3] ms_sdio[3] x pd[4] H 14 m ci_cmd ms_sclk x pd[5] J 14 m ci_clk ms_bs x pd[6] J 15 m ci_fbclk ms_fbclk H 15 x pd[7] mci_rod D IO ST LSR D IO ST LSR D IO ST LSR D IO ST LSR D IO ST LSR D IO ST LSR D IO ST LSR D IO ST LSR IO IO IO IO IO IO IO IO IO IO IO IO IO O O IO O O IO I I IO O O O GPIO IO, Port D MMC/SD data line MEMORY STICK data line GPIO IO, Port D MMC/SD data line MEMORY STICK data line GPIO IO, Port D MMC/SD data line MEMORY STICK data line GPIO IO, Port D MMC/SD data line MEMORY STICK data line GPIO IO, Port D MMC/SD command line MEMORY STICK clock line GPIO IO, Port D MMC/SD clock line MEMORY STICK bus state GPIO IO, Port D MMC/SD feedback clock MEMORY STICK feedback clock GPIO IO, Port D MMC/SD resistor open drain control 2-wire serial audio master clock line used for controlling the audio/PMU sub system 2-wire serial audio master data line used for controlling the audio/PMU sub system D IO ST PU LSR D IO ST PU LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR PAD Type I/O I IO IO I IO IO I IO IO IO IO IO IO IO IO IO IO IO Ball Description BOOT LOADER type select input DISPLAY data input/output (low byte) GPIO IO, Port C BOOT LOADER type select input DISPLAY data input/output (low byte) GPIO IO, Port C BOOT LOADER type select input DISPLAY data input/output (low byte) GPIO IO, Port C DISPLAY data input/output (low byte) GPIO IO, Port C DISPLAY data input/output (low byte) GPIO IO, Port C 2-WIRE SERIAL master/slave clock line DISPLAY data input/output (low byte) GPIO IO, Port C 2-WIRE SERIAL master/slave data line DISPLAY data input/output (low byte) 2-wire serial Audio Master M4 M3 CSCL CSDA D IO ST PU LSR D IO ST PU LSR Serial Synchronous Port © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 175 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Ball Nr. BGA224 C 11 H9 D 11 J 10 Ball Name s sp_fssout ssp_fssin s sp_clkout ssp_clkin ssp_rxd ssp_txd NandFlash / IDE C 13 A 13 B 14 D 13 B 13 C 12 G 11 B 12 C 14 E 12 F 11 D 15 F 12 E 13 D 14 E 14 F 14 n af_d[0] ide_hd[0] n af_d[1] ide_hd[1] n af_d[2] ide_hd[2] n af_d[3] ide_hd[3] n af_d[4] ide_hd[4] n af_d[5] ide_hd[5] n af_d[6] ide_hd[6] n af_d[7] ide_hd[7] n af_d[8] ide_hd[8] n af_d[9] ide_hd[9] n af_d[10] ide_hd[10] n af_d[11] ide_hd[11] n af_d[12] ide_hd[12] n af_d[13] ide_hd[13] n af_d[14] ide_hd[14] n af_d[15] ide_hd[15] n af_cle ide_dmarq n af_ale F 13 ide_iordy n af_wp_n G 12 ide_intrq D IO ST PD LSR D IO ST LSR D IO ST LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O I O I O I NAND FLASH data line (low byte) IDE data line (low byte) NAND FLASH data line (low byte) IDE data line (low byte) NAND FLASH data line (low byte) IDE data line (low byte) NAND FLASH data line (low byte) IDE data line (low byte) NAND FLASH data line (low byte) IDE data line (low byte) NAND FLASH data line (low byte) IDE data line (low byte) NAND FLASH data line (low byte) IDE data line (low byte) NAND FLASH data line (low byte) IDE data line (low byte) NAND FLASH data line (high byte) IDE data line (high byte) NAND FLASH data line (high byte) IDE data line (high byte) NAND FLASH data line (high byte) IDE data line (high byte) NAND FLASH data line (high byte) IDE data line (high byte) NAND FLASH data line (high byte) IDE data line (high byte) NAND FLASH data line (high byte) IDE data line (high byte) NAND FLASH data line (high byte) IDE data line (high byte) NAND FLASH data line (high byte) IDE data line (high byte) NAND FLASH command latch enable IDE DMA request used for DMA data transfers between host and device NAND FLASH address latch enable IDE IO ready signal used by device to extend host data transfer cycles NAND FLASH write protect not IDE interrupt request used by device to interrupt the host controller PAD Type I/O O I O I I O Ball Description S SP master, frame or slave select SSP slave, frame select S SP master, clock line SSP slave, clock line SSP receive data input SSP transmit data output D IO ST PU LSR D IO ST PU LSR D IO ST PU LSR D IO ST PU LSR © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 176 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Ball Nr. BGA224 E 15 Ball Name n af_ce0_n ide_cs0_n D IO ST LSR PAD Type I/O O O Ball Description NAND FLASH chip enable IDE chip select 0 used by the host to select command block registers in the device NAND FLASH chip enable IDE chip select 1 used by the host to select control block registers in the device NAND FLASH chip enable IDE host IO write strobe NAND FLASH chip enable IDE host IO read strobe NAND FLASH write enable not IDE DMA acknowledge used by the host to initiate DMA data transfers NAND FLASH read enable not IDE primary channel cable ID detect NAND FLASH ready / busy not IDE secondary channel cable ID select IDE host address IDE host address IDE host address IDE reset not, used by the host to reset the device IS2 data output data output from digital core to audio sub system, S DI a nd i 2so_sdata a re connected on the BGA I2S serial clock clock output from digital core to audio sub system, S CLK a nd i soi_sclk a re connected on the BGA I2S left/right clock clock output from digital core to audio sub system, L RCK a nd i 2so_lrck a re connected on the BGA I2S master clock clock output from digital core to audio sub system, M CLK a nd i 2so_mclk a re connected on the BGA I2S data input data output from audio sub system to digital core, S DO a nd i 2si_sdata a re connected on the BGA I 2S master serial clock serial clock output for external ADC if AS3525 is I2S master I2S slave serial clock serial clock input for external ADC if AS3525 is I2S slave I 2S master, left/right clock left/right clock output for external ADC if AS3525 is I2S master I2S slave, left/right clock left/right clock input for external ADC if AS3525 is I2S master I2S master, master clock I2S data input data input from external audio ADC n af_ce1_n H 11 ide_cs1_n D IO ST LSR O O J 11 G 13 G 14 H 12 F 15 A 12 H 10 D 12 G 10 n af_ce2_n ide_hiown n af_ce3_n ide_hiorn n af_we_n ide_dackn n af_re_n ide_npcblid n af_bsy_n ide_nscblid ide_ha[0] ide_ha[1] ide_ha[2] ide_reset_n I2S Output D IO ST LSR D IO ST LSR D IO ST LSR D IO ST LSR D IO ST LSR D OUT LSR D OUT LSR D OUT LSR D OUT LSR O O O O O O O I I I O O O O M6 i2so_sdata S DI i2so_sclk S CLK i2so_lrck L RCK i2so_mclk M CLK I2S Input D O UT LSR DI D O UT LSR DI D O UT LSR DI D O UT LSR DI O I O I O I O I N6 N5 M5 M7 i2si_sdata S DO i 2si_sclk_out D I N ST DO I O O E3 i2si_sclk_in i 2si_lrck_out D1 i2si_lrck_in E4 C1 i2si_mclk i 2si_sdata_in D IO ST LSR I O D IO ST LSR I D OUT LSR D I N ST PD O I © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 177 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Ball Nr. BGA224 Ball Name s pdif_data_in Audio Subsystem IRQ N1 I NTRQ i ntrq jtag_trst_n jtag_tms jtag_tck jtag_tdi jtag_tdo mpmc_addr[0] mpmc_addr[1] mpmc_addr[2] mpmc_addr[3] mpmc_addr[4] mpmc_addr[5] mpmc_addr[6] mpmc_addr[7] mpmc_addr[8] mpmc_addr[9] mpmc_addr[10] mpmc_addr[11] mpmc_addr[12] mpmc_addr[13] mpmc_addr[14] mpmc_addr[15] mpmc_addr[16] mpmc_addr[17] mpmc_addr[18] mpmc_addr[19] mpmc_addr[20] mpmc_cke[0] mpmc_cke[1] mpmc_clk[0] mpmc_clk[1] mpmc_fbclkin mpmc_dqm[0] mpmc_dqm[1] mpmc_cas_n DO D I N ST D IN ST PD D IN ST PU D IN ST PU D IN ST PU D IO ST PU LSR D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D IO ST PD LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV O I I I I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O u sed by the audio/PMU subsystem to interrupt the digital core, I NTRQ a nd i ntrq a re connected on the BGA JTAG reset not JTAG mode select JTAG clock JTAG data input JTAG data output EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY clock enable0 used for SDRAM devices only EXT. MEMORY clock enable 1 used for SDRAM devices only EXT. MEMORY clock 0 used for SDRAM devices only EXT. MEMORY clock 1 used for SDRAM devices only EXT. MEMORY feedback clock used for SDRAM devices only EXT. MEMORY data mask 0 used for SDRAM devices and static memories EXT. MEMORY data mask 1 used for SDRAM devices and static memories EXT. MEMORY column address strobe not used for SDRAM devices only EXT. MEMORY dynamic memory chip select 0 not PAD Type I/O I Ball Description SPDIF data input data input for SPDIF to I2S conversion JTAG Debugging IF C2 A1 B2 B1 D3 G5 B5 L4 A5 K5 D6 F6 C6 E6 A6 H5 B6 J5 D7 E7 C7 F7 A7 G6 B7 H6 F8 J6 E8 G7 L5 D8 L6 A8 K6 External Memory IF mpmc_dycs_n[0] D OUT LSR LV © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 178 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Ball Nr. BGA224 Ball Name PAD Type I/O Ball Description u sed for SDRAM devices only E9 J7 F9 D9 L7 A9 K7 D 10 L8 E 10 L9 F 10 K8 A 10 J8 B 10 H7 C 10 G8 E 11 G9 A 11 J9 B 11 G3 H3 A 14 C 15 F2 J1 H2 G2 G1 H1 K4 K2 J2 mpmc_dycs_n[1] D OUT LSR LV mpmc_ras_n mpmc_we_n mpmc_stcs_n[0] mpmc_stcs_n[1] mpmc_bls_n[0] mpmc_bls_n[1] mpmc_oe_n mpmc_data[0] mpmc_data[1] mpmc_data[2] mpmc_data[3] mpmc_data[4] mpmc_data[5] mpmc_data[6] mpmc_data[7] mpmc_data[8] mpmc_data[9] mpmc_data[10] mpmc_data[11] mpmc_data[12] mpmc_data[13] mpmc_data[14] mpmc_data[15] DBOP dbop_d[12] d bop_d[13] d bop_d[14] d bop_d[15] USB 2.0 OTG vdda33t vssa33t vssa33t vssa33t usb_dp usb_dm NC NC usb_rext PWP_VD_RDO_3V PWP_VS_RDO_3V PWP_VS_RDO_3V PWP_VS_RDO_3V USB_ESD_5VT USB_ESD_5VT ANA_BI_RXT_3V A P P P P A A USB 3.3V analog power supply for OTG transceiver block USB 3.3V analog ground supply for OTG transceiver block USB 3.3V analog ground supply for OTG transceiver block USB 3.3V analog ground supply for OTG transceiver block USB D+ signal from USB cable USB D- signal from USB cable test pin: m ust stay unconnected for normal operation mode test pin: m ust stay unconnected for normal operation mode USB external resistor connect analog signal to the external resistor for setting the bias 179 - 194 O O O O O O O O IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR D I O ST PD LSR D I O ST PD LSR D I O ST PD LSR EXT. MEMORY dynamic memory chip select 1 not used for SDRAM devices only EXT. MEMORY row address strobe not used for SDRAM devices only EXT. MEMORY write enable not used for SDRAM devices and static memories EXT. MEMORY static memory chip select 0 not used for static memory devices only EXT. MEMORY static memory chip select 0 not used for static memory devices only EXT. MEMORY byte lane select 0 not used for static memory devices only EXT. MEMORY byte lane select 1 not used for static memory devices only EXT. MEMORY output enable not used for static memory devices only EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line DISPLAY data input/output (high byte) D ISPLAY data input/output (high byte) D ISPLAY data input/output (high byte) D ISPLAY data input/output (high byte) © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 AS3525-A/-B C22O22 Data Sheet, Confidential Ball Nr. BGA224 J3 L2 F3 Ball Name PAD Type I/O Ball Description c urrent of the USB 2.0 OTG PHY, voltage level is 1.1-1.3V vdda33c NC V BUS u sb_vbus Supply Balls A 15 B9 C9 B 15 B8 C8 K1 L1 vdd_peri vdd_mem vdd_mem vss_peri vss_mem vss_mem vdd_core vss_core AFE Balls K3 L3 N2 P1 R1 R2 P2 R3 P3 R4 N3 P4 R5 R6 P5 P6 N4 N7 N8 P8 M8 R7 N9 M9 N 10 N 12 N 13 N 11 P9 DVDD PwrUP P_PVDD DVSS XIN_24M XOUT_24M LIN2R LIN2L LIN1R LIN1L MSUP2 MIC2_N MIC2_P MIC1_P MIC1_N MSUP1 LOUTR LOUTL AVDD AGND VREF AVSS HPGND HPCM HPR BVSS2 HPL BGND BVDD P DI PD AI P AIO AIO AI AI AI AI P AI AI AI AI P AO AO P AIO AIO P AIO AO AO P AO P P P I I P IO IO I I I I P I I I I P O O P IO IO P IO O O P O P P audio/PMU subsystem digital power supply to be connected to QLDO2 (2.9V) power Up input 5 State program input of PVDD regulator audio/PMU subsystem digital ground supply oscillator input 12-24MHz oscillator output 12-24MHz line input 2 right channel line input 2 left channel line input 1 right channel line input 1 left channel microphone supply 2 (2.95V) / remote input 2 microphone input 2N microphone input 2P microphone input 1P microphone input 1N microphone supply 1 (2.95V) / remote input 1 line output right channel / ear piece differential output N line output left channel / ear piece differential output P audio/PMU subsystem analog power supply analog reference (AVDD/2) decoupling cap terminal (10uF) analog reference ( filtered AVDD) decoupling cap terminal (10uF) audio/PMU subsystem digital power supply headphone amplifier reference decoupling cap terminal (100nF) headphone common GND output for DC-coupled speakers headphone output right channel headphone amplifier ground supply headphone output left channel speaker amplifier reference decoupling cap terminal (100nF) audio/PMU subsystem power supply (max. 5.5V) P P P P P P P P P P P P P P P P 3.3V peripheral power supply 3.3V (2.5V) external memory power supply 3.3V (2.5V) external memory power supply 3.3V peripheral ground supply 3.3V (2.5V) external memory ground supply 3.3V (2.5V) external memory ground supply 1.2V core power supply 1.2V core ground supply PWP_VD_ANA_3V P USB 3.3V analog power supply for common block test pin: m ust stay unconnected for normal operation mode USB20_VBUS_5VT_ AO U SB 5V supply generated by the PMU subsystem , OTG V BUS a nd u sb_vbus a re connected on the BGA AIO USB mini receptacle Vbus © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 180 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Ball Nr. BGA224 R9 P7 R8 R 10 P 10 R 11 R 12 P 11 P 12 R 15 Ball Name LSPR BVSS BVSS LSPL BVDD UVDD PVDD BVDD IOVDD CVDD AO P P AO P AO AO AO AO AO PAD Type I/O O P P O P O O O O O Ball Description speaker output right channel speaker amplifier ground supply speaker amplifier ground supply speaker output left channel audio/PMU subsystem power supply (max. 5.5V) LDO6 Regulator Output fixed to 3.262V to be used for USB transceiver supply LDO3 Regulator Output programmed to 1.7 - 3.33V audio/PMU subsystem power supply (max. 5.5V) LDO4 Regulator Output fixed to 3.109V charge pump output for digital core supply, programmed to 1.05 - 1.2V to be connected to vdd_core battery supply input for single cell application CVDD charge pump flying cap CVDD charge pump flying cap CVDD charge pump ground supply LDO2 regulator output fixed 2.9V to be connected to DVDD VBUS charge pump flying cap VBUS charge pump flying cap DCDC3V ground supply DCDC3V switch terminal DCDC15V switch terminal DCDC15V ground supply DCDC15V load current sink terminal charger input charger output programmable current (50-400mA) and voltage ( 3.9-4.25V) charger battery temperature sensor input (RNTC 100k) 32kHz RTC oscillator crystal terminal 32kHz RTC oscillator crystal terminal RTC supply regulator output supplied via BVDD, programmed to 1.0-2.5V M 13 P 15 N 15 M 15 M 14 L 14 L 13 L 15 K 15 K 14 M 12 M 11 N 14 P 14 M 10 R 14 R 13 P 13 VBAT_1V CP_1V CN_1V VSS_1V QLDO2 CP_5V CN_5V VSS_3V SW_3V SW_15V VSS_15V ISINK CHG_IN CHG_OUT BATTEMP XOUT_32k XIN_32k RVDD P AIO AIO P AO AIO AIO P AO AO P AO AI AO AIO AIO AIO AO P IO IO P O IO IO P O O P O I O IO IO IO O © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 181 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 8.3 CTBGA144 Package Drawings Figure 63 CTBGA144 Package Drawing AS3525B C22O22 AYWWZZZ Package Code AYYWWZZZ A A … for PB free Y Year WW working week assembly/packaging ZZZ Free choice 8.3.1 CTBGA144 Package Ball-out Figure 64 AS3525B Package Ball-out 1 A B C D E F G H J K L M dbop_d12 2 dbop_d13 3 i2si_sdata_in 4 xpc_2 5 xpa_6 6 xpa_7 7 vdd_peri 8 vss_peri 9 dbop_d14 10 naf_d_2 11 naf_d_1 12 naf_d_0 jtag_tdi jtag_tck jtag_tdo xpc_3 xpa_4 xpa_5 ssp_fssout ssp_clkout dbop_d15 naf_d_3 naf_d_9 naf_d_8 jtag_trst_n clk_ext jtag_tms xpc_4 xpa_2 xpa_3 ssp_rxd ssp_txd naf_d_4 naf_d_12 naf_d_11 naf_d_10 usb_dp clk_sel xpc_7 xpc_1 xpa_0 xpa_1 naf_d_7 naf_d_6 naf_d_5 naf_d_15 naf_d_14 naf_d_13 usb_dm tmsel xpc_6 xpc_0 naf_we_n naf_ce1_n naf_ce0_n naf_wp_n naf_ale naf_cle naf_re_n CHG_OUT usb_vssa33 usb_vdda33 xpc_5 xpd_4 xpd_3 xpd_2 xpd_1 xpd_0 naf_bsy_n xpd_5 ISINK SW_15V vss_core usb_rext id_dig xpb_2 xpb_1 xpb_0 xpd_7 xpd_6 CHG_IN CP_5V CN_5V SW_3V XIN_32k vdd_core VBUS xpb_7 xpb_6 xpb_5 xpb_4 xpb_3 QLDO2 VSS_3V CP_1V CN_1V XOUT_32k RVDD CSCL P_PVDD INTRQ PwrUP naf_ce2_n naf_ce3_n VSS_15V VSS_1V PVDD CVDD DVDD CSDA XRES MSUP1 MSUP2 BATTEMP HPGND BGND BVSS2 VBAT_1V BVDD BVDD XOUT_24M AVDD VREF MIC1_N MIC2_N LIN2L LIN1L LOUTL BVSS HPR HPL IOVDD XIN_24M AVSS AGND MIC1_P MIC2_P LIN2R LIN1R LOUTR HPCM LSPR LSPL UVDD © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 182 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 8.3.2 CTBGA144 Ball List Table 162 CTBGA144 Ball List Ball Nr. BGA144 K3 C2 D2 E2 G3 Ball Name X RES r esetext_n clk_ext clk_sel tmsel id_dig Port A D5 D6 C5 C6 B5 B6 A5 A6 xpa[0] xpa[1] xpa[2] xpa[3] xpa[4] xpa[5] xpa[6] xpa[7] x pb[0] G6 m pmc_stcs1mw[0 D IO ST PD LSR ]* dbop_c0 x pb[1] G5 m pmc_stcs1pol* dbop_c1 x pb[2] D IO ST PD LSR O IO I G4 m pmc_stcs1pb* D IO ST PD LSR O IO I D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR IO IO IO IO IO IO IO IO IO I GPIO IO, Port A GPIO IO, Port A GPIO IO, Port A GPIO IO, Port A GPIO IO, Port A GPIO IO, Port A GPIO IO, Port A GPIO IO, Port A GPIO IO, Port B static memory chip memory width setting for boot loader 0: 8 bit data bus 1: 16 bit data bus The value is latched at reset. DISPLAY control output GPIO IO, Port B static memory chip select polarity setting for boot loader 0: active LOW chip select 1: active high chip select The value is latched at reset. DISPLAY control output GPIO IO, Port B static memory byte lane polarity setting for boot loader 0: HIGH for reads, LOW for writes, used for we_n access 1: LOW for reads, LOW for writes, used for upper and lower byte access The value is latched at reset. DISPLAY control output GPIO IO, Port B test mode configuration (for testing purpose only !!!) The value is latched at reset. DISPLAY control output GPIO IO, Port B DISPLAY data input/output (high byte) GPIO IO, Port B DISPLAY data input/output (high byte) GPIO IO, Port B PAD Type DO D I N ST D IN ST PD D IN ST PD D IN ST PD D IN ST (PU) I I I/O O I I I Ball Description X RES i s generated by the PMU subsystem a nd connected to reset input (active low) on the BGA external clock input (10-26MHz) clock select 0 (low): clock from internal oscillator is used 1 (high): clock from pad c lk_ext i s used test mode select For testing purpose only, has to be set to “0”. USB mini receptacle identifier Has to be connected to USB jack ID pin. Port B / DISPLAY / UART dbop_c2 x pb[3] H8 m pmc_rel1config* D IO ST PD LSR dbop_c3 H7 H6 H5 x pb[4] dbop_d[8] x pb[5] dbop_d[9] xpb[6] D IO ST PD LSR D IO ST PD LSR D IO ST PU LSR O IO I O IO IO IO IO IO © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 183 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Ball Nr. BGA144 Ball Name u art_rxd d bop_d[10] x pb[7] H4 u art_txd dbop_d[11] x pc[0] E4 I ntBootSel* dbop_d[0] x pc[1] D4 b oot_sel[0] dbop_d[1] x pc[2] A4 b oot_sel[1] dbop_d[2] x pc[3] B4 b oot_sel[2] dbop_d[3] C4 F3 x pc[4] dbop_d[4] x pc[5] dbop_d[5] x pc[6] E3 c md_ms_sck dbop_d[6] x pc[7] D3 c md_ms_sda dbop_d[7] Port D / SD Card / Memory Stick x pd[0] F8 m ci_dat[0] ms_sdio[0] x pd[1] F7 m ci_dat[1] ms_sdio[1] x pd[2] F6 m ci_dat[2] ms_sdio[2] x pd[3] F5 m ci_dat[3] ms_sdio[3] x pd[4] F4 F 10 m ci_cmd ms_sclk x pd[5] mci_clk D IO ST LSR D IO ST LSR D IO ST LSR D IO ST LSR D IO ST LSR D IO ST LSR IO IO IO IO IO IO IO IO IO IO IO IO IO O O IO O GPIO IO, Port D MMC/SD data line MEMORY STICK data line GPIO IO, Port D MMC/SD data line MEMORY STICK data line GPIO IO, Port D MMC/SD data line MEMORY STICK data line GPIO IO, Port D MMC/SD data line MEMORY STICK data line GPIO IO, Port D MMC/SD command line MEMORY STICK clock line GPIO IO, Port D MMC/SD clock line 184 - 194 PAD Type I I/O UART receive line Ball Description IO IO D IO ST PU LSR O IO IO I D IO ST PD LSR IO IO D IO ST PD LSR I IO IO D IO ST PD LSR I IO IO D IO ST PD LSR I IO D IO ST PD LSR D IO ST PD LSR IO IO IO IO IO D IO ST PU LSR IO IO IO D IO ST PU LSR IO IO DISPLAY data input/output (high byte) GPIO IO, Port B UART transmit line DISPLAY data input/output (high byte) GPIO IO, Port C BOOT LOADER source select input 1: internal ROM 0: external ROM/Flash DISPLAY data input/output (low byte) GPIO IO, Port C BOOT LOADER type select input DISPLAY data input/output (low byte) GPIO IO, Port C BOOT LOADER type select input DISPLAY data input/output (low byte) GPIO IO, Port C BOOT LOADER type select input DISPLAY data input/output (low byte) GPIO IO, Port C DISPLAY data input/output (low byte) GPIO IO, Port C DISPLAY data input/output (low byte) GPIO IO, Port C 2-WIRE SERIAL master/slave clock line DISPLAY data input/output (low byte) GPIO IO, Port C 2-WIRE SERIAL master/slave data line DISPLAY data input/output (low byte) Port C / DISPLAY / 2-WIRE SERIAL © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 AS3525-A/-B C22O22 Data Sheet, Confidential Ball Nr. BGA144 Ball Name m s_bs x pd[6] G8 m ci_fbclk ms_fbclk G7 x pd[7] mci_rod D IO ST LSR D IO ST LSR PAD Type I/O O IO I I IO O O O Ball Description MEMORY STICK bus state GPIO IO, Port D MMC/SD feedback clock MEMORY STICK feedback clock GPIO IO, Port D MMC/SD resistor open drain control 2-WIRE SERIAL audio master clock line used for controlling the audio/PMU sub system 2-WIRE SERIAL audio master data line used for controlling the audio/PMU sub system S SP master, frame or slave select SSP slave, frame select S SP master, clock line SSP slave, clock line SSP receive data input SSP transmit data output NAND FLASH data line (low byte) NAND FLASH data line (low byte) NAND FLASH data line (low byte) NAND FLASH data line (low byte) NAND FLASH data line (low byte) NAND FLASH data line (low byte) NAND FLASH data line (low byte) NAND FLASH data line (low byte) NAND FLASH data line (high byte) NAND FLASH data line (high byte) NAND FLASH data line (high byte) NAND FLASH data line (high byte) NAND FLASH data line (high byte) NAND FLASH data line (high byte) 2-WIRE SERIAL Audio Master J3 K2 CSCL CSDA D IO ST PU LSR D IO ST PU LSR Serial Synchronous Port B7 B8 C7 C8 s sp_fssout ssp_fssin s sp_clkout ssp_clkin ssp_rxd ssp_txd NandFlash / IDE A 12 A 11 A 10 B 10 C9 D9 D8 D7 B 12 B 11 C 12 C 11 C 10 D 12 n af_d[0] naf_d[1] naf_d[2] naf_d[3] naf_d[4] naf_d[5] naf_d[6] naf_d[7] naf_d[8] naf_d[9] naf_d[10] naf_d[11] naf_d[12] naf_d[13] D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR IO IO IO IO IO IO IO IO IO IO IO IO IO IO D IO ST PU LSR D IO ST PU LSR D IO ST PU LSR D IO ST PU LSR O I O I I O © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 185 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Ball Nr. BGA144 D 11 D 10 E 10 E9 E8 E7 E6 Ball Name n af_d[14] n af_d[15] n af_cle n af_ale n af_wp_n n af_ce0_n naf_ce1_n n af_ce2_n n af_ce3_n n af_we_n n af_re_n n af_bsy_n I2S Input i 2si_sdata_in A3 spdif_data_in Audio Subsystem IRQ J5 I NTRQ i ntrq jtag_trst_n jtag_tms jtag_tck jtag_tdi jtag_tdo DBOP A1 A2 A9 B9 F2 F1 dbop_d[12] d bop_d[13] d bop_d[14] d bop_d[15] USB 2.0 OTG vdda33 vssa33 PWP_VD_ ANA_3V PWP_VS_ ANA_3V P P USB 3.3V analog power supply for common block USB 3.3V analog ground supply for common block D IO ST PD LSR D I O ST PD LSR D I O ST PD LSR D I O ST PD LSR IO IO IO IO DISPLAY data input/output (high byte) D ISPLAY data input/output (high byte) D ISPLAY data input/output (high byte) D ISPLAY data input/output (high byte) DO D I N ST D IN ST PD D IN ST PU D IN ST PU D IN ST PU D IO ST PU LSR O I I I I I O u sed by the audio/PMU subsystem to interrupt the digital core, I NTRQ a nd i ntrq a re connected on the BGA JTAG reset not JTAG mode select JTAG clock JTAG data input JTAG data output D IN ST PD I I I 2S data input data input from external audio ADC SPDIF data input data input for SPDIF to I2S conversion PAD Type I/O IO IO O O O O O O O O O I Ball Description NAND FLASH data line (high byte) NAND FLASH data line (high byte) NAND FLASH command latch enable NAND FLASH address latch enable NAND FLASH write protect not NAND FLASH chip enable NAND FLASH chip enable NAND FLASH chip enable NAND FLASH chip enable NAND FLASH write enable not NAND FLASH read enable not NAND FLASH ready / busy not D IO ST PD LSR D IO ST PD LSR D IO ST LSR D IO ST LSR D IO ST PD LSR D IO ST LSR D IO ST LSR J7 J8 E5 E 11 F9 D IO ST LSR D IO ST LSR D IO ST LSR D IO ST LSR D IO ST LSR JTAG Debugging IF C1 C3 B2 B1 B3 © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 186 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Ball Nr. BGA144 D1 E1 G2 Ball Name usb_dp usb_dm usb_rext PAD Type USB_ESD_5VT USB_ESD_5VT I/O A A Ball Description USB D+ signal from USB cable USB D- signal from USB cable H3 V BUS u sb_vbus Supply Balls U SB external resistor connect analog signal to the external resistor for setting the bias current of the USB 2.0 OTG PHY, voltage level is 1.1-1.3V USB20_VBUS_5V AO U SB 5V supply generated by the PMU subsystem , T_OTG V BUS a nd u sb_vbus a re connected on the BGA AIO USB mini receptacle Vbus P P P P P P P P 3.3V peripheral power supply 3.3V peripheral ground supply 1.2V core power supply N ote: This PIN has to be connected to CVDD! 1.2V core ground supply audio/PMU subsystem digital power supply to be connected to QLDO2 (2.9V) power Up input 5 State program input of PVDD regulator oscillator input 12-24MHz oscillator output 12-24MHz line input 2 right channel line input 2 left channel line input 1 right channel line input 1 left channel microphone supply 2 (2.95V) / remote input 2 microphone input 2N microphone input 2P microphone input 1P microphone input 1N microphone supply 1 (2.95V) / remote input 1 line output right channel / ear piece differential output N line output left channel / ear piece differential output P audio/PMU subsystem analog power supply analog reference (AVDD/2) decoupling cap terminal (10uF) analog reference ( filtered AVDD) decoupling cap terminal (10uF) audio/PMU subsystem digital power supply headphone amplifier reference decoupling cap terminal (100nF) headphone common GND output for DC-coupled speakers headphone output right channel headphone amplifier ground supply headphone output left channel speaker amplifier reference decoupling cap terminal (100nF) audio/PMU subsystem power supply (max. 5.5V) speaker output right channel speaker amplifier ground supply speaker output left channel audio/PMU subsystem power supply (max. 5.5V) ANA_BI_RXT_3V A A7 A8 H2 G1 vdd_peri vss_peri vdd_core vss_core AFE Balls K1 J6 J4 M1 L1 M6 L6 M7 L7 K5 L5 M5 M4 L4 K4 M8 L8 L2 M3 L3 M2 K7 M9 L 10 K9 L 11 K8 K 11 M 10 L9 M 11 K 12 DVDD PwrUP P_PVDD XIN_24M XOUT_24M LIN2R LIN2L LIN1R LIN1L MSUP2 MIC2_N MIC2_P MIC1_P MIC1_N MSUP1 LOUTR LOUTL AVDD AGND VREF AVSS HPGND HPCM HPR BVSS2 HPL BGND BVDD LSPR BVSS LSPL BVDD P DI PD AI AIO AIO AI AI AI AI P AI AI AI AI P AO AO P AIO AIO P AIO AO AO P AO P P AO P AO P P I I IO IO I I I I P I I I I P O O P IO IO P IO O O P O P P O P O P © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 187 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential Ball Nr. BGA144 M 12 J 11 L 12 J 12 Ball Name UVDD PVDD IOVDD CVDD AO AO AO AO PAD Type I/O O O O O Ball Description LDO6 Regulator Output fixed to 3.262V to be used for USB transceiver supply LDO3 Regulator Output programmed to 1.7 - 3.33V LDO4 Regulator Output fixed to 3.109V charge pump output for digital core supply, programmed to 1.05 - 1.2V N ote: This PIN has to be connected to vdd_core! battery supply input for single cell application CVDD charge pump flying cap CVDD charge pump flying cap CVDD charge pump ground supply LDO2 regulator output fixed 2.9V to be connected to DVDD VBUS charge pump flying cap VBUS charge pump flying cap DCDC3V ground supply DCDC3V switch terminal DCDC15V switch terminal DCDC15V ground supply DCDC15V load current sink terminal charger input charger output programmable current (50-400mA) and voltage ( 3.9-4.25V) charger battery temperature sensor input (RNTC 100k) 32kHz RTC oscillator crystal terminal 32kHz RTC oscillator crystal terminal RTC supply regulator output supplied via BVDD, programmed to 1.0-2.5V K 10 H 11 H 12 J 10 H9 G 10 G 11 H 10 G 12 F 12 J9 F 11 G9 E 12 K6 J1 H1 J2 VBAT_1V CP_1V CN_1V VSS_1V QLDO2 CP_5V CN_5V VSS_3V SW_3V SW_15V VSS_15V ISINK CHG_IN CHG_OUT BATTEMP XOUT_32k XIN_32k RVDD P AIO AIO P AO AIO AIO P AO AO P AO AI AO AIO AIO AIO AO P IO IO P O IO IO P O O P O I O IO IO IO O © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 188 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 8.4 Pad Cell Description 8.4.1 Digital Pads 8.4.1.1 D IN ST 8.4.1.2 D IN PD ST Figure 65 Digital Input with Schmitt Trigger Figure 66 Digital Input with Schmitt Trigger and Pull-Down Schmitt Schmitt PAD C PAD C 8.4.1.3 D IN PU ST 8.4.1.4 D IN (PU) Figure 67 Digital Input with Schmitt Trigger and Pull-Up Figure 68 Digital Input with enable controlled Pull-Up Schmitt PAD C REN PAD C 8.4.1.5 D OUT LSR 8.4.1.6 D IO ST LSR Figure 69 Digital Output with Limited Slew Rate Figure 70 Digital Schmitt Trigger Input and Limited Slew Rate Output I PAD Schmitt C I PAD © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 189 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 8.4.1.7 D IO ST PU LSR 8.4.1.8 D IO ST PD LSR Figure 71 Digital Schmitt Trigger Input with Pull-Up and Limited Slew Rate Output Figure 72 Digital Schmitt Trigger Input with Pull-Down and Limited Slew Rate Output Schmitt Schmitt C C I PAD I PAD 8.4.1.9 D OUT LSR LV 8.4.1.10 D IO ST PD LSR LV Figure 74 Digital Schmitt Trigger Input with Pull-Down and Limited Slew Rate Output (low voltage) Figure 73 Digital Output with Limited Slew Rate (low voltage) I PAD Schmitt C I PAD 9 9.1 Appendix Memory MAP ARM922T provides 32-bit address to access the peripherals and memory. With this 32-bit address ARM922T can access up to 4 Giga Bytes of memory. Cocoa does not use the complete 4 GB address space. Address 0x0000_0000 is mapped to internal ROM or External Memory interface based on the boot ROM selection by the external input pin (Port C, xpc[0] = intBootSel) Pin intBootSel=1 at startup selects the internal ROM, intBootSel = 0 selects the external memory. The address range starting at 0x0000_0000 is also mapped to internal RAM upon setting of the remap bit. This remap allows the user to select either RAM or ROM at 0x0000_0000. Table 163 Address Map S.No . Start (Base) Address 0 x0000_0000 0 x0000_0000 End Address Actual Block Size 128 KByte 4 MB Peripheral AHB Blocks 0x0001_FFFF 0x003F_FFFF Internal ROM External Memory IF (MPMC Bank1 – Ext Flash or Ext ROM) Embedded 1T-RAM Reserved External Memory IF (MPMC Bank1 – Ext Flash or Ext ROM) Remap = 0 and IntBootSel = 1 Remap = 0 and IntBootSel = 0 Remap = 1 Aliased Comment 0 x0000_0000 0 x0100_0000 0 x1000_0000 0x0004_FFFF 0x0FFF_FFFF 0x103F_FFFF 320 KByte 4 MB © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 190 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential S.No . Start (Base) Address 0 x1100_0000 0 x2000_0000 End Address 0x1FFF_FFFF 0x203F_FFFF Actual Block Size 4 MB Peripheral Reserved External Memory IF (MPMC Bank2 – External LCD Controller) Reserved External Memory IF (MPMC Bank 4 – SDRAM) External Memory If (MPMC Bank5 – SDRAM) Reserved Internal ROM Reserved Embedded 1T-RAM Reserved Internal ROM Reserved Embedded 1T-RAM Reserved USB2.0 Slave VIC DMAC Slave ExtMemIFSlave MemoryStick Slave CompactFlash/IDE Slave ARM922T Slave R eserved APB blocks 0 xC800_0000 0 xC801_0000 0 xC802_0000 0 xC803_0000 0 xC804_0000 0 xC805_0000 0 xC806_0000 0 xC807_0000 0 xC808_0000 0 xC809_0000 0 xC80A_0000 0 xC80B_0000 0 xC80C_0000 0 xC80D_0000 0 xC80E_0000 0 xC80F_0000 0 xC810_0000 0 xC811_0000 0 xC812_0000 0 xC813_0000 0xC800_FFFF 0xC801_FFFF 0xC802_FFFF 0xC803_FFFF 0xC804_FFFF 0xC805_FFFF 0xC806_FFFF 0xC807_FFFF 0xC808_FFFF 0xC809_FFFF 0xC80A_FFFF 0xC80B_FFFF 0xC80C_FFFF 0xC80D_FFFF 0xC80E_FFFF 0xC80F_FFFF 0xC810_FFFF 0xC811_FFFF 0xC812_FFFF 0xC813_FFFF Few Few Few Few Few Few Few Few Few Few Few Few Few Few Few Few Few Few Nand Flash / Smart Media Interface BistManager SD-MCI Reserved Timer Watchdog Timer I2C Master/Slave I2C Audio Master SSP I2S IN Interface I2S OUT Interface GPIO A GPIO B GPIO C GPIO D Clock Generation Unit Chip Control Unit Debug UART DBOP reserved Comment 0 x2100_0000 0 x3000_0000 0x2FFF_FFFF 0x3FFF_FFFF 256 MB 0 x4000_0000 0x4FFF_FFFF 256 MB 0 x5000_0000 0 x8000_0000 0 x8002_0000 0 x8100_0000 0 x8105_0000 0 xC000_0000 0 xC002_0000 0 xC100_0000 0 xC105_0000 0 xC600_0000 0 xC601_0000 0 xC602_0000 0 xC603_0000 0 xC604_0000 0 xC605_0000 0 xC606_0000 0 xC607_0000 0x7FFF_FFFF 0x8001_FFFF 0x80FF_FFFF 0x8104_FFFF 0xBFFF_FFFF 0xC001_FFFF 0xC0FF_FFFF 0xC104_FFFF 0xC5FF_FFFF 0xC600_FFFF 0xC601_FFFF 0xC602_FFFF 0xC603_FFFF 0xC604_FFFF 0xC605_FFFF 0xC606_FFFF 0 xC7FF_FFFF 128 KByte 320 KByte 128 KByte 320 KByte Few Few Few Few Few Few 4 KByte Aliased Aliased Aliased Aliased 9.2 Register definitions This section gives a short overview of all module registers. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 191 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 9.2.1 Base Address definitions Each module register block starts at a specific base address. Table 164 Base Addresses REGISTER Name A S3525_RAM_BASE A S3525_USB_BASE A S3525_VIC_BASE A S3525_DMAC_BASE A S3525_EXTMEM_ITF_BASE A S3525_MEMSTICK_BASE A S3525_CF_IDE_BASE A S3525_NAND_FLASH_BASE A S3525_BIST_MANAGER_BASE A S3525_SD_MCI_BASE A S3525_TIMER_BASE A S3525_WDT_BASE A S3525_I2C_MS_BASE A S3525_I2C_AUDIO_BASE A S3525_SSP_BASE A S3525_I2SIN_BASE A S3525_I2SOUT_BASE A S3525_GPIO1_BASE A S3525_GPIO2_BASE A S3525_GPIO3_BASE A S3525_GPIO4_BASE A S3525_CGU_BASE A S3525_CCU_BASE A S3525_UART_BASE A S3525_DBOP_BASE Register Address 0x00000000 0xC6000000 0xC6010000 0xC6020000 0xC6030000 0xC6040000 0xC6050000 0xC8000000 0xC8010000 0xC8020000 0xC8040000 0xC8050000 0xC8060000 0xC8070000 0xC8080000 0xC8090000 0xC80A0000 0xC80B0000 0xC80C0000 0xC80D0000 0xC80E0000 0xC80F0000 0xC8100000 0xC8110000 0xC8120000 © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 192 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 10 Ordering Information Table 165 ordering information Number A S3525A C21O20 TRA A S3525A C21O20T&R A S3525B C21O20TRA A S3525B C21O20T&R A S3525A C22O22 TRA A S3525A C22O22T&R A S3525B C22O22TRA A S3525B C22O22T&R Package Type CTBGA CTBGA CTBGA CTBGA CTBGA CTBGA CTBGA CTBGA 224 224 144 144 224 224 144 144 Delivery Form Tray Tape and Reel Tray Tape and Reel Tray Tape and Reel Tray Tape and Reel don’t don’t don’t don’t use use use use Description for for for for new new new new design design design design starts starts starts starts A S3525P V D Where V = Version P = Package Type: A: CTBGA 224, Thin ChipArray Ball Grid Array, 13x13mm package size, 0.8mm ball pitch B: CTBGA 144, Thin ChipArray Ball Grid Array, 10x10mm package size, 0.8mm ball pitch D = Delivery Form: TRA = Tray T&R = Tape and Reel All package variants are Pb-free/ RoHS package types. © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 193 - 194 AS3525-A/-B C22O22 Data Sheet, Confidential 11 Copyright Copyright © 2005-2007, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks of their respective companies. 12 Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent identification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. 13 Contact Information austriamicrosystems AG Business Unit Communications A 8141 Schloss Premstätten, Austria T. +43 (0) 3136 500 0 F. +43 (0) 3136 5692 info@austriamicrosystems.com For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 194 - 194