AS1506_1

Da t as heet AS1506 2 5 6 - Ta p D i g i ta l P o t e n t i o m e t e r w i t h S P I I n t e r f a c e a n d High Endurance EEPROM 1 General Description The AS1506 is a linear, 256-tap digital potentiometer specifically designed to replace discrete/mechanical potentiometers and is ideal for applications requiring a low-temperature-coefficient variable resistor, such as low-drift, programmable gain, and amplifier circuit configurations. The device is controlled via a 3-wire SPI-compatible interface and features an internal EEPROM for storing wiper positions. Several device variants are available differentiated by end-to-end resistance as shown in Table 1 (see also Ordering Information on page 16). Table 1. Standard Products Model AS1506-10 AS1506-50 AS1506-100 End-to-End Resistance (kΩ) 10 50 100 2 Key Features ! ! High Endurance: EEPROM up to 10M cycles High Reliability: EEPROM up to 150 years data retention @ 85°C Wiper Position Retained in EEPROM and loaded at Power-Up 256 Tap Positions ±0.5LSB DNL in Voltage Divider Mode ±0.5LSB INL in Voltage Divider Mode End-to-End Resistance: 10/50/100kΩ Low End-to-End Resistance Temperature Coefficient: 90ppm/ºC Low-Power Standby Mode: 100nA 5MHz SPI-Compatible Serial Interface Single-Supply Operation: +2.7V to +5.5V 8-pin TDFN 3x3mm Package ! ! ! ! ! ! ! ! ! ! The 3-wire SPI-compatible serial interface allows communication at data rates up to 5MHz.The internal EEPROM stores the last wiper position for initialization during power-up and a low-power standby mode. The devices are available in an 8-pin TDFN 3x3mm package. 3 Applications The device is ideal for mechanical potentiometer replacement, low-drift programmable gain amplifiers, audio volume control, LCD contrast control, and low-drift programmable filters. Figure 1. AS1506 - Block Diagram 1 VDD 8-Bit Shift Register 8 8-Bit Latch 8 256 8 HIGH 256-Position 256-Position Decoder 2 SCLK 3 SDIO 4 CSN SPI Interface PowerOn Reset 8-Bit 8-Bit EEPROM 7 WIPER 6 LOW AS1506 5 GND www.austriamicrosystems.com Revision 1.02 1 - 17 AS1506 Datasheet - P i n o u t 4 Pinout Pin Assignments Figure 2. Pin Assignments (Top View) VDD 1 8 HIGH SCLK 2 7 WIPER AS1506 SDIO 3 6 LOW CSN 4 5 GND Pin Descriptions Table 2. Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 N/A Description 2.7V to 5.5V Supply Voltage. Bypass with a 0.1µF capacitor to GND. Serial Clock Input Serial Data Input/Output Active-Low Chip Select Ground Low Terminal. The voltage at this pin can be greater than or less than the voltage at LOW pin HIGH. Current can flow into or out of this pin. Wiper Terminal WIPER High Terminal. The voltage at this pin can be greater than or less than the voltage HIGH at pin LOW. Current can flow into or out of this pin. Exposed Pad The exposed pad is not internally connected. Leave floating. Pin Name VDD SCLK SDIO CSN GND www.austriamicrosystems.com Revision 1.02 2 - 17 AS1506 Datasheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Absolute Maximum Ratings Parameter VDD to GND All Other Pins to GND AS1506-10 Maximum Continuous Current into Pins HIGH, WIPER, and LOW Electrostatic Discharge Latch-Up 1 Min -0.3 -0.3 Max +7.0 VDD + 0.3 Units V V Comments +0.55 +0.55 +0.55 1 -100 48 -40 -60 +85 +150 +150 100 kV mA ºC/W ºC ºC ºC The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020D “Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. The lead finish for Pb-free leaded packages is matte tin (100% Sn). HBM MIL-Std. 883E 3015.7 methods JEDEC 78 on PCB mA AS1506-50 AS1506-100 Thermal Resistance ΘJA Operating Temperature Range Storage Temperature Range Junction Temperature Package Body Temperature +260 ºC 1. The maximum rating voltage must not be exceeded during Latch-up test of the device. www.austriamicrosystems.com Revision 1.02 3 - 17 AS1506 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics VDD = +2.7 to +5.5V, HIGH = VDD, LOW = GND, TAMB = -40 to +85ºC. Typ values are at VDD = +5.0V, TAMB = +25ºC (unless otherwise specified). Table 4. Electrical Characteristics Symbol Power Supply VDD IDD Parameter Condition Min 2.70 0.1 110 Typ Max 5.5 0.5 200 Unit V µA µA Standby Current Digital Inputs = VDD or GND, TAMB = +25ºC Operating Current 1 IOP Includes Non-Volatile Write to Memory (CMOS write) DC Performance (Voltage Divider Mode) N Resolution AS1506-10 2 INL Integral Linearity AS1506-50 & -100 DNL TCR Differential Non-Linearity End-to-End Resistance Temperature Coefficient Full Scale Error 2 256 ±0.5 ±0.25 ±0.5 ±0.25 90 2.5 1.5 1.5 1 0.1 0.1 ±1 ±0.6 ±0.5 ±0.5 ±0.5 200 120 15 10 50 100 4 2.5 2.5 2 0.7 0.7 ±2 ±1.5 ±1 ±1 ±1 ±1 ±0.5 ±1 ±0.5 Taps LSB LSB ppm/ºC AS1506-10 AS1506-50 & -100 TAMB = 0 to +85ºC AS1506-10 AS1506-50 AS1506-100 AS1506-10 AS1506-50 AS1506-100 AS1506-10 AS1506-50 & -100 @ 3V AS1506-50 & -100 @ 5V AS1506-10 AS1506-50 & -100 VDD = 3V VDD = 5V AS1506-10 AS1506-50 AS1506-100 7.5 37.5 75 LSB Zero Scale Error DC Performance (Variable Resistor Mode) INL Integral Linearity 3 LSB LSB DNL Differential Non-Linearity LSB DC Performance (Resistor Characteristics) RW CW REE Wiper Resistance 4 Ω pF 12.5 62.5 125 kΩ Wiper Capacitance End-to-End Resistance Inputs and Outputs WIPER Voltage Range HIGH Voltage Range LOW Voltage Range VIH VIL ILEAK CIN ICONT Digital Input High Voltage Digital Input Low Voltage 5 GND0.3 VDD = 3V VDD = 5V VDD = 3V VDD = 5V 2.1 2.4 VDD+ 0.3 V V 0.6 0.8 500 560 V nA pF µA 5 Digital Input Leakage Current Digital Input Capacitance Continuous DAC current 200 5 www.austriamicrosystems.com Revision 1.02 4 - 17 AS1506 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 4. Electrical Characteristics (Continued) Symbol Parameter Condition AS1506-10 AS1506-50 AS1506-100 AS1506-10 AS1506-50 AS1506-100 TAMB = +85ºC TAMB = +25ºC TAMB = +85ºC Min Typ 1200 220 120 1100 1600 2200 150 10M 1M 20 Max Unit Dynamic Characteristics Wiper -3dB Bandwidth 6 kHz tS Wiper Settling Time 7 ns Non-Volatile Memory Reliability Data Retention Endurance tBUSY 8 8 Years Write Cycles ms Write Non-Volatile Register Busy Time 1. The programming current operates only during power-up and non-volatile memory writes. 2. DNL and INL are measured with the potentiometer configured as a voltage-divider with HIGH = VDD and LOW = GND. The wiper terminal is unloaded and measured with a high-input-impedance voltmeter. 3. DNL and INL are measured with the potentiometer configured as a variable resistor. HIGH is unconnected and LOW = GND. For the 5V condition, the wiper terminal is driven with a source current of 400µA @ 10kΩ, 80µA @ 50kΩ, 40µA @ 100kΩ. In 3V conditions, the wiper terminal is driven with a source current of 200µA @ 10kΩ, 40µA @ 50kΩ, 20µA @ 100kΩ. 4. The wiper resistance is measured using the source currents given in Note 3. The number is the worst case resistance over TAP positions. 5. The device draws higher supply current when the digital inputs are driven with voltages between (VDD - 0.5V) and (GND + 0.5V). 6. Wiper at midscale with a 10pF load (DC measurement) VDD = 5V, LOW = GND. An AC source (5V peak to peak sinus signal) is applied to HIGH and the WIPER output is measured. A 3dB bandwidth occurs when the AC WIPER/HIGH value is 3dB lower than the DC WIPER/HIGH value. 7. Wiper-settling time is the worst-case 0 to 50% rise-time measured between successive wiper positions. HIGH = VDD, LOW = GND; WIPER is unloaded and measured with a 10pF load. 8. This parameter is not tested but ensured by characterization. Timing Characteristics VDD = +2.7 to +5.5V, HIGH = VDD, LOW = GND, TAMB = -40 to +85ºC. Typ values are at VDD = +5.0V, TAMB = +25ºC (unless otherwise specified). See Figure 20 on page 9. Digital timing data is guaranteed by design and characterization, and is not production tested. Table 5. Timing Characteristics Symbol fSCLK tCP tCH tCL80 tCSS tCSH tDS tDH tCS0 tCS1 tCSW tBUSY Parameter SCLK Frequency SCLK Clock Period SCLK Pulse-Width High SCLK Pulse-Width Low CSN-Fall to SCLK Rise Setup SCLK-Rise to CSN-Rise Hold SDIO to SCLK Setup SDIO Hold after SCLK SCLK-Rise to CSN-Fall Delay CSN-Rise to SCLK-Rise Hold CSN Pulse-Width High Write Non-Volatile Register Busy Time Condition Min 200 40 40 40 40 10 0 40 40 200 20 Typ Max 5 Unit MHz ns ns ns ns ns ns ns ns ns ns ms www.austriamicrosystems.com Revision 1.02 5 - 17 AS1506 Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s 7 Typical Operating Characteristics VDD = 5V (unless otherwise specified). Figure 3. DNL vs. TAP Position 10kΩ, Divider Mode 1 0.8 0.6 Figure 4. INL vs. TAP Position 10kΩ, Divider Mode 1 0.8 0.6 DNL (LSB) . INL (LSB) . 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 32 64 96 128 160 192 224 256 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 32 64 96 128 160 192 224 256 Tap Position Tap Position Figure 5. DNL vs. TAP Position 50kΩ, Divider Mode 0.5 0.4 0.3 Figure 6. INL vs. TAP Position 50kΩ, Divider Mode 0.5 0.4 0.3 DNL (LSB) . 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 32 64 96 128 160 192 224 256 INL (LSB) . 0.2 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 32 64 96 128 160 192 224 256 Tap Position Tap Position Figure 7. DNL vs. TAP Position 100kΩ, Divider Mode 0.5 0.4 0.3 Figure 8. INL vs. TAP Position 100kΩ, Divider Mode 0.5 0.4 0.3 DNL (LSB) . 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 32 64 96 128 160 192 224 256 INL (LSB) . 0.2 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 32 64 96 128 160 192 224 256 Tap Position Tap Position www.austriamicrosystems.com Revision 1.02 6 - 17 AS1506 Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s Figure 9. DNL vs. TAP Position 10kΩ, Varistor Mode 1 0.8 0.6 Figure 10. INL vs. TAP Position 10kΩ, Varistor Mode 2 1.6 1.2 DNL (LSB) . 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 32 64 96 128 160 192 224 256 INL (LSB) . 0.4 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 -2 0 32 64 96 128 160 192 224 256 Tap Position Tap Position Figure 11. DNL vs. TAP Position 50kΩ, Varistor Mode 1 0.8 0.6 Figure 12. INL vs. TAP Position 50kΩ, Varistor Mode 1 0.8 0.6 DNL (LSB) . 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 32 64 96 128 160 192 224 256 INL (LSB) . 0.4 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 32 64 96 128 160 192 224 256 Tap Position Tap Position Figure 13. DNL vs. TAP Position 100kΩ, Varistor Mode Mode 1 0.8 0.6 Figure 14. INL vs. TAP Position 100kΩ, Varistor 1 0.8 0.6 DNL (LSB) . INL (LSB) . 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 32 64 96 128 160 192 224 256 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 32 64 96 128 160 192 224 256 Tap Position Tap Position www.austriamicrosystems.com Revision 1.02 7 - 17 AS1506 Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s Figure 15. Wiper Resistance vs. TAP; 5V 120 100 Figure 16. Wiper Resistance vs. TAP; 3V 180 160 . Resistance (Ω) Resistance (Ω ) 0 32 64 96 128 160 192 224 256 80 60 40 20 . 0 140 120 100 80 60 40 20 0 0 32 64 96 128 160 192 224 256 Tap Position Tap Position Figure 17. DAC Resistor vs. Temperature 118 117 Figure 18. Gain vs. Bandwidth 0 100kΩ 116 115 114 113 112 111 110 25 35 45 55 65 75 85 -3 . 50kΩ Resistance (kΩ) 10kΩ Gain (dB) . -6 -9 -12 1 10 100 1000 10000 Temperature (°C) Frequency (kHz) Figure 19. EEPROM Data Retention vs. Temperature 10000 Data Retension (years) . 1000 100 10 25 45 65 85 105 125 Temperature (°C) www.austriamicrosystems.com Revision 1.02 8 - 17 AS1506 Datasheet - D e t a i l e d D e s c r i p t i o n 8 Detailed Description The AS1506 contains a resistor array with 255 resistive elements (tap points), and has a total end-to-end resistance of 10, 50, or 100kΩ (see Ordering Information on page 16). The device provides high, low, and wiper terminals for a standard voltage-divider configuration. Pins HIGH, LOW, and WIPER can be connected in any configuration as long as their voltages fall between GND and VDD. A 3-wire, SPI-compatible serial interface controls movement of the wiper among the 256 tap points. The EEPROM stores the wiper position and recalls the stored wiper position upon power-up. The EEPROM typically holds wiper data for 150 years and up to 10M wiper store cycles. Analog Circuit The 256 tap points are accessible to the wiper along the resistor string between pins HIGH and LOW (similar to the end terminals of a mechanical potentiometer). The wiper tap point is selected by programming 8 data bits and a control byte via the 3-wire serial interface (see Programming the Device on page 10). Note: Integrated power-on reset circuitry loads the wiper position from the EEPROM at power-up. Digital Interface The AS1506 uses an SPI-compatible 3-wire interface for command settings of the device consisting of two input signals (chip-select - CSN, and data clock - SCLK) and one bi-directional data pin (SDIO). Driving CSN low enables serial interface and the command/data are passed into the device synchronously by each SCLK rising edge. There are 16-bit commands for write data into the wiper register or the non-volatile memory, and 8-bit commands for transferring data between wiper register and non-volatile memory and to read the data stored in the wiper register or non-volatile memory. The 8-bit commands can be implemented in 16-bit command structure alternatively. In this case the first 8 bits shifted through the SPI interface are not significant. The data byte passed at writing commands represents the position of the wiper. After loading the 8- or 16-bit command while CSN is low, the loaded command is executed at the next rising edge of CSN, simultaneously the serial interface is disabled. The CSN signal must be low during the whole serial input stream through the SPI, otherwise data on the SPI interface are corrupted. Note: If the data-in stream does not exactly contain 8 or 16 digits, no command is executed at the rising edge of CSN. Figure 20. Serial Data Timing CSN tCS0 tCSS SCLK tCL tCH ... tCSW tCS1 tCP tCSH ... tDS tDH SDIO ... Standby Mode Low-power standby mode is enable at CSN high. After an read access standby mode is entered 2 cycles of SCLK after issuing the last bit of the data wiper or non-volatile register. If the digital inputs are stable VDD or GND there is only leakage power dissipation of the device. This power dissipation is defined with 0.1uA (typ) at 25ºC. www.austriamicrosystems.com Revision 1.02 9 - 17 AS1506 Datasheet - D e t a i l e d D e s c r i p t i o n EEPROM (Non-Volatile Register) There is an internal EEPROM register implemented to retain the wiper position after power down. During an ongoing write cycle of the non-volatile register (tBUSY time) the system must not be powered down. Data retention defines the ability of an EEPROM to retain data over time. The qualification has been done according to JEDEC Retention Lifetime Specification (A117). The EEPROM is cycled to the specified endurance limit before the data retention test is done. Based on activation energy of 0.6eV the data retention time derates over temperature as shown in Figure 19 on page 8. For the non-volatile register 1M endurance cycles and a data retention of 150 years are typical at 85 ºC. The non-volatile register is factory trimmed to mid-scale. Power-Up The AS1506 contains an integrated power-up circuit. At power up, the data are transferred from the non-volatile memory to the wiper register. The wiper register moves to the stored position. This data transfer takes 5µs after the supply has reached the POR trigger level. Programming the Device Write commands (see Table 6) require 16 clock cycles (see Figure 22 on page 12) to clock in the command and data. Copy and Read commands (see Table 6) can use 8 clock cycles to clock in the command (see Figure 21 on page 11) or 16 clock cycles. At 16 clock cycle commands the 8 data bits (D7:D0) are insignificant. Table 6. Command/Data Word Format Command Write Wiper Register Write to Non-Volatile Register Copy Wiper Register to NonVolatile Register Copy Non-Volatile Register to Wiper Register Read Non-Volatile Register Read Wiper Register 1 C7 0 0 0 0 0 0 2 C6 0 0 0 0 0 1 3 C5 0 0 1 1 1 1 4 C4 0 1 0 1 0 0 5 C3 0 0 0 0 1 1 6 C2 0 0 0 0 0 0 7 C1 0 0 0 0 0 0 8 C0 0 0 0 0 0 0 9 D7 D7 D7 10 D6 D6 D6 11 D5 D5 D5 12 D4 D4 D4 13 D3 D3 D3 14 D2 D2 D2 15 D1 D1 D1 16 D0 D0 D0 - Commands Write Wiper Register This is a 16-bit command (see Figure 22 on page 12). The first byte represents the command word starting with the MSB bit of the command, the second byte represents the data written to the wiper register (starting with the MSB). Data 0000 0000 the wiper moves the closest position to LOW, with data 1111 1111 the wiper moves to the closest position to HIGH. Note: At power-up the wiper position stored in the non-volatile memory are automatically loaded into the wiper register, the wiper moves to the related position. Write to Non-Volatile Register This is a 16-bit command (see Figure 22 on page 12). The first byte represents the command word starting with the MSB bit of the command, the second byte represents the data written to the non-volatile memory. The wiper position is not changed by this command, since the wiper register is not affected. There is a write non-volatile register time defined in the timing specification, which is required for storing the data in the non-volatile register. During this time the device must not be powered down, otherwise the data stored in the non-volatile register is corrupted. www.austriamicrosystems.com Revision 1.02 10 - 17 AS1506 Datasheet - D e t a i l e d D e s c r i p t i o n Copy Wiper Register to Non-Volatile Register This command can be implemented as an 8- or 16-bit command. The data stored in the wiper register are transferred to the non-volatile memory, to keep the data during power-down. There is no automatic trigger of this command during power-down of the device. This command must be triggered before powering down the device. There is a write non-volatile register time defined in the timing specification, which is required for storing the data in the non-volatile register. During this time the device must not be powered down, otherwise the data stored in the non-volatile register is corrupted. Copy Non-Volatile Register to Wiper Register This command can be implemented as an 8- or 16-bit command. The data stored in the non-volatile register are transferred to the wiper register, the wiper register moves to the stored position. This command is automatically executed during power up of the system. Read Non-Volatile Register The AS1506 features the capability to read the data from the non-volatile register via the SPI interface (see Figure 23 on page 12). This command can be implemented as an 8- or 16-bit command. The SDIO pin is a bi-directional pin. During the CSN low phase of the sequence the SDIO pin is used as input pin to set the command byte. After CSN rising edge the pin SDIO is set as output pin, the data stored in the non-volatile register are read serially, MSB first. The data propagation starts at the second rising edge of SCLK after the rising edge of CSN. CSN must be high during the read operation. With the next falling edge of CSN the SDIO pin is set to an input pin again. Read Wiper Register The AS1506 features the capability to read the data from the wiper register via the SPI interface (see Figure 23 on page 12). This command can be implemented as an 8- or 16-bit command. The SDIO pin is a bi-directional pin. During the CSN low phase of the sequence, the SDIO pin is used as input pin to set the command byte. After CSN rising edge the pin SDIO is set as output pin, the data stored in the wiper register are read serially, MSB first. The wiper position is unchanged. The data propagation starts at the second rising edge of SCLK after the rising edge of CSN. CSN must be high during the read operation. With the next falling edge of CSN the SDIO pin is set to an input pin again. Figure 21. 8-Bit Command Word CSN SCLK SDIO C7 C6 C5 C4 C3 C2 C1 C0 www.austriamicrosystems.com Revision 1.02 11 - 17 AS1506 Datasheet - D e t a i l e d D e s c r i p t i o n Figure 22. 16-Bit Command/Data Word CSN SCLK SDIO C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 23. 16-Bit Read Command Word CSN SCLK SDIO C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 www.austriamicrosystems.com Revision 1.02 12 - 17 AS1506 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 9 Application Information The AS1506 is intended for circuits requiring digitally controlled adjustable resistance, such as LCD contrast control (where voltage biasing adjusts the display contrast), or programmable filters with adjustable gain and/or cutoff frequency. Programmable Filter Figure 24 shows the configuration for a 1st-order programmable filter. The DC gain of the filter is adjusted by R2 and can be calculated as: G = 1 + (R1/R2) The cutoff frequency (fC) is adjusted by R3, and can be calculated as: fC = 1/(2π x R3 x C) Figure 24. Programmable Filter Circuit CIN VIN HIGH + VOUT – WIPER R1 (EQ 1) (EQ 2) AS1506 R3 LOW HIGH AS1506 R2 LOW WIPER Offset Voltage and Gain Adjustment Connect the AS1506 to an op amp to nullify the offset voltage over the operating temperature range. Install another AS1506 potentiometer in the feedback path to adjust the gain of the op amp (Figure 25). Figure 25. Offset Voltage Adjustment Circuit 5V AS1506 + – www.austriamicrosystems.com Revision 1.02 13 - 17 AS1506 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Positive LCD Bias Control The device can be used in applications where a voltage-divider or variable resistor is used to make an adjustable, positive LCD-bias voltage, such as for the AS1120 LCD Driver. The op amp provides buffering and gain to the resistordivider network made by the potentiometer (Figure 26) or to a fixed resistor and a variable resistor (Figure 27). Figure 26. Positive LCD Bias Control using a Voltage Divider 5V HIGH 30V + VOUT – AS1506 WIPER LOW Figure 27. Positive LCD Bias Control using a Variable Resistor 5V 30V + VOUT – HIGH AS1506 LOW WIPER Adjustable Voltage Reference Figure 28 shows the device used as the feedback resistor in an adjustable voltage-reference application. Output voltages of external voltage references, supervisory reset thresholds, or LED brightness control can be independently adjusted by changing the wiper position of the AS1506. Figure 28. Adjustable Voltage Reference Circuit – VOUT = 1.23V(50kΩ/R2(kΩ) 5V VIN OUT HIGH ADJ VOUTREF WIPER LOW AS1506 www.austriamicrosystems.com Revision 1.02 14 - 17 AS1506 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 10 Package Drawings and Markings The device is available in an 8-pin TDFN 3x3mm package. Figure 29. 8-pin TDFN 3x3mm Package D D2 SEE DETAIL B B A L E2/2 aaa C 2x PIN 1 INDEX AREA (D/2 xE/2) D2/2 E2 K N N-1 e (ND-1) X e BTM VIEW E PIN 1 INDEX AREA (D/2 xE/2) aaa C 2x TOP VIEW b ddd bbb C CAB e DETAIL B e/2 Terminal Tip ccc C A3 C SEATING PLANE 0.08 C A Datum A or B EVEN TERMINAL SIDE Symbol A A1 A3 L1 L2 aaa bbb ccc ddd eee ggg Min 0.70 0.00 Typ 0.75 0.02 0.20 REF Max 0.80 0.05 0.15 0.13 0.15 0.10 0.10 0.05 0.08 0.10 Notes 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 Symbol D BSC E BSC D2 E2 L θ K b e N ND Min Typ 3.00 3.00 A1 SIDE VIEW Max 1.60 1.35 0.30 0º 0.20 0.25 0.40 2.50 1.75 0.50 14º 0.35 0.30 0.65 8 4 Notes 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2, 5 1, 2 1, 2, 5 Notes: 1. Figure 29 is shown for illustration only. 2. All dimensions are in millimeters; angles in degrees. 3. Dimensioning and tolerancing conform to ASME Y14.5 M-1994. 4. N is the total number of terminals. 5. The terminal #1 identifier and terminal numbering convention shall conform to JEDEC 95-1, SPP-012. Details of terminal #1 identifier are optional, but must be located within the zone indicated. The terminal #1 identifier may be either a mold or marked feature. 6. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 7. ND refers to the maximum number of terminals on side D. 8. Unilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals www.austriamicrosystems.com Revision 1.02 15 - 17 AS1506 Datasheet - O r d e r i n g I n f o r m a t i o n 11 Ordering Information The device is available as the standard products shown in Table 7. Table 7. Ordering Information Ordering Code AS1506-BTDT-10 AS1506-BTDT-50 AS1506-BTDT-100 Marking ASMO ASMN ASMM Description 256-Tap, Non-Volatile, SPI Digital Potentiometer 256-Tap, Non-Volatile, SPI Digital Potentiometer 256-Tap, Non-Volatile, SPI Digital Potentiometer End-to-End Resistance 10kΩ 50kΩ 100kΩ Delivery Form Tape and Reel Tape and Reel Tape and Reel Package 8-pin TDFN 3x3mm 8-pin TDFN 3x3mm 8-pin TDFN 3x3mm Note: All products are RoHS compliant and Pb-free. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect For further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor www.austriamicrosystems.com Revision 1.02 16 - 17 AS1506 Datasheet Copyrights Copyright © 1997-2009, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. 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