AS2524BT

austriamicrosystems Telephone Line Interface and Speakerphone Circuit AS2523, AS2524, AS2524B K ey Features - D ATA SHEET G eneral Description A S2523/24 is a CMOS integrated circuit that incorporates DC and AC line adaptation (DC-mask and synthesized ACimpedance of 1000 Ω ) as well as a speech circuit with softclipping, line loss compensation and Rx-volume control for handset and handsfree operation. It shall act as an a/bline powered device, which is controlled by a CPU via a serial interface on AS2523 or a standard dialler via a parallel interface on AS2524 and AS2524B. L ine/Speakerphone circuit on a 28-pin CMOS-IC, simple inventory: same die for AS2523/24 and AS2523/24B S erial I/F on AS2523, parallel I/F on AS2524 E nhanced voice switching B ackground noise monitoring T x- and Rx-gain programmable on AS2523 only D igital volume control of Rx signals on AS2523 only D C characteristic programmable on AS2523 only D ual softclipping in handset mode on AS2523 only D ual softclipping in handsfree mode on AS2523 only L oudspeaker amplifier for loudhearing and handsfree S upply voltage generation for external circuitry A utomatic line loss compensation on AS2523 / 24B only R eal and complex impedance selectable by external components S ide tone adaptation selectable by external components U nique EMC performance O perating range from 15mA to 100mA (down to 5mA with reduced performance) F ew external components A pplications E nhanced handsfree feature phones with CallerID and extended displays. The AS2524 and AS2524B are developed to interface with common Taiwanese dialers. P ackage A vailable in 28-pin SOIC or die B lock Diagram R evision 1.13 Page 1 of 19 D ata Sheet AS2523, AS2524, AS2524B a ustria micro systems P in description P in # 15 S ymbol LS F unction L ine Current S ense Input Analog input for sensing the line current 12 LI L ine I nput Analog input used for power extraction and line current sensing 13 RI R eceive I nput Analog input for ac-separated receive signal 9 S TB S ide T one B alance Input Analog input for side tone cancellation network 10 CS C urrent S hunt Control Output N-channel open drain output to control the external high power shunt transistor for synthesizing AC- and DC-impedance, modulation of line voltage and shorting the line during make periods of pulse dialing 16 CI C omplex I mpedance Input Analog input pin for the capacitor to program a complex impedance 14 SS S upply S ource Control Output N-channel open drain output to control the external high power source transistor for supplying (Vpp) the loudspeaker amplifier in off-hook loudspeaking/handsfree mode 11 V SS V oltage S ource S ource Negative Analog Power Supply 18 V DD V oltage D rain D rain Positive Analog Power Supply 19 A GND A nalog G round Special ground for the internal amplifiers 8 M1 M icrophone Input 1 D ifferential input for the handset microphone (electret) 6 M2 M icrophone Input 2 D ifferential input for the handset microphone (electret) 7 M3 M icrophone Input 3 D ifferential input for the handsfree microphone (electret) 5 M4 M icrophone Input 4 D ifferential input for the handsfree microphone (electret) 17 RO R eceive O utput to H andset Output for driving a dynamic earpiece with an impedance from 150 Ω t o 300 Ω R evision 1.13 Page 2 of 19 D ata Sheet AS2523, AS2524, AS2524B a ustria micro systems P in # 25 S ymbol x CS F unction C hip S elect on AS2523 Chip select input of the serial interface. Internal pull-up resistor ( 100kOhm ) M ute transmit-, receive- path and activate tone path on AS2524 and AS2524B / xMUTE 26 DI D ata I nput on AS2523 Data input of the serial interface. Internal pull-up resistor ( 100kOhm ) / xPD 27 C LK P ower down mode for AS2524 and AS2524B (On-hook) C l oc k o n AS2523 Clock input of the serial interface. Internal pull-up resistor ( 100kOhm ) H andsfree mode operation on AS2524 and AS2524B / HFE 23 2 3 4 1 20 21 24 22 28 LO F T1 T XO T XV C BN R ECI R ECV V SSA V PP T ONEIN L oudspeaker O utput. Output pin is for a 25 Ω A nalog output of the transmit signal l oudspeaker A nalog input pin for connecting a capacitor for offset cancellation. A nalog input for the transmit signal in the voice switching path A nalog input pin for connecting a capacitor for background noise monitoring. A nalog input for the handsfree receive path. Should be connected to RO via coupling capacitor. A nalog input for receive voice switching path. P ower supply pin for LO output amplifier. P ower supply pin for LO output amplifier. A nalog input for DTMF-signals. R evision 1.13 Page 3 of 19 D ata Sheet AS2523, AS2524, AS2524B a ustria micro systems D etailed Block Diagram R evision 1.13 Page 4 of 19 D ata Sheet AS2523, AS2524, AS2524B a ustria micro systems T he gain of the M3/M4 → L S is set to +46dB. This gain can be changed by programming from +39dB to +54dB in 1dB steps on AS2523. The input is differential with an impedance of 10k Ω . The soft clip circuit limits the output voltage at LS to 2V p . There is no LLC for this path. F unctional Description D C conditions T he normal operating mode is from 15mA to 100mA. An operating mode with reduced performance is from 5mA to 15mA. In the line hold range from 0mA to 5mA the device is in a power down mode. T he DC characteristic is determined by the voltage at LIpin and a 30 Ω r esistor between LI- and LS-pin. It can be calculated by the following equation: V LS = V LI + I Line * 3 0 Ω . V LI c an be programmed to be 3.5V or 4.5V. R eceive path T he gain of the LS → R O receive path is set to +7.5dB. T his gain can be changed by programming from –7.5dB to +7.5dB in 1dB steps (Register R xgain ). The receive input is the differential signal of RI and STB. The soft clip circuit limits the output voltage at RO to 1V p. I t prevents harsh distortion and acoustic shock. There is LLC for this path. T he gain of the LS → L O receive path is set to +32dB. This gain can be changed by programming from +19dB to 34dB in 1dB steps. The user can also change the gain via Register H andsfree receive end gain ( See section "Handsfree"). The receive input is the differential signal of RI and STB. The soft clip circuit limits the output voltage at LO to 1.1V p. I t prevents harsh distortion and acoustic shock. There is optional LLC for this path. 2 /4 wire conversion A S2523/24 has built in two Wheatstone bridges with one common ground. This provides a maximum of independence of AC-impedance and side tone from each other. One can adapt side tone without changing the ACimpedance. A C-impedance T he AC-impedance of AS2523/24 is set to t.m. 1000 Ω . With the external capacitor at CI-pin it can be programmed complex. With an external resistor of approx. 1.5k Ω c onnected to the LS-pin it can be programmed to 600 Ω . L ine Loss Compensation (AS2523, AS2524B) p rogrammable on AS2523 n ot activated at AS2524 p ermanently activated at AS2524B W hen it is activated, the transmit and receive gains for both I/O’s are decreased by 6dB at line currents from 20mA to 50mA or from 45mA to 75mA. - S ide Tone A g ood side tone cancellation can be achieved by using the following equation: Z BAL /Z LINE = 1 0 H andsfree T he handsfree function allows voice communication without using the handset (full 2-way speaker phone). Two voice controlled attenuators prevent acoustic coupling between the loudspeaker and the microphone. The voice switching circuit has three states, namely idle, transmit or receive. In receive mode the attenuation of the receive path and the transmit path can be controlled by Register H andsfree receive end gain b etween 0dB and -20dB. The following table shows how voice switching is controlled Transmit path T he gain of the M1/M2 → L S is set to +37dB. This gain can be changed by programming on AS2523 from +30dB to +45dB in 1dB steps (Register T xgain ), on AS2524 / 24B it is set to +37dB per default. The input is differential with an impedance of 10k Ω . The soft clip circuit limits the output voltage at LS to 2V p. T here is LLC for this path. voice switching circuit TX_atten RX Voice switching speech Backgnd noise monitor R evision 1.13 Page 5 of 19 D ata Sheet AS2523, AS2524, AS2524B a ustria micro systems LINE +14dB +8dB ~ +17dB Gmax = +9dB Gmin = -21dB … -40dB (Vol) +23dB +3dB TXO RO TXV Compress Peak detector speech Voice switching 0mV ~ 100mV Peak detector Compress Offset comp FT1 CBN Compress RECV Peak detector Cmicoffset CBckgnd RECI Gmax = -4dB … +16dB (Vol) Gmin = -33dB +9dB S peech R x > Tx_atten T x_atten > Rx T x_atten > Rx X NO Y ES M ode R eceive I dle T ransmit R x-gain 0 db to -20dB - 25 - 50dB T x-gain - 50dB to -30dB - 25 0 dB R emark a djustable with VOL-setting m iddle position i ndependent of VOL-setting IDLE-mode RX-mode 0dB TX-mode -10dB TX-gain -20dB Vol max Vol default Vol min -25dB -30dB -40dB RX-gain -50dB R evision 1.13 Page 6 of 19 D ata Sheet AS2523, AS2524, AS2524B a ustria micro systems Typical Characteristics of Line Loss Compensation (AS2523, AS2524B only) T he line-loss-compensation is programmable at the AS2523, not activated at the AS2524 and LLC high (45mA-75mA) activated at the AS2524B. ( dB) 35 34 33 32 31 30 29 T x Gain N o LLC (AS2523, AS2524) L LC low (AS2523) L LC high ( AS2523,AS2524B) f = 800 Hz Z LINE = 6 00 Ω V LS = - 10 dBm 20 30 40 50 60 70 80 D C Line Current ( mA) F igure 1 Typical Tx Gain Characteristics Line Loss Compensation ( dB) +4 +3 +2 +1 0 -1 -2 R x Gain N o LLC (AS2523, AS2524) L LC low (AS2523) L LC high ( AS2523,AS2524B) f = 800 Hz Z LINE = 6 00 Ω V LS = - 10 dBm V OL = 0 dB (neutral) 20 30 D C Line Current 40 50 60 70 80 ( mA) F igure 2 Typical Rx Gain Characteristics Line Loss Compensation R evision 1.13 Page 7 of 19 D ata Sheet AS2523, AS2524, AS2524B a ustria micro systems S erial Interface on AS2523 R egisters T he settings of the AS2523 are stored in 16 registers. Each register has 4 bit data width. T iming T he data format for writing to a register has the following form: xCS CLK DI N ote: A3 A2 A1 A0 D3 D2 D1 D0 The pins xCS,CLK,DI have internal pull-up resistors. P arameter C LK Pulse width HIGH C LK Pulse width LOW x CS to first falling CLKedge setup time D IN to CLK setup time D IN to CLK hold time t5 t1 t3 S ymbol T6 T5 T1 T3 T4 t6 t4 M IN 1 00ns 1 00ns 5 0ns 5 0ns 5 0ns T YP M AX xCS CLK DIN R evision 1.13 Page 8 of 19 D ata Sheet AS2523, AS2524, AS2524B a ustria micro systems S erial interface Registers T he following table shows the content of the 16 control registers. Address AAAA 3210 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Data DDDD 3210 Nop Control registers AS2523 Default value after reset for AS2523, AS2524HF for AS2524 LH bond option x x x x Conf-Tone: 0... No Conf Tone 1... Conf Tone na na na na 0111 na na na na 0111 Conf Llc1 Llc0 0...3.5V, 1...4.5V LIV: Voltage at pin LI LLC1 LLC0: Line loss compensation setting 0 0 20mA-50mA 0 1 NO Line loss compensation 1 0 45-75mA 1 1 NO Line loss compensation 0001 0...OFF, 1...ON BURS: Analog tone at RO 0...OFF, 1...ON BURL: Analog tone at LS CT1 CT0: @RO @LS 0 0 -36dB -15dB TONE-confidence level 0 1 -30dB -9dB rel. to pin LS 1 0 -24dB -3dB 1 1 -18dB +3dB Softclip-settings, Tx_comp_gain settings Bit1 Bit0 :Tx_comp_gain 0 0 +8dB 0 1 +11dB 1 0 +14dB 1 1 +17dB 0...OFF, SOFTRX: Softclip RX 0...OFF, SOFTTX: Softclip TX 1000 1000 0001 0101 Burs Liv CT1 0110 x x x tx_comp_gain Bit 1 tx_comp_gain Bit0 Soft-RX Soft-TX CT0 Burl x 1...ON 1...ON 0101 1100 0111 1000 16 gains Bit1 Bit0: Rx-offset setting 0 0 0mV 0 1 12mV 1 0 40mV 1 1 100mV 0... no delay Delay_10ms 0... BGN off Bnon Handsfree receive endgain Data 0x0 : 0xF RXgain -20dB : +0dB TXgain -30dB -50dB Rxoffset Bit1 Rxoffset Bit0 Delay_10ms Bnon 1... 10ms delay 1... BGN on 1111 1011 Min. receive volume Max. receive volume 0000 1100 1001 x x x x off1 off0: BGN-offset 0 0 120mV 0 1 180mV 1 0 240mV 1 1 300mV Hfs1 HFs0: Speed of voice switching 0 0 max speed 0 1 1 0 1 1 min speed Transmit gain [16], 16 steps, 1dB stepsize Data HS-mode HF-mode 0x0 30dB 39dB : : : 0xF 45dB 54dB Receive gain [16], 16 steps, 1dB stepsize Data 0x0 : 0xF HS-mode -6dB : +9dB HF-mode 19dB : 34dB 0... 0... 0... 0... Switch 0... fg=200Hz Rxcomp=AGND No mute Tx-signal path No mask 1... 1... 1... 1... fg=2000Hz Rxcomp=RECV Tx-path muted Ton in signal path Hfs1 1010 16 gains Hfs0 off1 off0 0111 0111 1011 16 gains 1111 1111 1100 Rec_on HP_on Tone Mute 1101 x x x x HP_on : rec_on : Mute : Tone : Mask, Lh, Hf, Hook Mask: His 0 1 1 1 1 HF x 0 0 1 1 LH: x 0 1 0 1 0100 1000 0100 1... Mask acitivated 0101 Mask His 1110 x Krat5 x Test3 x Test2 LH Hf Hook functions Power down Handset not allowed Handsfree Loudhearing 0000 0001 x slow_rec slow_rec: fast change to TX, slow change to RX, no IDLE Krat5,Test3,Test2: For factory test only ! Reset to defaults na na 1111 xx x x For a detailed description of the commands see Application note AN523/24. Revision 1.13 Page 9 of 19 D ata Sheet AS2523, AS2524, AS2524B a ustria micro systems A dditional settings in Handsfree mode N ote: change the default settings only if necessary: a ) A click-free startup can be achieved by starting up in handset mode (=default) and then switching to handsfree, once the chip has stabilized. b ) Change the Tx comparator preamplifier gain in register 6 Default = 14dB c ) Change the Receive DC offset and Background noise monitoring in Register 7 default = 0mV offset (higher val. puts more weight on Rx) switching delay default = on Background Noise Monitoring = on d ) Set the speaker amplifier volume in register 8 Default = 0B e ) Set the handsfree voice switching speed and Background Noise monitoring offset in register 9: default voice switching speed = 1ms/6dB (fastest) default BGN monitoring offset = 240mV (determines the Tx level required to switch from idle to Transmit) P rogramming Guidelines for the AS2523 T he AS2523 is programmed by means of a serial 8-bit shift register. MSB is clocked in first, LSB last. The first four bits (7,6,5,4) are the addresses of the registers, the last four bits (3,2,1,0) are the data bits. E ach register has a default setting (see data sheet), which is set after power-up of the chip. T he internal registers are RAM-cells. When the AS2523 loses VDD (as in on-hook state) it also loses the register contents. I t is therefore necessary to re-write the affected registers after each hook event. The register contents cannot be read, they can only be written. R egisters need to be re-written after each power-up and after each hook event (handset / handsfree / on-hook). I t is recommended to always initialize the chip with a “reset to defaults command” (Fx) first and then write the appropriate registers that need to be changed from the default setting. A lternatively, all registers (4 to 16) may be re-written in a bulk at each power-up and hook event (handset / handsfree / on-hook). T his guarantees safe operation in case of unexpected loss of power during normal operation. Re-writing all registers also eases later software updates, as only register contents need to be changed, but no additional command lines need to be inserted. A dditional settings during F lash D uring a Flash, the AS2523 should be powered down to avoid discharge of VDD: S et the MASK bit (bit3 in register D) to 1 A fter the line current is restored, the MASK bit must be cleared again. Other settings do not need to be re-written, as VDD has not discharged. As a safety margin however, it is recommended to re-write all registers after a flash A dditional settings during l ine breaks I f a line-break-detection (brief interruption of the line while in off-hook state) is implemented, the same rules apply as for a Flash: set the MASK bit to 1 to avoid discharge of VDD. It is recommended to re-write all registers after a line-break, as a line break may take long enough to discharge VDD, even when the MASK bit was set. E xample of a typical power-up sequence A t ypical power-up sequence will require the following programming. a ) determine the cause of power-up (handset / handsfree mode) and set register D accordingly. Default = handset mode b ) Set the LI voltage to 3.5V or 4.5V (default = 4.5V) and Line Loss Compensation (default = off) in register 4 c ) Set the Confidence Tone level (e.g. the DTMF level which is audible in the handset) and path in register 5 Default = off d ) Set the required Tx and Rx gains in Registers A and B Default = 37dB Tx gain, 1dB Rx gain G eneral Rules T he serial interface may be programmed at any time, it does not affect the speech quality, e.g. if a register is overwritten with the same value. I t is also possible to re-write all registers periodically. The register is static, therefore it can be clocked at any speed up to 5MHz. H owever, electromagnetic pulses on the clock and data lines may cause unwanted programming of the chip. It is therefore recommended to keep these lines short, filter them by a discrete lowpass filter and reduce the clock speed accordingly. R evision 1.13 Page 10 of 19 D ata Sheet AS2523, AS2524, AS2524B a ustria micro systems P arallel Interface on AS2524 and AS2524B I nput Signal on Pin X PD 0 0 0 0 1 1 1 1 x Mute 0 0 1 1 0 0 1 1 HF 0 1 0 1 0 1 0 1 M ode P ower down P ower down P ower down P ower down T one mode T one mode H andset mode H andsfree mode P ower down mode F or low power consumption the analog part is turned off during activated power down mode. The Power down mode is used during Flash and Pulse dialing and for On-hook operation. H andset mode S peech mode is Handset mode (M1-M2, RO active; LO deactivated) P arameter L I Voltage L LC T X-Gain R X-Gain R x-Softclip T x-Softclip T one A S2524 4 .5V N o LLC + 37dB + 7.5dB O ff O ff O ff A S2524B 4 .5V L LC high (45mA to 75mA) + 43dB + 7.5dB O ff O ff O ff H andsfree mode S peech mode is Handsfree mode (M3-M4, RO active; LO active) P arameter L I Voltage L LC H F TX-Gain H F RX-Gain R x-Softclip T x-Softclip T one B NM A S2524 4 .5V N o LLC + 46dB + 34dB O ff O ff O ff On A S2524B 4 .5V L LC high (45mA to 75mA) + 52dB + 34dB O ff O ff O ff On R evision 1.13 Page 11 of 19 D ata Sheet AS2523, AS2524, AS2524B a ustria micro systems T one mode T his mode is used to send DTMF and FSK data to the line. S peech mode is Tone mode (M1-M2;M3-M4 muted, Rx path muted, RO and LO active) P arameter L I Voltage L LC T one TX-Gain C onfidence tone level A S2524 4 .5V N o LLC + 14dB - 36dB@Ro – 15dB@Lo relative to Pin LS A S2524B 4 .5V L LC high (45mA to 75mA) + 14dB - 36dB@Ro – 15dB@Lo relative to Pin LS L oudhearing AS2524 and AS2524B (feature only available as DIE) S peech mode is Loudhearing (M3-M4, RO active; LO activated). Loudhearing can be activated via a bond-option (see document “AS2523/24 Delivery as Dice”). P arameter L I Voltage L LC T X-Gain R X-Gain T one S low_rec R ECV pin H ighpass V oice switching speed R X-Offset A S2524 4 .5V N o LLC + 37dB + 7.5dB O ff On D eactivated 2 000kHz (10nF from TXO->TXV) 1 20ms/6dB 3 00mV A S2524B 4 .5V L LC high (45mA to 75mA) + 43dB + 7.5dB O ff On D eactivated 2 000kHz (10nF from TXO->TXV) 1 20ms/6dB 3 00mV E lectrical characteristics E lectrical characteristics are measured with the Test Circuit application. Typical mean values will not be tested. A bsolute maximum ratings P ositive Supply Voltage I nput Current I nput Voltage (LS) I nput Voltage (LI, CS) I nput Voltage (STB, RI) D igital Input Voltage E lectrostatic Discharge (HBM 1.5k Ω -100pF) S torage Temperature - 0.3V