AS5040ASST

A S5040 1 0Bit 360° Programmable Magnetic Rotary Encoder 1 General Description The AS5040 is a contactless magnetic rotary encoder for accurate angular measurement over a full turn of 360°. It is a system-on-chip, combining integrated Hall elements, analog front end and digital signal processing in a single device. To measure the angle, only a simple two-pole magnet, rotating over the center of the chip, is required. The magnet may be placed above or below the IC. The absolute angle measurement provides instant indication of the magnet’s angular position with a resolution of 0.35° = 1024 positions per revolution. This digital data is available as a serial bit stream and as a PWM signal. Furthermore, a user-programmable incremental output is available, making the chip suitable for replacement of various optical encoders. An internal voltage regulator allows the AS5040 to operate at either 3.3 V or 5 V supplies. Figure 1: Typical Arrangement of AS5040 and Magnet Data Sheet 2 Key Features Contactless high resolution rotational position encoding over a full turn of 360 degrees Two digital 10bit absolute outputs: - Serial interface and - Pulse width modulated (PWM) output Three incremental output modes: - Quadrature A/B and Index output signal - Step / Direction and Index output signal - 3-phase commutation for brushless DC motors - 10, 9, 8 or 7 bit user programmable resolution User programmable zero / index position Failure detection mode for magnet placement monitoring and loss of power supply Rotational speeds up to 30,000 rpm Push button functionality detects movement of magnet in Z-axis Serial read-out of multiple interconnected AS5040 devices using Daisy Chain mode Wide temperature range: - 40°C to + 125°C Fully automotive qualified to AEC-Q100, grade 1 Small Pb-free package: SSOP 16 (5.3mm x 6.2mm) 3 Applications Industrial applications: - Contactless rotary position sensing - Robotics - Brushless DC motor commutation - Power tools Benefits Complete system-on-chip Flexible system solution provides absolute, PWM and incremental outputs simultaneously Ideal for applications in harsh environments due to contactless position sensing Tolerant to magnet misalignment and airgap variations No temperature compensation necessary No calibration required Automotive applications: - Steering wheel position sensing - Gas pedal position sensing - Transmission gearbox encoder - Headlight position control - Power seat position indicator Office equipment: printers, scanners, copiers Replacement of optical encoders Front panel rotary switches Replacement of potentiometers www.austriamicrosystems.com Revision 2.10 1 - 33 AS5040 Data Sheet 4 Pin Configuration Figure 2: Pin Configuration SSOP16 MagINCn MagDECn A_LSB_U B_Dir_V NC Index_W VSS Prog 1 2 16 15 VDD5V VDD3V3 NC NC PWM_LSB CSn CLK DO AS5040 3 4 5 6 7 8 14 13 12 11 10 9 Pin Description Table 2 shows the description of each pin of the standard SSOP16 package (Shrink Small Outline Package, 16 leads, body size: 5.3mm x 6.2mmm; see Figure 2). Pins 7, 15 and 16 are supply pins, pins 5, 13 and 14 are for internal use and must not be connected. Pins 1 and 2 are the magnetic field change indicators, MagINCn and MagDECn (magnetic field strength increase or decrease through variation of the distance between the magnet and the device). These outputs can be used to detect the valid magnetic field range. Furthermore those indicators can also be used for contact-less push-button functionality. Pins 3, 4 and 6 are the incremental pulse output pins. The functionality of these pins can be configured through programming the one-time programmable (OTP) register. Table 1: Pin Assignment for the Different Incremental Output Modes Output Mode 1.x: quadrature 2.x:step/direction 3.x: commutation Pin 3 A LSB U Pin 4 B Direction V Pin 6 Index Index W Pin 12 PWM PWM LSB Mode 1.x: Quadrature A/B Output Represents the default quadrature A/B signal mode. Mode 2.x: Step / Direction Output Configures pin 3 to deliver up to 512 pulses (up to 1024 state changes) per revolution. It is equivalent to the LSB (least significant bit) of the absolute position value. Pin 4 provides the information of the rotational direction. Both modes (mode 1.x and mode 2.x) provide an index signal (1 pulse/revolution) with an adjustable width of one LSB or three LSB’s. www.austriamicrosystems.com Revision 2.10 2 - 33 AS5040 Data Sheet Table 2 Pin Description SSOP16 Pin 1 2 3 A_LSB_U 4 B_Dir_V 5 6 7 8 Prog 9 10 11 12 13 14 15 16 D O_OD DO DI_PD DI_PU DO CLK CSn PWM_LSB NC NC VDD3V3 VDD5V digital digital digital digital DI_PD DO_T DI, ST DI_PU, ST DO S S NC Index_W VSS DO DO S DO Symbol MagINCn MagDECn Type DO_OD DO_OD Description Magnet Field Magnitude INCrease; active low, indicates a distance reduction between the magnet and the device surface. Magnet Field Magnitude DECrease; active low, indicates a distance increase between the device and the magnet. Mode1.x: Quadrature A channel Mode2.x: Least Significant Bit Mode3.x: U signal (phase1) Mode1.x: Quadrature B channel quarter period shift to channel A. Mode2.x: Direction of Rotation Mode3.x: V signal (phase2) Must be left unconnected Mode1.x and Mode2.x : Index signal indicates the absolute zero position Mode3.x: W signal (phase3) Negative Supply Voltage (GND) OTP Programming Input and Data Input for Daisy Chain mode. Internal pull-down resistor (~74kΩ). May be connected to VSS if programming is not used Data Output of Synchronous Serial Interface Clock Input of Synchronous Serial Interface; Schmitt-Trigger input Chip Select, active low; Schmitt-Trigger input, internal pull-up resistor (~50kΩ) connect to VSS in incremental mode (see 0) Pulse Width Modulation of approx. 1kHz; LSB in Mode3.x Must be left unconnected Must be left unconnected 3V-Regulator Output (see Figure 19) Positive Supply Voltage 5 V S DI DO_T ST supply pin digital input digital output /tri-state Schmitt-Trigger input output open drain output input pull-down input pull-up Mode 3.x: Brushless DC Motor Commutation Mode In addition to the absolute encoder output over the SSI interface, this mode provides commutation signals for brushless DC motors with either one pole pair or two pole pair rotors. The commutation signals are usually provided by 3 discrete Hall switches, which are no longer required, as the AS5040 can fulfill two tasks in parallel: absolute encoder + BLDC motor commutation. In this mode, pin 12 provides the LSB output instead of the PWM (Pulse-Width-Modulation) signal. Pin 8 (Prog) is also used to program the different incremental interface modes, the incremental resolution and the zero position into the OTP (see page 18). This pin is also used as digital input to shift serial data through the device in Daisy Chain configuration, (see page 11). Pin 11 Chip Select (CSn; active low) selects a device within a network of AS5040 encoders and initiates serial data transfer. A logic high at CSn puts the data output pin (DO) to tri-state and terminates serial data transfer. This pin is also used for alignment mode (page 21) and programming mode (page 16). www.austriamicrosystems.com Revision 2.10 3 - 33 AS5040 Data Sheet Pin 12 allows a single wire output of the 10-bit absolute position value. The value is encoded into a pulse width modulated signal with 1µs pulse width per step (1µs to 1024µs over a full turn). By using an external low pass filter, the digital PWM signal is converted into an analog voltage, allowing a direct replacement of potentiometers. 5 Electrical Characteristics Absolute Maximum Ratings (non operating) Stresses beyond those listed under “Absolute Maximum Ratings“ may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter DC supply voltage at pin VDD5V DC supply voltage at pin VDD3V3 Input pin voltage Input current (latchup immunity) Electrostatic discharge Storage temperature Body temperature (Lead-free package) Humidity non-condensing Symbol VDD5V VDD3V3 Vin Iscr ESD Tstrg TBody H Min -0.3 -0.3 -0.3 -0.3 -100 Max 7 5 VDD5V +0.3 7.5 100 ±2 Unit V V V mA kV °C °C % Note Pins MagIncn, MagDecn, CLK, CSn, Pin Prog Norm: JEDEC 78 Norm: MIL 883 E method 3015 Min – 67°F ; Max +257°F t=20 to 40s, Norm: IPC/JEDEC JStd-020C Lead finish 100% Sn “matte tin” -55 125 260 5 85 Operating Conditions Parameter Ambient temperature Supply current External supply voltage at pin VDD5V Internal regulator output voltage at pin VDD3V3 External supply voltage at pin VDD5V, VDD3V3 Symbol Tamb Isupp VDD5V VDD3V3 VDD5V VDD3V3 4.5 3.0 3.0 3.0 Min -40 16 5.0 3.3 3.3 3.3 Typ Max Unit 125 21 5.5 3.6 3.6 3.6 °C mA V V V V 5V operation 3.3V operation (pins VDD5V and VDD3V3 connected) -40°F…+257°F Note DC Characteristics for Digital Inputs and Outputs CMOS Schmitt-Trigger Inputs: CLK, CSn (CSn = internal Pull-up) (operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless otherwise noted) P arameter High level input voltage Low level input voltage Schmitt Trigger hysteresis Input leakage current Pull-up low level input current www.austriamicrosystems.com S ymbol VIH VIL VIon- VIoff ILEAK IiL M in 0.7 * VDD5V M ax U nit V N ote Normal operation 0.3 * VDD5V 1 -1 -30 Revision 2.10 V V CLK only CSn only, VDD5V: 5.0V 4 - 33 1 -100 µA µA AS5040 Data Sheet CMOS / Program Input: Prog (operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless otherwise noted) P arameter High level input voltage High level input voltage Low level input voltage Pull-down high level input current S ymbol VIH VPROG VIL IiL M in 0.7 * VDD5V M ax 5 0.3 * VDD5V 100 U nit V V V µA VDD5V: 5.5V During programming N ote See “programming conditions” CMOS Output Open Drain: MagINCn, MagDECn (operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless otherwise noted) P arameter Low level output voltage Output current Open drain leakage current S ymbol VOL IO IOZ M in M ax VSS+0.4 4 2 1 U nit V mA µA VDD5V: 4.5V VDD5V: 3V N ote CMOS Output: A, B, Index, PWM (operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless otherwise noted) P arameter High level output voltage Low level output voltage Output current S ymbol VOH VOL IO M in VDD5V-0.5 VSS+0.4 4 2 M ax U nit V V mA VDD5V: 4.5V VDD5V: 3V N ote Tristate CMOS Output: DO (operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless otherwise noted) P arameter High level output voltage Low level output voltage Output current Tri-state leakage current S ymbol VOH VOL IO IOZ M in VDD5V –0.5 VSS+0.4 4 2 1 M ax U nit V V mA µA VDD5V: 4.5V VDD5V: 3V N ote Magnetic Input Specification (operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless otherwise noted) Two-pole cylindrical diametrically magnetised source: P arameter Diameter Thickness Magnetic input field amplitude S ymbol dmag tmag Bpk M in 4 2.5 45 75 T yp 6 M ax U nit mm mm mT Note Recommended magnet: Ø 6mm x 2.5mm for cylindrical magnets Required vertical component of the magnetic field strength on the die’s surface, measured along a concentric circle with a radius of 1.1mm www.austriamicrosystems.com Revision 2.10 5 - 33 AS5040 Data Sheet P arameter Magnetic offset Field non-linearity Input frequency (rotational speed of magnet) S ymbol Boff M in T yp M ax ± 10 5 U nit mT % Hz Hz Note Constant magnetic stray field Including offset gradient Absolute mode: 600 rpm @ readout of 1024 positions (see Table 6) Incremental mode: no missing pulses at rotational speeds of up to 30,000 rpm (see Table 6) Max. X-Y offset between defined IC package center and magnet axis (see Figure 21) Max. X-Y offset between chip center and magnet axis. Placement tolerance of chip within IC package (see Figure 23) NdFeB (Neodymium Iron Boron) SmCo (Samarium Cobalt) fmag_abs fmag_inc 10 500 0.25 Displacement radius Disp 0.485 mm Chip placement tolerance Recommended magnet material and temperature drift -0.12 -0.035 ±0.23 5 mm %/K Electrical System Specifications (operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless otherwise noted) P arameter Resolution 7 bit 8 bit 9 bit 10 bit Integral non-linearity (optimum) S ymbol RES M in T yp M ax 10 U nit bit 0.352 deg N ote 2.813 LSB 1.406 0.703 0.352 INLopt ± 0.5 deg Maximum error with respect to the best line fit. Verified at optimum magnet placement, Tamb =25 °C. Maximum error with respect to the best line fit. Verified at optimum magnet placement , Tamb = -40 to +125°C Best line fit = (Errmax – Errmin) / 2 Over displacement tolerance with 6mm diameter magnet, Tamb = -40 to +125°C 10bit, no missing codes RMS equivalent to 1 sigma Incremental modes only deg Adjustable resolution only available for incremental output modes; Least significant bit, minimum step Integral non-linearity (optimum) INLtemp ± 0.9 deg Integral non-linearity INL ± 1.4 deg Differential non-linearity Transition noise Hysteresis Power-on reset thresholds On voltage; 300mV typ. hysteresis Off voltage; 300mV typ. hysteresis Power-up time System propagation delay absolute output DNL TN Hyst Von Voff tPwrUp tdelay 1.37 1.08 0.704 2.2 1.9 ± 0.176 0.12 deg Deg RMS deg 2.9 V 2.6 50 48 ms µs DC supply voltage 3.3V (VDD3V3) DC supply voltage 3.3V (VDD3V3) Until offset compensation finished Includes delay of ADC and DSP www.austriamicrosystems.com Revision 2.10 6 - 33 AS5040 Data Sheet P arameter System propagation delay incremental output Sampling rate for absolute output Read-out frequency S ymbol M in T yp M ax 192 U nit µs N ote Calculation over two samples Internal sampling rate, Tamb = 25°C 9.90 fS CLK 9.38 10.42 10.42 10.94 kHz 11.46 1 MHz Internal sampling rate, Tamb = -40 to +125°C Max. clock frequency to read out serial data Figure 3: Integral and Differential Non-linearity Example (exaggerated curve) 1023 α 10bit code Actual curve 2 1 0 1023 TN DNL+1LSB INL 0.35° 512 Ideal curve 512 0 0° 180° 360 ° α [degrees] Integral Non-Linearity (INL) is the maximum deviation between actual position and indicated position. Differential Non-Linearity (DNL) is the maximum deviation of the step length from one position to the next. Transition Noise (TN) is the repeatability of an indicated position. Timing Characteristics Synchronous Serial Interface (SSI) (operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless otherwise noted) P arameter Data output activated (logic high) First data shifted to output register Start of data output Data output valid Data output tristate Pulse width of CSn www.austriamicrosystems.com S ymbol t DO active tCLK FE T CLK / 2 t DO valid t DO tristate t CSn M in T yp M ax 100 U nit ns ns ns N ote Time between falling edge of CSn and data output activated Time between falling edge of CSn and first falling edge of CLK Rising edge of CLK shifts out one bit at a time Time between rising edge of CLK and data output valid After the last bit DO changes back to “tristate” CSn = high; To initiate read-out of next angular position 7 - 33 500 500 357 413 100 500 Revision 2.10 ns ns ns AS5040 Data Sheet P arameter Read-out frequency S ymbol fCLK M in >0 T yp M ax 1 U nit MHz N ote Clock frequency to read out serial data Pulse Width Modulation Output (operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless otherwise noted) P arameter PWM frequency Minimum pulse width Maximum pulse width S ymbol f PWM PW MIN PW MAX M in 0.927 0.878 0.90 922 T yp 0.976 0.976 1 1024 M ax 1.024 1.074 1.10 1126 U nit KHz µs µs N ote Signal period = 1025µs ±5% at Tamb = 25°C =1025µs ±10% at Tamb = -40 to +125°C Position 0d; angle 0 degree Position 1023d; angle 359.65 degree Incremental Outputs (operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless otherwise noted) P arameter Incremental outputs valid after power-up Directional indication valid S ymbol t Incremental outputs valid M in Typ M ax 500 500 U nit ns ns N ote Time between first falling edge of CSn after power-up and valid incremental outputs Time between rising or falling edge of LSB output and valid directional indication t Dir valid Programming Conditions (operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless otherwise noted) P arameter Programming enable time Write data start Write data valid Load programming data Rise time of VPROG before CLKPROG Hold time of VPROG after CLKPROG Write data – programming CLKPROG CLK pulse width Hold time of Vprog after programming Programming voltage Programming voltage off level Programming current Analog read CLK Programmed zener voltage (log.1) Unprogrammed zener voltage (log. 0) www.austriamicrosystems.com S ymbol t Prog enable t Data in t Data in valid t Load PROG t PrgR t PrgH CLK PROG t PROG t PROG finished V PROG V ProgOff I PROG CLKAread Vprogrammed Vunprogrammed M in 2 2 250 3 0 0 T yp M ax U nit µs µs ns µs µs N ote Time between rising edge at Prog pin and rising edge of CSn Write data at the rising edge of CLKPROG 5 250 µs kHz µs µs During programming; 16 clock cycles Programmed data is available after next power-on Must be switched off after zapping Line must be discharged to this level During programming Analog readback mode VRef-VPROG during analog readback mode (see Analog Readback Mode) 1.8 2 7.3 0 2 2.2 7.4 7.5 1 130 100 100 V V mA kHz mV V 1 Revision 2.10 8 - 33 AS5040 Data Sheet 6 Functional Description The AS5040 is manufactured in a CMOS standard process and uses a spinning current Hall technology for sensing the magnetic field distribution across the surface of the chip. The integrated Hall elements are placed around the center of the device and deliver a voltage representation of the magnetic field at the surface of the IC. Through Sigma-Delta Analog / Digital Conversion and Digital Signal-Processing (DSP) algorithms, the AS5040 provides accurate high-resolution absolute angular position information. For this purpose a Coordinate Rotation Digital Computer (CORDIC) calculates the angle and the magnitude of the Hall array signals. The DSP is also used to provide digital information at the outputs M a g I N C n and M a g D E C n that indicate movements of the used magnet towards or away from the device’s surface. A small low cost diametrically magnetized (two-pole) standard magnet provides the angular position information (see Figure 20). The AS5040 senses the orientation of the magnetic field and calculates a 10-bit binary code. This code can be accessed via a Synchronous Serial Interface (SSI). In addition, an absolute angular representation is given by a Pulse Width Modulated signal at pin 12 (PWM). Besides the absolute angular position information the device simultaneously provides incremental output signals. The various incremental output modes can be selected by programming the OTP mode register bits (see page 19). As long as no programming voltage is applied to pin Prog, the new setting may be overwritten at any time and will be reset to default when power is turned off. To make the setting permanent, the OTP register must be programmed (see Figure 15). The default setting is a quadrature A/B mode including the Index signal with a pulse width of 1 LSB. The Index signal is logic high at the user programmable zero position. The AS5040 is tolerant to magnet misalignment and magnetic stray fields due to differential measurement technique and Hall sensor conditioning circuitry. Figure 4: AS5040 Block Diagram www.austriamicrosystems.com Revision 2.10 9 - 33 AS5040 Data Sheet 7 10-bit Absolute Angular Position Output Synchronous Serial Interface (SSI) Figure 5: Synchronous Serial Interface with Absolute Angular Position Data CSn t CLK FE t CLK FE T CLK / 2 1 8 16 t CSn CLK 1 DO D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 OCF COF LIN Mag INC M ag Even D EC PAR D9 t DO active t DO valid Angular Position Data Status Bits t DO Tristate If CSn changes to logic low, Data Out (DO) will change from high impedance (tri-state) to logic high and the read-out will be initiated. After a minimum time tCLK FE, data is latched into the output shift register with the first falling edge of CLK. Each subsequent rising CLK edge shifts out one bit of data. The serial word contains 16 bits, the first 10 bits are the angular information D[9:0], the subsequent 6 bits contain system information, about the validity of data such as OCF, COF, LIN, Parity and Magnetic Field status (increase/decrease) . A subsequent measurement is initiated by a log. “high” pulse at CSn with a minimum duration of tCSn. Data Content: D 9:D0 a bsolute angular position data (MSB is clocked out first) O CF ( O ffset C ompensation F inished), logic high indicates the finished Offset Compensation Algorithm. For fast startup, this bit may be polled by the external microcontroller. As soon as this bit is set, the AS5040 has completed the startup and the data is valid (see Table 4) COF (Cordic Overflow), logic high indicates an out of range error in the CORDIC part. When this bit is set, the data at D9:D0 is invalid. The absolute output maintains the last valid angular value. This alarm may be resolved by bringing the magnet within the X-Y-Z tolerance limits. LIN (Linearity Alarm), logic high indicates that the input field generates a critical output linearity. When this bit is set, the data at D9:D0 may still be used, but can contain invalid data. This warning may be resolved by bringing the magnet within the X-Y-Z tolerance limits. MagINCn, (Magnitude Increase) becomes HIGH, when the magnet is pushed towards the IC, thus the magnetic field strength is increasing. MagDECn, (Magnitude Decrease) becomes HIGH, when the magnet is pulled away from the IC, thus the magnetic field strength is decreasing. Both signals HIGH indicate a magnetic field that is out of the allowed range (see Table 3). www.austriamicrosystems.com Revision 2.10 10 - 33 AS5040 Data Sheet Table 3: Magnetic Magnitude Variation Indicator M ag I NCn 0 0 1 1 M ag D ECn 0 1 0 1 D escription No distance change; Magnetic input field OK (in range, 45..75mT) Distance increase: Pull-function. This state is dynamic, it is only active while the magnet is moving away from the chip in Z-axis Distance decrease: Push- function. This state is dynamic, it is only active while the magnet is moving towards the chip in Z.-axis. Magnetic Input Field invalid – out of range: 75mT (or missing magnet) Note: Pins 1 and 2 (MagINCn, MagDECn) are open drain outputs and require external pull-up resistors. If the magnetic field is in range, both outputs are turned off. The two pins may also be combined with a single pull-up resistor. In this case, the signal is high when the magnetic field is in range. It is low in all other cases (see Table 3). Even Parity bit for transmission error detection of bits 1…15 (D9…D0, OCF, COF, LIN, MagINCn, MagDECn) The absolute angular output is always set to a resolution of 10 bit. Placing the magnet above the chip, angular values increase in clockwise direction by default. Data D9:D0 is valid, when the status bits have the following configurations: Table 4: Status Bit Outputs OCF COF LIN Mag INCn 0 1 0 0 0 1 Mag DECn 0 1 0 Parity even checksum of bits 1:15 The absolute angular position is sampled at a rate of 10kHz (0.1ms). This allows reading of all 1024 positions per 360 degrees within 0.1 seconds = 9.76Hz (~10Hz) without skipping any position. Multiplying 10Hz by 60, results the corresponding maximum rotational speed of 600 rpm. Readout of every second angular position allows for rotational speeds of up to 1200rpm. Consequently, increasing the rotational speed reduces the number of absolute angular positions per revolution (see Table 7). Regardless of the rotational speed or the number of positions to be read out, the absolute angular value is always given at the highest resolution of 10 bit. The incremental outputs are not affected by rotational speed restrictions due to the implemented interpolator. The incremental output signals may be used for high-speed applications with rotational speeds of up to 30,000 rpm without missing pulses. Daisy Chain Mode The Daisy Chain mode allows connection of several AS5040’s in series, while still keeping just one digital input for data transfer (see “Data IN” in Figure 6 below). This mode is accomplished by connecting the data output (DO; pin 9) to the data input (Prog; pin 8) of the subsequent device. An RC filter must be implemented between each PROG pin of device n and DO pin of device n+1, to prevent the encoders to enter the alignment mode, in case of ESD discharge, long cables, or not conform signal levels or shape. Using the values R=100R and C=1nF allow a max. CLK frequency of 1MHz on the whole chain. The serial data of all connected devices is read from the DO pin of the first device in the chain. The Prog pin of the last device in the chain should be connected to VSS. The length of the serial bit stream increases with every connected device, it is n * (16+1) bits: e.g. 34 bit for two devices, 51 bit for three devices, etc… The last data bit of the first device (Parity) is followed by a logic low bit and the first data bit of the second device (D9), etc… (see Figure 7). www.austriamicrosystems.com Revision 2.10 11 - 33 AS5040 Data Sheet Programming Daisy Chained Devices In Daisy Chain mode, the Prog pin is connected directly to the DO pin of the subsequent device in the chain (see Figure 6). During programming (see section 12), a programming voltage of 7.5V must be applied to pin Prog. This voltage level exceeds the limits for pin DO, so one of the following precautions must be made during programming: open the connection DO Prog during programming or add a Schottky diode between DO and Prog (Anode = DO, Cathode = Prog) Due to the parallel connection of CLK and CSn, all connected devices may be programmed simultaneously. Figure 6: Daisy Chain Hardware Configuration CSn CLK DI CSn CLK DO PROG 100R 1nF CSn CLK DO PROG 100R 1nF GND AS5040 CSn CLK DO PROG GND AS5040 MCU AS5040 GND Figure 7: Daisy Chain Mode Data Transfer CSn tCLK FE TCLK/2 1 8 16 D 1 2 3 CLK DO D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 OCF COF LIN Mag INC Mag DEC Even PAR D9 D8 D7 tDO active tDO valid Angular Position Data 1st Device Status Bits Angular Position Data 2nd Device 8 Incremental Outputs Three different incremental output modes are possible with quadrature A/B being the default mode. Figure 8 shows the two-channel quadrature as well as the step / direction incremental signal (LSB) and the direction bit in clockwise (CW) and counter-clockwise (CCW) direction. Quadrature A/B Output (Quad A/B Mode) The phase shift between channel A and B indicates the direction of the magnet movement. Channel A leads channel B at a clockwise rotation of the magnet (top view) by 90 electrical degrees. Channel B leads channel A at a counterclockwise rotation. LSB Output (Step / Direction Mode) Output LSB reflects the LSB (least significant bit) of the programmed incremental resolution (OTP Register Bit Div0, Div1). Output Dir provides information about the rotational direction of the magnet, which may be placed above or below the device (1=clockwise; 0=counter clockwise; top view). Dir is updated with every LSB change. In both modes (quad A/B, step/direction) the resolution and the index output are user programmable. The index pulse indicates the zero position and is by default one angular step (1LSB) wide. However, it can be set to three LSBs by programming the Index-bit of the OTP register accordingly (see Table 6). www.austriamicrosystems.com Revision 2.10 12 - 33 AS5040 Data Sheet Figure 8: Incremental Output Modes Q uad A/B-M ode A B M echanical Zero Position R otation Direction Change M echanical Zero Position I ndex=0 1 LSB I ndex H yst = 2 LSB S tep / Dir-Mode L SB Dir I ndex=1 3 L SB C lockwise cw C ounterclockwise ccw C Sn t I ncrem ental outputs valid t D ir valid Incremental Power-up Lock Option After power-up, the incremental outputs can optionally be locked or unlocked, depending on the status of the CSn pin: CSn = low at power-up: CSn has an internal pull-up resistor and must be externally pulled low (Rext ≤ 5kΩ). If Csn is low at power-up, the incremental outputs (A, B, Index) will be high until the internal offset compensation is finished. This unique state (A=B=Index = high) may be used as an indicator for the external controller to shorten the waiting time at power-up. Instead of waiting for the specified maximum power up-time (0), the controller can start requesting data from the AS5040 as soon as the state (A=B=Index = high) is cleared. CSn = high or open at power-up: In this mode, the incremental outputs (A, B, Index) will remain at logic high state, until CSn goes low or a low pulse is applied at CSn. This mode allows intentional disabling of the incremental outputs until for example the system microcontroller is ready to receive data. Incremental Output Hysteresis To avoid flickering incremental outputs at a stationary magnet position, a hysteresis is introduced. In case of a rotational direction change, the incremental outputs have a hysteresis of 2 LSB. Regardless of the programmed incremental resolution, the hysteresis of 2 LSB always corresponds to the highest resolution of 10 bit. In absolute terms, the hysteresis is set to 0.704 degrees for all resolutions. For constant rotational directions, every magnet position change is indicated at the incremental outputs (see Figure 9). If for example the magnet turns clockwise from position „x+3“ to „x+4“, the incremental output would also indicate this position accordingly. A change of the magnet’s rotational direction back to position „x+3“ means, that the incremental output still remains unchanged for the duration of 2 LSB, until position „x+2“ is reached. Following this direction, the incremental outputs will again be updated with every change of the magnet position. www.austriamicrosystems.com Revision 2.10 13 - 33 AS5040 Data Sheet Figure 9: Hysteresis Window for Incremental Outputs Incremental Output Indication X +4 X +3 X +2 X +1 X X Hysteresis: 0.7° X +1 X +2 X +3 X +4 X +5 Clockwise Direction Magnet Position Counterclockwise Direction 9 Pulse Width Modulation (PWM) Output The AS5040 provides a pulse width modulated output (PWM), whose duty cycle is proportional to the measured angle: Position = t on ⋅ 1025 (ton + toff ) − 1 The PWM frequency is internally trimmed to an accuracy of ±5% (±10% over full temperature range). This tolerance can be cancelled by measuring the complete duty cycle as shown above. Figure 10: PWM Output Signal Angle 0 deg (Pos 0) PW MIN 1µs 1025µs PW MAX 359.65 deg (Pos 1023) 1024µs 1 /fPWM www.austriamicrosystems.com Revision 2.10 14 - 33 AS5040 Data Sheet Table 5: PWM Signal Parameters P arameter PWM frequency MIN pulse width MAX pulse width S ymbol fPWM PWMIN PWMAX T yp 0.9756 1 1024 U nit kHz µs µs Signal period: 1025µs - Position 0d - Angle 0 deg - Position 1023d - Angle 359,65 deg N ote 10 Analog Output An analog output may be generated by averaging the PWM signal, using an external active or passive lowpass filter. The analog output voltage is proportional to the angle: 0°= 0V; 360° = VDD5V. Using this method, the AS5040 can be used as direct replacement of potentiometers. Figure 11: Simple Passive 2nd Order Lowpass Filter R1 R2 analog out Pin12 PWM VDD2 C1 C2 Pin7 VSS 0V2 0° 3 60° R1,R2 ≥ 4k7 C1,C2 ≥ 1µF / 6V R1 should be ≥4k7 to avoid loading of the PWM output. Larger values of Rx and Cx will provide better filtering and less ripple, but will also slow down the response time. 11 Brushless DC Motor Commutation Mode Brushless DC motors require angular information for stator commutation. The AS5040 provides U-V-W commutation signals for one and two pole pair motors. In addition to the three-phase output signals, the step (LSB) output at pin 12 allows high accuracy speed measurement. Two resolutions (9 or 10 bit) can be selected by programming Div0 according to Table 6. Mode 3.0 (3.1) is used for brush-less DC motors with one-pole pair rotors. The three phases (U, V, W) are 120 degrees apart, each phase is 180 degrees on and 180 degrees off. Mode 3.2 (3.3) is used for motors with two pole pairs requiring a higher pulse count to ensure a proper current commutation. In this case the pulse width is 256 positions, equal to 90 degrees. The precise physical angle at which the U, V and W signals change state (“Angle” in Figure 12 and Figure 13) is calculated by multiplying each transition position by the angular value of 1 count: Angle [deg] = Position x (360 degree / 1024) www.austriamicrosystems.com Revision 2.10 15 - 33 AS5040 Data Sheet Figure 12: U, V and V-signals for BLDC Motor Commutation (Div1=0, Div0=0) C ommutation - Mode 3.0 Width: 512 Steps ( One-pole-pair) Width: 512 Steps U V W CW Direction Position: Angle: 0 0.0 171 60.12 341 119.88 512 180.0 683 240.12 853 299.88 0 360.0 Figure 13: U, V and W-signals for 2-pole BLDC Motor Commutation (Div1=1; Div0=0) C ommutation - Mode 3.2 Width: 256 Steps ( Two-pole-pairs) Width: 256 Steps U V W CW Direction Position: Angle: 0 0.0 85 29.88 171 60.12 256 90.0 341 119.88 427 150.12 512 180.0 597 209.88 683 240.12 768 270.00 853 299.88 939 330.12 0 360.0 12 Programming the AS5040 After power-on, programming the AS5040 is enabled with the rising edge of CSn with Prog = high and CLK = low. 16 bit configuration data must be serially shifted into the OTP register via the Prog-pin. The first “CCW” bit is followed by the zero position data (MSB first) and the incremental mode setting as shown in Table 6. Data must be valid at the rising edge of CLK (see Figure 14). After writing data into the OTP register it can be permanently programmed by rising the Prog pin to the programming voltage VPROG. 16 CLK pulses (tPROG) must be applied to program the fuses (Figure 15). To exit the programming mode, the chip must be reset by a power-on-reset. The programmed data is available after the next power-up. Note: During the programming process, the transitions in the programming current may cause high voltage spikes generated by the inductance of the connection cable. To avoid these spikes and possible damage to the IC, the connection wires, especially the signals Prog and VSS must be kept as short as possible. The maximum wire length between the VPROG switching transistor and pin Prog (see Figure 16) should not exceed 50mm (2 inches). To suppress eventual voltage spikes, a 10nF ceramic capacitor should be connected close to pins Prog and VSS. This capacitor is only required for programming, it is not required for normal operation. The clock timing tclk must be selected at a proper rate to ensure that the signal Prog is stable at the rising edge of CLK (see Figure 14). Additionally, the programming supply voltage should be buffered with a 10µF capacitor mounted close to the switching transistor. This capacitor aids in providing peak currents during programming. The specified programming voltage at pin Prog is 7.3 – 7.5V (see section 0). To compensate for the voltage drop across the VPROG switching transistor, the applied programming voltage may be set slightly higher (7.5 - 8.0V, see Figure 16). www.austriamicrosystems.com Revision 2.10 16 - 33 AS5040 Data Sheet OTP Register Contents: CCW Counter Clockwise Bit ccw=0 – angular value increases in clockwise direction ccw=1 – angular value increases in counterclockwise direction Z [9:0] Indx Div1,Div0 Md1, Md0 Programmable Zero / Index Position Index Pulse Width Selection: 1LSB / 3LSB Divider Setting of Incremental Output Incremental Output Mode Selection OTP Default Setting The AS5040 can also be operated without programming. The default, un-programmed setting is shown in Table 6 (Mode 0.0): CCW: 0 = clockwise operation Z9 to Z0: 00 = no programmed zero position Indx: 0 = Index bit width = 1LSB Div0,Div1 : 00 = incremental resolution = 10bit Md0, MD1: 00 = incremental mode = quadrature Figure 14: Programming Access – Write Data (section of Figure 15) Figure 15: Complete Programming Sequence Write Data CSn Programming Mode Power Off Prog CLKPROG Data 1 16 7.5V VDD VProgOff 0V tLoad PROG tPrgH tPrgR tPROG tPROG finished www.austriamicrosystems.com Revision 2.10 17 - 33 AS5040 Data Sheet Figure 16: OTP Programming Connection of AS5040 (shown with AS5040 demoboard) Incremental Mode Programming Three different incremental output modes are available. Mode: Md1=0 / Md0=1 sets the AS5040 in quadrature mode. Mode: Md1=1 / Md0=0 sets the AS5040 in step / direction mode (see Table 1) In both modes, the incremental resolution may be reduced from 10 bit down to 9, 8 or 7 bit using the divider OTP bits Div1 and Div0. (see Table 6 below ). Mode: Md1=1 / Md0=1 sets the AS5040 in brushless DC motor commutation mode with an additional LSB incremental signal at pin 12 (PWM_LSB). To allow programming of all bits, the default factory setting is all bits = 0. This mode is equal to mode 1:0 (quadrature A/B, 1LSB index width, 256ppr). The absolute angular output value, by default, increases with clockwise rotation of the magnet (top view). Setting the CCW-bit (see Figure 14) allows reversing the indicated direction, e.g. when the magnet is placed underneath the IC: CCW = 0 – angular value increases clockwise; CCW = 1 – angular value increases counterclockwise. By default, the zero / index position pulse is one LSB wide. It can be increased to a three LSB wide pulse by setting the Index-bit of the OTP register. Further programming options (commutation modes) are available for brushless DC motor-control. Md1 = Md0 = 1 changes the incremental output pins 3, 4 and 6 to a 3-phase commutation signal. Div1 defines the number of pulses per revolution for either a two-pole (Div1=0) or four-pole (Div1=1) rotor. In addition, the LSB is available at pin 12 (the LSB signal replaces the PWM signal), which allows for high rotational speed measurement of up to 30,000 rpm. www.austriamicrosystems.com Revision 2.10 USB 18 - 33 AS5040 Data Sheet Table 6: One Time Programmable (OTP) Register Options Mode Md1 Default (Mode0.0) quadAB-Mode1.0 quadAB-Mode1.1 quadAB-Mode1.2 quadAB-Mode1.3 quadAB-Mode1.4 quadAB-Mode1.5 quadAB-Mode1.6 quadAB-Mode1.7 Step/Dir-Mode2.0 Step/Dir-Mode2.1 Step/Dir -Mode2.2 Step/Dir -Mode2.3 Step/Dir -Mode2.4 Step/Dir -Mode2.5 Step/Dir -Mode2.6 Step/Dir -Mode2.7 CommutationMode3.0 CommutationMode3.1 CommutationMode3.2 CommutationMode3.3 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 OTP-Mode-Register-Bit Md0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 Div1 0* 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 Div0 0* 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 Index 0* 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 U(0º) 0 0 0 U’ (0º, 180º) V’ (60º, 240º) Pin # 3 4 6 1LSB 1LSB 3LSBs 1LSB A B 3LSBs 1LSB 3LSBs 1LSB 3LSBs 1LSB 3LSBs 1LSB LSB Dir 3LSBs 1LSB 3LSBs 1LSB 3LSBs PWM 10 bit PWM 10 bit 12 Pulses per Revolution ppr 2x256 Incremental Resolution bit 10 2x128 2x64 2x32 512 256 128 64 9 8 7 10 9 8 7 10 V(120º) W(240º) LSB 3x1 9 10 W’ (120º, 300º) LSB 2x3 9 Note: Div1, Div0 and Index cannot be programmed in Mode 0:0 Zero Position Programming Zero position programming is an OTP option that simplifies assembly of a system, as the magnet does not need to be manually adjusted to the mechanical zero position. Once the assembly is completed, the mechanical and electrical zero positions can be matched by software. Any position within a full turn can be defined as the permanent new zero/index position. For zero position programming, the magnet is turned to the mechanical zero position (e.g. the “off”-position of a rotary switch) and the actual angular value is read. This value is written into the OTP register bits Z9:Z0 (see Figure 14) and programmed as described in section 12. This new absolute zero position is also the new Index pulse position for incremental output modes. Note: The zero position value may also be modified before programming, e.g. to program an electrical zero position that is 180° (half turn) from the mechanical zero position, just add 512 to the value read at the mechanical zero position and program the new value into the OTP register. www.austriamicrosystems.com Revision 2.10 19 - 33 AS5040 Data Sheet Repeated OTP Programming Although a single AS5040 OTP register bit can be programmed only once (from 0 to 1), it is possible to program other, unprogrammed bits in subsequent programming cycles. However, a bit that has already been programmed should not be programmed twice. Therefore it is recommended that bits that are already programmed are set to “0” during a programming cycle. Non-permanent Programming It is also possible to re-configure the AS5040 in a non-permanent way by overwriting the OTP register. This procedure is essentially a “Write Data” sequence (see Figure 14) without a subsequent OTP programming cycle. The “Write Data” sequence may be applied at any time during normal operation. This configuration remains set while the power supply voltage is above the power-on reset level (see 0). See Application Note AN5000-20 for further information. Analog Readback Mode Non-volatile programming (OTP) uses on-chip zener diodes, which become permanently low resistive when subjected to a specified reverse current. The quality of the programming process depends on the amount of current that is applied during the programming process (up to 130mA). This current must be provided by an external voltage source. If this voltage source cannot provide adequate power, the zener diodes may not be programmed properly. In order to verify the quality of the programmed bits, an analog level can be read for each zener diode, giving an indication whether this particular bit was properly programmed or not. To put the AS5040 in analog readback mode, a digital sequence must be applied to pins CSn, Prog and CLK as shown in Figure 17. The digital level for this pin depends on the supply configuration (3.3V or 5V; see section 14). The second rising edge on CSn (OutpEN) changes pin Prog to a digital output and the log. high signal at pin Prog must be removed to avoid collision of outputs (grey area in Figure 17). The following falling slope of CSn changes pin Prog to an analog output, providing a reference voltage Vref, that must be saved as a reference for the calculation of the subsequent programmed and unprogrammed OTP bits. Following this step, each rising slope of CLK outputs one bit of data in the reverse order as during programming. (see Figure 17: Md0-MD1-Div0,Div1-Indx-Z0…Z9, ccw) During analog readback, the capacitor at pin Prog (see Figure 16) should be removed to allow a fast readout rate. . If the capacitor is not removed the analog voltage will take longer to stabilize due to the additional capacitance. The measured analog voltage for each bit must be subtracted from the previously measured Vref, and the resulting value gives an indication on the quality of the programmed bit: a reading of 1V indicates a properly unprogrammed bit. A reading between 100mV and 1V indicates a faulty bit, which may result in an undefined digital value, when the OTP is read at power-up. Following the 16th clock (after reading bit “ccw”), the chip must be reset by disconnecting the power supply. Figure 17: OTP Register Analog Read P ro g E N CSn V re f P ro g I n te rn a l te s t b it d ig ita l O u tp E N A n a lo g R e a d b a c k D a ta a t P ro g P o w e r-o n R e se t; tu rn o ff s u p p ly V p ro g ra m m e d M d 0 M d 1 D iv 0 D iv1 V u n p ro g ra m m e d Z 5 1 Z6 Z7 Z8 Z9 ccw 16 C L K A re a d P ro g c h a n g e s to O u tp u t CLK t L o a d P ro g www.austriamicrosystems.com Revision 2.10 20 - 33 AS5040 Data Sheet 13 Alignment Mode The alignment mode simplifies centering the magnet over the chip to gain maximum accuracy and XY-alignment tolerance. This electrical centering method allows a wider XY-alignment tolerance (0.485mm radius) than mechanical centering (0.25mm radius) as it eliminates the placement tolerance of the die within the IC package (+/- 0.235mm). Alignment mode can be enabled with the falling edge of CSn while Prog = logic high (Figure 18). The Data bits D9-D0 of the SSI change to a 10-bit displacement amplitude output. A high value indicates large X or Y displacement, but also higher absolute magnetic field strength. The magnet is properly aligned, when the difference between highest and lowest value over one full turn is at a minimum. Under normal conditions, a properly aligned magnet will result in a reading of less than 32 over a full turn. The MagINCn and MagDECn indicators will be = 1 when the alignment mode reading is < 32. At the same time, both hardware pins MagINCn (#1) and MagDECn (#2) will be pulled to VSS. A properly aligned magnet will therefore produce a MagINCn = MagDECn = 1 signal throughout a full 360° turn of the magnet. Stronger magnets or short gaps between magnet and IC may show values larger than 32. These magnets are still properly aligned as long as the difference between highest and lowest value over one full turn is at a minimum. The alignment mode can be reset to normal operation mode by a power-on-reset (disconnect / re-connect power supply). Figure 18: Enabling the Alignment Mode Prog AlignMode enable CSn Read-out via SSI 2µs 2µs min. min. 14 3.3V / 5V Operation The AS5040 operates either at 3.3V ±10% or at 5V ±10%. This is made possible by an internal 3.3V Low-Dropout (LDO) voltage regulator. The internal supply voltage is always taken from the output of the LDO, meaning that the internal blocks are always operating at 3.3V. For 3.3V operation, the LDO must be bypassed by connecting VDD3V3 with VDD5V (see Figure 19). For 5V operation, the 5V supply is connected to pin VDD5V, while VDD3V3 (LDO output) must be buffered by a 2.2...10µF capacitor, which is supposed to be placed close to the supply pin (see Figure 19). The VDD3V3 output is intended for internal use only It must not be loaded with an external load. The output voltage of the digital interface I/O’s corresponds to the voltage at pin VDD5V, as the I/O buffers are supplied from this pin (see Figure 19). www.austriamicrosystems.com Revision 2.10 21 - 33 AS5040 Data Sheet Figure 19: Connections for 5V / 3.3V Supply Voltages 5V Operation 2.2...10µF 3.3V Operation VDD3V3 VDD3V3 100n 100n VDD5V LDO Internal VDD DO VDD5V LDO Internal VDD DO 4.5 - 5.5V I N T E R F A C E PWM_LSB CLK CSn A_LSB_U B_Dir_V Index_W Prog VSS 3.0 - 3.6V I N T E R F A C E PWM_LSB CLK CSn A_LSB_U B_Dir_V Index_W Prog VSS A buffer capacitor of 100nF is recommended in both cases close to pin VDD5V. Note that pin VDD3V3 must always be buffered by a capacitor. It must not be left floating, as this may cause an instable internal 3.3V supply voltage which may lead to larger than normal jitter of the measured angle. 15 Choosing the Proper Magnet Typically the magnet should be 6mm in diameter and ≥2.5mm in height. Magnetic materials such as rare earth AlNiCo, SmCo5 or NdFeB are recommended. The magnet’s field strength perpendicular to the die surface should be verified using a gauss-meter. The magnetic field Bv at a given distance, along a concentric circle with a radius of 1.1mm (R1), should be in the range of ±45mT…±75mT. (see Figure 20). www.austriamicrosystems.com Revision 2.10 22 - 33 AS5040 Data Sheet Figure 20: Typical Magnet and Magnetic Field Distribution typ. 6mm diameter N S Magnet axis R1 Vertical field component Bv (45…75mT) Magnet axis Vertical field component 0 360 N S R1 concentric circle; radius 1.1mm Physical Placement of the Magnet The best linearity can be achieved by placing the center of the magnet exactly over the defined center of the IC package as shown in Figure 21: Figure 21: Defined IC Center and Magnet Displacement Radius 3.9 mm 1 3.9 mm 2.433 mm Defined center Rd 2.433 mm Area of recommended maximum magnet misalignment Magnet Placement The magnet’s center axis should be aligned within a displacement radius Rd of 0.25mm from the defined center of the IC with reference to the edge of pin #1 (see Figure 21). This radius includes the placement tolerance of the chip within the SSOP-16 package (+/- 0.235mm). The displacement radius Rd is 0.485mm with reference to the center of the chip (see section 13: Alignment Mode) www.austriamicrosystems.com Revision 2.10 23 - 33 AS5040 Data Sheet The vertical distance should be chosen such that the magnetic field on the die surface is within the specified limits (see Figure 20). The typical distance “z” between the magnet and the package surface is 0.5mm to 1.8mm with the recommended magnet (6mm x 2.5mm). Larger gaps are possible, as long as the required magnetic field strength stays within the defined limits. A magnetic field outside the specified range may still produce usable results, but the out-of-range condition will be indicated by MagINCn (pin 1) and MagDECn (pin 2), see Table 3. Figure 22: Vertical Placement of the Magnet N Die surface S Package surface z 0.576mm ± 0.1mm 1.282mm ± 0.15mm 16 Simulation Modelling Figure 23: Arrangement of Hall Sensor Array on Chip (principle) With reference to Figure 23, a diametrically magnetized permanent magnet is placed above or below the surface of the AS5040. The chip uses an array of Hall sensors to sample the vertical vector of a magnetic field distributed across the device package surface. The area of magnetic sensitivity is a circular locus of 1.1mm radius with respect to the center of the die. The Hall sensors in the area of magnetic sensitivity are grouped and configured such that orthogonally related components of the magnetic fields are sampled differentially. The differential signal Y1-Y2 will give a sine vector of the magnetic field. The differential signal X1-X2 will give an orthogonally related cosine vector of the magnetic field. www.austriamicrosystems.com Revision 2.10 24 - 33 AS5040 Data Sheet The angular displacement (Θ) of the magnetic source with reference to the Hall sensor array may then be modelled by: Θ = arctan (Y 1 − Y 2) ± 0.5° ( X 1 − X 2) The ±0.5° angular error assumes a magnet optimally aligned over the center of the die and is a result of gain mismatch errors of the AS5040. Placement tolerances of the die within the package are ±0.235mm in X and Y direction, using a reference point of the edge of pin #1 (Figure 23). In order to neglect the influence of external disturbing magnetic fields, a robust differential sampling and ratiometric calculation algorithm has been implemented. The differential sampling of the sine and cosine vectors removes any common mode error due to DC components introduced by the magnetic source itself or external disturbing magnetic fields. A ratiometric division of the sine and cosine vectors removes the need for an accurate absolute magnitude of the magnetic field and thus accurate Z-axis alignment of the magnetic source. The recommended differential input range of the magnetic field strength (B(X1-X2),B(Y1-Y2)) is ±75mT at the surface of the die. In addition to this range, an additional offset of ±5mT, caused by unwanted external stray fields is allowed. The chip will continue to operate, but with degraded output linearity, if the signal field strength is outside the recommended range. Too strong magnetic fields will introduce errors due to saturation effects in the internal preamplifiers. Too weak magnetic fields will introduce errors due to noise becoming more dominant. 17 Failure Diagnostics The AS5040 also offers several diagnostic and failure detection features: Magnetic Field Strength Diagnosis By software: the MagINCn and MagDECn status bits will both be high when the magnetic field is out of range. By hardware: Pins #1 (MagINCn) and #2 (MagDECn) are open-drain outputs and will both be turned on (= low with external pull-up resistor) when the magnetic field is out of range. If only one of the outputs is low, the magnet is either moving towards the chip (MagINCn) or away from the chip (MagDECn). Power Supply Failure Detection By software: If the power supply to the AS5040 is interrupted, the digital data read by the SSI will be all “0”s. Data is only valid, when bit OCF is high, hence a data stream with all “0”s is invalid. To ensure adequate low levels in the failure case, a pull-down resistor (~10kΩ) should be added between pin DO and VSS at the receiving side. By hardware: The MagINCn and MagDECn pins are open drain outputs and require external pull-up resistors. In normal operation, these pins are high ohmic and the outputs are high (see Table 3). In a failure case, either when the magnetic field is out of range or the power supply is missing, these outputs will become low. To ensure adequate low levels in case of a broken power supply to the AS5040, the pull-up resistors (>10kΩ) from each pin must be connected to the positive supply at pin 16 (VDD5V). By hardware: PWM output: The PWM output is a constant stream of pulses with 1kHz repetition frequency. In case of power loss, these pulses are missing. By hardware: Incremental outputs: In normal operation, pins A(#3), B(#4) and Index (#6) will never be high at the same time, as Index is only high when A=B=low. However, after a power-on-reset, if VDD is powered up or restarts after a power supply interruption, all three outputs will remain in high state until pin CSn is pulled low. If CSn is already tied to VSS during power-up, the incremental outputs will all be high until the internal offset compensation is finished (within tPwrUp). www.austriamicrosystems.com Revision 2.10 25 - 33 AS5040 Data Sheet 18 Angular Output Tolerances Accuracy Accuracy is defined as the error between measured angle and actual angle. It is influenced by several factors: the non-linearity of the analog-digital converters, internal gain and mismatch errors, non-linearity due to misalignment of the magnet As a sum of all these errors, the accuracy with centered magnet = (Errmax – Errmin)/2 is specified as better than ±0.5 degrees @ 25°C (see Figure 25). Misalignment of the magnet further reduces the accuracy. Figure 24 shows an example of a 3D-graph displaying nonlinearity over XY-misalignment. The center of the square XY-area corresponds to a centered magnet (see dot in the center of the graph). The X- and Y- axis extends to a misalignment of ±1mm in both directions. The total misalignment area of the graph covers a square of 2x2 mm (79x79mil) with a step size of 100µm. For each misalignment step, the measurement as shown in Figure 25 is repeated and the accuracy (Errmax – Errmin)/2 (e.g. 0.25° in Figure 25) is entered as the Z-axis in the 3D-graph. Figure 24: Example of Linearity Error over XY Misalignment Linearity Error over XY-misalignment [°] 6 5 4 ° 3 2 1 0 1000 800 600 1000 800 600 400 200 0 -200 -400 400 -600 200 -200 -800 -400 -600 -1000 -800 -1000 0 x y The maximum non-linearity error on this example is better than ±1 degree (inner circle) over a misalignment radius of ~0.7mm. For volume production, the placement tolerance of the IC within the package (±0.235mm) must also be taken into account. The total nonlinearity error over process tolerances, temperature and a misalignment circle radius of 0.25mm is specified better than ±1.4 degrees. The magnet used for this measurement was a cylindrical NdFeB (Bomatec® BMN-35H) magnet with 6mm diameter and 2.5mm in height. www.austriamicrosystems.com Revision 2.10 26 - 33 AS5040 Data Sheet Figure 25: Example of Linearity Error over 360° linearity error with centered magnet [degrees] 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 1 55 109 163 217 271 325 379 433 487 541 595 649 703 757 811 865 919 973 Errmi Errmax transition noise Transition Noise Transition noise is defined as the jitter in the transition between two steps. Due to the nature of the measurement principle (Hall sensors + Preamplifier + ADC), there is always a certain degree of noise involved. This transition noise voltage results in an angular transition noise at the outputs. It is specified as 0.12 degrees rms (1 sigma)*1. This is the repeatability of an indicated angle at a given mechanical position. The transition noise has different implications on the type of output that is used: Absolute output; SSI interface: The transition noise of the absolute output can be reduced by the user by applying an averaging of readings. An averaging of 4 readings will reduce the transition noise by 6dB or 50%, e.g. from 0.12°rms to 0.06°rms (1 sigma). PWM interface: If the PWM interface is used as an analog output by adding a low pass filter, the transition noise can be reduced by lowering the cutoff frequency of the filter. If the PWM interface is used as a digital interface with a counter at the receiving side, the transition noise may again be reduced by averaging of readings. Incremental mode: In incremental mode, the transition noise influences the period, width and phase shift of the output signals A, B and Index. However, the algorithm used to generate the incremental outputs guarantees no missing or additional pulses even at high speeds (up to 30,000 rpm and higher) *1 : statistically, 1 sigma represents 68.27% of readings, 3 sigma represents 99.73% of readings. www.austriamicrosystems.com Revision 2.10 27 - 33 AS5040 Data Sheet High Speed Operation Sampling Rate The AS5040 samples the angular value at a rate of 10.42k samples per second. Consequently, the incremental, as well as the absolute outputs are updated each 96µs. At a stationary position of the magnet, this sampling rate creates no additional error. Absolute Mode with Serial Communication: With the given sampling rate of 10.4 kHz, the number of samples (n) per turn for a magnet rotating at high speed can be calculated by: n= 60 rpm ⋅ 96 μs In practice, there is no upper speed limit. The only restriction is that there will be fewer samples per revolution as the speed increases. Regardless of the rotational speed, the absolute angular value is always sampled at the highest resolution of 10 bit. Likewise, for a given number of samples per revolution (n), the maximum speed can be calculated by: rpm = 60 n ⋅ 96 μs In absolute mode with serial communication, 610 rpm is the maximum speed, where 1024 readings per revolution can be obtained. In incremental mode, the maximum error caused by the sampling rate of the ADCs is 0/+96µs. It has a peak of 1LSB = 0.35° at 610 rpm. At higher speeds this error is reduced again due to interpolation and the output delay remains at 192µs as the DSP requires two sampling periods (2x96µs) to synthesize and redistribute any missing pulses. Absolute Mode with PWM: The principle is the same as with the serial communication. The PWM output is refreshed with a rate of 1.025ms, the number of samples (n) per turn for a magnet rotating at high speed can be calculated by: n= 60 rpm ⋅1.025ms In absolute mode with PWM output, 57 rpm is the maximum speed, where 1024 readings per revolution can be obtained. Incremental Mode: Incremental encoders are usually required to produce no missing pulses up to several thousand rpm’s. Therefore, the AS5040 has a built-in interpolator, which ensures that there are no missing pulses at the incremental outputs for rotational speeds of up to 30,000 rpm, even at the highest resolution of 10 bits (512 pulses per revolution). Table 7: Speed Performance A bsolute Output Mode 610rpm = 1024 samples / turn 1220rpm = 512 samples / turn 2441rpm = 256 samples / turn etc… I ncremental Output Mode no missing pulses @ 10 bit resolution (512ppr): max. speed = 30,000 rpm Propagation Delays The propagation delay is the delay between the time that a sample is taken until it is converted and available as angular data. This delay is 48µs for the absolute interface and 192µs for the incremental interface. Using the SSI interface for absolute data transmission, an additional delay must be considered, caused by the asynchronous sampling (t= 0…1/fs) and the time it takes the external control unit to read and process the data. www.austriamicrosystems.com Revision 2.10 28 - 33 AS5040 Data Sheet Angular Error Caused by Propagation Delay A rotating magnet will therefore cause an angular error caused by the output delay. This error increases linearly with speed: esampling = rpm ∗ 6 * prop.delay w here: e sampling r pm p rop.delay = a ngular error [°] = r otating speed [rpm] = p ropagation delay [seconds] Note: since the propagation delay is known, it can be automatically compensated by the control unit that is processing the data from the AS5040, thus reducing the angular error caused by speed. Internal Timing Tolerance The AS5040 does not require an external ceramic resonator or quartz. All internal clock timings for the AS5040 are generated by an on-chip RC oscillator. This oscillator is factory trimmed to ±5% accuracy at room temperature (±10% over full temperature range). This tolerance influences the ADC sampling rate and the pulse width of the PWM output: Absolute output; SSI interface: A new angular value is updated every 100µs (typ.) Incremental outputs: the incremental outputs are updated every 100µs (typ.) PWM output: A new angular value is updated every 100µs (typ.). The PWM pulse timings Ton and Toff also have the same tolerance as the internal oscillator. If only the PWM pulse width Ton is used to measure the angle, the resulting value also has this timing tolerance. However, this tolerance can be cancelled by measuring both Ton and Toff and calculating the angle from the duty cycle (see section 9): Position = t on ⋅1025 (ton + toff ) − 1 Temperature Magnetic Temperature Coefficient One of the major benefits of the AS5040 compared to linear Hall sensors is that it is much less sensitive to temperature. While linear Hall sensors require a compensation of the magnet’s temperature coefficient, the AS5040 automatically compensates for the varying magnetic field strength over temperature. The magnet’s temperature drift does not need to be considered, as the AS5040 operates with magnetic field strengths from ±45…±75mT. Example: A NdFeB magnet has a field strength of 75mT @ –40°C and a temperature coefficient of -0.12% per Kelvin. The temperature change is from –40° to +125° = 165K. The magnetic field change is: 165 x -0.12% = -19.8%, which corresponds to 75mT at –40°C and 60mT at 125°C. The AS5040 can compensate for this temperature related field strength change automatically, no user adjustment is required. Accuracy over Temperature The influence of temperature in the absolute accuracy is very low. While the accuracy is ≤ ±0.5° at room temperature, it may increase to ≤±0.9° due to increasing noise at high temperatures. www.austriamicrosystems.com Revision 2.10 29 - 33 AS5040 Data Sheet Timing Tolerance over Temperature The internal RC oscillator is factory trimmed to ±5%. Over temperature, this tolerance may increase to ±10%. Generally, the timing tolerance has no influence in the accuracy or resolution of the system, as it is used mainly for internal clock generation. The only concern to the user is the width of the PWM output pulse, which relates directly to the timing tolerance of the internal oscillator. This influence however can be cancelled by measuring the complete PWM duty cycle (see Internal Timing Tolerance). www.austriamicrosystems.com Revision 2.10 30 - 33 AS5040 Data Sheet 19 Package Drawings and Markings Figure 26: 16-Lead Shrink Small Outline Package SSOP-16 AYWWIZZ AS5040 Dimensions Marking: AYWWIZZ mm Symbol Min A A1 A2 b c D E E1 e K L 0° 0.63 1.73 0.05 1.68 0.25 0.09 6.07 7.65 5.2 Typ 1.86 0.13 1.73 0.315 6.20 7.8 5.3 0.65 0.75 8° 0.95 0° .025 Max 1.99 0.21 1.78 0.38 0.20 6.33 7.9 5.38 Min .068 .002 .066 .010 .004 .239 .301 .205 Typ .073 .005 .068 .012 .244 .307 .209 .0256 .030 8° .037 Max .078 .008 .070 .015 .008 .249 .311 .212 Thermal Resistance Rth(j-a): typ. 151 K/W in still air, soldered on PCB IC's marked with a white dot or the letters "ES" denote Engineering Samples inch A: Pb-free Identifier Y: Last Digit of Manufacturing Year WW: Manufacturing Week I: Plant Identifier ZZ: Traceability Code JEDEC Package Outline Standard: MO - 150 AC www.austriamicrosystems.com Revision 2.10 31 - 33 AS5040 Data Sheet 20 Packing Options Delivery: Tape and Reel (1 reel = 2000 devices) Tubes (1 box = 100 tubes à 77 devices) for delivery in tubes for delivery in tape and reel Order # AS5040ASSU Order # AS5040ASST 21 Recommended PCB Footprint Recommended Footprint Data A B C D E mm 9.02 6.16 0.46 0.65 5.01 inch 0.355 0.242 0.018 0.025 0.197 www.austriamicrosystems.com Revision 2.10 32 - 33 AS5040 Data Sheet 22 Copyrights Copyright © 1997-2009, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. 23 Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com Revision 2.10 33 - 33