AS5043

A S5043 D ata Sheet - Pin Configuration AS5043 P rogrammable 360° Magnetic Angle Encoder with Absolute SSI and Analog Outputs 1 General Description The AS5043 is a contactless magnetic angle encoder for accurate measurement up to 360°. It is a system-on-chip, combining integrated Hall elements, analog front end and digital signal processing in a single device. The AS5043 provides a digital 10-bit as well as a programmable analog output that is directly proportional to the angle of a magnet, rotating over the chip. The analog output can be configured in many ways, including user programmable angular range, adjustable output voltage range, voltage or current output, etc.. An internal voltage regulator allows operation of the AS5043 from 3.3V or 5.0V supplies. Data Sheet 3 Key Features 360° contactless high resolution angular position encoding User programmable zero position Two 10-bit absolute outputs: Serial digital interface and Versatile analog output programmable angular range up to 360° programmable ratiometric output voltage range Failure detection mode for magnet field strength and loss of power supply Serial read-out of multiple interconnected AS5043 devices using daisy chain mode Mode input for optimizing noise vs. speed Alignment mode for magnet placement guidance Wide temperature range: - 40°C to + 125°C Small package: SSOP 16 (5.3mm x 6.2mm) 2 Benefits Complete system-on-chip Flexible system solution provides absolute output, both digital and analog Angle measurement with software programmable range up to 360° High reliability due to non-contact magnetic sensing Ideal for applications in harsh environments Robust system, tolerant to magnet misalignment, airgap variations, temperature variations and external magnetic fields No calibration required 4 Applications The AS5043 is ideal for applications with an angular travel range from a few degrees up to a full turn of 360°, such as - Industrial applications: - Contactless rotary position sensing - Robotics - Valve Controls - Automotive applications: - Throttle position sensors - Gas / brake pedal position sensing - Headlight position control Front panel rotary switches Replacement of potentiometers Figure 1: Typical Arrangement of AS5043 and Magnet www.austriamicrosystems.com Revision 1.80 1 – 36 A S5043 D ata Sheet - Pin Configuration 5 Pin Configuration Figure 2: AS5043 Pin Configuration SSOP16 MagRngn Mode CSn CLK NC DO VSS Prog_DI 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD5V VDD3V3 NC NC Vout FB DACout DACref Package = SSOP16 (16 lead Shrink Small Outline Package) Table 1: Pin Description SSOP16 Pin Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type Description Magnet Field Magnitude RaNGe warning; active low, indicates that the magnetic field strength is outside of the recommended limits. Mode input. Select between low noise (low, connect to VSS) and high speed (high, connect to VDD5V) mode at power up. Internal pull-down resistor. Chip Select, active low; Schmitt-Trigger input, internal pull-up resistor (~50kΩ) Clock Input of Synchronous Serial Interface; Schmitt-Trigger input must be left unconnected Data Output of Synchronous Serial Interface Negative Supply Voltage (GND) OTP Programming Input and Data Input for Daisy Chain mode. Internal pull-down resistor (~74kΩ). Should be connected to VSS if programming is not used DAC Reference voltage input for external reference DAC output (unbuffered, Ri ~8kΩ) Feedback, OPAMP inverting input OPAMP output Must be left unconnected Must be left unconnected 3V-Regulator Output for internal core, regulated from VDD5V.Connect to VDD5V for 3V supply voltage. Do not load externally. Positive Supply Voltage, 3.0 to 5.5 V MagRngn DO_OD Mode CSn CLK NC DO VSS Prog_DI DACref DACout FB Vout NC NC VDD3V3 VDD5V DI_PD, ST DI_PU, ST DI,ST DO_T S DI_PD AI AO AI AO S S DO_OD digital output open drain DI_PD digital input pull-down DI_PU digital input pull-up S DO_T ST supply pin digital output /tri-state Schmitt-trigger input AI AO DI analog input analog output digital input www.austriamicrosystems.com Revision 1.80 2 – 36 A S5043 D ata Sheet - Pin Configuration 5.1 Pin Description Pins 7, 15 and 16 are supply pins, pins 5, 13 and 14 are for internal use and must be left open. Pin 1 is the magnetic field strength indicator, MagRNGn. It is an open-drain output that is pulled to VSS when the magnetic field is out of the recommended range (45mT to 75mT). The chip will still continue to operate, but with reduced performance, when the magnetic field is out of range. When this pin is low, the analog output at pins #10 and #12 will be 0V to indicate the out-of-range condition. Pin 2 MODE allows switching between filtered (slow) and unfiltered (fast mode). This pin must be tied to VSS or VDD5V, and must not be switched after power up. See section 0. Pin 3 Chip Select (CSn; active low) selects a device for serial data transmission over the SSI interface. A “logic high” at CSn forces output DO to digital tri-state. Pin 4 CLK is the clock input for serial data transmission over the SSI interface (see section 1) Pin 6 DO (Data Out) is the serial data output during data transmission over the SSI interface (see section 1) Pin 8 PROG_DI is used to program the different operation modes, as well as the zero-position in the OTP register. This pin is also used as a digital input to shift serial data through the device in Daisy Chain Configuration, (see page 9). Pin 9 D ACref is the external voltage reference input for the Digital-to-Analog Converter (DAC). If selected, the analog output voltage on pin 12 (Vout) will be ratiometric to the voltage on this pin. Pin10 D ACout is the unbuffered output of the DAC. This pin may be used to connect an external OPAMP, etc. to the DAC. Pin 11 FB (Feedback) is the inverting input of the OPAMP buffer stage. Access to this pin allows various OPAMP configurations. Pin 12 Vout is the analog output pin. The analog output is a DC voltage, ratiometric to VDD5V (3.0 – 5.5V) or an external voltage source and proportional to the angle. www.austriamicrosystems.com Revision 1.80 3 – 36 A S5043 D ata Sheet – Functional Description 6 Functional Description The AS5043 is manufactured in a CMOS standard process and uses a spinning current Hall technology for sensing the magnetic field distribution across the surface of the chip. The integrated Hall elements are placed in a circle around the center of the device and deliver a voltage representation of the magnetic field perpendicular to the surface of the IC. Through Sigma-Delta Analog / Digital Conversion and Digital Signal-Processing (DSP) algorithms, the AS5043 provides accurate high-resolution absolute angular position information. For this purpose a Coordinate Rotation Digital Computer (CORDIC) calculates the angle and the magnitude of the Hall array signals. The DSP is also used indicate movements of the magnet towards or away from the chip and to indicate, when the magnetic field is outside of the recommended range (status bits = MagInc, MagDec; hardware pin = MagRngn). A small low cost diametrically magnetized (two-pole) standard magnet, centered over the chip, is used as the input device. The AS5043 senses the orientation of the magnetic field and calculates a 10-bit binary code. This code can be accessed via a Synchronous Serial Interface (SSI). In addition, the absolute angular representation is converted to an analog signal, ratiometric to the supply voltage. The analog output can be configured in many ways, such as 360°/180°/90° or 45° angular range, external or internal DAC reference voltage, 0-100%*VDD or 10-90% *VDD analog output range, external or internal amplifier gain setting. The various output modes as well as a user programmable zero position can be programmed in an OTP register. As long as no programming voltage is applied to pin PROG, the new setting may be overwritten at any time and will be reset to default when power is cycled. To make the setting permanent, the OTP register must be programmed by applying a programming voltage. The AS5043 is tolerant to magnet misalignment and unwanted external magnetic fields due to differential measurement technique and Hall sensor conditioning circuitry. It is also tolerant to airgap and temperature variations due to Sin-/Cos- signal evaluation. Figure 3: AS5043 Block Diagram MagRNGn Mode Sin Ang DO Cos Mag CSn CLK DACref 10 FB Vout + DACout Prog_DI www.austriamicrosystems.com Revision 1.80 4 – 36 A S5043 D ata Sheet – 3.3V / 5V Operation 7 3.3V / 5V Operation The AS5043 operates either at 3.3V ±10% or at 5V ±10%. This is made possible by an internal 3.3V Low-Dropout (LDO) Voltage regulator. The core supply voltage is always taken from the LDO output, as the internal blocks are always operating at 3.3V. For 3.3V operation, the LDO must be bypassed by connecting VDD3V3 with VDD5V (see Figure 4 ). For 5V operation, the 5V supply is connected to pin VDD5V, while VDD3V3 (LDO output) must be buffered by a 1...10µF capacitor, which should be placed close to the supply pin. The VDD3V3 output is intended for internal use only. It should not be loaded with an external load. The voltage levels of the digital interface I/O’s correspond to the voltage at pin VDD5V, as the I/O buffers are supplied from this pin (see Figure 4). Figure 4: Connections for 5V / 3.3V Supply Voltages A buffer capacitor of 100nF is recommended in both cases close to pin VDD5V. Note that pin VDD3V3 must always be buffered by a capacitor. It must not be left floating, as this may cause an instable internal 3.3V supply voltage which may lead to larger than normal jitter of the measured angle. www.austriamicrosystems.com Revision 1.80 5 – 36 A S5043 D ata Sheet – 10-bit Absolute Synchronous Serial Interface (SSI) 8 10-bit Absolute Synchronous Serial Interface (SSI) The serial data transmission timing is outlined in Figure 5: if CSn changes to logic low, Data Out (DO) will change from high impedance (tri-state) to logic high and the read-out sequence will be initiated. After a minimum time tCLK FE, data is latched into the output shift register with the first falling edge of CLK. Each subsequent rising CLK edge shifts out one bit of data. The serial word contains 16 bits, the first 10 bits are the angular information D[9:0], the subsequent 6 bits contain system information, about the validity of data such as OCF, COF, LIN, Parity and Magnetic Field status (increase / decrease / out of range) . A subsequent measurement is initiated by a logic “high” pulse at CSn with a minimum duration of tCSn. Data transmission may be terminated at any time by pulling CSn = high. 8.1 Serial Data Contents D9:D0 absolute angular position data (MSB is clocked out first). OCF (Offset Compensation Finished), logic high indicates that the Offset Compensation Algorithm has finished and data is valid. COF (Cordic Overflow), logic high indicates an out of range error in the CORDIC part. When this bit is set, the data at D9:D0 is invalid. The absolute output maintains the last valid angular value. This alarm may be resolved by bringing the magnet within the X-Y-Z tolerance limits. LIN (Linearity Alarm), logic high indicates that the input field generates a critical output linearity. When this bit is set, the data at D9:D0 may still be used, but may contain invalid data. This warning may be resolved by bringing the magnet within the X-Y-Z tolerance limits. Data D9:D0 is valid, when the status bits have the following configurations: Table 2: Status Bit Outputs OCF COF LIN Mag INC 0 1 0 0 0 1 Mag DEC 0 1 0 even checksum of bits 1:15 Parity MagInc, (Magnitude Increase) becomes HIGH, when the magnet is pushed towards the IC, thus the magnetic field strength is increasing. MagDec, (Magnitude Decrease) becomes HIGH, when the magnet is pulled away from the IC, thus the magnetic field strength is decreasing. Both signals HIGH indicate a magnetic field that is out of the allowed range (see Table 3). Note: Pin 1 (MagRngn) is a combination of MagInc and MagDec. It is active low via an open drain output and requires an external pull-up resistor. If the magnetic field is in range, this output is turned off. (logic “high”). Even Parity bit for transmission error detection of bits 1…15 (D9…D0, OCF, COF, LIN, MagInc, MagDec) The absolute angular output is always set to a resolution of 10 bit / 360°. Placing the magnet above the chip, angular values increase in clockwise direction by default. Figure 5: Synchronous Serial Interface with Absolute Angular Position Data CSn t CLK FE T CLK / 2 1 8 16 t CSn t CLK FE CLK 1 DO D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 OCF COF LIN Mag INC Mag DEC Even PAR D9 t DO active t DO valid Angular Position Data Status Bits t DO Tristate www.austriamicrosystems.com Revision 1.80 6 – 36 A S5043 D ata Sheet – 10-bit Absolute Synchronous Serial Interface (SSI) 8.2 Z-Axis Range Indication (Push Button Feature, Red/Yellow/Green Indicator) The AS5043 provides several options of detecting movement and distance of the magnet in the vertical (Z-) direction. Signal indicators MagINC, MagDEC and LIN are available as status bits in the serial data stream, while MagRngn is an open-drain output that indicates an out-of range status (on in YELLOW or RED range). Additionally, the analog output provides a safety feature in the form that it will be turned off when the magnetic field is too strong or too weak (RED range). The serial data is always available, the red/yellow/green status is indicated by the status bits as shown below: Table 3: Magnetic Field Strength Indicators SSI Status Bits Mag INC 0 0 1 1 Mag DEC 0 1 0 1 LIN 0 0 0 0 Hardware Pins Mag Rngn Off Off Off On Analog Output enabled enabled enabled enabled Description No distance change Magnetic Input Field OK (GREEN range, ~45…75mT) Distance increase, GREEN range; Pull-function. This state is dynamic and only active while the magnet is moving away from the chip. Distance decrease, GREEN range; Push- function. This state is dynamic and only active while the magnet is moving towards the chip. YELLOW Range: Magnetic field is ~ 25…45mT or ~75…135mT. The AS5043 may still be operated in this range, but with slightly reduced accuracy. RED Range: Magnetic field is ~~135mT. The analog output will be turned off in this range by default. It can be enabled permanently by OTP programming (see 11.1.2). It is still possible to use the absolute serial interface in the red range, but not recommended. 1 1 1 On disabled www.austriamicrosystems.com Revision 1.80 7 – 36 A S5043 D ata Sheet – Mode Input Pin 9 Mode Input Pin The absolute angular position is sampled at a rate of 10.4kHz (t=96µs) in fast mode and at a rate of 2.6kHz (t=384µs) in slow mode. These modes are selected by pin MODE (#2) during the power up of the AS5043. This pin activates or deactivates an internal filter, which is used to reduce the digital jitter and consequently the analog output noise. Activating the filter by pulling Mode = LOW reduces the transition noise to 90% VDD**) Broken positive power supply (VOUT pull down resistor at receiving side) Broken power supply ground (VOUT pull down resistor at receiving side) Broken positive power supply (VOUT pull up resistor at receiving side) Broken power supply ground (VOUT pull up resistor at receiving side) with pull down resistor at DO (receiving side), all bits read by the SSI will be “0”s, indicating a non-valid output *) Vref = internal: ½ * VDD5V (pin #16) or external: VDACref (pin#9), depending on Ref_extEN bit in OTP (0=int., 1=ext.) **) VDD = positive supply voltage at receiving side (3.0 – 5.5V) www.austriamicrosystems.com Revision 1.80 11 – 36 A S5043 D ata Sheet – Programming the AS5043 12 Programming the AS5043 After power-on, programming the AS5043 is enabled with the rising edge of CSn and Prog = logic high. 16 bit configuration data must be serially shifted into the OTP register via the Prog-pin. The first “CCW” bit is followed by the zero position data (MSB first) and the Analog Output Mode setting as shown in Table 5. Data must be valid at the rising edge of CLK (see Figure 10). Following this sequence, the voltage at pin Prog must be raised to the programming voltage VPROG (see Figure 10). 16 CLK pulses (tPROG) must be applied to program the fuses. To exit the programming mode, the chip must be reset by a power-on-reset. The programmed data is available after the next power-up. Note: During the programming process, the transitions in the programming current may cause high voltage spikes generated by the inductance of the connection cable. To avoid these spikes and possible damage to the IC, the connection wires, especially the signals PROG and VSS must be kept as short as possible. The maximum wire length between the VPROG switching transistor and pin PROG (see Figure 12) should not exceed 50mm (2 inches). To suppress eventual voltage spikes, a 10nF ceramic capacitor should be connected close to pins PROG and VSS. This capacitor is only required for programming, it is not required for normal operation. The clock timing tclk must be selected at a proper rate to ensure that the signal PROG is stable at the rising edge of CLK (see Figure 10). Additionally, the programming supply voltage should be buffered with a 10µF capacitor mounted close to the switching transistor. This capacitor aids in providing peak currents during programming. The specified programming voltage at pin PROG is 7.3 – 7.5V (see section 19.7). To compensate for the voltage drop across the VPROG switching transistor, the applied programming voltage may be set slightly higher (7.5 - 8.0V, see Figure 12). OTP Register Contents: CCW Counter Clockwise Bit ccw=0 – angular value increases with clockwise rotation ccw=1 – angular value increases with counterclockwise rotation Z [9:0]: Programmable Zero / Index Position FB_intEN: OPAMP gain setting: 0=external, 1=internal RefExtEN: DAC reference: 0=internal, 1=external ClampMd EN: Analog output span: 0=0-100%, 1=10-90%*VDD Output Range (OR0, OR1): Analog Output Range Selection [1:0] 00 = 360° 01 = 180° 10 = 90° 11 = 45° Figure 10: Programming Access – OTP Write Cycle (section of) CSn tDatain Prog CCW Z9 Z8 Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 FB_int EN RefExt EN Clamp Md En Output Range1 Output Range0 CLKPROG 1 8 16 tProg enable tDatain valid tclk see text Zero Position Analog Modes www.austriamicrosystems.com Revision 1.80 12 – 36 A S5043 D ata Sheet – Programming the AS5043 Figure 11: Complete OTP Programming Sequence Write Data CSn Programming Mode Power Off Prog CLKPROG Data 1 16 7.5V VDD VProgOff 0V tLoad PROG tPrgH tPrgR tPROG tPROG finished Figure 12: OTP Programming Hardware Connection of AS5043 (shown with AS5043 demoboard) 12.1 Zero Position Programming The AS5043 allows easy assembly of the system, as the actual angle of the magnet does not need to be considered. By OTP programming, any position can be assigned as the new permanent zero position with an accuracy of 0.35° (all modes). Using the same procedure, the AS5043 can be calibrated to assign a given output voltage to a given angle. With this approach, all offset errors (DAC + OPAMP) are also compensated for the calibrated position. Essentially, for a given mechanical position, the angular measurement system is electrically rotated (by changing the Zero Position value in the OTP register), until the output matches the desired mechanical position. The example in Figure 13 below shows a configuration for 5V supply voltage and 10%-90% output voltage range. It adjusted by Zero Position Programming to provide an analog output voltage of 2.0 Volts at an angle of 180°. The slope of the curve may be further adjusted by changing the gain of the OPAMP output stage and by selecting the desired angular range (360°/180°/90°/45°). www.austriamicrosystems.com Revision 1.80 USB 13 – 36 A S5043 D ata Sheet – Programming the AS5043 Figure 13: Zero Position Programming (shown for 360° mode) VDD5V 5V analog output voltage 2V 0V Mechanical 360° angle the output can be electrically rotated to match a given output voltage to any mechanical position 0° 90° 180° 270° 12.2 Analog Mode Programming The analog output can be configured in many ways: It consists of three major building blocks, a digital range preselector, a 10-bit Digital-to-Analog-Converter (DAC) and an OP-AMP buffer stage. In the default configuration (all OTP bits = 0), the analog output is set for 360° operation, internal DAC reference (VDD5V/2), external OPAMP gain, 0-100% ratiometric to VDD5V. Shown below is a typical example for a 0°-360° range, 0-5V output. The complete application requires only one external component, a buffer capacitor at VDD3V3 and has only 3 connections VDD, VSS and Vout (connectors 1-3). Note: the default setting for the OPAMP feedback path is:FB_intEn=0=external. The external resistors Rf and Rg must be installed. In the programmed state (FB_intEn=1=internal), these resistors do not need to be installed as the feedback path is internal (Rf_int and Rg_int). www.austriamicrosystems.com Revision 1.80 14 – 36 A S5043 D ata Sheet – Programming the AS5043 Figure 14: Analog Output Block Diagram Magnetic field range alarm. Active low. Leave open or connect to VSS if not used Mode pin. Default = open (low noise) External DAC reference pin. Leave open or connect to VSS if not used 1 16 Connect pins 15 and 16 for VDD= 3.0-3.6V. Do NOT connect for VDD = 4.5-5.5V ! VDD 1 2 Mode DACref 9 VDD5V AS5043 MagRngn 15 REF_extEN 1=ext 0 0 1 1 OR1 from DSP 360° 180° 90° 45° OR0 0 1 0 1 Vref 10bit digital VDD5V / 2 0=int 10 DACout 0 - 100% VDD5V /2 10bit analog DAC output pin. Leave open if not used Range Selector DAC + VOUT 12 ClampMdEN 0= 0-100% * Vref (def.) 1= 10-90% * Vref 0=ext 1=int FB_intEN Gain = 2x (int) Rf_int 30k Rf Rg_int 30k FB 11 CSn CLK DO 3 4 6 PROG 8 for OTP programming and alignment mode only. Leave open or connect to VSS if not used NC NC 5 13 NC 14 VDD VSS 7 OP-Amp feedback pin. Leave open if not used. Test pins. Leave open Digital serial interface, 10bit/360°. Leave open if not used. CSn and CLK may also be tied to VSS if not used Vout 0 12.2.1 Angular Range Selector The Angular Range selector allows a digital pre-selection of the angular range. The AS5043 can be configured for a full scale angular range of 45°, 90°, 180° or 360°. In addition, the Output voltage versus angle response can be fine-tuned by setting the gain of the OP-AMP with external resistors and the maximum output voltage can be set in the DAC. The combination of these options allows to configure the operation range of the AS5043 for all angles up to 360° and output voltages up to 5.5V. The response curve for the analog output is linear for the selected range (45°/90°/180°/360°). In addition, the slope is mirrored at 180° for 45°- and 90°- modes and has a step response at 270° for the 180°-mode. This allows the AS5043 to be used in a variety of applications. In these three modes, the output remains at Vout,max and Vout,min to avoid a sudden output change when the mechanical angle is rotated beyond the selected analog range. In 360°-mode, a jitter between Vout,max and Vout,min at the 360° point is also prevented due to a hysteresis. www.austriamicrosystems.com Revision 1.80 + 1-10µF Vout LDO 3.3V VDD3V3 2 RLmin = 4k7 CL 0 MHz www.austriamicrosystems.com Revision 1.80 31 – 36 A S5043 D ata Sheet – Electrical Characteristics Figure 24: Integral and Differential Non-Linearity (exaggerated curve) 1023 α 10bit code Actual curve 2 1 0 1023 TN DNL+1LSB INL 0.35° 512 Ideal curve 512 0 0° 180° 360 ° α [degrees] Integral Non-Linearity (INL) is the maximum deviation between actual position and indicated position. Differential Non-Linearity (DNL) is the maximum deviation of the step length from one position to the next. Transition Noise (TN) is the repeatability of an indicated position. 19.6 Timing Characteristics Synchronous Serial Interface (SSI) (operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless otherwise noted) Parameter Data output activated (logic high) First data shifted to output register Start of data output Data output valid Data output tristate Pulse width of CSn Read-out frequency Symbol t DO active tCLK FE T CLK / 2 t DO valid t DO tristate t CSn fCLK Min Typ Max 100 Unit ns ns ns Note Time between falling edge of CSn and data output activated Time between falling edge of CSn and first falling edge of CLK Rising edge of CLK shifts out one bit at a time Time between rising edge of CLK and data output valid After the last bit DO changes back to “tristate” CSn = high; To initiate read-out of next angular position Clock frequency to read out serial data 500 500 413 100 500 >0 1 ns ns ns MHz 19.7 Programming Conditions (operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0-3.6V (3V operation) VDD5V = 4.5-5.5V (5V operation) unless otherwise noted) Parameter Programming enable time Write data start Write data valid Symbol t Prog enable t Data in t Data in valid Min 2 2 250 Typ Max Unit Note µs µs ns Write data at the rising edge of CLKPROG Time between rising edge at Prog pin and rising edge of CSn www.austriamicrosystems.com Revision 1.80 32 – 36 A S5043 D ata Sheet – Electrical Characteristics Parameter Load programming data Rise time of VPROG before CLK PROG Symbol t Load PROG t PrgR t PrgH CLK PROG t PROG t PROG finished V PROG V ProgOff I PROG CLKAread Vprogrammed Vunprogrammed Min 3 0 0 Typ Max Unit Note µs µs Hold time of VPROG after CLK PROG 5 250 µs kHz µs µs During programming; 16 clock cycles Programmed data is available after next power-on Must be switched off after zapping Line must be discharged to this level During programming Analog readback mode VRef-VPROG during analog readback mode (see 13) Write data – programming CLK PROG CLK pulse width Hold time of Vprog after programming Programming voltage Programming voltage off level Programming current Analog read CLK Programmed zener voltage (log.1) Unprogrammed zener voltage (log. 0) 1.8 2 7.3 0 2 2.2 7.4 7.5 1 130 100 100 V V mA kHz mV V 1 www.austriamicrosystems.com Revision 1.80 33 – 36 A S5043 D ata Sheet – Package Drawings and Markings 20 Package Drawings and Markings Figure 25: 16-Lead Shrink Small Outline Package SSOP-16 AYWWIZZ AS5043 Dimensions mm Symbol Min A A1 A2 b c D E E1 e K L 1.73 0.05 1.68 0.25 0.09 6.07 7.65 5.2 0.65 0° 0.63 0.75 8° 0.95 Marking: AYWWIZZ inch Typ 1.86 0.13 1.73 0.315 6.20 7.8 5.3 A: Pb-Free Identifier Y: Last Digit of Manufacturing Year WW: Manufacturing Week I: Plant Identifier ZZ: Traceability Code JEDEC Package Outline Standard: MO - 150 AC Thermal Resistance Rth(j-a): typ. 151 K/W in still air, soldered on PCB IC’s marked with a white dot or the letters “ES” denote Engineering samples Max 1.99 0.21 1.78 0.38 0.20 6.33 7.9 5.38 Min .068 .002 .066 .010 .004 .239 .301 .205 .0256 0° .025 Typ .073 .005 .068 .012 .244 .307 .209 .030 Max .078 .008 .070 .015 .008 .249 .311 .212 8° .037 21 Packing Options Delivery: Tape and Reel (1 reel = 2000 devices) Tubes (1 box = 100 tubes á 77 devices) for delivery in tubes for delivery in tape and reel Order # AS5043ASSU Order # AS5043ASST www.austriamicrosystems.com Revision 1.80 34 – 36 A S5043 D ata Sheet – Recommended PCB Footprint 22 Recommended PCB Footprint Recommended Footprint Data A B C D E mm 9.02 6.16 0.46 0.65 5.01 inch 0.355 0.242 0.018 0.025 0.197 www.austriamicrosystems.com Revision 1.80 35 – 36 A S5043 D ata Sheet – Contact Information Copyrights Copyright © 1997-2009, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. This product is protected by U.S. Patent No. 7,095,228. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com Revision 1.80 36 – 36