AS5130ATSU

AS5130 8 B i t P r o g r a m m a b l e M a g n e t i c R o ta r y E n c o d e r with Motion Detection & Multiturn D a ta S he e t 1 General Description The AS5130 is a contactless magnetic rotary encoder for accurate angular measurement over a full turn of 360º. It is a system-on-chip, combining integrated Hall elements, analog front end and digital signal processing in a single device. The angle can be measured using only a simple two-pole magnet rotating over the center of the chip. The magnet may be placed above or below the IC. The absolute angle measurement provides instant indication of the magnet’s angular position with a resolution of 8 bit = 256 positions per revolution. This digital data is available as a serial bit stream and as a PWM signal. The AS5130 can be operated in pulsed mode (Vsupply=off), which reduces the average power consumption significantly. During Vsupply=off, the measured angle can be stored using an internal storage register supplied by a low power voltage line. This mode achieves very low power consumption during polling of the rotary position of the magnet. If the position of the magnet changes, then the motion detection feature wakes up an external system. The device is capable of counting the amount of magnet revolutions. The multi turn counter value is stored in a register and can be read in addition to the angle information. Furthermore, any arbitrary position can be set as zero-position. The system is tolerant to misalignment, air gap variations, temperature variations and external magnetic fields and high reliability due to non-contact sensing. Figure 1. Block Diagram 2 Key Features 360º contactless angular position encoding Two digital 8-bit absolute outputs: - Serial interface - Pulse width modulated (PWM) output User programmable zero position High speed: up to 30000 rpm Failure detection mode for magnet placement monitoring and loss of power supply Wide temperature range: - 40ºC to + 125ºC Multi Turn counter / Movement detection Small Pb-free package: SSOP-16 (5,3mm x 6,2mm) Automotive qualified to AEC-Q100, grade 1 3 Applications The AS5130 is an ideal solution for Ignition key position sensing, Steering wheel position sensing, Transmission gearbox encoder, Front panel rotary switches and replacement of Potentiometers. SINP / SINN / COSP / COSN PWM Decoder Sin PWM Hall Array & Frontend Amplifier Cos tracking ADC & Angle decoder Angle Zero Pos. Mag AGC Absolute Serial Interface (SSI) DIO CS DCLK C1 CAO AGC power management OTP PROG www.austriamicrosystems.com Revision 1.00 1 - 41 AS5130 Data Sheet - A p p l i c a t i o n s Contents 1 General Description.............................................................................................................................. 2 Key Features ........................................................................................................................................ 3 Applications .......................................................................................................................................... 4 Pin Assignments................................................................................................................................... Pin Descriptions ................................................................................................................................................... 1 1 1 4 4 5 Absolute Maximum Ratings.................................................................................................................. 6 Electrical Characteristics ...................................................................................................................... Timing Characteristics .......................................................................................................................................... Magnetic Input Range .......................................................................................................................................... 5 6 9 9 7 Detailed Description ........................................................................................................................... Connecting the AS5130 ..................................................................................................................................... Serial 3-Wire Connection (Default Setting) .................................................................................................... Serial 3-Wire Connection (OTP Programming Option) .................................................................................. 1-Wire PWM Connection................................................................................................................................ Analog Output ................................................................................................................................................ Analog Sin/Cos Outputs with External Interpolator ........................................................................................ Serial Synchronous Interface (SSI) .................................................................................................................... 10 10 10 12 12 13 14 15 Commands of the SSI in Normal Mode.......................................................................................................... 15 Commands of the SSI in Extended Mode ...................................................................................................... 16 Multi Turn Counter.............................................................................................................................................. AS5130 Status Indicators ................................................................................................................................... 19 20 Lock Status Bit ............................................................................................................................................... 20 Magnetic Field Strength Indicators................................................................................................................. 20 “Pushbutton” Feature ......................................................................................................................................... High Speed Operation ........................................................................................................................................ Propagation Delay.......................................................................................................................................... Sampling Rate................................................................................................................................................ Chip Internal Lowpass Filtering ...................................................................................................................... Digital Readout Rate ...................................................................................................................................... Total Propagation Delay of the AS5130 ......................................................................................................... Reduced Power Modes ...................................................................................................................................... 21 21 22 22 22 22 22 23 Low Power Mode ........................................................................................................................................... 23 Power Cycling Mode ...................................................................................................................................... 24 Polling Mode .................................................................................................................................................. 24 8 Application Information ....................................................................................................................... Benefits of AS5130............................................................................................................................................ Application Example 1 ........................................................................................................................................ Application Example II 3-wire sensor with magnetic field strength indication..................................................... Application Example III: Low-power encoder ..................................................................................................... Application Example IV: Polling mode................................................................................................................ Accuracy of the Encoder system ........................................................................................................................ Quantization Error .......................................................................................................................................... Vertical Distance of the Magnet ..................................................................................................................... Choosing the Proper Magnet ......................................................................................................................... Magnet Placement ......................................................................................................................................... 28 28 28 28 29 30 30 30 32 32 33 www.austriamicrosystems.com Revision 1.00 2 - 41 AS5130 Data Sheet - A p p l i c a t i o n s Lateral Displacement of the Magnet .............................................................................................................. 35 Magnet Size ................................................................................................................................................... 36 9 Package Drawings and Markings ....................................................................................................... Recommended PCB Footprint ........................................................................................................................... 38 39 10 Ordering Information......................................................................................................................... 40 www.austriamicrosystems.com Revision 1.00 3 - 41 AS5130 Data Sheet - P i n A s s i g n m e n t s 4 Pin Assignments Figure 2. Pin Assignments (Top View) CAO PROG VSS SINP SINN COSP COSN TestCoil 1 2 3 4 5 6 7 8 16 15 14 DVDD PWM WAKE C1 AVDD DIO CS DCLK AS5130 13 12 11 10 9 Pin Descriptions Table 1. Pin Descriptions Pin Name CAO PROG VSS SINP SINN COSP COSN Test Coil DCLK CS DIO AVDD C1 WAKE PWM DVDD Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description Indicates if the magnetic field is present. If the field is too low, the signal is HI. OTP Programming Pad, programming voltage. For normal operation it must be left unconnected. Supply Ground. Used for factory testing. For normal operation it must be left unconnected. Used for factory testing. For normal operation it must be left unconnected. Used for factory testing. For normal operation it must be left unconnected. Used for factory testing. For normal operation it must be left unconnected. Test pin. Must be left unconnected. Clock Source for SSI communication. Schmitt trigger input. Chip Select for SSI. Active high. Schmitt trigger input. Data input / output for SSI communication. Positive Supply Voltage 5V. Test mode selector. For normal operation it must be connected to VSS. Interrupt output. Used for polling mode. Open Drain NMOS. Use pull-up resistor with >1.5kΩ. Pulse Width Modulation output. 0.5us width step per LSB. Pin to connect to low power supply for polling mode. Must be connected to VSS in normal mode. www.austriamicrosystems.com Revision 1.00 4 - 41 AS5130 Data Sheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 6 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter Supply Voltage Input Pin Voltage Input Current (latchup immunity) Electrostatic Discharge Package Thermal Resistance SSOP-16 Package Thermal Resistance SSOP-16 Storage Temperature Ambient Temperature Junction Temperature 70 -55 -40 Min 0.3 VSS-0.5 -100 Max 7 AVDD 100 ±2 137.1 86 125 125 150 Units V V mA kV K/W K/W ºC ºC ºC Norm: IPC/JEDEC J-STD-020C. The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020C “Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. The lead finish for Pb-free leaded packages is matte tin (100% Sn). Norm: EIA/JESD78 ClassII Level A Norm: JESD22-A114E Still Air / Single Layer PCB Still Air / Multi Layer PCB, JEDEC Standard Testboard Comments Only relevant for polling operation mode, supply voltage with capacitor of the integrated storage register during toff phase of AVDD Package body temperature 260 ºC Humidity non-condensing 5 85 % www.austriamicrosystems.com Revision 1.00 5 - 41 AS5130 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics TAMB = -40 to 125ºC, unless otherwise noted. Table 3. Electrical Characteristics Symbol AVDD DVDD IDD Ioff N Parameter Positive Supply Voltage Polling Mode Supply Voltage Power Supply Current Power Down Mode Resolution Startup from zero TPwrUp Power Up Time Startup with preset AGC (Supplied during toff phase of AVDD from the external buffer capacitor via DVDD pin) Startup from sleep power mode tda tdd tdelay T INLcm TN PORr PORf Hyst Parameters for Magnet n N MD MT Bi s BDC Rotational Speed Resolution Magnet diameter Magnet thickness Magnetic input range Magnetic Sensitivity of AGC Magnetic Offset Valid for use of full range of sensitivity AGC value available at SSI Magnetic stray field without gradient 32 0.5 Diametrically magnetized 6 2.5 75 5 4 Frequencies above 1000 rpm causes an additional not specified DNL Error -30000 30000 8 rpm bit mm mm mT LSB/ mT mT Power-On-Reset levels Propagation Delay Tracking rate Signal Processing Delay Analog filter time constant Accuracy Transition Noise Analog signal path; over full temperature range Step rate of tracking ADC; 1 step = 1.406º Total signal processing delay, Analog + Digital + SSI readout ( tda + tdd + tSSI) Internal lowpass filter Centered Magnet Within horizontal displacement radius (see parameters for magnet) rms (1 sigma) VDD rising VDD falling Hysteresis | PORr - PORf | 3,7 3,4 4 3,7 500 4.1 -2 -3 6.6 0.85 15 1.15 1.4 8 1.406 2000 250 150 17 1.45 21.55 12.5 2 3 0.235 4,3 3,9 V V mV µs µs µs µs µs Conditions Except OTP programming Min 4.5 3.6 Typ 5 5 Max 5.5 5.5 19 2 Units V V mA mA bit www.austriamicrosystems.com Revision 1.00 6 - 41 AS5130 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 3. Electrical Characteristics (Continued) Symbol Parameter Conditions Startup from zero TPwrUp Power up time Startup with preset AGC (Supplied during toff phase of AVDD from the external buffer capacitor via DVDD pin) Startup from sleep power mode Vout_wake up Min Typ Max 2000 250 150 5 Units us Wake up output Angle difference threshold for wake up generation Open drain output with tri-state behavior, see Fig 10 Factory setting is 4 LSB, value is accessible by SSI in buffered register and can be changed by customer. 0 V WakeLSB 127 LSB DC/AC Characteristics for Digital Inputs and Outputs CMOS Input VIH VIL ILEAK High level Input voltage Low level Input Voltage Input Leakage Current CMOS Output VOH VOL CL tslew High level Output voltage Low level Output Voltage Capacitive Load Slew Rate External capacitive load C_L = 35pF External series resistance R = 0Ω Junction temperature TJ = 136ºC Rise time of the internal driver t_rise = 3ns Fall time of the internal driver t_fall = 3ns static voltage at pin PROG 8.0 VDD 0.5 VSS + 0.4 35 30 V V pF ns 0.7 x VDD 0.3 x VDD 1 V V µA tdelay Time Rise Fall 15 ns Programming Parameters VPROG IPROG TambPROG tPROG VR,prog VR,unprog NPWM PWMIN PWMAX PWP fPWM Programming Voltage Programming Current Programming ambient temperature Programming time Analog readback voltage during programming timing is internally generated during Analog Readback mode at pin PROG 0 2 2,2 8 angle = 0º (00H) angle = 358.6º (FFH) over full temperature range =1 / PWM period 0,59 150,9 151,5 5,44 0,556 142,8 7 0,526 135 9,18 142,3 134,61 8.5 100 85 4 0.5 3,5 V mA ºC µs V 8-bit PWM output PWM resolution PWM pulse width PWM pulse width PWM period PWM frequency bit µs µs µs kHz www.austriamicrosystems.com Revision 1.00 7 - 41 AS5130 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 3. Electrical Characteristics (Continued) Symbol Hyst Serial 8-bit Output fCLK tCLK fCLK, P Clock Frequency Clock Frequency Normal operation During OTP programming 6 166.6 250 500 MHz ns kHz Parameter Digital hysteresis Conditions at change of rotation direction Min Typ 1 Max Units bit www.austriamicrosystems.com Revision 1.00 8 - 41 AS5130 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s Timing Characteristics TAMB = -40 to 125 ºC, unless otherwise noted. Table 4. Timing Characteristics Symbol t0 t1 t2 t3 t4 t5 Parameter Rising CLK to CS Chip select to positive edge of CLK Chip select to drive bus externally Setup time command bit, Data valid to positive edge of CLK Hold time command bit, Data valid after positive edge of CLK Float time, Positive edge of CLK for last command bit to bus float Bus driving time, Positive edge of CLK for last command bit to bus drive Setup time data bit, Data valid to positive edge of CLK Hold time data bit, Data valid after positive edge of CLK Hold time chip select, Positive edge CLK to negative edge of chip select Bus floating time, Negative edge of chip select to float bus Timeout period in 2-wire mode (from rising edge of CLK) Conditions Min 15 15 -30 30 30 CLK/2 +0 CLK/2 +0 CLK/2 +0 30 CLK/2 CLK/2 +30 CLK/2 +30 CLK/2 +30 Typ Max ---Units ns ns ns ns ns ns t6 t7 t8 t9 ns ns ns ns t10 tTO 0 20 30 24 ns µs Magnetic Input Range The magnetic input range is defined by the AGC loop. This regulating loop keeps the Hall sensor output in the optimum range for low SNR by adjusting the Hall bias current. This loop can adjust to a magnetic field strength variation of ±38%. The AGC output voltage is an indicator for the magnetic field. The nominal magnetic field for a balanced AGC is defined by the Hall bias and the Hall sensitivity and can be set by a variable gain in the signal path. The gain can be set in 8 steps in the OTP or by the SSI in a mirror register. The resulting magnetic input range is a value of Bnominal±38% inside of a range of 32mT … 75mT, if the trimming is performed by the customer. Table 5. Magnetic Input Range Setting Binary Gain A Blimit 0 000 0.9 Max. 75mT 1 001 1.05 2 010 1.2 3 011 1.4 4 100 1.65 5 101 1.9 6 110 2.2 7 111 2.55 Min. 32mT www.austriamicrosystems.com Revision 1.00 9 - 41 AS5130 Data Sheet - D e t a i l e d D e s c r i p t i o n 7 Detailed Description Connecting the AS5130 The AS5130 can be connected to an external controller in several ways as listed below: Serial 3-wire connection (default setting) Serial 3-wire connection (OTP programming option) 1-wire PWM connection Analog output Analog Sin/Cos outputs with external interpolator Serial 3-Wire Connection (Default Setting) In this mode, the AS5130 is connected to the external controller via three SSI signals: Chip Select (CS), Clock (CLK) input and DIO (Data) in/output. This configuration not only helps to read and write data but also defines different operation modes. The data transfer in all cases is done via the DIO port. Figure 3. Standard SSI Serial Data Interface +5V AVDD VDD CS 100n AS5130 AS5130 CLK DIO micro controller VDD VSS VSS VSS www.austriamicrosystems.com Revision 1.00 10 - 41 AS5130 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 4. Normal Operation Mode CMD_PHASE DATA_PHASE DCLK t0 CS t5 CMD 4 LO CMD 0 t1 t9 DIO t3 DIO t4 CMD t7 t8 D 15 D 14 D0 t6 t10 READ t11 t12 DIO D 15 D 14 t10 WRITE D0 Table 6. Serial Bit Sequence (16bit read/write) Write Command C4 C3 C2 Read/Write Data D8 D7 D6 D5 D4 D3 D2 D1 D0 C1 C0 D15 D14 D13 D12 D11 D10 D9 Figure 5. Extended Operation Mode (for access of OTP only) CMD_PHASE DATA_PHASE_EXTENDED DCLK t0 CS t5 DIO CMD4 HI CMD2 CMD0 t1 t9 CMD t7 t10 READ t3 DIO t4 t6 D45 t8 D44 D0 t11 DIO D45 t10 t12 D44 D0 WRITE Table 7. Serial Bit Sequence (16bit read/write) Write Command C4 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 Read/Write Data D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 www.austriamicrosystems.com Revision 1.00 11 - 41 AS5130 Data Sheet - D e t a i l e d D e s c r i p t i o n Serial 3-Wire Connection (OTP Programming Option) This mode provides with an option to configure the serial interface for programming the OTP register. Using a clock input (CLK), DIO (Data) in/output and CS pin, it is possible to write and read out data from the OTP Register. The data transfer is done via the DIO channel. For programming, the PROG pin must be connected to +8V. Analog readout for trimming verification is mandatory. Figure 6. Serial Data Transmission in Continuous Readout Mode +5V AVDD VDD CS 100n AS5130 DCLK AS5130 DIO PROG VSS +8V VSS VSS micro controller VDD 1-Wire PWM Connection If the line (PWM) is used as angle output, the total number of connections can be reduced to three, including the supply lines. This type of configuration is especially useful for remote sensors. Low power mode is not possible in this configuration. If the AS5130 angular data is invalid, the PWM output will remain at low state. Figure 7. Data Transmission with Pulse Width Modulated (PWM) Output +5V AVDD VDD AS5130 PWM VSS VDD 100n micro controller VSS VSS The minimum PWM pulse width tON (PWM = high) is 1 LSB @ 0º (Angle reading = 00H). 1LSB = nom. ,0.556µs. The PWM pulse width increases with 1LSB per step. At the maximum angle 358.6º (Angle reading = FFH), the pulse width tON (PWM = high) is 256 LSB and the pause width tOFF (PWM = low) is 1 LSB. This leads to a total period (tON + tOFF) of 257LSB. www.austriamicrosystems.com Revision 1.00 12 - 41 AS5130 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 8. PWM out 5V 5V 0 0.556µs 71.7µs 142.3µs ton 142.3µs 71.15µs 128 0.556µs 255 toff Position Table 8. Position 0 127 128 255 Angle 0º 178.59 180º 358.59º High 1 128 129 256 t_high 0,556 71,15µs 71,7µs 142,3µs Low 256 129 128 1 t_low 142,3 71,7µs 71,15µs 0,556µs Duty-Cycle 0.39% 49.4% 50.2% 99.6% This means that the PWM pulse width is (position + 1) LSB, where position is 0….255. The tolerance of the absolute pulse width and frequency can be eliminated by calculating the angle with the duty cycle rather than with the absolute pulse width: t ON angle [ 8 - bit ] = ⎛ 257 --------------------------⎞ -1 ⎝ t ON + t OFF⎠ results in an 8-bit value from 00H to FFH, 360 angle [ º ] = -------256 results in a degree value from 0º ...358.6º Note: The absolute frequency tolerance is eliminated by dividing tON by (tON+TOFF), as the change of the absolute timing effects both TON and TOFF in the same way. t ON ⎛ 257 --------------------------⎞ – 1 ⎝ t ON + t OFF⎠ (EQ 2) (EQ 1) Analog Output The AS5130 can generate a ratiometric analog output voltage by low-pass filtering the PWM output. Figure 9 shows a simple passive 2nd order low pass filter as an example. In order to minimize the ripple on the analog output, the cut-off frequency of the low pass filter should be well below the PWM base frequency. www.austriamicrosystems.com Revision 1.00 13 - 41 AS5130 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 9. Ratiometric Analog Output +5V AVDD VDD VDD 100n AS5130 PWM VSS R≥4k7 C≥1µF analog out micro controller VSS VSS Figure 10. 5V Analog out 0V PWMout Angle 0º 180º 360º Analog Sin/Cos Outputs with External Interpolator By connecting C1 to VDD, the AS5130 provides analog Sine and Cosine outputs (SINP, COSP) of the Hall array frontend for test purposes. These outputs allow the user to perform the angle calculation by an external ADC + µC, e.g. to compute the angle with a high resolution. In addition, the inverted Sinus and Cosine signals (SINN, COSN; see dotted lines) are available for differential signal transmission. The input resistance of the receiving amplifier or ADC should be greater than 100kΩ. The signal lines should be kept as short as possible, longer lines should be shielded in order to achieve best noise performance. The SINN / COSN / SINP / COSP signals are amplitude controlled to ~1.3Vp (differential) by the internal AGC controller. The DC bias voltage is 2.25 V. If the SINN and COSN outputs cannot be sampled simultaneously, it is recommended to disable the automatic gain control (see Table 9) as the signal amplitudes may be changing between two readings of the external ADC. This may lead to less accurate results. www.austriamicrosystems.com Revision 1.00 14 - 41 AS5130 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 11. Sine and Cosine Outputs for External Angle Calculation +5V VDD VDD DA micro controller DA VSS VSS C1 VDD SINN SINP COSN COSP VSS AS5130 AS5130 100n Serial Synchronous Interface (SSI) Commands of the SSI in Normal Mode Table 9. SSI in Normal Mode # 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 RD_BOTH STORE REF RD2SIN RD_MULTI RD_ANGLE cmd WRITE CUST WD2COS SET TEST CFG1 reserved HYST_RST WD2SIN WRITE CONFIG -READ CUST RD2COS bin 10111 10110 10101 10100 10011 10010 10001 10000 00111 00110 00101 00100 00011 00010 00001 00000 mode write write write write write write write write read read read read read read read read store _ok xen_ 7 lock lock vdd_ ok Multiturn reg_ set nc inv_ 6 nc xen_ 5 nc inv_ 5 nc xen_ 4 inv_ 4 xen_ 3 angle angle_stored inv_ 3 xen_ 2 inv_ 2 xen_ 1 inv_ 1 xen_ 0 parit y inv_ 0 parit y parit y wlsb_ wlsb_ wlsb 6 5 _4 xen_ 7 inv_7 xen_ 6 wlsb _3 inv_ 6 wlsb _2 xen_ 5 wlsb _1 inv_ 5 wlsb _0 xen_ 4 gain _2 inv_ 4 gain _1 xen_ 3 gain _0 inv_ 3 nc xen_ 2 nc inv_ 2 nc xen_ 1 nc inv_ 1 nc xen_ 0 parit y inv_ 0 rst_ot p xen_ 7 go2sl eep rst_multi inv_7 xen_ 6 setHyst inv_ 6 xen_ 5 inv_ 5 xen_ 4 inv_ 4 xen_ 3 inv_ 3 xen_ 2 inv_ 2 xen_ 1 inv_ 1 xen_ 0 inv_ 0 15 14 13 12 wlsb _3 inv_ 6 11 wlsb _2 xen_ 5 10 wlsb _1 inv_ 5 gen_ rst 9 wlsb _0 xen_ 4 8 gain _2 inv_ 4 7 gain _1 xen_ 3 6 gain _0 inv_ 3 5 nc xen_ 2 4 nc inv_ 2 3 nc xen_ 1 2 nc inv_ 1 1 nc xen_ 0 0 nc inv_ 0 wlsb_ wlsb_ wlsb 6 5 _4 xen_ 7 inv_7 xen_ 6 inv_7 xen_ 6 agc agc Multiturn angle WD2COS / WD2SIN: xen_X disables Hall element X from the sensor array in the cosine or sine channel; xinv_X inverts the voltage output of Hall element X in the channels. www.austriamicrosystems.com Revision 1.00 15 - 41 AS5130 Data Sheet - D e t a i l e d D e s c r i p t i o n RD2COS / RD2SIN: The Hall array configuration for cosine and sine channel can be read out by these commands, initial values are 0. SET TEST CFG 1: gen_rst HI triggers a digital reset. WRITE CONFIG: go2sleep HI activates the sleep mode of the AS5130. The power consumption is significantly reduced. go2sleep LO returns to normal operation mode. During sleep mode, the lock bit in command 0 and command 1 is LO. WRITE CUST: With “wlsb_x” the threshold level for generation of a WAKE pulse is set (only important in polling mode). The initial value is 4 LSB. No value lower than 4 LSB can be set. The maximum value is 127 LSB. “gain_x” sets the gain in the signal HYST_RST: “setHyst” enables an additional hysteresis of the digital output signal. It is enabled by default. Only after 2 consecutive equal signals the output is changed. “rst_otp” forces the IC to read out the OTP in polling mode. This reset has to be performed after initial startup and every WAKE signal. “rst_multi” resets the multi turn counter to 0. READ CUST: With this command “wlsb_x” and “gain_x” can be read out. RD_BOTH: Angle and multi turn counter value can be read out simultaneously by this command. Due to limited data size, the parity bit is not available in this command. STORE REF: This command stores the actual angle as reference angle in the storage registers (only important in polling mode). The output is the stored angle (angle_stored), a flag, if the voltage at DVDD is OK (store_ok), a flag, if the supply voltage is OK (vdd_ok) and a check bit, if the register was written. RD_MULTI: Command for read out of multi turn register (multiturn) and AGC value (agc). “Lock” indicates a locked ADC and “parity” an even parity checksum. RD_ANGLE: Command for read out of angle value and AGC value (agc). “Lock” indicates a locked ADC and “parity” an even parity checksum. Commands of the SSI in Extended Mode For programming or readout of the OTP data, the chip has to be started with DVDD at a low voltage (polling mode off or cap discharged) or the OTP reset has to be performed. If not, the OTP is not read out and the OTP data is not available. Table 10. SSI in Extended Mode # 31 30 29 28 27 26 25 24 15 PROG_ OTP cmd WRITE_ OTP bin mode OTP Test ID OTP lock VREF Hall Bias Osc Zero Angle Redund Sensiti Wake ancy vity enable 11111 xt write 11110 xt write 11101 xt write 11100 xt write 11011 xt write 11010 xt write 11001 xt write 11000 xt write 01111 xt read OTP Test ID OTP lock VREF Hall Bias Osc Redund Sensiti Wake ancy vity enable Zero Angle OTP Test ID OTP lock VREF Hall Bias Osc Redund Sensiti Wake ancy vity enable Zero Angle www.austriamicrosystems.com Revision 1.00 16 - 41 AS5130 Data Sheet - D e t a i l e d D e s c r i p t i o n Table 10. SSI in Extended Mode # 14 13 12 11 10 9 8 cmd bin mode 01110 xt read 01101 xt read 01100 xt read 01011 xt read 01010 xt read RD_OTP 01001 xt read _ANA 01000 xt read WRITE OTP: Writing of the OTP register. The written data is volatile. “Zero Angle” is the angle, which is set for zero position. “Wake enable” enables the polling mode. “Sensitivity” is the gain setting in the signal path. “Redundancy is a number of bits, which allows the customer to overwrite one of the customer OTP bits . PROG_OTP: Programming of the OTP register. Only Bits can be programmed by the customer. RD_OTP: Read out the content of the OTP register. Data written by WRITE_OTP and PROG_OTP is read out. RD_OTP_ANA: Analog read out mode. The analog value of every OTP bit is available at pin 2 (PROG), which allows for a verification of the fuse process. No data is available at the SSI. OTP Programming For programming of the OTP, an additional voltage has to be applied to the pin PROG. It has to be buffered by a fast 100nF capacitor (ceramic) and a 10µF capacitor. The information to be programmed is set by command 25. The OTP bits 16 to 45 are used for AMS factory trimming and cannot be overwritten. Figure 12. OTP Programming Connection +5V AVDD VDD Output Output micro I/O controller 8.0 - 8.5V VSS VSS + 10µF 100n VDD CS DCLK DIO PROG C1 AS5130 AS5130 100n VSS www.austriamicrosystems.com Revision 1.00 17 - 41 AS5130 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 13. External Circuitry for OTP Programming maximum parasitic cable inductance L1.5K The voltage at pin 16 (DVDD) determines whether polling mode is activated or not. Any voltage above 3.6V activates the polling functionality. This voltage must always be present at DVDD in order to hold the information in the registers. The procedure is as follows: 1. Initial startup: The circuit starts up with invalid trim values, which are read back from the storage registers; the command rst_otp (command 19 – 10011) must be sent to read out valid trim values from the OTP. 2. These values are copied to the storage registers if OTP (Wake enable) is set (must be set for polling mode). 3. The values of AGC counter, actual angle, multi turn counter, hysteresis setting, wake threshold and gain setting are continuously updated in the storage registers. 4. The actual angle is stored as a reference by sending command STORE REF (command 3 – 00011). without this reference angle, a WAKE is generated at every startup. 5. The update of the storage registers is stopped if VDD drops below 4.45V and then the information is stored (DVDD) at the next startup (VDD on), the values are read back from the storage registers and the measured angle is compared with the stored reference angle; if the difference between both exceeds the threshold, a WAKE pulse is generated. www.austriamicrosystems.com Revision 1.00 25 - 41 AS5130 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 19. VDD on (fast) POR (40us... 150us) LO reset & reset_storage WAKE (26 clk periods) OTP readout (46bit - 140us ... 400us) LO Normal mode WAKE_ON store_ok ? Copy to Storage Normal mode HI true WAKE (20 clk periods) true command rst_otp false store_ok reset digital core only Retrieve values from storage registers Wait (162 clks - 86us ... 95us) Compare mode | α measured – HI α stored| > α threshold false OTP readout (OTP = HI Figure 21 shows the behavior of the wake up signal. The wake up signal will be low for twakeup = 10us. After that, the wake up signal will go to tri-state condition. In case of an angle comparison with a result below the threshold, the signal will remain in tri-state condition. After switching on AVDD, the system needs max. 250us to generate an angle with maximum accuracy. A WAKE signal cannot be expected until the end of this period. WAKE Interface An open drain NMOS structure is used in the WAKE pad. In order to generate a clear output signal level, a pull up resistor is required. The pad can drive 4mA. www.austriamicrosystems.com Revision 1.00 26 - 41 AS5130 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 20. WAKE Output Pin AVDD pull up resistor PAD WAKE AS5130 Table 16. Symbol Rpull_up twake up ton toff Parameter Pull up resistor Wake up pulse On-time Off-time Min 1.5 10 250 --Max 100 17 ----Unit kΩ µs µs ms Notes The used pad can drive 4mA. Interrupt signal to external devices, tri-state output, low active. Time for power up in polling mode. (1) No limit unless DVDD is always supplied. Figure 21. Wake Up Signal During Polling Mode of AVDD t_on t_off t_on AVDD tri-state WAKE tri-state t_wakeup delta (actual - reference angle) > threshold delta (actual - reference angle) 1µF 100n +5V AS5130 N S AS5130 VSS Once powered up for at least 2.5ms, the AS5130 can be operated in a pulsed mode, where it is periodically turned on/ off by a high side FET (PMOS) switching transistor with a low Ron (0 and AGC < 63). In any case, if a magnet other than the recommended 6mm diameter magnet is used, two paramters should be verified: Verify, that the magnetic field produces a sinusoidal wave, when the magnet is rotated. Note that this can be done with the SIN-/COS- outputs of the AS5130; e.g. rotate the magnet at constant speed and analyze the SIN- (or COS-) output with an FFT-analyzer. It is recommended to disable the AGC for this test (see Analog Sin/Cos Outputs with External Interpolator on page 14). Verify that the Bz-Curve between the poles is as linear as possible (see Figure 30). This curve may be available from the magnet supplier(s). Alternatively, the SIN- or COS- output of the AS5130 may also be used together with an X-Y- table to get a Bz-scan of the magnet (as in Figure 30 or Figure 31). Furthermore, the sinewave tests www.austriamicrosystems.com Revision 1.00 36 - 41 AS5130 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n described above may be re-run at defined X-and Y- misplacements of the magnet to determine the maximum acceptable lateral displacement range. It is recommended to disable the AGC for both these tests (see Analog Sin/ Cos Outputs with External Interpolator on page 14). Note: For preferred magnet suppliers, please refer to the austriamicrosystems website (Rotary Encoder section). www.austriamicrosystems.com Revision 1.00 37 - 41 AS5130 Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 9 Package Drawings and Markings The device is available in a 16-Lead Shrink Small Outline Package. Figure 33. SSOP-16 Package Drawings AYWWIZZ AS5130 Table 17. SSOP-16 package dimensions Symbol A A1 A2 b c D E E1 e K L 0º 0.63 mm Min 1.73 0.05 1.68 0.25 0.09 6.07 7.65 5.2 Typ 1.86 0.13 1.73 0.315 6.20 7.8 5.3 0.65 0.75 8º 0.95 0º 0.025 Max 1.99 0.21 1.78 0.38 0.20 6.33 7.9 5.38 Min 0.068 0.002 0.066 0.010 0.004 0.239 0.301 0.205 inch Typ 0.073 0.005 0.068 0.012 0.244 0.307 0.209 0.0256 0.030 8º 0.037 Max 0.078 0.008 0.070 0.015 0.008 0.249 0.311 0.212 www.austriamicrosystems.com Revision 1.00 38 - 41 AS5130 Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s Recommended PCB Footprint Figure 34. PCB Footprint Table 18. Recommended Footprint Data Symbol A B C D E mm 9.02 6.16 0.46 0.65 5.01 inch 0.355 0.242 0.018 0.025 0.197 www.austriamicrosystems.com Revision 1.00 39 - 41 AS5130 Data Sheet - O r d e r i n g I n f o r m a t i o n 10 Ordering Information The devices are available as the standard products shown in Table 19. Table 19. Ordering Information Model AS5130ATST AS5130ATSU Description Delivery Form Tape & Reel Tubes Package www.austriamicrosystems.com Revision 1.00 40 - 41 AS5130 Data Sheet - O r d e r i n g I n f o r m a t i o n Copyrights Copyright © 1997-2007, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com Revision 1.00 41 - 41