A S5163
1 2 BIT AUTOMOTIVE Angle Position Sensor
D ATA SHEET
General Description
T he AS5163 is a contactless magnetic angle position sensor for accurate angular measurement over a full turn of 360°. A sub range can be programmed to achieve the best resolution for the application. It is a system-on-chip, combining integrated Hall elements, analog front end, digital signal processing and best in class automotive protection features in a single device. To measure the angle, only a simple two-pole magnet, rotating over the center of the chip, is required. The magnet may be placed above or below the IC. The absolute angle measurement provides instant indication of the magnet’s angular position with a resolution of 0.022° = 16384 positions per revolution. According to this resolution the adjustment of the application specific mechanical positions are possible. The angular output data is available over a 12 bit PWM signal or 12 bit ratiometric analog output. The AS5163 operates at a supply voltage of 5 V and the supply and output pins are protected against overvoltage up to +27 V. In addition the supply pins are protected against reverse polarity up to – 18 V.
Benefits
U nique fully differential patented solution B est protections for automotive applications E asy to program F lexible interface selection PWM, analog output I deal for applications in harsh environments due to contactless position sensing R obust system, tolerant to magnet misalignment, air gap variations, temperature variations and external magnetic fields N o calibration required because of inherent accuracy. H igh driving capability of analog output (including diagnostics)
-
Key Features
− − − − 3 60° contactless high resolution angular position encoding U ser programmable start and end point of the application region. U ser programmable clamping levels and programming of the transition point. P owerful analog output • s hort circuit monitor • − − − H igh driving capability for resistive and capacitive loads
F igure 1: Typical arrangement of AS5163 and magnet
W ide temperature range: - 40°C to + 150°C S mall Pb-free package: TSSOP 14. B roken GND and VDD detection over a wide range of different load conditions.
Applications
A utomotive applications: - throttle and valve position sensing - gearbox position sensor - Headlight position control - Torque sensing - pedal position sensing - non contact potentiometers
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Blockdiagram
F igure 2: Block diagram AS5163
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Contents
1 P IN CONFIGURATION ............................................................................................................ 7 1 .1 2 P IN D ESCRIPTION ................................................................................................................... 7
E LECTRICAL CHARACTERISTICS ....................................................................................... 8 2 .1 2 .2 2 .3 2 .4 2 .5 A BSOLUTE M AXIMUM R ATINGS ............................................................................................... 8 O PERATING C ONDITIONS ......................................................................................................... 8 T IMING C ONDITIONS ............................................................................................................... 8 M AGNETIC I NPUT S PECIFICATION ............................................................................................ 8 E LECTRICAL S YSTEM S PECIFICATIONS ..................................................................................... 9
3 4
F UNCTIONAL DESCRIPTION ................................................................................................. 9 O PERATION ........................................................................................................................... 10 4 .1 V DD V OLTAGE M ONITOR ..................................................................................................... 10 4 .1.1 V DD Overvoltage Management ...................................................................................... 10 4 .1.2 V DD5 Undervoltage Management .................................................................................. 11
5
A NALOG OUTPUT ................................................................................................................. 11 5 .1 P ROGRAMMING P ARAMETERS ................................................................................................ 12 5 .1.1 A pplication specific angular range programming ........................................................... 12 5 .1.2 A pplication specific programming of the break point ...................................................... 12 5 .1.3 F ull Scale Mode ............................................................................................................ 13 5 .1.4 R esolution of the Parameters ......................................................................................... 13 5 .1.5 A nalogue Output Diagnostic Mode ................................................................................. 14 5 .2 A NALOG O UTPUT D RIVER P ARAMETERS ................................................................................. 15
6 7 8
P ULSE WIDTH MODULATION (PWM) OUTPUT ................................................................. 16 K ICK DOWN FUNCTION ....................................................................................................... 17 P ROGRAMMING THE AS5163............................................................................................... 18 8 .1 H ARDWARE S ETUP ............................................................................................................... 19 8 .2 P ROTOCOL TIMING AND COMMANDS OF SINGLE PIN INTERFACE ................................................ 19 8 .2.1 U nblock ........................................................................................................................ 21 8 .2.2 W RITE128 ..................................................................................................................... 22 8 .2.3 R EAD128 ...................................................................................................................... 23 8 .2.4 D OWNLOAD ................................................................................................................. 24 8 .2.5 U PLOAD ....................................................................................................................... 24 8 .2.6 F USE ............................................................................................................................ 24 8 .2.7 P ASS2FUNC ................................................................................................................. 25 8 .2.8 R EAD ............................................................................................................................ 25 8 .2.9 W RITE .......................................................................................................................... 25 8 .3 O TP P ROGRAMMING D ATA ................................................................................................... 26 8 .4 R EAD /W RITE USER DATA ...................................................................................................... 28 8 .5 P ROGRAMMING P ROCEDURE .................................................................................................. 29
9
C HOOSING THE PROPER MAGNET .................................................................................... 30 9 .1 9 .2 P HYSICAL P LACEMENT OF THE M AGNET ................................................................................. 31 M AGNET P LACEMENT ........................................................................................................... 31
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10 11 12
P ACKAGE DRAWINGS AND MARKINGS ......................................................................... 32 O RDERING INFORMATION............................................................................................... 32 R EVISION HISTORY........................................................................................................... 33
C ONTACT ..................................................................................................................................... 33 H EADQUARTERS ......................................................................................................................... 33 C OPYRIGHTS ............................................................................................................................... 33 D ISCLAIMER................................................................................................................................ 33
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List of Figures
F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE F IGURE 1 : T YPICAL ARRANGEMENT OF A S5163 A ND MAGNET ................................................................ 1 2 : B LOCK DIAGRAM A S5163 ................................................................................................... 2 3 : P IN CONFIGURATION T SSOP14 ............................................................................................ 7 4 : C ONNECTIONS FOR 5 V S UPPLY VOLTAGES .......................................................................... 10 5 : P ROGRAMMING OF AN INDIVIDUAL APPLICATION RANGE ...................................................... 12 6 : I NDIVIDUAL PROGRAMMING OF THE BREAK POINT B P .......................................................... 13 7 : F ULL SCALE MODE ............................................................................................................ 13 8 : O VERVIEW ABOUT THE ANGULAR OUTPUT VOLTAGE ............................................................ 14 9 : P WM O UTPUT SIGNAL ....................................................................................................... 16 1 0: K ICK D OWN H YSTERESIS IMPLEMENTATION ...................................................................... 17 1 1: P ROGRAMMING SCHEMATIC OF THE A S5163 ..................................................................... 19 1 2: B IT CODING OF THE SINGLE PIN PROGRAMMING INTERFACE ................................................ 19 1 3: P ROTOCOL D EFINITION .................................................................................................... 20 1 4: B US TIMING FOR THE W RITE128 C OMMAND ..................................................................... 20 1 5: B US TIMING FOR THE R EAD128 C OMMAND ....................................................................... 20 1 6: B US TIMING FOR THE R EAD C OMMANDS .......................................................................... 21 1 7: U NBLOCK SEQUENCE ....................................................................................................... 21 1 8: F RAME ORGANISATION OF THE W RITE128 C OMMAND ....................................................... 22 1 9: F RAME ORGANISATION OF THE R EAD128 C OMMAND ......................................................... 23 2 0: F RAME O RGANISATION OF THE D OWNLOAD C OMMAND .................................................. 24 2 1: F RAME ORGANISATION OF THE U PLOAD C OMMAND ......................................................... 24 2 2: F RAME ORGANISATION OF THE F USE C OMMAND ............................................................... 24 2 3: F RAME ORGANISATION OF THE P ASS2FUNC C OMMAND .................................................... 25 2 4: F RAME ORGANISATION OF THE R EAD C OMMAND .............................................................. 25 2 5: F RAME ORGANISATION OF THE W RITE C OMMAND ............................................................. 25 2 6: T YPICAL MAGNET ( 6 X 3 MM ) A ND MAGNETIC FIELD DISTRIBUTION ....................................... 30 2 7: D EFINED CHIP CENTER AND MAGNET DISPLACEMENT RADIUS ............................................. 31 2 8: V ERTICAL PLACEMENT OF THE MAGNET ............................................................................ 31 2 9: P ACKAGE D IMENSIONS AND M ARKING ............................................................................. 32
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List of Tables
T ABLE T ABLE T ABLE T ABLE T ABLE T ABLE T ABLE T ABLE T ABLE T ABLE T ABLE T ABLE T ABLE T ABLE T ABLE T ABLE T ABLE T ABLE T ABLE 1 : P IN DESCRIPTION T SSOP14 .................................................................................................. 7 2 : A BSOLUTE MAXIMUM RATINGS ............................................................................................. 8 3 : O PERATING C ONDITIONS ...................................................................................................... 8 4 T IMING CONDITIONS .............................................................................................................. 8 5 : M AGNET I NPUT S PECIFICATION ............................................................................................. 9 6 : R ESOLUTION OF THE PROGRAMMING PARAMETERS ............................................................... 13 7 : D IFFERENT FAILURE CASES OF A S5163 ................................................................................ 15 8 : G ENERAL P ARAMETERS O UTPUT D RIVER ............................................................................. 15 9 : E LECTRICAL PARAMETERS FOR THE ANALOGUE OUTPUT STAGE ............................................. 16 1 0: P WM S IGNAL PARAMETERS .............................................................................................. 17 1 1: E LECTRICAL PARAMETERS FOR THE P WM O UTPUT MODE .................................................... 17 1 2: P ROGRAMMING PARAMETERS FOR THE K ICK D OWN FUNCTION ............................................. 18 1 3: E LECTRICAL PARAMETERS OF THE K DOWN O UTPUT .......................................................... 18 1 4: O TP C OMMANDS AND COMMUNICATION INTERFACE MODES ................................................. 20 1 5: O TP D ATA O RGANISATION P ART 1 .................................................................................... 26 1 6: O TP D ATA O RGANISATION P ART 2 .................................................................................... 27 1 7: R EAD /W RITE DATA .......................................................................................................... 28 1 8: P ACKAGE D IMENSIONS ..................................................................................................... 32 1 9: O RDERING I NFORMATION ................................................................................................. 32
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1
P in Configuration
VDD VDD5 NC VDD3 GNDA NC NC
1
14
OUT NC GNDP KDOWN NC NC GNDD
3 4 5 6 7
AS5163
2
13 12 11 10 9 8
F igure 3: Pin configuration TSSOP14
1 .1
P in Description
T able 1: Pin description TSSOP14 shows the description of each pin of the standard TSSOP14 package (Thin Shrink Small Outline Package, 14 leads; see Figure 3). Pins 1, 2, 4, 5, 8 and 12 are supply pins and outputs of the internal voltage regulators. Pins 3, 6, 7, 9, 10 and 13 are used for fabrication test purpose and should be connected according Table 1 at the application board. Pin 11 is one additional output pin which can be used for a compare function including a hysteresis. An open drain configuration is used. If the internal angle is above a programmable threshold the output is switched to low. Below the threshold the output is high using a pull up resistor. Pin 14 is the output pin which is used for the analog output or digital PWM output mode. In addition this pin is used for programming of the device. P in
1 2 3 4 5 6 7 8 9 10 11 12 13 14
S ymbol
VDD VDD5 NC VDD3 GNDA NC NC GNDD NC NC KDOWN GNDP NC OUT
T ype
S S DIO/AIO S S DIO/AIO DIO/AIO S DIO/AIO DIO/AIO DO_OD S DIO/AIO DIO/AIO
D escription
Positive supply pin. This pin is over voltage protected. 4,5V-Regulator output, internally regulated from VDD. This pin needs an external ceramic capacitor of 2.2 µF Test pins for fabrication. Connected to ground in the application. 3,45V-Regulator output, internally regulated from VDD5. This pin needs an external ceramic capacitor of 2.2 µF Analogue ground pin. Connected to ground in the application. Test pins for fabrication. Connected to ground in the application. Test pins for fabrication. Open in the application. Digital ground pin. Connected to ground in the application. Test pins for fabrication. Connected to ground in the application. Test pins for fabrication. Connected to ground in the application. Kick down functionality. Analogue ground pin. Connected to ground in the application. Test pins for fabrication. Connected to ground in the application. Output pin can be programmed as analogue output or PWM output. Over this pin the programming is possible.
T able 1: Pin description TSSOP14 S DO_OD DI/AIO DO_T s upply pin digital output open drain multi purpose pin digital output /tri-state w ww.austriamicrosystems.com P age 7 of 33
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2
2 .1
E lectrical Characteristics
A bsolute Maximum Ratings
S tresses beyond those listed under “Absolute Maximum Ratings“ may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
P arameter DC supply voltage at pin VDD Overvoltage Output voltage OUT Output voltage KDOWN DC supply voltage at pin VDD3 DC supply voltage at pin VDD5 Input current (latchup immunity) Electrostatic discharge Storage temperature Body temperature (Lead-free package) Humidity non-condensing
S ymbol VDD Vout VKDOWN VDD3 VDD5 Iscr ESD Tstrg TBody H
M in -18 -0.3 -0.3 -0.3 -0.3 -100
V alue 27 27 27 5.5 7 100 ±4
U nit V V V V V mA kV °C °C %
N ote No operation permanent permanent
Norm: JEDEC 78 Norm: MIL 883 E method 3015 VDD, GND, OUT and KDOWN Pin. All other pins ± 2 kV Min – 67°F ; Max +257°F t=20 to 40s, Norm: IPC/JEDEC J-Std-020C Lead finish 100% Sn “matte tin”
-55
125 260
5
85
T able 2: Absolute maximum ratings
2 .2
O perating Conditions
Symbol Tamb Isupp VDD VDD3 VDD5 4.5 3.3 Min -40 15 5.0 3.45 4.5 5.5 3.6 Typ Max +150 Unit °C mA V V V 5V Operation Note -40°F…+302°F
Parameter Ambient temperature Supply current Supply voltage at pin VDD Voltage regulator output voltage at pin VDD3 Voltage regulator output voltage at pin VDD5
T able 3: Operating Conditions
2 .3
T iming Conditions
Symbol FRCOT TCLK TDETWD Min 4.05 Typ 4.5 222.2 12
T able 4 Timing conditions
Parameter Internal Master Clock Interface Clock Time WachDog error detection time
Max 4.95
Unit MHz ns ms
Note ±10% TCLK = 1 / FRCOT
2 .4
M agnetic Input Specification
( Operating conditions: T am b = - 40 to +150°C, VDD5 = 4.5-5.5V (5V operation) unless otherwise noted)
T wo-pole cylindrical diametrically magnetized source: P arameter Diameter Thickness Magnetic input field amplitude S ymbol dmag tmag Bpk 2.5 30 70 M in T yp 6 M ax U nit mm mm mT N ote Recommended magnet: Ø 6mm x 2.5mm for cylindrical magnets Required vertical component of the magnetic field strength on the die’s surface, measured along a concentric circle with a radius of 1.1mm
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P arameter Magnetic offset Field non-linearity Displacement radius Eccentricity Recommended magnet material and temperature drift
S ymbol Boff
M in
T yp
M ax ± 10 5
U nit mT % mm m
%/K
N ote Constant magnetic stray field Including offset gradient Offset between defined device center and magnet axis (see Figure 27). Dependant on the selected magnet. Eccentricity of magnet center to rotational axis NdFeB (Neodymium Iron Boron) SmCo (Samarium Cobalt)
Disp Ecc
0.25 100
-0.12 -0.035
1
T able 5: Magnet Input Specification
2 .5
E lectrical System Specifications
S ymbol RES INLopt INLtemp M in T yp M ax 12 ± 0.5 ± 0.9 U nit bit deg deg Maximum error with respect to the best line fit. Centered magnet without calibration, Tamb =25 °C. Maximum error with respect to the best line fit. Centered magnet without calibration, Tamb = -40 to +150°C Best line fit = (Errmax – Errmin) / 2 Over displacement tolerance with 6mm diameter magnet, without calibration, Tamb = -40 to +150°C 1 sigma DC supply voltage 3.3V (VDD3) DC supply voltage 3.3V (VDD3) N ote
( Operating conditions: T am b = - 40 to +150°C, VDD = 4.5-5.5V (5V operation) unless otherwise noted)
P arameter Resolution Analog and PWM Output Integral non-linearity (optimum) 360 degree full turn Integral non-linearity (optimum) 360 degree full turn Integral non-linearity 360 degree full turn Transition noise Power-on reset thresholds
On voltage; 300mV typ. hysteresis Off voltage; 300mV typ. hysteresis
INL TN Von Voff tPwrUp tdelay 1.37 1.08 0.06 2.2 1.9
± 1.4
deg Deg RMS
2.9 2.6 10 100
V V ms s
Power-up time System propagation delay absolute output : delay of ADC, DSP and absolute interface
Fast mode, times 2 in slow mode
T able 5: Electrical System Specifications
N ote : The INL performance is specified over the full turn of 360 degrees. An operation in an angle segment increases the accuracy. A two point linearization is recommended to achieve the best INL performance for the chosen angle segment.
3
F unctional Description
T he AS5163 is manufactured in a CMOS process and uses a spinning current Hall technology for sensing the magnetic field distribution across the surface of the chip. The integrated Hall elements are placed around the center of the device and deliver a voltage representation of the magnetic field at the surface of the IC. Through Sigma-Delta Analog / Digital Conversion and Digital Signal-Processing (DSP) algorithms, the AS5163 provides accurate high-resolution absolute angular position information. For this purpose a Coordinate Rotation Digital Computer (CORDIC) calculates the angle and the magnitude of the Hall array signals. The DSP is also used to provide digital information at the outputs that indicate movements of the used magnet towards or away from the device’s surface.
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A s mall low cost diametrically magnetized (two-pole) standard magnet provides the angular position information (see Figure 26). The AS5163 senses the orientation of the magnetic field and calculates a 14-bit binary code. This code is mapped to a programmable output characteristic. The type of output is programmable and can be selected as PWM or analog output. This signal is available at the pin 14 ( OUT ). The analog and PWM output can be configured in many ways. The application angular region can be programmed in a user friendly way. The start angle position T 1 a nd the end point T 2 c an be set and programmed according the mechanical range of the application with a resolution of 14 bits. In addition the T 1Y a nd T 2Y p arameter can be set and programmed according the application. The transition point 0 to 360 degree can be shifted using the break point parameter B P . This point is programmable with a high resolution of 14 bits of 360 degrees. The voltage for clamping level low C LL a nd clamping level high C LH c an be programmed with a resolution of 7 bits. Both levels are individually adjustable. These parameters are also used to adjust the PWM duty cycle. The AS5163 provides also a compare function. The internal angular code is compared to a programmable level using hysteresis. The function is available over the output pin 11 ( KDOWN ). The output parameters can be programmed in an OTP register. No additional voltage is required to program the AS5163. The setting may be overwritten at any time and will be reset to default when power is cycled. To make the setting permanent, the OTP register must be programmed by using a lock bit the content could be frozen for ever. The AS5163 is tolerant to magnet misalignment and unwanted external magnetic fields due to differential measurement technique and Hall sensor conditioning circuitry.
4
O peration
T he AS5163 operates at 5V ±10%, using two internal Low-Dropout (LDO) voltage regulators. For operation, the 5V supply is connected to pin V DD . While V DD3 a nd V DD5 ( LDO outputs) must be buffered by 2.2 F capacitors, the V DD r equires a 1 F capacitor. All capacitors (low ESR ceramic) are supposed to be placed close to the supply pins (see Figure 4). The V DD3 a nd V DD5 o utputs are intended for internal use only. It must not be loaded with an external load.
5V Operation
2.2µF 2.2µF
VDD5
1F
VDD3
VDD
LDO
Internal VDD4.5V
LDO
Internal VDD3.45V
4.5 - 5.5V
GND
F igure 4: Connections for 5V supply voltages
N ote : The pins V DD3 a nd V DD5 m ust always be buffered by a capacitor. It must not be left floating, as this may cause instable internal supply voltages which may lead to larger output jitter of the measured angle. The supply pins are over voltage protected up to 27 V. In addition the device has a reverse polarity protection.
4 .1
4 .1.1
V DD Voltage Monitor
V DD Overvoltage Management
I f the voltage applied to the VDD pin exceeds the over-voltage upper threshold for longer than the detection time the device enters a low power mode reducing the power consumption. When the overvoltage event has passed and the voltage applied
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t o the VDD pin falls below the over-voltage lower threshold for longer than the recovery time the device enters the normal mode. 4 .1.2 V DD5 Undervoltage Management
W hen the voltage applied to the VDD5 pin falls below the under-voltage lower threshold for longer than the VDD5_detection time the device stops the clock of the digital part and the output drivers are turned off to reduce the power consumption. When the voltage applied to the VDD5 pin exceeds the VDD5 undervoltage upper threshold for longer than the VDD5_recovery time the clock is restarted and the output drivers are turned on.
5
A nalog Output
B y default (after programmed M em_Lock_AMS O TP bit) the analog output mode is selected. The pin O UT p rovides an analog voltage that is proportional to the angle of the rotating magnet and ratiometric to the supply voltage V DD . It can source or sink currents up to ± 8mA in normal operation. Above this limit the short circuit operation mode is activated. Due to an intelligent approach a permanent short circuit will not damage the device. This is also feasible in a high voltage condition up to 27 V and at the highest specified ambient temperature. After the digital signal processing (DSP) a 12-bit Digital-to-Analog converter and output stage provides the output signal. The DSP maps the application range to the output characteristic. An inversion of the slope is also programmable to allow inversion of the rotation direction. The reference voltage for the Digital-to-Analog converter (DAC) is taken internally from V DD / 2 . In this mode, the output voltage is ratiometric to the supply voltage. An on-chip diagnostic feature force the analog output in the desired failure band. This will happen in case of a broken supply, too high or low magnetic field, short circuit and overvoltage condition. The Analog output is selected with the unprogrammed OTP bit O P_MODE(0 ).
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5 .1
P rogramming Parameters
T he analog output voltage modes are programmable by OTP. Depending on the application, the analog output can be adjusted. The user can program the following application specific parameters: T1 T2 T 1Y T 2Y C LL C LH BP M echanical angle start point M echanical angle end point V oltage level at the T1 position V oltage level at the T2 position C lamping Level Low C lamping Level High B reak point (transition point 0 to 360 degree)
These parameters are input parameters. Over the provided programming software and programmer these parameters are converted and finally written into the AS5163 128 bit OTP memory.
5 .1.1
A pplication specific angular range programming
T he application range can be selected by programming T 1 w ith a related T 1Y a nd T 2 w ith a related T 2Y i nto the AS5163. The internal gain factor is calculated automatically. The clamping levels C LL a nd C LH c an be programmed independent from the T 1 a nd T 2 p osition and both levels can be separately adjusted.
F igure 5: Programming of an individual application range
F igure 5 shows a simple example of the selection of the range. The mechanical starting point T 1 a nd the mechanical end point T 2 a re defining the mechanical range. A sub range of the internal Cordic output range is used and mapped to the needed output characteristic. The analog output signal has 12 bit, hence the level T 1Y a nd T 2Y c an be adjusted with this resolution. As a result of this level and the calculated slope the clamping region low is defined. The break point B P d efines the transition between C LL a nd C LH . In this example the B P i s set to 0 degree. The B P i s also the end point of the clamping level high C LH . This range is defined by the level C LH a nd the calculated slope. Both clamping levels can be set independently form each other. The minimum application range is 10 degrees.
5 .1.2
A pplication specific programming of the break point
T he break point B P c an be programmed as well with a resolution of 14 bits. This is important when the default transition point is inside the application range. In such a case the default transition point must be shifted out of the application range. The parameter B P d efines the new position. The function can be used also for an on-off indication.
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90 degree T2
Application range
electrical range mechanical range
T1 CLH 0 degree 180 degree CLL BP 270 degree
100%VDD CLH T2Y
clamping range high
T1Y CLL 0 clamping range low
T1
T2
clamping range low
F igure 6: Individual programming of the break point BP
5 .1.3
F ull Scale Mode
W ithout programming the parameters T 1 a nd T 2 t he AS5163 is in the full scale mode.
Analogue output Voltage
F igure 7: Full scale mode
F or simplification, Figure 7 describes a linear output voltage from rail to rail (0V to VDD) over the complete rotation range. In practice, this is not feasible due to saturation effects of the output stage transistors. The actual curve will be rounded towards the supply rails (as indicated Figure 7).
5 .1.4
R esolution of the Parameters
T he programming parameters have a wide resolution up to 14 bits. P arameter Mechanical angle start point Mechanical angle stop point Mechanical start voltage level Mechanical stop voltage level Clamping level low Clamping level high Break point S ymbol T1 T2 T1Y T2Y CLL CLH BP R esolution 14 bits 14 bits 12 bits 12 bits 7 bits 7 bits 14 bits 4096 LSBs is the max. level 31 LSBs is the min. level N ote
T able 6: Resolution of the programming parameters
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100 96
Failure Band High
Clamping Region High CLH
T2Y
Application Region
T1Y CLL Clamping Region Low 4 0 Failure Band Low
F igure 8: Overview about the angular output voltage
F igure 8 gives an overview about the different ranges. The failure bands are used to indicate a wrong operation of the AS5163. This can be caused due to a broken supply line. By using the specified load resistors the output level will remain in these bands during a fail. It is recommended to set the clamping level C LL a bove the lower failure band and the clamping level C LH b elow the higher failure band.
5 .1.5
A nalogue Output Diagnostic Mode
D ue to the low pin count in the application a wrong operation must be indicated by the output pin O UT . This could be realized using the failure bands. The failure band is defined with a fixed level. The failure band low is specified from 0 to 4 % of the supply range. The failure band high is defined from 100 to 96 %. Several failures can happen during operation. The output signal remains in these bands over the specified operating and load conditions. All different failures can be grouped into the internal alarms (failures) and the application related failures. CLOAD ≤ 42 nF, RPU= 2k…5.6kOhm RPD= 2k…5.6kOhm load pull-up
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T ype
F ailure mode Out of magnetic range (too less or too high magnetic input) Cordic overflow Offset compensation finished Watch dog fail Oscillator fail
S ymbol
F ailure band
N ote Could be switched off by one OTP bit ALARM_DISABLE Programmable by OTP bit DIAG_HIGH. Programmable by OTP bit DIAG_HIGH. Programmable by OTP bit DIAG_HIGH. Programmable by OTP bit DIAG_HIGH. Programmable by OTP bit DIAG_HIGH.
MAGRng
High/Low
Internal alarms (failures)
COF OCF WDF OF
High/Low High/Low High/Low High/Low
Overvoltage condition Application related failures Broken VDD Broken VSS Short circuit output
OV BVDD BVSS SCO High/Low High/Low
Dependent on the load resistor Pull up Pull down Switch off failure band high failure band low short circuit dependent
T able 7: different failure cases of AS5163
F or efficient use of diagnostics it is recommended to program to clamping levels C LL a nd C LH .
5 .2
A nalog Output Driver Parameters
T he output stage is configured in a push-pull output. Therefore it is possible to sink and source currents. CLOAD≤ 42 nF, RPU= 2k…5.6kOhm RPD= 2k…5.6kOhm load pull-up Parameter Short circuit output current (low side driver) Short circuit output current (high side driver) Short circuit detection time Short circuit recovery time Output Leakage current Output voltage broken GND with pull-up Output voltage broken GND with pull-down Output voltage broken VDD with pull-up Output voltage broken VDD with ull-down Symbol IOUTSCL IOUTSCH TSCDET TSCREC ILEAKOUT BGNDPU BGNDPD BVDDPU BVDDPD Min 8 -8 20 1.5 -20 96 0 96 0 Typ Max 32 -32 400 15 20 100 4 100 4 Unit mA mA us ms uA %VDD %VDD %VDD %VDD Note VOUT=27V VOUT=0V output stage turned off output stage turned on VOUT=5V; VDD=0V
T able 8: General Parameters Output Driver
N ote: A P ull-Up/Down load up to 1kOhm with increased diagnostic bands from 0%-6% and 94%-100%.
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Parameter Output Voltage Range Output Integral nonlinearity Output Differential nonlinearity Output Offset Update rate of the Output Output Step Response Output Voltage Temperature drift Output ratiometricity error Noise
Symbol VOUT VOUTINL VOUTDNL VOUTOFF VOUTUD VOUTSTEP VOUTDRIFT VOUTRATE VOUTNOISE
Min 4
Typ
Max 96 10
Unit % VDD LSB LSB mV us
Note
-10 -50 100
10 50
at 2048 LSB level info parameter Between 10% and 90 %, RPUOUT =1kOhm, CLOUT=1nF; VDD=5V of value at mid code; info parameter 0.04*VDD≤VOUT≤0.96*VDD 1Hz…30kHz; at 2048 LSB level
555 -1 -1.5 1 1.5 10
us % %VDD mVpp
T able 9: Electrical parameters for the analogue output stage
6
P ulse Width Modulation (PWM) Output
T he AS5163 provides a pulse width modulated output (PWM), whose duty cycle is proportional to the measured angle. This output format is selectable over the OTP memory O P_MODE(0) b it. If output pin O UT i s configured as open drain configuration an external load resistor (pull up) is required. The PWM frequency is internally trimmed to an accuracy of ± 10% over full temperature range. This tolerance can be cancelled by measuring the ratio between the on and off state. In addition the programmed clamping levels C LL a nd C LH w ill also adjust the PWM signal characteristic.
F igure 9: PWM output signal
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T he PWM frequency can be programmed by the OTP bits P WM_frequency (1:0). T herefore 4 different frequencies are possible. P arameter PWM frequency1 PWM frequency2 PWM frequency3 PWM frequency4 MIN pulse width MAX pulse width S ymbol fPWM1 fPWM2 fPWM3 fPWM4 PWMIN PWMAX M in 123.60 247.19 494.39 988.77 T yp 137.33 274.66 549.32 1098.63 (1+1)*1/ fPWM (1+4094)*1/ fPWM M ax 151.06 302.13 604.25 1208.50 U nit Hz Hz Hz Hz s ms N ote PWM_frequency (1:0) = “00” PWM_frequency (1:0) = “01” PWM_frequency (1:0) = “10” PWM_frequency (1:0) = “11”
T able 10: PWM signal parameters
T aking into consideration the AC characteristic of the PWM output including load it is recommended to use the clamping function. The 0 to 4 % and 96 to 100 % range is recommended. Parameter Output voltage low Output leakage PWM duty cycle range PWM slew rate Voltage difference between VDD of ASIC and pull-up load supply Symbol PWMVOL ILEAK PWMDC PWMSRF Min 0 -20 4 1 2 Typ Max 0.4 20 96 4 Unit V uA % Between 75 % and 25 % V/us RPUOUT = 1k , CLOUT= 1nF, VDD= 5V Note IOUT=8mA VOUT=5V
∆SUPP
100
mV
T able 11: Electrical parameters for the PWM output mode
7
K ick Down function
T he AS5163 provides a special compare function. Using a programmable angle value with a programmable hysteresis this function is implemented. It will be indicated over the open drain output pin K DOWN. I f the actual angle is above the programmable value plus the hysteresis, the output is switched to low. The output will remain at low level until the value KD is reached in the reverse direction.
F igure 10: Kick Down Hysteresis implementation
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P arameter Kick down angle
S ymbol KD
R esolution 6 bits
N ote
KDHYS (1:0) = “00” Kick down Hysteresis KDHYS 2 bits KDHYS (1:0) = “01” KDHYS (1:0) = “10” KDHYS (1:0) = “11”
T able 12: Programming parameters for the Kick Down function
8 LSB hysteresis 16 LSB hysteresis 32 LSB hysteresis 64 LSB hysteresis
Pull up resistance 1k to 5.6K to VDD Cload max 42nF Parameter Short circuit output current (Low Side Driver) Short circuit detection time Short circuit recovery time Output voltage low Output leakage KDOWN slew rate (falling edge) Symbol IOUTSC TSCDET TSCREC KDVOL KDILEAK KDSRF Min 6 20 1.5 0 -20 1 2 Typ Max 24 400 15 1.1 20 4 Unit mA us ms V uA V/us Note VKDOWN=27V output stage turned off output stage turned on IKDOWN=6mA VKDOWN=5V Between 75 % and 25 %, RPUKD = 1k , CLKD= 1nF, VDD= 5V
T able 13: Electrical parameters of the KDOWN output
8
P rogramming the AS5163
T he AS5163 programming is a one-time-programming (OTP) method, based on polysilicon fuses. The advantage of this method is that no additional programming voltage is needed. The internal LDO provides the current for programming. The OTP consists of 128 bits; several bits are available for user programming. In addition factory settings are stored in the OTP memory. Both regions are independently lockable by build in lock bits. A single OTP cell can be programmed only once. Per default, the cell is “0”; a programmed cell will contain a “1”. While it is not possible to reset a programmed bit from “1” to “0”, multiple OTP writes are possible, as long as only unprogrammed “0”bits are programmed to “1”. Independent of the OTP programming, it is possible to overwrite the OTP register temporarily with an OTP write command. This is possible only if the user lock bit is not programmed. Due to the programming over the output pin the device will initially start in the communication mode. In this mode the digital angle value can be read with a specific protocol format. It is a bidirectional communication possible. Parameters can be written into the device. A programming of the device is triggered by a specific command. With another command (pass2func) the device can be switched into operation mode (analog or PWM output). In case of a programmed user lock bit the AS5163 automatically starts up in the functional operation mode. No communication of the specific protocol is possible after this.
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8 .1
H ardware Setup
F or OTP memory access the pin OUT and the supply connection is required. Without the programmed M em_Lock_USER O TP bit the device will start up in the communication mode and will remain into an IDLE operation mode. The pull up resistor R Communica tion i s required during startup. Figure 1 shows the configuration of an AS5163.
F igure 11: Programming schematic of the AS5163
8 .2
P rotocol timing and commands of single pin interface
D uring the communication mode the output level is defined by the external pull up resistor R Communication . The output driver of the device is in tri-state. The bit coding (shown in Figure 12) has been chosen in order to allow the continuous synchronization during the communication, which can be required due to the tolerance of the internal clock frequency. Figure 12 shows how the different logic states '0' and '1' are defined. The period of the clock T CLK i s defined with 222.2 ns. The voltage levels V H a nd V L a re CMOS typical. Each frame is composed by 20 bits. The 4 MSB (CMD) of the frame specifies the type of command that is passed to the AS5163. 16 data bits contains the communication data. There will be no operation in case of the usage of a not specified CMD. The sequence is oriented in a way that the LSB of the data is coming first followed by the command. Depending on the command the number of frames is different. The single pin programming interface block of the AS5163 can operate in slave communication or master communication mode. In the slave communication mode the AS5163 receives the data organized in frames. The programming tool is the driver of the single communication line and can pull down the level. In case of the master communication mode the AS5163 transmits data in the frame format. The single communication line can be pulled down by the AS5163.
F igure 12: Bit coding of the single pin programming interface
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F igure 13: Protocol Definition
P ossible Interface c ommands UNBLOCK WRITE128 READ128 UPLOAD DOWNLOAD FUSE PASS2FUNC READ WRITE Resets the interface Writes 128 bits (user + factory settings) into the device Read 128 bits (user + factory settings) from the device Transfers the register content into the OTP memory Transfers the OTP content to the register content Command for permanent programming Change operation mode from communication to operation Read related to the address the user data Write related to the address the user data D escription
A S5X63 C ommunication M ode SLAVE SLAVE SLAVE and MASTER SLAVE SLAVE SLAVE SLAVE SLAVE and MASTER SLAVE
C ommand C MD 0x0 0x9 (0x1) 0xA 0x6 0x5 0x4 0x7 0xB 0xC
N umber of F rames 1 8 9 1 1 1 1 2 1
T able 14: OTP commands and communication interface modes
N ote : T he command CMD 0x2 is reserved for AMS test purpose.
When single pin programming interface bus is in high impedance state the logical level of the bus is held by the pull up resistor R Communica tion . Each communication begins by a condition of the bus level which is called START. This is done by forcing the bus in logical low level (done by the programmer or AS5163 depending on the communication mode). Afterwards the bit information of the command is transmitted as shown in Figure 14.
F igure 14: Bus timing for the WRITE128 command
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
F igure 15: Bus timing for the READ128 command
I n case of READ or READ128 command (Figure 15) the idle phase between the command and the answer is 10 TBIT (TSW).
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MSB
LSB
LSB
LSB
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MSB
MSB LSB
MSB
MSB
F igure 16: Bus timing for the READ commands
I n case of a WRITE command, the device stays in slave communication mode and will not switch to master communication mode. When using other commands like DOWNLOAD, UPLOAD, etc. instead of READ or WRITE, it does not matter what is written in the address fields (ADDR1, ADDR2).
8 .2.1
U nblock
T he Unblock command can be used to reset only the one-wire interface of the AS5163 in order to recover the possibility to communicate again without the need of a POR after a stacking event due to noise on the bus line or misalignment with the AS5163 protocol. The command is composed by a not idle phase of at least 6 TBIT followed by a packet with all 20 bits at zero (see picture below).
F igure 17: Unblock sequence
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MSB
LSB
LSB
LSB
LSB
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8 .2.2
W RITE128
F igure 18 shows the format of the frame and the command:
DATA1
LSB MSB LSB
DATA0
MSB LSB
CMD
MSB
1
DATA3
LSB MSB LSB
0
0
1
DATA2
MSB LSB
CMD
MSB
1
DATA5
LSB MSB LSB
0
0
0
DATA4
MSB LSB
CMD
MSB
1
DATA7
LSB MSB LSB
0
0
0
DATA6
MSB LSB
CMD
MSB
1
DATA9
LSB MSB LSB
0
0
0
DATA8
MSB LSB
CMD
MSB
1
DATA11
LSB MSB LSB
0
0
0
DATA10
MSB LSB
CMD
MSB
1
DATA13
LSB MSB LSB
0
0
0
DATA12
MSB LSB
CMD
MSB
1
DATA15
LSB MSB LSB
0
0
0
DATA14
MSB LSB
CMD
MSB
1
F igure 18: Frame organisation of the WRITE128 command
0
0
0
T he command contains 8 frames. With this command the AS5163 is only receiving frames. This command will transfer the data in the special function registers (SFRs) of the device. The data is not permanent programmed using this command. Table 15 and Table 16 describe the organization of the OTP data bits. The access is performed with CMD field set to 0x9. The next 7 frames with CMD field set to 0x1. The 2 bytes of the first command will be written at address 0 and 1 of the SFRs, the 2 bytes of the second at address 2 and 3 and so on in order to cover all the 16 bytes of the 128 SFRs.
N ote : It is important to complete always the command. All 8 frames are needed. In case of a wrong command or a communication error a power on reset must be performed. The device will be delivered with the programmed M em_Lock_AMS O TP bit. This bit locks the content of the factory settings. It is impossible to overwrite this particular region. The written information will be ignored.
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8 .2.3
R EAD128
F igure 19 shows the format of the frame and the command:
F igure 19: Frame organisation of the READ128 command
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T he command is composed by a first frame transmitted to the AS5163. The device is in slave communication mode. The device remains for the time T SW ITCH i n IDLE mode before changing into the master communication mode. The AS5163 starts to send 8 frames. This command will read the SFRs. The numbering of the data bytes correlates with the address of the related SFR. An even parity bit is used to guarantee a correct data transmission. Each parity (P) is related to the frame data content of the 16 bit word. The MSB of the CMD dummy (P) is reserved for the parity information.
8 .2.4
D OWNLOAD
F igure 20 shows the format of the frame.
DO NOT CARE
LSB MSB LSB
DO NOT CARE
MSB LSB
CMD
MSB
1
F igure 20: Frame Organisation of the DOWNLOAD command
0
1
0
T he command consists of one frame received by the AS5163 (slave communication mode). The OTP cell fuse content will be downloaded into the SFRs. The access is performed with CMD field set to 0x5.
8 .2.5
U PLOAD
F igure 21 shows the format of the frame:
DO NOT CARE
LSB MSB LSB
DO NOT CARE
MSB LSB
CMD
MSB
0
F igure 21: Frame organisation of the UPLOAD command
1
1
0
T he command consists of one frame received by the AS5163 (slave communication mode) and transfers the data from the SFRs into the OTP fuse cells. The OTP fuses are not permanent programmed using this command. The access is performed with CMD field set to 0x6.
8 .2.6
F USE
F igure 22 shows the format of the frame:
DO NOT CARE
LSB MSB LSB
DO NOT CARE
MSB LSB
CMD
MSB
0
F igure 22: Frame organisation of the FUSE command
0
1
0
T he command consists of one frame received by the AS5163 (slave communication mode) and it is giving the trigger to permanent program the non volatile fuse elements. The access is performed with CMD field set to 0x4. N ote : After this command the device starts to program automatically the build in programming procedure. It is not allowed to send other commands during this programming time. This time is specified to 4ms after the last CMD bit.
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8 .2.7
P ASS2FUNC
F igure 23 shows the format of the frame:
DO NOT CARE
LSB MSB LSB
DO NOT CARE
MSB LSB
CMD
MSB
1
F igure 23: Frame organisation of the PASS2FUNC command
1
1
0
T he command consists of one frame received by the AS5163 (slave communication mode). This command stops the communication receiving mode, releases the reset of the DSP of the AS5163 device and starts to work in functional mode with the values of the SFR currently written. The access is performed with CMD field set to 0x7. 8 .2.8 R EAD
F igure 24 shows the format of the frame:
F igure 24: Frame organisation of the READ command
T he command is composed by a first frame sent to the AS5163. The device is in slave communication mode. The device remains for the time T SW ITCH i n IDLE mode before changing into the master communication mode. The AS5163 starts to send the second frame transmitted by the AS5163. The access is performed with CMD field set to 0xB. When the AS5163 has received the first frame it sends a frame with data value of the address specified in the field of the first frame. Table 17 shows the possible readable data information for the AS5163 device. An even parity bit is used to guarantee a correct data transmission. The parity bit (P) is generated by the 16 data bits. The MSB of the CMD dummy (P) is reserved for the parity information. 8 .2.9 W RITE
F igure 25 shows the format of the frame:
DATA
LSB MSB LSB
ADDR
MSB LSB
CMD
MSB
0
F igure 25: Frame organisation of the WRITE command
0
1
1
T he command consists of one frame received by the AS5163 (slave communication mode). The data byte will be written to the address. The access is performed with CMD field set to 0xC. Table 17 shows the possible write data information for the AS5163 device. N ote : It is not recommended to access OTP memory addresses using this command.
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8 .3
O TP Programming Data
Data Byte Bit Nr.
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Symbol
AMS_Test AMS_Test AMS_Test AMS_Test AMS_Test AMS_Test AMS_Test AMS_Test AMS_Test AMS_Test AMS_Test AMS_Test ChipID ChipID ChipID ChipID ChipID ChipID ChipID ChipID ChipID ChipID ChipID ChipID ChipID ChipID ChipID ChipID ChipID ChipID ChipID ChipID ChipID MemLock_AMS KD KD KD KD KD KD ClampLow ClampLow ClampLow ClampLow ClampLow ClampLow ClampLow DITH_DISABLE ClampHi ClampHi ClampHi ClampHi ClampHi ClampHi ClampHi DIAG_HIGH OffsetIn OffsetIn OffsetIn OffsetIn OffsetIn OffsetIn OffsetIn OffsetIn
Default
FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS FS 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Description
DATA15 (0x0F)
AMS Test area
DATA14 (0x0E) Factory Settings
DATA13 (0x0D)
Chip ID
DATA12 (0x0C)
Lock of the Factory Setting Area
DATA11 (0x0B)
Kick Down Threshold
DATA10 (0x0A) Custom er Settings
Clamping Level Low
DAC12/DAC10 Mode
DATA9 (0x09)
Clamping Level High
Diagnostic Mode, default =0 for Failure Band Low
DATA8 (0x08)
Offset
T able 15: OTP Data Organisation Part 1
N ote: F actory settings (FS) are used for testing and programming at AMS. These settings are locked (only read access possbile).
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DATA7 (0x07)
DATA6 (0x06)
DATA5 (0x05)
DATA4 (0x04)
DATA3 (0x003)
DATA2 (0x02)
DATA1 (0x01)
DATA0 (0x00)
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
OffsetIn OffsetIn OffsetIn OffsetIn OffsetIn OffsetIn OP_Mode OP_Mode OffsetOut OffsetOut OffsetOut OffsetOut OffsetOut OffsetOut OffsetOut OffsetOut OffsetOut OffsetOut OffsetOut OffsetOut KDHYS KDHYS PWM Frequency PWM Frequency BP BP BP BP BP BP BP BP BP BP BP BP BP BP FAST_SLOW EXT_RANGE Gain Gain Gain Gain Gain Gain Gain Gain Gain Gain Gain Gain Gain Gain Invert_slope Lock_OTPCUST redundancy redundancy redundancy redundancy redundancy redundancy redundancy redundancy
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Offset
Selection of Analog="00" or PWM="01"
Output Offset
Kick Down Hysteresis select the PWM frequency (4 frequencies)
Break Point
Output Data Rate enables a wider z-Range
Gain
Clockwise/counterclockwise rotation Customer Memory Lock
Redundancy Bits
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D ata Content:
• • • • • • • • • • • • • • • • •
R edundancy (7:0): F or a better programming reliability a redundancy is implemented. In case, the programming of one bit failed this function can be used. With an address (7:0) one bit can be selected and programmed. L ock_OTPCUST = 1 , locks the customer area in the OTP and the device is starting up from now on in operating mode. I nvert_Slope = 1 , inverts the output characteristic in analog output mode. G ain (7:0): W ith this value one can adjust the steepness of the output slope. E XT_RANGE = 1 , provides a wider z-Range of the magnet by turning off the alarm function. F AST_SLOW = 1 , improves the noise performance due to internal filtering. B P (13:0): T he breakpoint can be set with resolution of 14 bit. P WM Frequency (1:0): 4 d ifferent frequency settings possible. Please refer to Table 10. K DHYS (1:0) a voids flickering at the KDOWN output (pin 11). For settings refer to Table 12. O ffsetOut (11:0) O utput characteristic parameter A NALOG_PWM = 1 , selects the PWM output mode. O ffsetIn (13:0) O utput characteristic parameter D IAG_HIGH = 1 : In case of an error, the signal goes into high failure-band. C lampHI (6:0) s ets the clamping level high with respect to VDD. D ITH_DISABLE d isables filter at DAC C lampLow (6:0) s ets the clamping level low with respect to VDD. K D (5:0) s ets the kick-down level with respect to VDD.
8 .4
R ead/Write user data
Address
0x10 0x11 0x12 0x17
Area Region
Address
16 17 18 23
Bit7
0 OCF
Bit6
0 COF
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W USER DATA
CORDIC_OUT[7:0] CORDIC_OUT[13:8] 0 0 0 AGC_VALUE[7:0] 0 DSP_RES R1K_10K
Read only Read and Write
Table 17: Read/Write data
D ata Content:
D ata only for read: • • • C ORDIC_OUT(13:0): 1 4 bit absolute angular position data. O CF ( O ffset C ompensation F inished): logic high indicates the finished Offset Compensation Algorithm. As soon as this bit is set, the AS5163 has completed the startup and the data is valid. C OF ( C ordic O ver f low): Logic high indicates an out of range error in the CORDIC part. When this bit is set, the C ORDIC_OUT(13:0) d ata is invalid. The absolute output maintains the last valid angular value. This alarm may be resolved by bringing the magnet within the X-Y-Z tolerance limits. A GC_VALUE (7:0) m agnetic field indication.
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D ata for write and read: • • D SP_RES r esets the DSP part of the AS5163 the default value is 0. This is active low. The interface is not affected by this reset. R 1K_10K d efines the threshold level for the OTP fuses. Can bit can be changed for verification purpose. A verification of the programming of the fuses is possible. The verification is mandatory after programming.
8 .5
• • • • • • • • • • • • • • •
P rogramming Procedure
P ull-up on out pin; V DD=5V; W ait startup time, device enters communication mode; W rite128 command: the trimming bits are written in the SFR memory; R ead128 command: the trimming bits are read back; U pload command: the SFR memory is transferred into the OTP RAM; F use command: the OTP RAM is written in the Poly Fuse cells. W ait fuse time (6 ms); W rite command (R1K_10K=1): Poly Fuse cells are transferred into the RAM cells compared with 10KOhm resistor; D ownload command: the OTP RAM is transferred into the SFR memory; R ead128 command: the fused bits are read back; W rite command (R1K_10K=0): Poly Fuse cells are transferred into the RAM cells compared with 1KOhm resistor; D ownload command: the OTP RAM is transferred into the SFR memory; R ead128 command: the fused bits are read back; P ass2Func command: go back in normal mode.
For Further information please refer to Application Note AN_AS5163-10.
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9
C hoosing the Proper Magnet
T he AS5163 works with a variety of different magnets in size and shape. A typical magnet could be 6mm in diameter and ≥2.5mm in height. Magnetic materials such as rare earth AlNiCo/SmCo5 or NdFeB are recommended. The magnetic field strength perpendicular to the die surface has to be in the range of ±30mT…±70mT (peak). The magnet’s field strength should be verified using a gauss-meter. The magnetic field B v a t a given distance, along a concentric circle with a radius of 1.1mm (R1), should be in the range of ±30mT…±70mT (see Figure 26).
typ. 6mm diameter
N
S
Magnet axis R1
Magnet axis
Vertical field component
N
S
R1 concentric circle; radius 1.1mm Vertical field component Bv (30…70mT)
0
36 0
360
F igure 26: Typical magnet (6x3mm) and magnetic field distribution
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9 .1
P hysical Placement of the Magnet
T he best linearity can be achieved by placing the center of the magnet exactly over the defined center of the chip as shown in the drawing below:
3.2 mm
1
3.2 mm
2.5 mm Defined center
Rd
2.5 mm Area of recommended maximum magnet misalignment
F igure 27: Defined chip center and magnet displacement radius
9 .2
M agnet Placement
T he magnet’s center axis should be aligned within a displacement radius R d o f 0.25mm (larger magnets allow more displacement) from the defined center of the IC. The magnet may be placed below or above the device. The distance should be chosen such that the magnetic field on the die surface is within the specified limits (see Figure 27). The typical distance “z” between the magnet and the package surface is 0.5mm to 1.5mm, provided the use of the recommended magnet material and dimensions (6mm x 3mm). Larger distances are possible, as long as the required magnetic field strength stays within the defined limits. However, a magnetic field outside the specified range may still produce usable results, but the out-of-range condition will be indicated by an alarm forcing the output into the failure band.
N
Die surface
S
Package surface
0.2299±0.100
0.2341±0.100
F igure 28: Vertical placement of the magnet
0.7701±0.150
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A S5163 12-BIT PROGRAMMABLE MAGNETIC ROTARY ENCODER
1 0 P ackage Drawings and Markings
1 4-Lead Thin Shrink Small Outline Package TSSOP-14
F igure 29: Package Dimensions and Marking
D imensions
mm S ymbol M in A A1 A2 b D E E1 e 0 .0 5 0 .8 0 . 19 4 .9 6 .2 4 .3 5 6 .4 4 .4 0 .65
T able 18: Package Dimensions
M arking: AYWWIZZ i nch A : Pb-Free Identifier M ax . 0 47 Y: Last Digit of Manufacturing Year WW: Manufacturing Week I: Plant Identifier ZZ: Traceability Code
T yp
M ax 1.2
M in
T yp
0 .10 1
0 . 15 1 .05 0 .30 5 .1 6 .6 4 .48
. 002 0 .031 0 .007 0 .193 0 .244 0 .169
. 00 4 0 .039 0 .197 0 .252 0 .173 . 0256
. 00 6 0 .041 0 .012 0 .201 0 .260 0 .176
JEDEC Package Outline Standard: M O - 153 T hermal Resistance R th(j-a) : 89 K/W in still air, soldered on PCB I C's marked with a white dot or the
1 1 O rdering Information
T he devices are available as standard products, shown in Table 19. M odel A S5163HTSU D escription 12 –Bit Programmable Magnetic Rotary Encoder
T able 19: Ordering Information
D elivery F orm Tubes
P ackage TSSOP 14
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1 2 R evision History
R evision D ate O wner D escription
1.1 1.2 2.02 2.1 2.2 2.3 2.4
04-Nov-2008 23-Feb-2009 19-May-2009 14-July-2009 05-Nov-2009 27-Nov-2009 10-Dec-2009
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First draft Timing in communication-protocol, corrections of OTP-table, new structure of chapters Draft for ES2 + Errata Sheet rename ALARM_DISABLE to EXT_RANGE, add Rev.History table Update of Digital Protocol (Chapter 7) Remove Digital Protocol (Chapter 7) Update of Benefits
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www.austriamicrosystems.com
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D isclaimer
D evices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
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