AS5215

Data Sheet AS5215 Programmable 360º Magnetic Angle Encoder with Buffered SINE & COSINE Output Signals 1 General Description The AS5215 is a redundant, contactless rotary encoder sensor for accurate angular measurement over a full turn of 360º and over an extended ambient temperature range of -40ºC to +150ºC. Based on an integrated Hall element array, the angular position of a simple two-pole magnet is translated into analog output voltages. The angle information is provided by means of buffered sine and cosine voltages. This approach gives maximum flexibility in system design, as it can be directly integrated into existing architectures and optimized for various applications in terms of speed and accuracy. With two independent dies in one package, the device offers true redundancy. Usually the bottom die, which is exposed to slightly less magnetic field is employed for plausibility check. An SSI Interface is implemented for signal path configuration as well as a one time programmable register block (OTP), which allows the customer to adjust the signal path gain to adjust for different mechanical constraints and magnetic field. 2 Key Features Contactless angular position encoding High precision analog output Buffered Sine and Cosine signals SSI Interface Low power mode Two programmable output modes: Differential or Single ended Wide magnetic field input range: 20 – 80 mT Wide temperature range: -40ºC to +150ºC Fully automotive qualified to AEC-Q100, grade 0 Thin punched 32-pin QFN (7x7mm) package 3 Applications The AS5215 is ideal for Electronic Power Steering systems and general purpose for automotive or industrial applications in microcontroller-based systems. Figure 1. AS5215 Block Diagram PROG OTP Register AS5215 Digital Part CS DCLK DIO SSI Interface POWER MANAGEMENT VDD VSS BUFFER Stage SINP/SINN SINN/SINP/CM_SIN BUFFER Stage Hall Array & Frontend Amplifier COSP/COSN COSN/COSP/CM_COS Note: This Block Diagram presents only one die. www.austriamicrosystems.com/AS5215 Revision 1.9 1 - 24 AS5215 Data Sheet - C o n t e n t s Contents 1 General Description .................................................................................................................................................................. 2 Key Features............................................................................................................................................................................. 3 Applications............................................................................................................................................................................... 4 Pin Assignments ....................................................................................................................................................................... 4.1 Pin Descriptions.................................................................................................................................................................................... 1 1 1 3 3 5 Absolute Maximum Ratings ...................................................................................................................................................... 6 Electrical Characteristics........................................................................................................................................................... 6.1 Timing Characteristics .......................................................................................................................................................................... 5 6 7 7 Detailed Description.................................................................................................................................................................. 7.1 Magnet Diameter and Vertical Distance ............................................................................................................................................... 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 8 8 The Linear Range ........................................................................................................................................................................ 8 Magnet Thickness...................................................................................................................................................................... 11 Axial Distance (Airgap) .............................................................................................................................................................. 12 Angle Error vs. Radial and Axial Misalignment.......................................................................................................................... 12 Mounting the Magnet ................................................................................................................................................................. 12 Summary ................................................................................................................................................................................... 14 8 Application Information ........................................................................................................................................................... 8.1 Sleep Mode ........................................................................................................................................................................................ 8.2 SSI Interface....................................................................................................................................................................................... 8.3 Device Communication / Programming .............................................................................................................................................. 8.4 Waveform – Digital Interface at Normal Operation Mode................................................................................................................... 8.5 Waveform – Digital Interface at Extended Mode ................................................................................................................................ 8.6 Waveform – Digital Interface at Analog Readback of the Zener Diodes ............................................................................................ 8.7 EasyZapp OTP Content ..................................................................................................................................................................... 8.8 Analog Sin/Cos Outputs with External Interpolator ............................................................................................................................ 8.9 OTP Programming.............................................................................................................................................................................. 15 15 15 16 18 18 19 19 20 21 9 Package Drawings and Markings ........................................................................................................................................... 10 Ordering Information............................................................................................................................................................. 22 24 www.austriamicrosystems.com/AS5215 Revision 1.9 2 - 24 AS5215 Data Sheet - P i n A s s i g n m e n t s 4 Pin Assignments Figure 2. Pin Assignments (Top View) DCLK_2 DCLK_1 VDD_2 VDD_1 CS_2 CS_1 NC 32 31 30 29 28 27 26 25 DIO_1 DIO_2 TC_1 TC_2 A_TST_1 A_TST_2 PROG_1 PROG_2 1 2 3 4 5 6 7 8 9 VSS_1 10 11 12 13 14 15 16 SINP_1 / SINN_1 VSS_2 COSN_1 / COSP_1 / CM_COS_1 SINP_2 / SINN_2 SINN_1 / SINP_1 / CM_SIN_1 SINN_2 / SINP_2 / CM_SIN_2 COSP_1 / COSN_1 24 23 22 NC NC NC NC NC NC COSN_2 / COSP_2 / CM_COS_2 COSP_2 / COSN_2 NC 21 20 19 18 17 AS5215 4.1 Pin Descriptions Table 1. Pin Descriptions Pin Name DIO_1 DIO_2 TC_1 TC_2 A_TST_1 A_TST_2 PROG_1 PROG_2 Pin Number 1 2 3 4 5 6 7 8 Data I/O for digital interface Test coil Analog test pin OTP Programming Pad Description www.austriamicrosystems.com/AS5215 Revision 1.9 3 - 24 AS5215 Data Sheet - P i n A s s i g n m e n t s Table 1. Pin Descriptions Pin Name VSS_1 VSS_2 SINP_1 / SINN_1 SINN_1 / SINP_1 / CM_SIN_1 SINP_2 / SINN_2 SINN_2 / SINP_2 / CM_SIN_2 COSP_1 / COSN_1 COSN_1 / COSP_1 / CM_COS_1 COSP_2 / COSN_2 COSN_2 / COSP_2 / CM_COS_2 NC NC NC NC NC NC NC NC VDD_1 VDD_2 DCLK_1 DCLK_2 CS_1 CS_2 Pin Number 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Digital + analog supply Clock input for digital interface Clock input for digital interface -----Supply ground Switchable buffered analog output Switchable buffered analog or common mode output Switchable buffered analog output Switchable buffered analog or common mode output Switchable buffered analog output Switchable buffered analog or common mode output Switchable buffered analog output Switchable buffered analog or common mode output Description www.austriamicrosystems.com/AS5215 Revision 1.9 4 - 24 AS5215 Data Sheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 6 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter Supply voltage (VDD) Input pin voltage (V_in) Input current (latchup immunity), I_scr Electrostatic discharge (ESD) Total power dissipation (Ptot) Package thermal resistance (Θ_JA) Storage temperature (T_strg) -65 Min -0.3 VSS - 0.5 -100 Max 7 7 100 ±2 275 27 150 Units V V mA kV mW ºC/W ºC Norm: IPC/JEDEC J-STD-020C. The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020C “Moisture/Reflow Sensitivity Classification for NonHermetic Solid State Surface Mount Devices”. The lead finish for Pb-free leaded packages is matte tin (100% Sn). MSL = 3 Velocity =0; Multi Layer PCB; Jedec Standard Testboard Norm: EIA/JESD78 Class II Level A Norm: JESD22-A114E Comments Package body temperature (T_body) 260 ºC Humidity non-condensing 5 85 % www.austriamicrosystems.com/AS5215 Revision 1.9 5 - 24 AS5215 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics Unless otherwise noted all in this specification defined tolerances of parameters are assured over the whole operation conditions range and also over lifetime. Table 3. Operating Conditions Symbol VDD VSS T_amb Parameter Positive Supply Voltage Negative Supply Voltage Ambient temperature Condition Min 4.5 0.0 -40 Typ Max 5.5 0.0 150 Unit V V ºC Table 4. DC/AC Characteristics for Digital Inputs and Outputs Symbol CMOS Input V_IH V_IL I_LEAK CMOS Output V_OH V_OL C_L t_slew t_delay CMOS Output Tristate I_OZ Tristate Leakage Current 1 µA High level Output voltage Low level Output Voltage Capacitive Load Slew Rate Time Rise Fall 4 mA 4 mA VDD 0.5 VSS + 0.4 35 30 15 V V pF ns ns High level Input voltage Low level Input Voltage Input Leakage Current 0.7 * VDD VDD 0.5 VDD + 0.5 VDD + 0.5 1 V V µA Parameter Condition Min Typ Max Unit Table 5. Magnetic Input Specification Symbol dMAG Bpp frot Parameter Diameter Magnetic input field amplitude Rotational speed 200 – 800 Gauss Max 30000 RPM Condition Min 4 20 0 Typ 6 50 80 500 Max Unit mm mt Hz Two pole cylindrical magnet, diametrically magnetized: Table 6. Electrical System Specifications Symbol IDD tpower_on tprop M Vout Parameter Current Consumption Power up time Propagation delay Magnetic Sensitivity Analog output range -40 to 150ºC 1G = 0.1 mT 18 1 Vss+ 0.25 22 Condition Max value derived at maximum I_H (Hall Bias Current) Note: For single die only. 1.275 30 6 Vdd0.5 ms µs mV/G V Min 20 Typ Max 28 Unit mA www.austriamicrosystems.com/AS5215 Revision 1.9 6 - 24 AS5215 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 6. Electrical System Specifications Symbol SF=SF25C - (AP1_1/ AP2_1) SF=AP1_ 1/AP2_1 Voffset1 Voffset2 DCoffdrift THD SR CLOAD Parameter Amplitude ratio tracking accuracy over temperature Amplitude ratio mismatch at room temperature DC Offset DC Offset Drift Total Harmonic Distortion Slew Rate Capacitive Load 1 1000 Ratiometric to VDD -40 to 150ºC Condition -40 to 150ºC Min -1 Typ Max +1 Unit % -2 0.294 0.49 -50 0.3 0.5 2 0.306 0.51 +50 0.2 % V / VDD V / VDD µV/ºC % V/µs pF 6.1 Timing Characteristics Table 7. Timing Characteristics Symbol t1_3 t2_3 t3 t4 t5 t6 t7 t8 t9_3 t10_3 t11 t12 t13_3 Parameter Chip select to positive edge of DCLK Chip select to drive bus externally Setup time command bit Data valid to positive edge of DCLK Hold time command bit Data valid after positive edge of DCLK Float time Positive edge of DCLK for last command bit to bus float Bus driving time Positive edge of DCLK for last command bit to bus drive Data valid time Positive edge of DCLK to bus valid Hold time data bit Data valid after positive edge of DCLK Hold time chip select Positive edge DCLK to negative edge of chip select Bus floating time Negative edge of chip select to float bus Setup time data bit at write access Data valid to positive edge of DCLK Hold time data bit at write access Data valid after positive edge of DCLK Bus floating time Negative edge of chip select to float bus Condition Min 30 0 30 15 DCLK/ 2+0 DCLK/ 2+0 DCLK/ 2+0 DCLK/ 2+0 30 15 Typ Max DCLK/ 2+0 DCLK/ 2+30 30 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Remark: The digital interface will be reset during the low phase of the CS signal. www.austriamicrosystems.com/AS5215 Revision 1.9 7 - 24 AS5215 Data Sheet - D e t a i l e d D e s c r i p t i o n 7 Detailed Description The AS5215 is a redundant rotary encoder sensor front end. Based on an integrated Hall element array, the angular position of a simple two-pole magnet is translated into analog output voltages. The angle information is provided by means of sine and cosine voltages. This approach gives maximum flexibility in system design, as it can be directly integrated into existing architectures and optimized for various applications in terms of speed and accuracy. With two independent dies in one package, the device offers true redundancy. Usually the bottom die, which is exposed to slightly less magnetic field is employed for plausibility check. An SSI (SPI standard) protocol is implemented for internal test access to the different circuit blocks and for signal path configuration. A One Time Programmable register block (OTP) allows the customer to adjust the signal path gain to adjust for different mechanical constraints and magnetic field strengths. Furthermore, for internal use, the test mode can be enabled and the system oscillator is trimmable, DC offset of the output signal can be set to either 1.5V or 2.5V. A unique chip ID is stored to ensure traceability. For operating point control, a band gap circuit is implemented together with a central bias block to distribute all reference bias currents for the analog signal conditioning. The digital signal part is based on a 2MHz system, CLK derived via. divider from a 4MHz system oscillator. Figure 3. Typical Arrangement of AS5215 and Magnet 7.1 Magnet Diameter and Vertical Distance Note: Following is just an abstract taken from the elaborate application note on the Magnet. For more detailed information, please visit our homepage www.austriamicrosystems.com → Magnetic Rotary Encoders → Magnet Application Notes 7.1.1 The Linear Range The Hall elements used in the AS5000-series sensor ICs are sensitive to the magnetic field component Bz, which is the magnetic field vertical to the chip surface. Figure 4 shows a 3-dimensional graph of the Bz field across the surface of a 6mm diameter, cylindrical NdFeB N35H magnet at an axial distance of 1mm between magnet and IC. The highest magnetic field occurs at the north and south poles, which are located close to the edge of the magnet, at ~2.8mm radius (see Figure 5). Following the poles towards the center of the magnet, the Bz field decreases very linearly within a radius of ~1.6mm. This linear range is the operating range of the magnet with respect to the Hall sensor array on the chip. For best performance, the Hall elements should always be within this linear range. www.austriamicrosystems.com/AS5215 Revision 1.9 8 - 24 AS5215 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 4. 3D-Graph of Vertical Magnetic Field of a 6mm Cylindrical Magnet BZ; 6mm magnet @ Z=1mm area of X- Y-misalignment from center: ±0.5mm circle of Hall elements on chip Bz [mT] Y -displacement [mm] X -displacement [mm] As shown in Figure 5 (grey zone), the Hall elements are located on the chip at a circle with a radius of 1mm. Since the difference between two opposite Hall sensors is measured, there will be no difference in signal amplitude when the magnet is perfectly centered or if the magnet is misaligned in any direction as long as all Hall elements stay within the linear range. www.austriamicrosystems.com/AS5215 Revision 1.9 9 - 24 AS5215 Data Sheet - D e t a i l e d D e s c r i p t i o n For the 6mm magnet (shown in Figure 5), the linear range has a radius of 1.6mm, hence this magnet allows a radial misalignment of 0.5mm (1.6mm linear range radius; 1mm Hall array radius). Consequently, the larger the linear range, the more radial misalignment can be tolerated. By contrast, the slope of the linear range decreases with increasing magnet diameter, as the poles are further apart. A smaller slope results in a smaller differential signal, which means that the magnet must be moved closer to the IC (smaller airgap) or the amplification gain must be increased, which leads to a poorer signal-to-noise ratio. More noise results in more jitter at the angle output. A good compromise is a magnet diameter in the range of 5…8mm. Small Diameter Magnet (6mm) + wider linear range = larger horizontal misalignment area - weaker differential signal = poorer signal / noise ratio, smaller airgaps Bz; 6mm magnet @ y=0; z=1mm Hall elements (side view) X -displacement [mm] www.austriamicrosystems.com/AS5215 Revision 1.9 Bz [mT] 10 - 24 AS5215 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.1.2 Magnet Thickness Figure 6 shows the relationship of the peak amplitude in a rotating system (essentially the magnetic field strength of the Bz field component) in relation to the thickness of the magnet. The X-axis shows the ratio of magnet thickness (or height) [h] to magnet diameter [d] and the Y-axis shows the relative peak amplitude with reference to the recommended magnet (d=6mm, h=2.5mm). This results in an h/d ratio of 0.42. Figure 6. Relationship of Peak Amplitude vs. Magnet Thickness B z amplitude vs. magnet thickness of a cylindrical diametric magnet with 6mm diameter 160% 140% Relative peak amplitude [%] 120% 100% 80% 60% 40% 20% 0% 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 1,8 thickness to diameter [h/d] ratio d= 6mm x h= 2.5mm ref. magnet: h/d = 0.42 Rel. amplitude = 100% As the graph in Figure 6 shows, the amplitude drops significantly at h/d ratios below this value and remains relatively flat at ratios above 1.3. Therefore, the recommended thickness of 2.5mm (at 6mm diameter) should be considered as the low limit with regards to magnet thickness. It is possible to get 40% or more signal amplitude by using thicker magnets. However, the gain in signal amplitude becomes less significant for h/ d ratios >~1.3. Therefore, the recommended magnet thickness for a 6mm diameter magnet is between 2.5 and ~8 mm. www.austriamicrosystems.com/AS5215 Revision 1.9 11 - 24 AS5215 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.1.3 Axial Distance (Airgap) Figure 7. Sinusoidal Magnetic Field Generated by the Rotating Magnet B vertical field 0 360º The recommended magnetic field, measured at the chip surface on a radius equal to the Hall sensor array radius (typ 1mm) should be within a certain range. This range lies between 45 and 75mT or between 20 and 80mT, depending on the encoder product. Linear position sensors are more sensitive as they use weaker magnets. The allowed magnetic range lies typically between 5 and 60mT. 7.1.4 Angle Error vs. Radial and Axial Misalignment The angle error is the deviation of the actual angle vs. the angle measured by the encoder. There are several factors in the chip itself that contribute to this error, mainly offset and gain matching of the amplifiers in the analog signal path. On the other hand, there is the nonlinearity of the signals coming from the Hall sensors, caused by misalignment of the magnet and imperfections in the magnetic material. Ideally, the Hall sensor signals should be sinusoidal, with equal peak amplitude of each signal. This can be maintained, as long as all Hall elements are within the linear range of the magnetic field Bz (see Figure 5). 7.1.5 Mounting the Magnet Generally, for on-axis rotation angle measurement, the magnet must be mounted centered over the IC package. However, the material of the shaft into which the magnet is mounted, is also of big importance. Magnetic materials in the vicinity of the magnet will distort or weaken the magnetic field being picked up by the Hall elements and cause additional errors in the angular output of the sensor. Figure 8. Magnetic Field Lines in Air Figure 8 shows the ideal case with the magnet in air. No magnetic materials are anywhere nearby. www.austriamicrosystems.com/AS5215 Revision 1.9 12 - 24 AS5215 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 9. Magnetic Field Lines in Plastic or Copper Shaft If the magnet is mounted in non-magnetic material, such as plastic or diamagnetic material, such as copper, the magnetic field distribution is not disturbed. Even paramagnetic material, such as aluminium may be used. The magnet may be mounted directly in the shaft (see Figure 9). Note: Stainless steel may also be used, but some grades are magnetic. Therefore, steel with magnetic grades should be avoided. Figure 10. Magnetic Field Lines in Iron Shaft If the magnet is mounted in a ferromagnetic material, such as iron, most of the field lines are attracted by the iron and flow inside the metal shaft (see Figure 10). The magnet is weakened substantially. This configuration should be avoided! www.austriamicrosystems.com/AS5215 Revision 1.9 13 - 24 AS5215 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 11. Magnetic Field Lines with Spacer Between Magnet and Iron Shaft If the magnet has to be mounted inside a magnetic shaft, a possible solution is to place a non-magnetic spacer between shaft and magnet, as shown in Figure 11. While the magnetic field is rather distorted towards the shaft, there are still adequate field lines available towards the sensor IC. The distortion remains reasonably low. 7.1.6 Summary Small diameter magnets (6 mm Ø) have a wider linear range and allow a wider lateral misalignment. The flatter slope requires shorter axial distances. The linear range decreases with airgap; Best performance is achieved at shorter airgaps. The ideal vertical distance range can be determined by using magnetic range indicators provided by the encoder ICs. These indicators are named MagInc, MagDec, MagRngn, or similar, depending on product. www.austriamicrosystems.com/AS5215 Revision 1.9 14 - 24 AS5215 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n 8 Application Information 8.1 Sleep Mode The target is to provide the possibility to reduce the total current consumption. No output signal will be provided when the IC is in sleep mode. Enabling or disabling sleep mode is done by sending the SLEEP or WAKEUP commands via. the SSI interface. Analog blocks are powered down with respect to fast wake up time. 8.2 SSI Interface The setup for the device is handled by the digital interface. Each communication starts with the rising edge of the chip select signal. The synchronization between the internal free running analog clock oscillator and the external used digital clock source for the digital interface is done in a way that the digital clock frequency can vary in a wide range. Table 8. SSI Interface Pin Description Port Chip select DCLK Bidirectional data input output Table 9. SSI Interface Parameter Description Symbol f_DCLK f_EZ_RW Parameter Clock frequency at normal operation Clock frequency at easy zap read write access Notes The nominal value for the clock frequency can be derived from a 10MHz oscillator source. Min no limit no limit Typ 5 5 Max 6 6 Unit MHz kHz Symbol CS DCLK DIO Function Indicates the start of a new access cycle to the device CS = LO → reset of the digital interface Clock source for the communication over the digital interface Command and data information over one single line The first bit of the command defines a read or write access f_EZ_PR OG Correct access to the programmable zener diode block needs a strict timing – the zap pulse is exact one period. Clock frequency at easy zap access program OTP The nominal value for the clock frequency can be derived from a 10MHz oscillator source. Clock frequency at easy zap analog readback 20pF external load allowed. The nominal value for the clock frequency can be derived from a 10MHz oscillator source. 200 - 650 kHz f_EZ_AR B no limit 156.3 162.5 kHz Interface General at normal mode Protocol: 5 command bit + 16 data input output Command Data Interface General at extended mode Protocol: 5 command bit + 46 data input output Command Data Interface Modes Normal read operation mode Extended read operation mode Normal write operation mode Extended write operation mode cmd = → 1 DCLK per data bit cmd = → 4 DCLK per data bit cmd = → 1 DCLK per data bit cmd = → 4 DCLK per data bit 5 bit command: cmd ← bit 34 bit data: data ← bit 5 bit command: cmd ← bit 16 bit data: data ← bit www.austriamicrosystems.com/AS5215 Revision 1.9 15 - 24 AS5215 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n 8.3 Device Communication / Programming Table 10. Digital Interface at Normal Mode # 23 16 command WRITE CONFIG 1 EN_PROG bin 10111 10000 mode write write 15 go2sleep 1 14 gen_rst 0 0 0 1 1 13 12 11 10 9 analog_sig 0 8 OB_bypassed 0 1 0 1 0 1 1 1 0 7 6 5 4 3 2 1 0 Name go2sleep gen_rst analog_sig OB_bypassed Generates global reset Functionality Enter/leave low power mode (no output signals) Switches the channels to the test bus after the PGA Disable and bypass output buffer for testing purpose Table 11. Digital Interface at Extended Mode Factory Settings # command bin mode otp test otp test otp test ID ID ID 10µbiastrim 10µbiastrim 10µbiastrim vref vref vref osc osc osc lock_O TP lock_O TP lock_O TP n.c. n.c. n.c. invert_ channel invert_ channel invert_ channel cm_sin cm_sin cm_sin User Settings cm_cos cm_cos cm_cos gain gain gain dc_ offset dc_ offset dc_ offset hall_ bias hall_ bias hall_ bias 31 WRITE OTP 25 PROG_OTP 15 RD_OTP 9 RD_OTP_ANA 11111 11001 01111 01001 xt write xt write xt read xt read Remark: 1. Send EN PROG (command 16) in normal mode before accessing the OTP in extended mode. 2. OTP assignment will be defined/updated. Name Otp_test ID n.c. 10µbiastrim vref osc lock_OTP invert_channel cm_sin cm_cos gain dc_offset Hall_b Dummy fuse bit used in production test Part identification Not connected 10µ bias current trim bits Bias Block reference voltage trim bits Oscillator trimming bits To disable the programming of the factory bits Inverts SIN and COS channel before the PGA for inverted output function (0...SIN/COS, 1...SINN/ COSN) Common mode voltage output enabled at SINN / CM pin (0...differential, 1...common) Common mode voltage output enabled at COSN / CM pin (0...differential, 1...common) PGA gain setting (influences overall magnetic sensitivity), 2bit Output DC offset (0…1.5V, 1…2.5V) Hall bias setting (influences overall magnetic sensitivity), 6bit Functionality www.austriamicrosystems.com/AS5215 Revision 1.9 16 - 24 AS5215 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n Figure 12. Sensitivity Gain Settings - Relative Sensitivity in % Magnetic Sensitivity vs. OTP Hall Current & PGA Gain Setting 600 550 500 Relative Sensitivity in % 450 400 350 300 250 200 150 100 0 10 20 30 40 50 60 Hall Current OTP setting (6 bits) M_PGA_00 M_PGA_01 M_PGA_10 M_PGA_11 The amplitude of the output signal is programmable via sensitivity (6bit) and/or gain (2bit) settings (see Figure 12). Figure 13. Sensitivity Gain Settings - Sensitivity [mV/mT] Magnetic Sensitivity vs. OTP Hall Current & PGA Gain Setting 70 60 50 Sensitivity [mV/mT] M_PGA_00 M_PGA_01 M_PGA_10 30 M_PGA_11 40 20 10 0 0 10 20 30 40 50 60 Hall Current OTP setting (6 bits) www.austriamicrosystems.com/AS5215 Revision 1.9 17 - 24 AS5215 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n 8.4 Waveform – Digital Interface at Normal Operation Mode Figure 14. Digital Interface at Normal Operation Mode CMD_PHASE DATA_PHASE DCLK t1_3 CS t2_3 DIO DIO CMD4 t3 t4 CMD3 CMD2 CMD1 CMD0 t6 D15 t11 t12 DIO D15 D14 D13 t5 t7 t8 D14 D13 t10_3 D0 t13_3 D0 WRITE CMD READ t9_3 8.5 Waveform – Digital Interface at Extended Mode In the extended mode, the digital interface needs four clocks for one data bit. During this time, the device is able to handle internal signals for special access (e.g. the easy zap interface). Figure 15. Digital Interface at Extended Mode CMD_PHASE DATA_PHASE DCLK t1_3 CS DIO DIO t2_3 CMD4 CMD3 CMD2 CMD1 t9_3 t5 CMD0 t7 t8 D45 D44 t12 D45 D44 D0 D0 t13_3 WRITE t10_3 CMD READ t3 t4 t11 t6 DIO www.austriamicrosystems.com/AS5215 Revision 1.9 18 - 24 AS5215 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n 8.6 Waveform – Digital Interface at Analog Readback of the Zener Diodes To be sure that all Zener-Diodes are correctly burned, an analog readback mechanism is defined. Perform the ‘READ OTP ANA’ sequence according to the command table and measure the value of the diode at the end of each phase. Figure 16. Digital Interface at Analog Readback of Zener Diodes CMD_PHASE EXT D45 DCLK EXT D44 DATA_PHASE_EXTENDED EXT D1 EXT D0 CS DIO CMD4 CMD3 CMD2 CMD1 CMD0 OTP D45 PROG OTP D44 OTP D43 OTP D0 perform analog measurements at PROG Table 12. Serial Bit Sequence (16-bit read / write) Write Command C4 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 Read / Write Data D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 8.7 EasyZapp OTP Content Each AS5215 die has an integrated 32-bit OTP ROM (Easyzapp) for trimming and configuration purposes. The PROM can be programmed via. the serial interface. For irreversible programming, an external programming voltage at PROG pin is needed. For security reasons, the factory trim bits can be locked by a lock bit. Name Hall Bias DC offset gain Lock invert_channel cm_sin cm_cos Bit Count 6 1 2 1 1 1 1 OTP Start 0 6 7 13 11 10 9 OTP End 5 6 8 13 11 10 9 Access user user user austriamicrosystems user user user Comments Sets overall sensitivity Output DC offset setting Programmable gain amplifier setting Set in production test Inverts SIN and COS channel before the PGA for inverted output function Common mode voltage output enabled at SINN / CM pin Common mode voltage output enabled at COSN / CM pin Remark: OTP assignment will be defined/updated. www.austriamicrosystems.com/AS5215 Revision 1.9 19 - 24 AS5215 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n 8.8 Analog Sin/Cos Outputs with External Interpolator Figure 17. Sine and Cosine Outputs for External Angle Calculation +5V VDD 100k VDD VDD PROG SINP_1/SINN_1 SINN_1/SINP_1/CM_SIN_1 SINP_2 / SINN_2 SINN_2/SINP_2/CM_SIN_2 AS5130 COSP_1/COSN_1 COSN_1/COSP_1/CM_COS_1 COSP_2/COSN_2 COSN_2/COSP_2/CM_COS_2 VSS DA AS5215 Micro Controller DA DA 100n DA VSS VSS Notes: 1. We recommend to use a 100k pull-up resistance. 2. Default conditions for unused pins are: DCLK_1/2, CS_1/2, DIO_1/2, TC_1/2, A_TST_1/2, TBO_1/2, TB1_1/2, TB2_1/2, TB3_1/2 connect to VSS The AS5215 provides analog Sine and Cosine outputs (SINP, COSP) of the Hall array front-end for test purposes. These outputs allow the user to perform the angle calculation by an external ADC + µC, e.g. to compute the angle with a high resolution. The output driver capability is 1mA. The signal lines should be kept as short as possible, longer lines should be shielded in order to achieve best noise performance. Through the programming of one bit, you have the possibility to choose between the analog Sine and Cosine outputs (SINP, COSP) and their inverted signals (SINN, COSN). Furthermore, by programming the bits you can enable the common mode output signals of SIN and COS. The DC bias voltage is 1.5 or 2.5 V. www.austriamicrosystems.com/AS5215 Revision 1.9 20 - 24 AS5215 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n 8.9 OTP Programming Figure 18. OTP Programming Connection +5V VDD VDD Output Output I/O Output Output I/O 8.0 - 8.5V CS_1 DCLK_1 DIO_1 CS_2 DCLK_2 DIO_2 VDD AS5130 AS5215 100n Micro Controller VSS PROG 10µF 100n VSS + - VSS maximum parasitic cable inductance L