AS8268

AS8267 / AS8268 Single-Phase 2-Current Energy Measurement Integrated Circuits with Microcontroller, RTC, Programmable Multi-Purpose I/Os, LCD Driver and On-Chip FLASH Memory D ATA SHEET 1 . Key Features - - M ains current lead/lag status indication for reactive energy measurement. L ow power battery operating mode for meter reading when Mains voltage is not present. A S8267: 20 x 4 segment LCDD 9 x multi-purpose I/O (MPIO) A S8268: 24 x 4 segment LCDD 12 x multi-purpose I/O (MPIO) P recision single-phase, one or two current input energy measurement front-end including SigmaDelta modulators for A/D-conversion and digital signal processor (DSP). L ow current consumption of 5mA, depending on MCU activity. D igital phase correction and selectable gain on both current channels for use with two current transformers (CT) or one CT and one shunt. P ower-supply monitor (PSM) for power-on reset and reset when the supply voltage falls below a defined threshold. C ustomer programmable 8-bit 8051 compatible microcontroller (MCU). P rogrammable MCU clock for optional low power operating conditions. H ighly reliable 32kBytes of non-volatile Flash memory is provided on-chip for storage of both program and data. P rogram and data security is provided by optional password and attack counter protection. 2 x U niversal Asynchronous Receiver / Transmitters (UART) for external communications such as programme download and debugging. P rogrammable watchdog timer (WDT) and external system reset pin. R eal-time clock/calendar (RTC) with on-chip digital calibration and separate battery supply pin. O n-chip temperature sensor for optional temperature compensation. O n-chip voltage reference (VREF) with small temperature coefficient (15ppm/K typ.). L ow power 3.0 – 4.0MHz crystal oscillator. S PI compatible interface for optional external non-volatile EEPROM memory selectable up to 32kBytes. - - - - - 2 . General Description T he AS8267 / AS8268 are highly integrated CMOS single-phase energy metering devices for fully electronic LCD meter systems. The AS8267 / AS8268 have been designed to ensure a meters full compliance with the international Standards IEC62052 and ANSI. The AS8267 / AS8268 ICs include all the functions required for conventional 1 current or 2-current anti-tamper meters. The functions include precision energy measurement, an 8-bit microcontroller unit (MCU) with 32kBytes of Flash memory, an on-chip Liquid Crystal Display driver (LCDD), programmable multi-purpose Inputs/Outputs (MPIO), a real time clock/calendar (RTC) for complex tariff functions such as time-of-use or maximum demand billing and a Serial Peripheral Interface (SPI) for reading data from and writing data to an optional external non-volatile memory (EEPROM). The AS8267 / AS8268 ICs have a dedicated energy measurement front-end, which includes an analog front-end and programmable Digital Signal Processor (DSP) from which active energy, mains voltage and mains current are provided. Reactive and apparent energy can also be calculated. The on-chip 8-bit 8051 compatible microcontroller is freely programmable and provides user access to the various functional blocks. The dedicated Universal Asynchronous Receiver / Transmitter (UART1) in the System Control block allows access to various system functions and blocks. A second UART (UART2) is also provided, which may for example be used for debugging. The on-chip memory includes 32kByte of highly reliable nonvolatile Flash program (and data) memory and - - - - - - - - - - - R evision 1.0, 19-Jun-07 Page 1 of 136 D ata Sheet AS8267 / AS8268 1 kByte volatile data memory. The meter system designer also has the option of an additional external EEPROM memory, which is selectable in size from 1kByte to 32kByte (in binary steps). Program and data stored in the on-chip non-volatile Flash memory can be secured by password protection, in addition to an attack counter which ‘locks’ access after 5 unauthorised attacks. An on-chip programmable watchdog timer (WDT) is available to automatically initiate a system reset if a regular ‘hold-off’ signal is not detected. The system timing and real time clock (RTC) has a dedicated external battery supply pin (VDD_BAT), enabling the oscillator and RTC to continue operation during ‘power-down’. The RTC may be digitally calibrated for oscillator frequency accuracy. The on-chip temperature sensor provides the meter designer the option of temperature compensation for any of the measured parameters or functional blocks provided, over the full operating temperature range of the device. The LCD Driver (LCDD) block enables the display of information provided by the microcontroller, directly to the LCD. Two dedicated data register banks are provided to simplify programming, particularly in the case where scrolled display data is required. The programmable multi-purpose I/O pins (MPIO) may be independently configured as inputs or outputs. All the I/O pins are programmable for data direction, pull-up/pull-down resistors and drive strength (4mA/8mA). Typical functions may include LED energy consumption pulse output, energy direction and fault condition indication depending on current 1 or current 2 being active for the energy calculation, push button for display scrolling, mains isolation relay control for prepayment meters, optical interface etc. An on-chip analog ground buffer (ABUF) and voltage reference (VREF) ensures that no external circuitry is required. A power-supply monitor (PSM) provides a reset, when VDD falls below a safe operating threshold. A reset pin (RES_N) is available for external system reset. The AS8267 / AS8268 ICs are available in LQFP64 plastic package. Revision 1.0, 19-Jun-07 Page 2 of 136 D ata Sheet AS8267 / AS8268 3 . Typical Application Circuit 3.3V 3.3V + + LCD 3.3V XIN XOUT 32 33 Low Power Oscillator VDDA 7 Low Power Divider 13 VDDD 22 LBP0 LBP1 LBP2 LBP3 kWh Vrms Irms 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 9 LSD0 LSD1 LSD2 LSD3 LSD4 LSD5 LSD6 LSD7 LSD8 LSD9 LSD10 LSD11 LSD12 LSD13 LSD14 LSD15 LSD16 LSD17 LSD18 LSD19 LSD20 LSD21 LSD22 LSD23 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 LED DIRO FAULT VDD_BAT 31 RTC System Timing & RTC LOAD I1P 3 Analog Front End LCD Driver SDM I1N I2N 4 6 SDM I2P VP 5 1 DSP MCU SDM VN RES_N 2 34 I/Os Examples only 10 11 WDT Temperature Sensor FLASH Memory Multipurpose I/Os 12 15 16 17 18 19 26 27 28 Push-Button Reference pulses for calibration AS8268 only System Control UART1 23 20 24 25 S_N MISO MOSI SC SPI 29 TXD VI VO 30 RXD 3.3V 8 VSSA 14 VSSD 21 VSSD EEPROM S1 Q 2 3.3V W 3 VSS 4 8 VCC 3.3V HOLD 3.3V 7 6C 5D + GND N L F igure 1: Typical application circuit of the AS8267 / AS8268 Revision 1.0, 19-Jun-07 AS8268 only Page 3 of 136 D ata Sheet AS8267 / AS8268 4 . Pin Out LSD19 LSD18 LSD17 LSD16 LSD15 LSD14 LSD13 LSD12 LSD11 LSD10 LSD23 LSD22 LSD21 LSD20 LSD19 LSD18 LSD17 LSD16 LSD15 LSD14 LSD13 LSD12 LSD11 LSD10 51 LSD9 LSD8 LSD9 50 64 63 62 61 60 59 58 57 56 55 54 53 52 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VP VN I1P I1N I2P I2N VDDA VSSA IO0 IO1 IO2 IO3 VDDD VSSD IO4 IO5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 LSD7 LSD6 LSD5 LSD4 LSD3 LSD2 LSD1 LSD0 LBP3 LBP2 LBP1 LBP0 n.c. n.c. RES_N XOUT VP VN I1P I1N I2P I2N VDDA VSSA IO0 IO1 IO2 IO3 VDDD VSSD IO4 IO5 49 LSD8 48 47 46 45 44 43 42 n.c. n.c. n.c. n.c. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 LSD7 LSD6 LSD5 LSD4 LSD3 LSD2 LSD1 LSD0 LBP3 LBP2 LBP1 LBP0 n.c. n.c. RES_N XOUT AS8267 LQFP64 41 40 39 38 37 36 35 34 33 AS8268 LQFP64 41 40 39 38 37 36 35 34 33 VDD_BAT IO6 IO7 IO8 IO9 IO10 MISO MOSI IO11 S_N VSSD TXD VDDD 5 . Pin Description Pin No. 1 2 3 Pin Name Pin Name AS8267 AS8268 VP VN I1P VP VN I1P Type AI AI AI Description Positive input for the voltage channel. VP is a differential input with VN. The typical differential voltage is ±100mV peak. Negative input for the voltage channel. VN is a differential input with VP. Positive input for the first current channel. I1P is a differential input with I1N. The input gain is programmable depending on the desired current sensor. The typical differential voltage is ±150mV peak (Gain = 4). Negative input for the first current channel. I1N is a differential input with I1P. The input gain is programmable depending on the desired current sensor. The typical differential voltage is ±150mV peak (Gain = 4). Positive input for the second current channel. I2P is a differential input with I2N. The input gain is programmable depending on the desired current sensor. The typical differential voltage is ±150mV peak (Gain = 4). Negative input for the second current channel. I2N is a differential input with I2P. The input gain is programmable depending on the desired current sensor. The typical differential voltage is ±150mV peak (Gain = 4). Positive supply voltage for the analog circuitry. The required supply voltage is 3.3V ±10%. Ground reference for the analog circuitry. Programmable multi-purpose input/output, with selectable pull-up or pull-down resistors and selectable drive strength. Programmable multi-purpose input/output, with selectable pull-up or pull-down resistors and selectable drive strength. 4 I1N I1N AI 5 I2P I2P AI 6 I2N I2N AI 7 8 9 10 VDDA VSSA IO0 IO1 VDDA VSSA IO0 IO1 S S DIO DIO Revision 1.0, 19-Jun-07 VDD_BAT VDDD VSSD MISO MOSI RXD RXD S_N TXD XIN XIN IO6 IO7 IO8 SC n.c. n.c. n.c. SC Page 4 of 136 D ata Sheet AS8267 / AS8268 Pin No. 11 12 13 14 15 16 17 18 19 20 Pin Name Pin Name AS8267 AS8268 IO2 IO3 VDDD VSSD IO4 IO5 IO6 IO7 IO8 MISO IO2 IO3 VDDD VSSD IO4 IO5 IO6 IO7 IO8 MISO Type DIO DIO S S DIO DIO DIO DIO DIO Description Programmable multi-purpose input/output, with selectable pull-up or pull-down resistors and selectable drive strength. Programmable multi-purpose input/output, with selectable pull-up or pull-down resistors and selectable drive strength. Positive supply voltage to the digital circuitry and is internally connected to pin 22. The required supply voltage is 3.3V ±10%. Ground reference for the digital circuitry. Programmable multi-purpose input/output, with selectable pull-up or pull-down resistors and selectable drive strength. Programmable multi-purpose input/output, with selectable pull-up or pull-down resistors and selectable drive strength. Programmable multi-purpose input/output, with selectable pull-up or pull-down resistors and selectable drive strength. Programmable multi-purpose input/output, with selectable pull-up or pull-down resistors and selectable drive strength. Programmable multi-purpose input/output, with selectable pull-up or pull-down resistors and selectable drive strength. DIOPD Serial peripheral interface (SPI): Serial Data input in Master mode Serial Data output in Slave mode S S Ground reference for the digital circuitry. Positive digital supply. VDDD provides the positive supply voltage to the digital circuitry and is internally connected to pin 13. The required supply voltage is 3.3V ±10%. 21 22 VSSD VDDD VSSD VDDD 23 24 S_N MOSI S_N MOSI DIOPU Serial peripheral interface (SPI): Chip select DIOPD Serial peripheral interface (SPI): Serial Data output in Master mode Serial Data input in Slave mode DIOPU Serial peripheral interface (SPI): Serial clock DIO DIO DIO DO DIPU S AI AO Programmable multi-purpose input/output, with selectable pull-up or pull-down resistors and selectable drive strength. Programmable multi-purpose input/output, with selectable pull-up or pull-down resistors and selectable drive strength. Programmable multi-purpose input/output, with selectable pull-up or pull-down resistors and selectable drive strength. Universal Asynchronous Receiver/Transmitter (UART1) serial transmit data output. Universal Asynchronous Receiver/Transmitter (UART1) serial receive data input. Battery backup supply voltage input for the real time clock (RTC). A 3.0 to 4.0MHz crystal may be connected across XIN and XOUT. Alternatively, an external clock signal may be applied to XIN. See XIN above, for the connection of a crystal. When an external clock is applied to XIN, XOUT is not connected. System reset active low. Not connected 25 26 27 28 29 30 31 32 33 34 35 SC n.c. n.c. n.c. TXD RXD SC IO9 IO10 IO11 TXD RXD VDD_BAT VDD_BAT XIN XOUT RES_N n.c. XIN XOUT RES_N n.c. Revision 1.0, 19-Jun-07 Page 5 of 136 D ata Sheet AS8267 / AS8268 Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name Pin Name AS8267 AS8268 n.c. LBP0 LBP1 LBP2 LBP3 LSD0 LSD1 LSD2 LSD3 LSD4 LSD5 LSD6 LSD7 LSD8 LSD9 LSD10 LSD11 LSD12 LSD13 LSD14 LSD15 LSD16 LSD17 LSD18 LSD19 n.c. n.c. n.c. n.c. n.c. LBP0 LBP1 LBP2 LBP3 LSD0 LSD1 LSD2 LSD3 LSD4 LSD5 LSD6 LSD7 LSD8 LSD9 LSD10 LSD11 LSD12 LSD13 LSD14 LSD15 LSD16 LSD17 LSD18 LSD19 LSD20 LSD21 LSD22 LSD23 Type Description Not connected AO AO AO AO AO AO AO AO AO AO AO AO AO AO AO AO AO AO AO AO AO AO AO AO AO AO AO AO LCD back-plane driver output signal. LCD back-plane driver output signal. LCD back-plane driver output signal. LCD back-plane driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. LCD segment driver output signal. N ote: Shaded pins above only available with AS8268 IC PIN Types: S AI AO DIPU DO DIO DIOPD DIOPU Supply pin Analog Input pin Analog Output pin Digital Input pin with pull-up resistor Digital Output pin Programmable Digital Input or Output pin Digital Input or Output pin with pull-down resistor Digital Input or Output pin with pull-up resistor Revision 1.0, 19-Jun-07 Page 6 of 136 D ata Sheet AS8267 / AS8268 T able of Contents 1. 2. 3. 4. 5. 6. K ey Features .........................................................................................................................................1 G eneral Description ...............................................................................................................................1 T ypical Application Circuit ......................................................................................................................3 P in Out..................................................................................................................................................4 P in Description ......................................................................................................................................4 E lectrical Characteristics........................................................................................................................8 6 .1 A bsolute Maximum Ratings (Non-Operating) ......................................................................................8 6 .2 O perating Conditions ........................................................................................................................8 6 .3 D C/AC Characteristics for Digital Inputs and Outputs..........................................................................9 6 .4 E lectrical System Specification ........................................................................................................ 10 P erformance Graphs ............................................................................................................................ 12 D etailed Functional Description ............................................................................................................ 15 8 .1 E nergy Measurement Front End (Including DSP) .............................................................................. 17 8 .2 T emperature Sensor ....................................................................................................................... 50 8 .3 L CD Driver (LCDD) ......................................................................................................................... 52 8 .4 P rogrammable Multi-Purpose I/Os (MPIO) ........................................................................................ 57 8 .5 S erial Peripheral Interface (SPI) ...................................................................................................... 67 8 .6 E xternal EEPROM Requirements ..................................................................................................... 78 8 .7 F LASH Memory............................................................................................................................... 83 8 .8 8 051 Microcontroller (MCU) ............................................................................................................. 90 8 .9 S ystem Control (SCT) ................................................................................................................... 110 8 .10 S erial Interface – UART1 ............................................................................................................... 118 C ircuit Diagram.................................................................................................................................. 127 7. 8. 9. 1 0. P arts List........................................................................................................................................... 128 1 1. P ackaging ......................................................................................................................................... 130 1 2. P roduct Ordering Guide ..................................................................................................................... 130 1 3. C ollection of Formulae ....................................................................................................................... 131 1 4. T erminology ...................................................................................................................................... 135 1 5. R evision ............................................................................................................................................ 136 1 6. C opyright .......................................................................................................................................... 136 1 7. D isclaimer ......................................................................................................................................... 136 1 8. C ontact ............................................................................................................................................. 136 Revision 1.0, 19-Jun-07 Page 7 of 136 D ata Sheet AS8267 / AS8268 6 . Electrical Characteristics 6 .1 Absolute Maximum Ratings (Non-Operating) S tresses beyond the ‘Absolute Maximum Ratings’ may cause permanent damage to the AS8267 / AS8268 ICs. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under ‘Operating Conditions’ is not implied. C aution: E xposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter DC supply voltage Input pin voltage Electrostatic discharge Storage temperature Lead temperature profile Humidity non-condensing Symbol VDD Vin ESD Tstrg Tlead 5 85 % -55 Min -0.3 -0.3 Max +5.0 VDD+0.3 1000 125 Unit Notes V V V °C Norm: IPC/JEDEC-020C Norm: MIL 883 E method 3015 6 .2 Operating Conditions Symbol VDDA VSSA A-D VDDD VSSD VDD_BAT Tamb Isupp fosc 3.0 Min 3.0 0 -0.1 3.0 0 2.0 -40 3.3 25 5 3.579545 4.0 3.3 Typ 3.3 Max 3.6 0 0.1 3.6 0 3.6 85 Unit V V V V V V °C mA MHz Depending on MCU activity VDDA – VDDD VSSA – VSSD Notes Parameter Positive analog supply voltage Negative analog supply voltage Difference of supplies Positive digital supply voltage Negative digital supply voltage Battery supply voltage Ambient temperature Supply current System clock frequency Revision 1.0, 19-Jun-07 Page 8 of 136 D ata Sheet AS8267 / AS8268 6 .3 DC/AC Characteristics for Digital Inputs and Outputs C MOS Input with Schmitt Trigger and Pull-up Resistor (RXD, RES_N) Parameter High level input voltage Low level input voltage Low level input current Symbol VIH VIL IIL -100 Min 0.7 x VDD 0.3 x VDD -15 Typ Max Unit V V µA Tested at VDD=3.6V and Vin=0V Notes C MOS Output (TXD) Parameter High level output voltage Low level output voltage High level output current Low level output current Symbol VOH VOL IOH IOL -4 Min 2.5 0.4 4 Typ Max Unit V V mA mA Notes Tested at VDD=3.0V Tested at VDD=3.0V Tested at VDD=3.0V and Vout=VOH Tested at VDD=3.0V and Vout=VOL M PIO Inputs with Pull-up or Pull-down Resistor (SC, S_N, MISO, MOSI) Parameter High level input voltage Low level input voltage High level output voltage Low level output voltage High level output current Low level output current Pull-up High level input leakage Low level input current Pull-down High level input leakage Low level input current IIH IIL 100 -1 15 1 µA µA Tested at VDD=Vin=3.6V; ‘pull-down’ Tested at VDD=3.6V and Vin=0V IIH IIL -1 -100 1 -15 µA µA Tested at VDD=Vin=3.6V Tested at VDD=3.6V and Vin=0V; ‘pull-up’ Symbol VIH VIL VOH VOL IOH IOL -4 2.5 0.4 4 Min 0.7*VDD 0.3*VDD Max Unit Notes V V V V mA mA Note: VOH, VOL, IOH and IOL are tested at VDD=3.0V. IOL is tested at Vout=VOL IOH is tested at Vout=VOH Revision 1.0, 19-Jun-07 Page 9 of 136 D ata Sheet AS8267 / AS8268 M PIO Inputs with Schmitt Trigger and Selectable Pull-up/Pull-down Parameter High level input voltage Low level input voltage High level input current Low level input current Symbol VIH VIL IIH IIL 15 -100 Min 0.7 x VDD 0.3 x VDD 100 -15 Typ Max Unit V V µA µA Tested at VDD=3.6V and Vin=3.6V; ‘pull-down’ Tested at VDD=3.6V and Vin=0V; ‘pull-up’ Notes M PIO Outputs with Programmable Drive Strength Parameter High level output current Low level output current High level output current Low level output current High level output current Low level output current Symbol VOH VOL IOH IOL IOH IOL -8 -4 8 Min 2.5 0.4 4 Typ Max Unit V V mA mA mA mA Notes Tested at VDD=3.0V Tested at VDD=3.0V If ‘4mA’ is selected. Tested at VDD=3.0V and Vout=VOH If ‘4mA’ is selected. Tested at VDD=3.0V and Vout=VOL If ‘8mA’ is selected. Tested at VDD=3.0V and Vout=VOH If ‘8mA’ is selected. Tested at VDD=3.0V and Vout=VOL L CDD Outputs T he Liquid Crystal display driver (LCDD) outputs are specified in the LCD Driver section of this data sheet. 6 .4 Electrical System Specification Symbol |VVP| |VI1P|, |VI2P| |VI1P|, |VI2P| |VI1P|, |VI2P| fmains DR(I) DR(P) 45 600:1 2000:1 0.1 err(dr) 0.2 % % Reading 1) Min Typ 100 150 38 30 Max 212 212 54 42 65 Unit mVp mVp mVp mVp Hz Notes Referenced to VSSA Referenced to VSSA Referenced to VSSA Referenced to VSSA Parameter Input Signals Voltage channel input voltage Current channel input voltage (Gain=4) Current channel input voltage (Gain=16) Current channel input voltage (Gain=20) Mains frequency Dynamic range current Dynamic range power Accuracy Error variation over dyn. range Revision 1.0, 19-Jun-07 Page 10 of 136 D ata Sheet AS8267 / AS8268 Parameter Error variation over temperature Error variation over cos(phi) Error variation with VDD Output pulse jitter Mains voltage Measured current Measurement bandwidth Symbol err(temp) err(cosphi) err(VDD) J Vmains Imax BW Min Typ Max 0.5 0.5 0.2 0.1 264 120 Unit % % % % V(rms) A(rms) kHz Notes Within operating temperature range, 1) From 1 to 0.5, 1) 1) 2) 240V + 10%, 3) 3) 1.75 Notes: 1) Errors determined during energy measurement using a demo board and a reference meter with high accuracy (0.05%), which calculates the actual error. 2) Difference between largest and smallest error of 20 successive error samples; maximum meter constant: 1,600i/kWh; reference meter: 10,000 x DUT-meter-constant; measured at 5% Ib, Ib and I max . 3) What is used for system considerations/calculations. Revision 1.0, 19-Jun-07 Page 11 of 136 D ata Sheet AS8267 / AS8268 7 . Performance Graphs 0.3 0.3 0.2 0.2 0.1 0.1 Error [%] Gain 4 0 Gain 20 Error [%] 0 Gain 16 -0.1 -0.1 Gain 16 Gain 20 Gain 4 -0.2 -0.2 -0.3 0.01 0.1 1 10 100 I [A] -0.3 0.01 0.1 I [A] 1 10 100 G raph 1: 0.3 Error as a % of reading for gain setting 4, 16, 20 – Channel l1 G raph 2: 0.3 Error as a % of reading for gain setting 4, 16, 20 – Channel I2 0.2 0.2 0.1 0.1 290V 230V 0 230V Error [%] Error [%] 290V 0 170V -0.1 -0.1 170V -0.2 -0.2 -0.3 0.01 0.1 I [A] 1 10 100 -0.3 0.01 0.1 I [A] 1 10 100 G raph 3: Error as a % of reading with mains voltage variation – Channel I1 G raph 4: Error as a % of reading with mains voltage variation – Channel I2 0,3 0.3 0,2 0.2 3V6 0,1 0.1 Error [%] Error [%] 3V6 0 3V3 3V3 0 -0,1 -0.1 3V0 3V0 -0,2 -0.2 -0,3 0,01 0,1 I [A] 1 10 100 -0.3 0.01 0.1 I [A] 1 10 100 G raph 5: Error as a % of reading with variation in VDD – Channel I1 G raph 6: Error as a % of reading with variation in VDD – Channel I2 Revision 1.0, 19-Jun-07 Page 12 of 136 D ata Sheet AS8267 / AS8268 0.5 0.4 0.3 0.2 0.1 0 -0.1 0.5 0.4 0.3 0.2 PF=-0.8 0.1 Error [%] Error [%] PF=0.5 PF=1.0 0 -0.1 PF=0.5 -0.2 -0.2 PF=1.0 -0.3 -0.4 -0.5 0.01 -0.3 -0.4 -0.5 0.01 PF=-0.8 0.1 I [A] 1 10 100 0.1 I [A] 1 10 100 G raph 7: Error as a % of reading for PF=1, PF=-0.8, PF=0.5 at -40°C – Channel I1 G raph 8: Error as a % of reading for PF=1, PF=-0.8, PF=0.5 at -40°C – Channel I2 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.01 0.5 0.4 0.3 PF=0.5 PF=1.0 0.2 0.1 0 -0.1 PF=-0.8 -0.2 -0.3 -0.4 -0.5 0.01 PF=1.0 PF=0.5 Error [%] PF=-0.8 Error [%] 0.1 1 10 100 0.1 1 10 100 I [A] I [A] G raph 9: Error as a % of reading for PF=1, PF=-0.8, PF=0.5 at 25°C – Channel I1 G raph 10: Error as a % of reading for PF=1, PF=-0.8, PF=0.5 at 25°C – Channel I2 0.5 0.4 0.3 PF=0.5 0.5 0.4 0.3 PF=0.5 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.01 0.2 0.1 Error [%] PF=1.0 Error [%] 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.01 PF=1.0 PF=-0.8 PF=-0.8 0.1 1 10 100 I [A] 0.1 I [A] 1 10 100 G raph 11: Error as a % of reading for PF=1, PF=-0.8, PF=0.5 at 85°C – Channel I1 G raph 12: Error as a % of reading for PF=1, PF=-0.8, PF=0.5 at 85°C – Channel I2 Revision 1.0, 19-Jun-07 Page 13 of 136 D ata Sheet AS8267 / AS8268 0.3 0.3 0.2 0.2 0.1 0.1 Error [%] Error [%] 0 0 -0.1 -0.1 -0.2 -0.2 -0.3 0.01 0.1 I [A] 1 10 100 -0.3 0.01 0.1 1 10 100 I [A] G raph 13: Error as a % of reading using vconst for mains voltage value – Channel I1 G raph 14: Error as a % of reading using vconst for mains voltage value – Channel I2 0.3 0.3 0.2 0.2 0.1 0.1 Error [%] Error [%] HP_off 0 HP_off 0 -0.1 HP_on -0.1 HP_on -0.2 -0.2 -0.3 58 60 62 -0.3 58 60 62 F [Hz] F [Hz] G raph 15: Error as a % of reading with variation in line frequency – Channel I1 G raph 16: Error as a % of reading with variation in line frequency – Channel I2 N ote: All measurements taken for the compilation of the graphs above were made using a reference meter design using the application circuit depicted on page 3 of this data sheet and incorporating the AS8267 / AS8268 integrated circuits. For all graphical measurements, where the temperature was not specified, measurements were made at ambient (25 °C). Revision 1.0, 19-Jun-07 Page 14 of 136 D ata Sheet AS8267 / AS8268 8 . Detailed Functional Description T he AS8267 / AS8268 integrated circuits have a dedicated measurement front end, which is capable of measuring active and reactive energy, RMS mains voltage, RMS mains current as well as power factor. There are two completely separate differential current channel inputs, for measurement of both the Live and Neutral currents. The two current inputs may be connected to a shunt resistor (I1) and a current transformer (I2). Both current channels have programmable gains; thus it is possible to connect the shunt resistor to any of the two differential current inputs. The option to use two current transformers is also available. The AS8267 / AS8268 ICs may be programmed to accept either of the two measured currents for the energy calculation, or may be programmed to accept the larger of the two currents for the energy calculation. The AS8267 / AS8268 ICs may also be used for conventional 1-phase single current measurement applications, where only the Live current is measured. In this case, the I2P and I2N pins are left unconnected and the second current channel modulator can be powered down. The voltage channel input for measurement of the line voltage is also differential and is connected to a tap of a resistive divider of the line voltage. The resistive divider can be set to accommodate any line voltage standard (V mains ) including 100V, 110V, 220V, 230V or 240V. A 3.0 to 4.0MHz low power oscillator generates the system clock for the AS8267 / AS8268 ICs. The absolute clock frequency may be calibrated on-chip. A low power divider is used to generate a 1Hz clock for the on-chip real time clock/calendar (RTC). The supply voltage to the low power oscillator, the low power divider and the RTC may be buffered with an external battery in case of mains power drops or failures. The integrated temperature sensor can be used to compensate for temperature drift of the quartz crystal to improve measurement accuracy. The LCD driver (LCDD) signals LSD0 … LSD23 and LBP0 … LBP3 can be directly connected to a liquid crystal display (LCD), which is used to display the various measured parameters. A total of 80 LCD segments may be driven by the AS8267 IC and 96 segments may be driven by the AS8268 IC. A maximum of 12 programmable multi-purpose input/output (MPIO) pins are available for various meter functions, for example light-emitting diodes (LED) to signal energy consumption, energy direction, fault condition, etc. These I/O pins may also be programmed for use as bi-directional communication channels such as an optical interface or an additional Universal Asynchronous Receiver/Transmitter (UART2) Interface, should it so be required. The AS8267 has 9 x MPIO pins, while the AS8268 has 12 x MPIO pins. A dedicated Serial Peripheral Interface (SPI) which can be configured as master or slave is also provided. In master mode an external EEPROM (1kByte up to 32kByte) with a compatible serial peripheral interface can be connected if required. In slave mode the interface allows direct access to the internal Flash memory. The on-chip 8051 compatible microcontroller performs all the required calculations and enables the user to customize the input and output configuration of the meter. The microcontroller has a 1kB data memory, a square root calculation facility and a second UART (UART2) for debugging purposes. The highly reliable 32kByte Flash memory allows storage of program and data. With the integrated security concept Flash Data can be protected against unauthorised access. The security concept offers password protection as well as an attack counter which blocks the Flash after five unauthorised attacks. Revision 1.0, 19-Jun-07 Page 15 of 136 D ata Sheet AS8267 / AS8268 A p rogrammable watchdog timer is provided to automatically initiate a system reset when a regular hold-off signal is not detected by the watchdog timer. The watchdog timer is an optional function which is software enabled. A dedicated serial Universal Asynchronous Receiver/Transmitter (UART1) Interface within the System Control is provided to communicate with the AS8267 / AS8268 ICs and perform all the required programming and reading of data, especially during the meter production process. The AS8267 / AS8268 ICs supply voltages (2 x VDDD and VDDA) are typically 3.3 Volts. These supply voltages should be derived from the V mains w ith the use of a standard voltage regulated power supply circuit. An on-chip power supply monitor (PSM) ensures that a reset is generated independently of the supply voltage rise and fall times. Monitoring of the V mains i s provided to ensure early power-down detection. A reset pin (RES_N) is also available for external system reset. The RES_N pin can be left unconnected if not required. The individual functional elements of the AS8267 / AS8268 ICs, as well as the relationships between the various functional blocks are shown in the following block diagram. A detailed description of the AS8267 / AS8268 ICs system and the flexibility available to the kWh meter designer, through the system programmability is also described below: XIN XOUT LBP3 ... 0 LSD 23 ... 0 VDD_ BAT VP VN I1P I1N I2P I2N RXD TXD SC S_N MOSI MISO Analog Front End IO 11 ... 0 DSP UART 1 F igure 2: AS8267 / AS8268 block diagram Revision 1.0, 19-Jun-07 Page 16 of 136 D ata Sheet AS8267 / AS8268 8 .1 Energy Measurement Front End (Including DSP) T he Energy Measurement Front End is made up of the analog front end and the digital signal processing block (DSP), which performs the active energy measurement calculations for the microcontroller. The analog front end comprises of the three Sigma-Delta modulators for the sampling of the mains voltage, Line current and a second current channel, for the optional measurement of the Neutral current. Also included in the analog front end is the voltage reference, which provides the temperature stability to the Sigma-Delta modulators. Setting up for the optimum input conditions for the voltage and current channels is also described in this section. The digital signal processing block (DSP) provides the filtering and processing of the output data from the sigma-delta modulators and ensures that the specified measurement accuracy is provided by the AS8267 / AS8268. The DSP offers programming of measurement parameters and provides for fast and efficient meter production calibration procedures. A power supply monitor (PSM) ensures that a reset is generated independently of the rise and fall times of the supply voltage (VDD). The PSM is also described in this section. A nalog Front End T he analog front end comprises of three identical Sigma-Delta modulators, which convert the differentially connected analog voltage and current inputs into digital signals. The two current inputs are gain adjustable to accommodate both directly connected or galvanically isolated current sensors. The on-chip voltage reference (VREF) is the most important contributor to the accuracy of the AS8267 / AS8268 ICs due to it providing temperature stability to the circuit. Considering that the voltage and current signals are multiplied to derive the energy value, errors introduced prior to multiplication function results in errors being multiplied. Thus the introduction of errors into the voltage and the current channel inputs will result in a doubling of the percentage error after multiplication at the energy output. The temperature coefficient of the VREF is specified at 15 ppm/K typical (30 ppm/K max.). C urrent Inputs for Energy Calculation T he AS8267 / AS8268 ICs have 2 identical current inputs, I1P/I1N and I2P/I2N, for measurement of both the Live and Neutral currents. Either of the two current inputs may be selected for calculating the energy value. These two differential current inputs are second order Sigma-Delta modulators, with each of the inputs being provided with selectable gains of 4, 16 and 20. The selectable gains are provided so that the AS8267 / AS8268 ICs may be easily adapted for use with either 2 current transformers or alternatively a shunt resistor and a current transformer for current sensing. The AS8267 / AS8268 ICs may also be used in a conventional single current configuration with either a current transformer or shunt resistor being used for current sensing. The current input signal levels may be programmed by means of on-chip programmable gain settings. The required gain setting is selected as follows: Revision 1.0, 19-Jun-07 Page 17 of 136 D ata Sheet AS8267 / AS8268 C urrent Input Gain Settings G ain 20 16 4 20 16 4 I nput Voltage - 30mV ≤ V I1P ≤ 30mV -38mV ≤ V I1P ≤ 38mV - 150mV ≤ V I1P ≤ 150mV -30mV ≤ V I2P ≤ 30mV -38mV ≤ V I2P ≤ 38mV - 150mV ≤ V I2P ≤ 150mV C omments S hunt mode; default setting CT mode or shunt mode CT mode Shunt mode CT mode or shunt mode C T mode; default setting C urrent Inputs I1P, I1N C urrent Inputs I2P, I2N N otes: 1) Refer to the Settings Register (SREG) in the DSP section for programming of the Gain Settings. For optimum operating conditions, the input signal at the Maximum Current (I max ) condition should be set at ± 30mVp, when the Gain = 20, or ± 150mVp, when the Gain = 4. The default Gain, the AS8267 / AS8268 ICs current input gain settings without any programming required, is Gain = 20 for the I1 input and Gain = 4 for the I2 input. The value of an ideal shunt resistor, may be calculated as follows: Assuming an I max r ating of 60A (rms) → 8 4.85A (peak), then a shunt value of 350µ Ω w ould be suitable. Rshunt = 30mVp 84.85 A p = 354μΩ t hus a standard 350µ Ω s hunt resistor may be selected. The mains currents are sampled at 3.4956kHz, assuming that the recommended crystal oscillator frequency of 3.5795MHz, is used. The current transformer(s) must be terminated with a voltage setting resistor (R VS ) to ensure the optimum voltage input level to the current input(s) of the AS8267 / AS8268 ICs. The value of R VS i s calculated as follows: R VS = Vin (p ) IL 2 = C T RMS secondary current at rated conditions (V m ains ; I max ) w here I L V in(p) = T he peak input voltage to the IC at rated conditions (V mains ; I max ). For example, if Gain = 4, V in(p) s hould be set at 150mVpeak. Example: A current transformer is specified at 60A/24mA and the Gain = 4: R VS = Vin (p ) IL 2 = 150mV 24mA 2 = 4.42Ω ⇒ 4.3Ω t hus a 4.3 Ω B urden resistor may be selected Revision 1.0, 19-Jun-07 Page 18 of 136 D ata Sheet AS8267 / AS8268 V oltage Input for Energy Calculation T he voltage channel input consisting of inputs VP and VN which are differential, with VP connected to the tap of a resistor divider circuit of the line voltage and VN connected to VSSA. For optimum operating conditions, the input signal at VP should be set at 100mVp for the rated voltage condition. The resistor values for an ideal voltage divider may be calculated as follows: Assuming a V mains o f 230V (rms) → 3 25V (peak) and R2 = 470 Ω ( according to the voltage divider shown below), the value of R1A+R1B may be calculated as follows: Vmains R1A+R1B R2 Vin R1A + R1B = R2 × ( Vmains − Vin(P) ) Vin(P) = 470Ω × 325 V − 100mV = 1.53MΩ 100mV t hus R1A = 820k Ω a nd R1B = 750k Ω r esistors may be selected. The mains voltage is also sampled at 3.4956kHz, assuming that the recommended crystal oscillator frequency of 3.5795MHz is used. D igital Signal Processing Block (DSP) T he digital signal processing (DSP) block provides the signal processing required to ensure that the specified measured accuracy is performed and that the microcontroller (MCU) is provided with the appropriate data and protocol to perform all the required meter functions. For the description below, please refer to the following block diagram (Figure 3). The DSP makes allowance for phase correction of the two current channels (i1 and i2) within the Sinc d ecimation filters in the phase correction block. The applicable phase correction setting (pcorr_i1 or pcorr_i2) is selected (sel_i), depending upon which current (i1 or i2) is being used for the power calculation. The equalization filters on the voltage and current channels which may be by-passed (sel_equ), correct for the attenuation introduced by the decimation filters at the edge of the input frequency band, while the high pass filters, which may also be by-passed (sel_hp), eliminate any DC offsets introduced into the input channels. Independent calibration of the voltage (cal_v) and current signals (cal_i1 and cal_i2) is done after the voltage and current signals are provided for power calculation. This ensures that calibration of the voltage (sos_v), current channel 1 (sos_i1), current channel 2 (sos_i2) has no influence on the power (np) calibration. 3 Revision 1.0, 19-Jun-07 Page 19 of 136 D ata Sheet AS8267 / AS8268 T he iMux (current multiplexer) allows the selection of the applicable current for power calculation (sel_i), while the vMux (voltage multiplexer) allows the selection of either the mains voltage data, or a constant voltage value, vconst (sel_v). The multiplication of the appropriately selected voltage and current signals is then performed. After multiplication, the next multiplexer (sel_p) enables the selection of either instantaneous power or real power, which is derived through low pass filtering, PLP. The direction indicator output (diro) is derived from the output of the power low pass filter (PLP). The following multiplexer (creep) allows the selection of the power signal, or blocks the power signal, depending on the required anti-creep and starting current thresholds, which may be set in the microcontroller. Only when constant voltage value (vconst) is selected by the vMux (voltage multiplexer) or when diro=1, it is necessary to derive the absolute power value, for measurement (Abs). The first pulse generator (Fast Pulse Gen) produces fast internal pulses, with the number of pulses being proportional to the measured energy. The multiplexer enables the selection of the appropriate pulse level (pulselev_i1 or pulselev_i2) depending on the current being used for energy measurement (sel_i). The output of the Fast Pulse Gen is always directly proportional to the LED pulse output, generated in the LED Pulse Gen. The LED output pulse rate is selectable (mconst). The polarity of the LED output pulses is also selectable (ledpol). To ensure that the power data transferred to the microcontroller (MCU) is identical to that of the LED pulses, the power accumulator (P_ACCU) counts the pulses generated by the Fast Pulse Gen. After a defined number of sampling periods (nsamp), an interrupt is sent to the MCU, for the MCU to collect the accumulated energy data. Revision 1.0, 19-Jun-07 Page 20 of 136 D ata Sheet AS8267 / AS8268 pddeton Registers PD_DET alarm v ADC P hase Correction Equ Filter HP Filter X Square Accu sos_v cal_v i1 ADC Equ Filter HP Filter X Square Accu sos_i1 cal_i1 i2 ADC Equ Filter sel_equ HP Filter sel_hp sel_i X Square Accu sos_i2 cal_i2 vconst Mux sel_i iMux vMux sel_v pcorr_i1 pcorr_i2 X PLP Flash memory is reserved for external interface and MCU remains halted. 3. Send one or several Flash commands (Flash must not be busy before sending the next Flash command) 4. Release Flash request (Clear REQ bit in FLASH_STAT register) -> MCU is running again Request is needed for all Flash commands Concurrent access of both MCU independent interfaces is not allowed. Revision 1.0, 19-Jun-07 Page 72 of 136 D ata Sheet AS8267 / AS8268 R ead The SPI_Flash is selected by pulling S_N low. The 8-bit read instruction is transmitted to the SPI_Flash followed by the 16-bit address with the MSB (address[15]) of the address word being don’t care. After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the MOSI pin. (After an access time of 13 system clocks the Flash data is available in the SPI transit register). The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (7FFFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. Rising the S_N pin terminates the read operation. T iming S_N 0 SC Instruction 16 Bit Address 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 MISO 0 0 0 0 0 0 1 1 15 14 13 12 2 1 0 Data Out MOSI High Impedance 7 6 5 4 3 2 1 0 E xample Read FLASH Sequence 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 0x01 0x04 0x05 0x03 0x00 0x80 Dat0 Dat1 … 0x01 0x00 … … set REQ bit by writing 0x04 to status register … -“… read Flash status register until Flash is ready … read Flash instruction … Start address, e.g. 80h … -“… read byte 0 from address … read byte 1 from address + 1 … read bytes as long as you want, after address overrun it restarts at address 0. … clear REQ bit by writing 0x00 to status register … -“- P age Program The whole memory of 32K bytes is split into 512 pages with 64 bytes per page. Each page can be written with 64 bytes at once or, it can be written byte-wise or in groups of bytes. The addressing order is arbitrary. Prior to any attempt to write data to the SPI_Flash or status register, the write enable latch must be set by issuing the WREN instruction. Setting S_N low and then clocking out the proper instruction into the SPI_Flash does this. After all eight bits of the instruction are transmitted; the S_N must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without S_N being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Once the write enable latch is set, the user may proceed by setting the S_N low, issuing a write instruction, followed by the address, and then the data to be written. Up to 64 bytes of data can be sent to the SPI_Flash before a program cycle is necessary. The only restriction is that all of the bytes must reside in the same page. An address consists of a page address (9 bits) and the address in page (6 bits), where the page address = address [15:6] and the address in page is address [5:0]. If the internal address counter reaches 0x7FFF and the clock continues, the counter will roll over to the first address 0x0000. Revision 1.0, 19-Jun-07 Page 73 of 136 D ata Sheet AS8267 / AS8268 For the data to be actually written, the S_N must be brought high after the least significant bit (D0) of the n data byte has been clocked in. If S_N is brought high at any other time, the write operation will not be completed. While the write is in progress, the status register may be read to check the status. A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset. th B yte Write S_N TWC 0 SC 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 Instruction 16 Bit Address Data Byte MISO 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0 MOSI High Impedance P age Program (max. 64 bytes) S_N 0 SC Instruction 16 Bit Address Data Byte 1 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 MISO 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0 S_N 32 SC Data Byte 2 Data Byte 3 Data Byte n (64 max) 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 MISO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 E xample PROG Page Sequence 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 0x01 0x04 0x05 0x06 0x02 0x00 0x80 Dat0 Dat1 … 0x01 0x00 … set REQ bit by writing 0x04 to status register … -“… read Flash status register until Flash is ready … set Flash write enable … write Flash instruction … Start address, e.g. 80h … -“… put byte 0 to address … put byte 1 to address + 1 … max. 64 bytes (page size), then repeat sequence from step 2. … clear REQ bit by writing 0x00 to status register … -“- Revision 1.0, 19-Jun-07 Page 74 of 136 D ata Sheet AS8267 / AS8268 W rite Enable Sequence S_N 0 SC 1 2 3 4 5 6 7 MISO 0 0 0 0 0 1 1 0 MOSI High Impedance W rite Disable Sequence S_N 0 SC 1 2 3 4 5 6 7 MISO 0 0 0 0 0 1 0 0 MOSI High Impedance R ead Status Register W rite Status Register Revision 1.0, 19-Jun-07 Page 75 of 136 D ata Sheet AS8267 / AS8268 P age Erase Instruction Address S_N SC MISO MOSI 0 1 2 3 4 5 6 7 8 9 10 11 19 20 21 22 23 1 1 0 1 1 0 0 0 15 14 13 12 11 4 3 2 1 0 High Impedance M ass Erase R eset S erial Input Timing (MOSI) TCSD S_N TCSS TR TF TCSH TCLD TCLE SC TSU THD MISO MSB In High Impedance LSB In MOSI Revision 1.0, 19-Jun-07 Page 76 of 136 D ata Sheet AS8267 / AS8268 S erial Output Timing (MISO) S_N THI TLO TCSH SC TV THO TDIS MISO MSB Out LSB Out MOSI Don’t Care T iming Characteristics P arameter S _N Setup Time S _N Hold Time S _N Disable Time D ata SetupTime D ata Hold Time S C Rise Time S C Fall Time S C High Time S C Low Time S C Delay Time S C Enable Time O utput Valid from Clock Low O utput Hold Time O utput Disable Time S ymbol T CSS T CSH T CSD T SU T HD TR TF T HI T LO T CLD T CLE TV T HO T DIS M in 1 00 1 50 5 00 30 50 1 50 1 50 50 50 0 - M ax 2 2 1 50 2 00 U nit ns ns ns ns ns ns ns ns ns ns ns ns ns ns N ote Revision 1.0, 19-Jun-07 Page 77 of 136 D ata Sheet AS8267 / AS8268 8 .6 External EEPROM Requirements A n external EEPROM with SPI bus serial interface is used for non-volatile program and data storage. The SPI master block that communicates with the EEPROM is specified above. This section explains the requirement for Serial EEPROMs. It shows the most important figures and tables as a reference. For the details please turn to the data sheet of your specifically applied EEPROM. The following minimum requirements must be fulfilled: P ins T here must be at least the typical SPI pins like serial data input (EEP_SI), serial data output (EEP_SO) serial clock input (EEP_SC), chip select input (EEP_S_N) C lock Rate T he applicable clock rate pin EEP_SC must be ≥ 1 MHz. S tatus Register m ust look like this: B it 0 must be the WIP bit, indicating that a write operation is in progress. Only this bit is polled during the EEPROM upload, means programming of the EEPROM. The Status register can be accessed via the RDSR instruction. D ata Protection T he write protection block size is given in the table below: S tatus Register Bits B P1 0 0 1 1 P rotected Block N one U pper quarter U pper half W hole memory B P0 0 1 0 1 A rray Addresses Protected E xample only None 6000h – 7FFFh 4000h – 7FFFh 0000h – 7FFFh N ote: The array addresses must be referenced from the data sheet of the specific EEPROM used. BP1, BP0 allows the selection of one out of 4 protection schemes. Revision 1.0, 19-Jun-07 Page 78 of 136 D ata Sheet AS8267 / AS8268 I n order to protect against inadvertent programming the user can see these bits. Please note that the protected range of EEPROM cannot be overwritten via an SCT command there anymore. Reprogramming must be done with a dedicated program then. I nstruction Set Instruction Name READ WRITE Instruction Description Format 03h 02h Read data from memory starting with selected address Write data to memory beginning at selected address. Most EEPROMs allow page writing of pages 16, 32, 64 or even more bytes for faster device programming. Before every page write operation a WREN instruction must be applied – see also bootloading and uploading sequence for details. Write enable EEPROM, enables write operation Read EEPROM Status register Write disable EEPROM, disable write operation Write EEPROM Status register WREN RDSR WRDI WRSR 06h 05h 08h 01h S PI Modes T hese devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: - C POL = 0, CPHA = 0 - C POL = 1, CPHA = 1 (It is recommended to set CPOL = 1, CPHA = 1 in your program: The build-in bootloader uses this setting as well.) For these two modes, input data is latched in on the rising edge of Serial Clock (SC), and output data is issued on the falling edge of Serial Clock (SC). The recommended mode is shown in Figure 11. The clock polarity SC is ‘1’ when the bus master is in Stand-by mode and not transferring data (idle state): - S C remains at 1 for (CPOL = 1, CPHA = 1) 1 1 E EP_SC(in) EEP_SI(in) EEP_SO(out ) F igure 11: SPI modes recommended Revision 1.0, 19-Jun-07 Page 79 of 136 D ata Sheet AS8267 / AS8268 A ddress Roll Over W hen the highest address on the EEPROM is reached, e.g. 7FFFh for a 32kB device, then the address counter must roll over to 0000h. U nused Upper Address Bits U nused upper address bits must be ignored in any case. E.g. an 8kB device has a maximum address of 1FFFh must interpret 7FFFh as 1FFFh, ignoring the higher bits. E xample Pin List Pin Name EEP_S_N Type Input Functionality Chip select, active low Description When this input signal is High, the device is deselected and Serial Data Output (SO) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Standby mode. Driving Chip Select (S_N) Low enables the device, placing it in the active power mode. This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (SC). This input signal is used to transfer data serially into the device. It receives instructions, addresses and the data to be written. Values are latched on the rising edge of Serial Clock (SC). This input signal provides the timing of the serial interface. Instructions, addresses or data present at Serial Data Input (SI) are latched on the rising edge of Serial Clock (SC). Data on Serial Data Output (SO) changes after the falling edge of Serial Clock (SC). EEP_SO EEP_SI Output Input Serial data output Serial data input EEP_SC Input Serial clock EEP_WP_N 1) Input Write protect, active low The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status register). This pin must be driven either High or Low and must be stable during all write operations. Hold, active low The Hold (HOLD_N) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial Clock (SC) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S_N) driven Low. EEP_HOLD_N 1) Input EEP_VCC EEP_VSS Supply Positive supply voltage Supply Negative supply voltage N ote: 1) No Write Protect (EEP_WP_N) and Hold (EEP_HOLD_N) pins are available on the AS8267 / AS8268 ICs. These pins must be tied ‘high’ directly at the EEPROM device. Revision 1.0, 19-Jun-07 Page 80 of 136 D ata Sheet AS8267 / AS8268 I nstructions Timings W rite Enable (WREN) E EP_S_N(in) EEP_SC(in) EEP_SI(in) EEP_SO(out ) F igure 12: Write enable (WREN) sequence R ead Status Register (RDSR) E EP_S_N(in) EEP_SC(in) EEP_SI(in) EEP_SO(out ) F igure 13: Read Status register (RDSR) sequence R ead from Memory Array (READ) E EP_S_N(in) EEP_SC(in) E EP_SI(in) EEP_SO(out ) F igure 14: Read from memory array (READ) sequence Revision 1.0, 19-Jun-07 Page 81 of 136 D ata Sheet AS8267 / AS8268 W rite to Memory Array (WRITE) E EP_S_N(in) EEP_SC(in) E EP_SI(in) EEP_SO(out ) F igure 15: Byte write (WRITE) sequence E EP_S_N(in) E EP_SC(in) E EP_SI(in) EEP_S_N(in) E EP_SC(in) E EP_SI(in) F igure 16: Page write (WRITE) sequence Revision 1.0, 19-Jun-07 Page 82 of 136 D ata Sheet AS8267 / AS8268 8 .7 FLASH Memory T he AS8267 / AS8268 provide a 32kByte Flash Memory for program and data. This Flash is organised in 512 pages with 64Bytes each. When the memory is erased all bytes are 0x00. To speed up writing to the Flash Memory, a page write mode is available. A page program writes the data in the addressed memory page. It is also possible to write parts of a page or a single byte. Data that has not been addressed remains unchanged. Before data can be written to the memory, the addressed page or the whole memory must be erased. A mass erase sets all bit cells in the memory to logic ‘0’. A page erase sets all bit cells of an addressed page to logic ‘0’. The Flash memory can be accessed via System Control in UART1 or the SPI_Flash commands. F LASH Registers Register Name FLASH_STAT FLASH_ATTACK Address 9700h 9701h Reset Value 0rra.0000 000s.ssss Note 1) 1) Note: 1) rr and s.ssss status bits are copied from Flash memory during boot sequence ‘a‘ is dependent of LOCK bit after reset. If LOCK bit is set then ‘a‘ becomes 0 (access denied) otherwise ‘a‘ becomes 1 and access is granted. F LASH Status Register MSB C PU_PE Bit 7 6 LOCK ATK_EN ACCESS_EN REQ WEL LSB WIP Symbol CPU_PE Function 5 4 3 2 1 0 N ote: CPU page erase, triggers a page erase process of the Flash on next CPU write access. Must be cleared by CPU afterwards (Not to be used by UART1) (read/write) Locks the Flash memory against unauthorized read access from outside using LOCK SET_PW(f7h) or SET_PW1(f8h) command via UART1. Stored in Flash memory (nonvolatile) (read only) Enables the attack counter using SET_PW1 (f8h) command via UART1. Stored in Flash ATK_EN memory (non-volatile) (read only) ACCESS_EN Grant access to Flash if password entered correctly (read only) REQ WEL WIP Not used External Flash Request (Not to be used by CPU due to dead lock!) (read/write) Write enable latch (only writeable by SPI “WREN” command) Write in progress (read only) The WIP bit is set as soon as a Write, Page Erase or Mass Erase command is sent and reset when the Flash is ready again. Revision 1.0, 19-Jun-07 Page 83 of 136 D ata Sheet AS8267 / AS8268 F LASH Attack Register If enabled by the ATK_EN bit in the Flash status register, the attack register logs any unauthorized access to the device and stores it in the Flash memory. After five attacks the device disables the UART1 interface forever. MSB Bit 7 6 5 4 3 2 1 0 - - A5 A4 A3 A2 LSB A1 Symbol A5 A4 A3 A2 A1 Function N ot used N ot used N ot used 5 th a ttack 4 attack 3 2 1 rd nd st th a ttack a ttack a ttack W henever the password is not entered correctly and the attack counter is enabled one bit of the attack register is set and its copy is updated in the Flash memory. D ata Organisation in the FLASH Memory 1. 2. 3. 4. 5. 6. 7. 8. Program data are stored beginning at address 0000h. Program data size must not be bigger than 32768 – 16 (0000h – 7FEFh). The length of the program is stored at the two topmost bytes. For the 32k Flash memory this means: Length (takes 2 bytes) is stored at 7FFE to 7FFFh. The 8byte password is stored at 7FF0h to 7FF7h. Non-volatile Flash status flags are located at 7FF8h to 7FF9h. Meter data and system parameters are stored in the remaining memory space. The allocation of memory space is totally up to the MCU program. The program data will not be protected against overwriting processes from the MCU program. In case there is no program stored in the Flash (boot loader detects all 0s or all 1s at the program length address) the boot loader forces the MCU to loop on address 0 (“SJMP $”, Hex code: 80FEh). F LASH Timing Parameter P rogram time E rase time Typ 6.75 3.39 Unit ms ms Note fclk = 3.58MHz fclk = 3.58MHz Revision 1.0, 19-Jun-07 Page 84 of 136 D ata Sheet AS8267 / AS8268 F LASH Memory Reliability T he 32kByte Flash memory implemented in the AS8267 / AS8268 ICs provide an outstanding performance in respect to data retention time and endurance. Endurance is the parameter that specifies the cumulative write/erase cycles of the memory cells within the Flash memory. The data retention time of a Flash memory is a critical end-of-life parameter. This parameter specifies the maximum period of time, after programming, that data can be expected to be retrieved valid from the memory. According to the JEDEC A117 specification the Flash memory has a minimum endurance of 100,000 cycles and a retention time of 500 years at 65°C. D ata Retention EEPROM austriamicrosystems AG Ea=0.6eV 300 275 250 225 200 Retention [Years] 175 150 125 100 75 50 25 0 75 85 95 105 115 125 135 145 Junction Temperature [°C] F LASH Security T he AS8267 / AS8268 comprise of two different possibilities to protect Flash content against copying and manipulation. The detailed implementation will be explained in this chapter. Revision 1.0, 19-Jun-07 Page 85 of 136 D ata Sheet AS8267 / AS8268 G eneral Description B ased on the software development flow it only makes sense to lock the software after the development is finished. Therefore we can distinguish between access to the Flash during the software development and access to the Flash after the development is finished. The protection is implemented in such a way that the external Flash memory access (UART1, SPI via SPI_Flash) is blocked. A ccess during Software Development D uring the development phase of the meter software each external access to the Flash must be enabled. This means that the listed commands are enabled R EAD W RITE Byte W RITE Page P AGE ERASE M ASS ERASE A ccess after Software Development A fter the completion of the software development there are two possible modes of protecting the Flash content. a) Protection via PASSWORD If this mode is selected the listed commands are disabled: R EAD W RITE Byte W RITE Page P AGE ERASE M ASS ERASE b) Protection via PASSWORD and ATTACK COUNTER If this mode is selected the listed commands are disabled and the Attack Counter is enabled: R EAD W RITE Byte W RITE Page P AGE ERASE M ASS ERASE Revision 1.0, 19-Jun-07 Page 86 of 136 D ata Sheet AS8267 / AS8268 B lock Diagram T he block diagram shows the main block involved in the security concept. According to the block diagram there are four possibilities to get access to the internal Flash memory. 1. Access via UART1 In this mode program/data can be read from or written in the Flash using commands defined in the SCT (System Control). Access via SPI_FLASH Interface In this mode program/data can be read from or written to the Flash using the SPI_Flash interface. This path also includes a command interpreter which is able to handle different Flash access commands. Please refer to the SPI section in this document. To use this mode the SPI interface must be configured as slave (SPI_Flash). Access via SPI2 Interface In this mode it is not possible to directly access the Flash memory from extern due to the missing command interpreter. A direct access to the Flash therefore would only be possible if there would be a program available in the mcu doing the command interpretation. Access via UART2 In this mode there is also no command interpreter in the communication path, so that a direct access to Flash is not possible. 2. 3. 4. The Flash memory access via UART1 or SPI_Flash interface is an external Flash memory access and therefore protected by password. The Flash memory access via SPI2 interface or UART2 interface is an internal Flash memory and therefore not protected by password. The protection of this path is up to the user. Revision 1.0, 19-Jun-07 Page 87 of 136 D ata Sheet AS8267 / AS8268 P assword Protection I f the protection schema “Protection via PASSWORD” is selected the listed commands are disabled: R EAD W RITE Byte W RITE Page P AGE ERASE M ASS ERASE The password is entered via the SET_PW command (instruction code F7h in the UART1 command interpreter) followed by the 8byte password. RXD TXD 0 1 2 3 4 5 6 7 D0 D1 D7 SET_PASSWORD CMD 8 bytes 0 1 2 3 4 5 6 7 ACK / NACK O nce a password is entered it is encrypted and stored in the Flash memory. At the same time the Flash memory ‘LOCK’ bit (bit6) is set in Flash status register (9700h). When ‘LOCK’ bit is set the top page of the Flash memory (storage of program length, password, non-volatile status flags) is blocked for page erase and write access even when access is granted. This also guarantees that the protection remains even the device is powered down and powered up again. Based on the blocked write access of the top page of the Flash memory it is not possible to change an existing password. A new password can only be assigned after a MASS ERASE. Once the correct password is entered the listed commands are enabled again. If the device memory is blank (e.g. after FAB-out) the access to the Flash memory is open and no password is required. P assword + Attack Counter Protection I f the protection schema “Protection via PASSWORD and ATTACK COUNTER” is selected the listed commands are disabled: R EAD W RITE Byte W RITE Page P AGE ERASE M ASS ERASE The password is entered in this case via the SET_PW1 command (instruction code F8h in the UART1 command interpreter) followed by the 8byte password. Revision 1.0, 19-Jun-07 Page 88 of 136 D ata Sheet AS8267 / AS8268 RXD TXD 0 1 2 3 4 5 6 7 D0 D1 D7 SET_PASSWORD CMD 8 bytes 0 1 2 3 4 5 6 7 ACK / NACK I n this mode the ATK_EN bit (bit5) is enabled in the Flash status register (9700h), and the attack register logs any unauthorized access to the device and stores it in the Flash memory. Also in this mode once a password is entered it is encrypted and stored in the Flash memory. At the same time the Flash memory ‘LOCK’ bit (bit6) is set in Flash status register. When ‘LOCK’ bit is set the top page of the Flash memory (storage of program length, password, non-volatile status flags) is blocked for page erase and write access even when access is granted. This also guarantees that the protection remains even the device is powered down and powered up again. Based on the blocked write access of the top page of the Flash memory it is not possible to change an existing password. A new password can only be assigned after a MASS ERASE. Once the correct password is entered the listed commands are enabled again. In case an incorrect password is entered the Attack Counter is increased. After five attacks the UART1 will be disabled by switching off the internal clock for the UART1. In this state the device is locked forever. If the device memory is blank (e.g. after FAB-out) the access to the Flash memory is open and no password is required. To give the user the possibility of reusing a blocked device he has to implement special functionality in his software. The following example describes a possible implementation. M onitoring of one of the non blocked interfaces (SPI2 or UART2) within the customer specific MCU software I f a specific (defined by the developer) sequence is applied the MCU can perform a page erase of the up most page (holds also program length) in the Flash memory. A fter a reset the device will now start with its default parameters and will not perform an automatic program load via the boot loader. I n this operating mode it is than possible to write the program length again into the Flash memory. Also a new password can be entered. A fter a reset the meter will work again and also stored metering data can be accessed. M CU Access to the FLASH Memory T he listed commands are available for the MCU access. R EAD W RITE Byte P AGE ERASE Initiation of a PAGE ERASE by the MCU the CPU_PE bit in the FLASH Status Register (9700h) has to be set. After this a WRITE command with the selected address has to be performed. After completion of the page erase procedure the CPU_PE bit has to be cleared by the MCU. Revision 1.0, 19-Jun-07 Page 89 of 136 D ata Sheet AS8267 / AS8268 8 .8 8051 Microcontroller (MCU) T he MCU is a derivative of the well-known 8051 microcontroller. The MCU block consists of an 8051 compatible microprocessor core, Flash memory, data memory (X_RAM), squareroot calculation unit and two UARTs for debugging and communication purposes. The Special Function Registers (SFR) section enfolds the standard blocks like the 16 bit timer (Timer 0), 128 bytes of internal data memory (I_RAM) and a serial interface (UART1). Furthermore, a squareroot block and a second serial interface (UART2) are also provided. Timer 1, Port 0 to 3 and the UART are not implemented exactly the same as in the original 8051. Instead, the bus extension (Port 0, 2 on single chip 8051) provides access to on-chip periphery, which comprises a serial peripheral interface (SPI), a real time clock (RTC), nine general purpose I/Os (MPIO), the LCD driver (LCDD), the DSP block that interfaces to the analog front end and system control registers (SCT). The MCU block is configured as Von Neumann architecture with the program in the Flash memory staring from 0000h and the data memory (X_RAM) and periphery section starting from 8000h up to FFFFh. All 64kB of memory can be accessed with both, the MOVC instruction (for program fetches and data read) and the MOVX instruction (for data read/store). The interrupt controller enfolds 7 internal interrupt sources, for having all necessary peripherals already on chip. Optional Serial EEPROM LC Display Internal Interrupt Sources MCU Interrupt Control 128 bytes I_RAM Timer 0 32kB FLASH SPI M/S LCDD RTC Temperature Sensor CPU Clock Divider SQRT UART2 1kB X_RAM UART1 SCT MPIO DSP Mclk rxd2 txd2 I/Os AFE RXD TXD F igure 17: MCU block diagram L egend C PU ................ 8051 compatible microcontroller core I_RAM ............. 128 bytes static RAM, range 00h to 7Fh of 8051 X_RAM ............ 1024 bytes static RAM, (extended) memory for data storage FLASH ............ 32kB Flash memory, primarily for program storage, maybe used also for data Timer 0............ 16 bit timer (due to 8051 standard) UART1 ............ serial interface RS232 (due to 8051 standard) with extended baudrate generator UART2 ............ serial interface RS232 with extended baudrate generator SQRT .............. square root calculation out of 5 bytes (40 bits) input, 2.5 bytes (20 bits) output Revision 1.0, 19-Jun-07 Page 90 of 136 D ata Sheet AS8267 / AS8268 S PI.................. serial peripheral interface, used to access an external EEPROM LCDD .............. LCD driver block RTC ................ real time clock, time/data may be set via UART1 (SCT) MPIO............... multi-purpose I/O pins, configurable inputs and outputs DSP ................ digital signal processing unit interfaces to analog front end (AFE) AFE................. analog front end, includes amplifiers and A to D converters SCT ................ system control unit, combined with UART1 used for debugging/programming of the device K ey Features - 8 051 compatible 8 bit oriented microcontroller core 1 28 bytes of internal data memory (I_RAM) 3 2kB Flash memory 1 kB data memory (X_RAM) V on Neumann architecture, shared program and data memory C ycle optimized compared to standard 8051, some instructions are executed in a single clock cycle 1 28 bytes of SFR range S tandard SFRs: Timer 0, UART1 (with 16 baudrate reg.) S pecific SFRs: UART2 (with 16 bit baudrate reg.), SQRT block F ully compatible 8051 instruction set including DA, MUL and DIV instruction 7 i nternal interrupt sources P orts P0, P1, P2, P3 are not implemented P 0 and P2 are accessible as registers R egister PCON is not implemented N o idle mode via PCON A utomatic bootload of application program after power-on reset 6 c lock cycles per instruction (12 cycles in standard 8051) 1 d ata pointer DPTR Revision 1.0, 19-Jun-07 Page 91 of 136 D ata Sheet AS8267 / AS8268 I nstruction Set T he instruction set is fully compatible to the 8051 standard. This allows the use of commonly available software development tools for A51 Assembler, C-Compiler and code simulators. The instructions marked with the note 2) a re cycle optimised and execute in a single cycle compared to two cycles in standard 8051 controllers. H ex C ode 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F M nemonic NOP AJMP LJMP RR INC INC INC INC INC INC INC INC INC INC INC INC JBC ACALL LCALL RRC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC JB AJMP RET RL ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD A O perands B /C 1) H ex C ode 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F M nemonic JNB ACALL RETI RLC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC JC AJMP ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL JNC ACALL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL A O perands bit addr, code addr code addr B /C 1) 1/1 code addr code addr A A dir @R0 @R1 R0 R1 R2 R3 R4 R5 R6 R7 bit addr, code code addr code addr A A dir @R0 @R1 R0 R1 R2 R3 R4 R5 R6 R7 bit addr, code code addr 2/2 3/2 1/1 1/1 2/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 3/2 2/2 3/2 1/1 1/1 2/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 3/2 2/2 1/2 1/1 1/1 2/1 2/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 A, #data A, dir A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 3/2 2/2 1/2 1/1 2/1 2/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 2/2 2/2 2/1 3/2 2/1 2/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 2/2 2/2 2/1 3/2 2/1 2/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 A, #data A, dir A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 code addr code addr dir, A dir, #data A, #data A, dir A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 code addr code addr dir, A dir, #data A, #data A, dir A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 Revision 1.0, 19-Jun-07 Page 92 of 136 D ata Sheet AS8267 / AS8268 H ex C ode 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F M nemonic JZ AJMP XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL JNZ ACALL ORL JMP MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV SJMP AJMP ANL MOVC DIV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV O perands code addr code addr dir, A dir, #data A, #data A, dir A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 code addr code addr C, bit addr @A+DPTR A, #data dir, #data @R0, #data @R1, #data R0, #data R1, #data R2, #data R3, #data R4, #data R5, #data R6, #data R7, #data code addr code addr C, bit addr A, @A+PC AB dir, dir dir, @R0 dir, @R1 dir, R0 dir, R1 dir, R2 dir, R3 dir, R4 dir, R5 dir, R6 dir, R7 B /C 1) H ex C ode 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF M nemonic MOV ACALL MOV MOVC SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB ORL AJMP MOV INC MUL n/a MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV ANL ACALL CPL CPL CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE O perands DPTR, #data code addr bit addr, C A, @A+DPTR A, #data A, dir A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 C, /bit addr code addr C, bit addr DPTR AB (reserved) @R0, dir @R1, dir R0, dir R1, dir R2, dir R3, dir R4, dir R5, dir R6, dir R7, dir C, /bit addr code addr bit addr C A, #data, code A, dir, code @R0, #data, code @R1, #data, code R0, #data, code R1, #data, code R2, #data, code R3, #data, code R4, #data, code R5, #data, code R6, #data, code R7, #data, code B /C 1) 2/2 2/2 2/1 3/2 2/1 2/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 2/2 2/2 2/1 2 ) 1/2 2/1 2/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 2/2 2/2 2/1 2 ) 2/2 1/4 3/2 2/1 2/1 2/1 2/1 2/1 2/1 2) 2) 2) 2) 2) 2) 3/2 2/2 2/1 2) 2/2 2/1 2/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 2/1 2 ) 2/2 2/1 1/1 2 ) 1/4 1/1 2/1 2 ) 2/1 2 ) 2/1 2 ) 2/1 2 ) 2/1 2 ) 2/1 2/1 2/1 2/1 2/1 2) 2) 2) 2) 2) 2/1 2 ) 2/2 2/1 1/1 3/2 3/2 3/2 3/2 3/2 3/2 3/2 3/2 3/2 3/2 3/2 3/2 2/1 2 ) 2/1 2 ) 2/1 2 ) 2/1 2 ) Revision 1.0, 19-Jun-07 Page 93 of 136 D ata Sheet AS8267 / AS8268 H ex C ode C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF M nemonic PUSH AJMP CLR CLR SWAP XCH XCH XCH XCH XCH XCH XCH XCH XCH XCH XCH POP ACALL SETB SETB DA DJNZ XCHD XCHD DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ dir O perands B /C 1) H ex C ode E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF M nemonic MOVX AJMP MOVX MOVX CLR MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVX ACALL MOVX MOVX CPL MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV O perands A, @DPTR code addr A, @R0 A, @R1 A A, dir A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 @DPTR, A code addr @R0, A @R1, A A dir, A @R0, A @R1, A R0, A R1, A R2, A R3, A R4, A R5, A R6, A R7, A B /C 1) 2/1 2) 2/2 2/2 2/2 2/2 1/1 2/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/2 2/2 1/2 1/2 1/1 2/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 code addr bit addr C A A, dir A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 dir code addr bit addr C A dir, code addr A, @R0 A, @R1 R0, code addr R1, code addr R2, code addr R3, code addr R4, code addr R5, code addr R6, code addr R7, code addr 2/2 2/1 1/1 1/1 2/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 2/1 2 ) 2/2 2/1 1/1 1/1 3/2 1/1 1/1 2/2 2/2 2/2 2/2 2/2 2/2 2/2 2/2 d ir .............. variable in I_RAM code addr ... address in code memory data ........... immediate data bit addr....... address of a bit in bit-addressable I_RAM Notes: 1) ‘B’ = number of bytes ‘C’ = number of cycles 2) Optimised execution in a single cycle; normally 2 cycles Revision 1.0, 19-Jun-07 Page 94 of 136 D ata Sheet AS8267 / AS8268 A ddressing Modes T he MCU comprises all standard 8051 addressing modes. For completeness they are listed here. There are five types. In two byte instructions the destination is specified first, then the source. M ode R egister addressing D irect addressing R egister indirect addressing I mmediate addressing I ndex addressing E xamples MOV A, R0 MOV R0, A MOV @R0, A MOVX @DPTR, A MOV R0, #data MOVC A, @A+DPTR MOVC A, @A+PC N otes Register R0 in I_RAM one out of 4 banks selected Moves contents of A to R0 Moves contents of A to location addressed by R0, or by DPTR Moves immediate #data to R0 Moves contents of location addressed by A+DPTR, or A+PC to A. For reading lookup tables, applies to program memory only I nterrupt Controller T he 8051 core provides 7 interrupt sources: 2 of them are the same as in the standard 8051, the others are tied to specific internal sources. Each interrupt causes the program to jump to the corresponding interrupt vector if the interrupt is enabled in the interrupt enable register (IE). The interrupt priority can be controlled via the interrupt priority register (IP) in order to override the predefined priority, starting with IP.0 as highest. For further information on the interrupt sources refer to the appropriate chapters. I nterrupt Enable Register (IE) E ach of the interrupt sources can be individually enabled or disabled by setting the corresponding bit in the IE register. This register contains a global enable bit EA. By clearing this bit all interrupts can be disabled at once. IE MSB EA ERTC ES2 ES ESPI EIOX ET0 LSB EDSP Enable bit = 0 disables the interrupt Enable bit = 1 enables the interrupt I nterrupt Priority Register (IP) IP MSB P RTC PS2 PS PSPI PIOX PT0 LSB PDSP Priority bit = 1 assigns high priority Priority bit = 0 assigns low priority Revision 1.0, 19-Jun-07 Page 95 of 136 D ata Sheet AS8267 / AS8268 Interrupt Source Interrupt Vector R TC 0 033h UART2 002Bh UART1 0023h SPI 001Bh MPIO 0013h Timer 0 000Bh DSP 0003h Note: Timer0 must have the highest priority in the IP register. No other interrupt should be assigned with a high priority. Symbol EA ERTC ES2 ES ESPI EIOX ET0 EDSP N ote: 1) Position 1 IE.7 IE.6 IE.5 IE.4 1 IE.3 IE.2 1 IE.1 IE.0 Function Disables all interrupt when 0. If EA = 1 each interrupt is individually enabled due to its enable bit. RTC real time clock, interrupt enable bit UART2, serial port, interrupt enable bit UART1, serial port, interrupt enable bit SPI serial port, interrupt enable bit MPIO external pin, interrupt enable bit Timer 0, interrupt enable bit DSP data available Priority Lowest Highest Standard 8051 bits I nterrupt Priorities E ach interrupt source can be individually assigned one of two priority levels. A low priority interrupt can always be interrupted by a higher-priority interrupt, but not by another low priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If the corresponding IP bit is set then this interrupt is serviced first if another interrupt request occurs at the same time where the IP bit is zero. Interrupt on the same priority level are serviced due to the internal polling sequence starting with DSP highest down to RTC lowest. Symbol PRTC PS2 PS PSPI PIOX PT0 PDSP N ote: 1) Position IP.7 IP.6 IP.5 1 IP.4 IP.3 IP.2 1 IP.1 IP.0 Function Real time clock, priority bit UART2 serial port, priority bit UART1 serial port, priority bit SPI serial port, priority bit MPIO external pin, priority bit Timer 0, priority bit DSP priority bit Source Flags TSA, STF, A1F, A2F RI, TI RI, TI ITRA in Status 0 / Status 1 TF0 dai, alarm Standard 8051 bits Revision 1.0, 19-Jun-07 Page 96 of 136 D ata Sheet AS8267 / AS8268 Source PDSP IE Register IP Register IP = 1 IP = 0 Priority Level High Priority Level Low PTO High Priority Interrupt PIOX PSPI Polling Sequence PS PS2 PRTC Low Priority Interrupt Global enable Individual enables F igure 18: Interrupt control system Revision 1.0, 19-Jun-07 Page 97 of 136 D ata Sheet AS8267 / AS8268 M emory Maps T he 8051 MCU is configured as Von Neumann architecture merging program and data range into one 64kB address space. This space is completely accessible via MOVX and partly accessible via MOVC (0000h – 5FFFh). Besides, there is the typical 8051 structure with 128 bytes of internal memory (I_RAM) and the special function registers (SFRs) also in a 128 byte address space. XDATA Memory FFFFh unused 9FFFh C000h unused Direct addressing A000h 9000h 8000h Internal Memory 7Fh 32kB FLASH 7FFFh 1kB X_RAM 9500h 9400h 9300h 9200h 9100h 9000h SFRs FFh Special Function Registers 80h unused MPIO SPI DSP LCDD RTC SCT 128 bytes I_RAM 00h 0000h Direct addressing Register addressing (4 banks) Bit addressing Register indirect addressing MOVX A, @DPTR MOVX @DPTR, A MOVC A, @A+PC MOVC A, @A+DPTR MOVX @Ri, A MOVXA, @Ri with Ri ε {R0, R1}, P2 represents upper address bits } only for 0000h – 7FFFh F LASH Memory T he Flash memory shares address and output data lines with the X_RAM. 32kB out of 64kB addressable memory are used: 0000h – 7FFFh for program data storage. Revision 1.0, 19-Jun-07 Page 98 of 136 D ata Sheet AS8267 / AS8268 D ata Memory (X_RAM) and Block Interfaces T he following table shows the start (and stop) addresses for the X_RAM and the block interfaces. These locations can be accessed with the MOVX instruction. Start Address 8000h 9000h 9100h 9180h 9200h 9300h 9400h 9500h 9600h 9700h Stop Address 83FFh 9007h 9134h 9184h 9220h 9338h 9403h 951Fh 9604h 9701h Contents X_RAM SCT RTC WDT LCDD DSPREG (MDR/SREG) EEP_SPI MPIO TEMPSENS FLASH (STAT/ATTACK) D etailed Memory map: Address Contents 8000h 9000h 9100h 9104h 9108h 910Ch 9110h 9114h 9118h 911Ch 9130h 9180h 9200h 9204h 9208h 920Ch 9210h 9214h 9218h 921Ch Seconds/VL Weekdays Cont./Status1 Min.Alarm 1 YearsAlarm 1 Mon. Alarm 2 DivReg B 0 WDTE reg1[7:0] reg1[39:32] reg1[71:64] reg2[7:0] reg2[39:32] reg2[71:64] … Address Contents 83FFh 9001h 9101h 9105h 9109h 910Dh 9111h 9115h 9119h 911Dh 9131h 9181h 9201h 9205h 9209h 920Dh 9211h 9215h 9219h 921Dh X_RAM enable signals Minutes Months/Cent. Cont./Status2 Hour Alarm 1 Min.Alarm 2 YearsAlarm 2 DivReg B 1 WDTCLK reg1[15:8] reg1[47:40] reg1[79:72] reg2[15:8] reg2[47:40] reg2[79:72] - Address Contents Address Contents X_RAM 9002h 9102h 9106h 910Ah 910Eh 9112h 9116h 911Ah 911Eh 9132h clkdiv[2:0] Hours Years Sec.Tim.B 0 Day Alarm 1 Hour Alarm 2 DivReg B 2 9003h 9103h 9107h 910Bh 910Fh 9113h 9117h 911Bh 911Fh 9133h Days Sec.Tim.B 1 Mon. Alarm 1 Day Alarm 2 Freq. Trim SCT RTC WDT 9202h 9206h 920Ah 920Eh 9212h 9216h 921Ah 921Eh reg1[23:16] reg1[55:48] reg1[87:80] reg2[23:16] reg2[55:48] reg2[87:80] use_reg 9203h 9207h 920Bh 920Fh 9213h 9217h 921Bh 921Fh reg1[31:24] reg1[63:56] reg1[95:88] reg2[31:24] reg2[63:56] reg2[95:88] selvlcd[2:0] LCDD Revision 1.0, 19-Jun-07 Page 99 of 136 D ata Sheet AS8267 / AS8268 Address Contents 9220h 9300h 9304h 9308h 930Ch 9310h 9314h 9318h 931Ch 9320h 9324h 9328h 932Ch 9330h 9334h 9338h 9400h 9500h 9504h 9508h 950Ch 9510h 9514h 9518h 951Ch 9600h 9604h 9700h lcdd_pd samptoend 0 np[23:16] sos_v[23:16] sos_i1[15:8] sos_i1[47:40] sos_i2[23:16] sos_i2[53:48] pcorr_i1[7:0] cal_v[7:0] cal_i2[7:0] pulselev_i1 2 mconst[3:0] vconst[7:0] Status SSPCON make_irq0 out_mux2 sel_drv1 sel_refp out1 out5 out9 pcnt1 TS_Status TS_OffsetCorr1 FLASH_STAT Address Contents Address Contents Address Contents 9301h 9305h 9309h 930Dh 9311h 9315h 9319h 931Dh 9321h 9325h 9329h 932Dh 9331h 9335h 9339h 9401h 9501h 9505h 9509h 950Dh 9511h 9515h 9519h 951Dh 9601h samptoend 1 np[31:24] sos_v[31:24] sos_i1[23:16] sos_i1[53:48] sos_i2[31:24] pcorr_i1[8] cal_v[15:8] cal_i2[15:8] pulselev_i2 0 vconst[13:8] SSPCLKDIV make_irq1 set_en0 sel_pupd0 in0 out2 out6 out10 pcnt2 TS_Result0 9302h 9306h 930Ah 930Eh 9312h 9316h 931Ah 931Eh 9322h 9326h 932Ah 932Eh 9332h 9336h 933Ah 9402h 9502h 9506h 950Ah 950Eh 9512h 9516h 951Ah 951Eh 9602h np[7:0] sos_v[7:0] sos_v[35:32] sos_i1[31:24] sos_i2[7:0] sos_i2[39:32] pcorr_i2[7:0] cal_i1[7:0] pulselev_i1 0 pulselev_i2 1 nsamp[7:0] Select SSPSTAT out_mux0 set_en1 sel_pupd1 in1 out3 out7 out11 Status0 TS_Result1 9303h 9307h 930Bh 930Fh 9313h 9317h 931Bh 931Fh 9323h 9327h 932Bh 932Fh 9333h 9337h 933Bh 9403h 9503h 9507h 950Bh 950Fh 9513h 9517h 951Bh 951Fh 9603h np[15:8] sos_v[15:8] sos_i1[7:0] sos_i1[39:32] sos_i2[15:8] sos_i2[47:40] pcorr_i2[8] cal_i1[15:8] pulselev_i1 1 pulselev_i2 2 nsamp[15:8] Gains SSPBUF out_mux1 sel_drv0 sel_in out0 out4 out8 pcnt0 Status1 TS_OffsetCorr0 TS MPIO SPI2 DSP 9701h FLASH_ATTACK 9702h - 9703h - FLASH Revision 1.0, 19-Jun-07 Page 100 of 136 D ata Sheet AS8267 / AS8268 I nternal Memory (I_RAM) 1 28 bytes of I_RAM are provided, which can be accessed via 3 address modes. - A ll memory 00h to 7Fh is directly addressable. - 0 0h to 1Fh are register addressable in four banks. Bank switching is done in PSW (Program Status Word). - 2 0h to 2Fh are bit addressable, which means that each bit of these registers can be set/cleared separately. I _RAM Locations 7 8h 7 0h 6 8h 6 0h 5 8h 5 0h 4 8h 4 0h 3 8h 3 0h 2 8h b it 40-47 2 0h b it 00-07 1 8h R 0 1 0h R 0 0 8h R 0 0 0h R 0 7 9h 7 1h 6 9h 6 1h 5 9h 5 1h 4 9h 4 1h 3 9h 3 1h 2 9h b it 48-4F 2 1h b it 08-0F 1 9h R 1 1 1h R 1 0 9h R 1 0 1h R 1 7 Ah 7 2h 6 Ah 6 2h 5 Ah 5 2h 4 Ah 4 2h 3 Ah 3 2h 2Ah b it 50-57 22h b it 10-17 1 Ah R 2 1 2h R 2 0 Ah R 2 0 2h R 2 7 Bh 7 3h 6 Bh 6 3h 5 Bh 5 3h 4 Bh 4 3h 3 Bh 3 3h 2 Bh bit 58-5F 2 3h bit 18-1F 1 Bh R3 1 3h R3 0 Bh R3 0 3h R3 7 Ch 7 4h 6 Ch 6 4h 5 Ch 5 4h 4 Ch 4 4h 3 Ch 3 4h 2Ch bit 60-67 24h bit 20-27 1 Ch R4 1 4h R4 0 Ch R4 0 4h R4 7 Dh 7 5h 6 Dh 6 5h 5 Dh 5 5h 4 Dh 4 5h 3 Dh 3 5h 2Dh bit 68-6F 25h bit 28-2F 1 Dh R5 1 5h R5 0 Dh R5 0 5h R5 7 Eh 7 6h 6 Eh 6 6h 5 Eh 5 6h 4 Eh 4 6h 3 Eh 3 6h 2Eh b it 70-77 26h b it 30-37 1 Eh R 6 1 6h R 6 0 Eh R 6 0 6h R 6 7 Fh 7 7h 6 Fh 6 7h 5 Fh 5 7h 4 Fh 4 7h 3 Fh 3 7h 2 Fh b it 78-7F 2 7h b it 38-3F 1 Fh R 7 1 7h R 7 0 Fh R 7 0 7h R 7 T he first 4 x 8 bytes of the internal memory can be addressed via instructions using the register addressing mode (register bank 0, 1, 2, 3). The following 16 bytes (16 x 8 = 128 bits, address 20h to 2Fh) can be addressed via instructions using the direct-bit addressing mode. The address space from 30h to 7Fh is accessible via the direct addressing mode only. Gray-shaded R0 and R1 registers can be used for register indirect addressing. S pecial Function Registers (SFR) T he following table shows the locations of the Special Function Registers. SFRs in bold style are original 8051 registers. SFRs in italic style are additional registers specific to the AS8267 / AS8268 ICs. Revision 1.0, 19-Jun-07 Page 101 of 136 D ata Sheet AS8267 / AS8268 S FR Locations F 8h F 0h B E 8h S QRTIN0 E0h A CC D 8h D 0h P SW C 8h C 0h S CON2 B 8h I P B 0h S OVR2 A 8h I E A 0h P 2 9 8h S CON 9 0h S OVR 8 8h T CON 8 0h P 0 F 9h F 1h E 9h S QRTIN1 E 1h D 9h D 1h C 9h C 1h S BUF2 B 9h B 1h A 9h A 1h 9 9h S BUF 9 1h 8 9h T MOD 8 1h S P F Ah F 2h EAh S QRTIN2 E 2h D Ah D 2h C Ah C 2h S BAUDL2 B Ah B 2h A Ah A 2h 9 Ah S BAUDL 9 2h 8 Ah T L0 8 2h D PL F Bh F 3h E Bh SQRTIN3 E 3h D Bh D 3h C Bh C 3h SBAUDH2 B Bh B 3h A Bh A 3h 9 Bh SBAUDH 9 3h 8 Bh 8 3h DPH F Ch F 4h ECh SQRTIN4 E 4h D Ch D 4h C Ch C4h B Ch B 4h A Ch A 4h 9Ch 9 4h 8 Ch TH0 8 4h F Dh F 5h EDh SQRTOUT0 E 5h D Dh D 5h C Dh C 5h B Dh B 5h A Dh A 5h 9 Dh 9 5h 8 Dh 8 5h F Eh F 6h E Eh S QRTOUT1 E 6h D Eh D 6h C Eh C 6h B Eh B 6h A Eh A 6h 9 Eh 9 6h 8 Eh T 0PRE 8 6h F Fh F 7h E Fh SQRTOUT2 E 7h D Fh D 7h C Fh C 7h B Fh B 7h A Fh A 7h 9 Fh 9 7h 8 Fh 8 7h 1 28 bytes of SFR address space is available using the direct addressing mode. The following table describes the use of the register bytes: S ymbol A CC B P SW SP D PTR D PL D PH P0 P2 IP IE T MOD T CON T H0 T L0 S CON S BUF T 0PRE S OVR S BaudL S BaudH S CON2 S BUF2 R egister Name Accumulator B R egister Program Status Word Stack Pointer Data Pointer 2 Bytes Low Byte High Byte Port 0 Port 2 Interrupt Priority Control Interrupt Enable Control Timer Mode Control Timer Control Timer 0 High Byte Timer 0 Low Byte Serial Control (UART1) Serial Data Buffer (UART1) Timer 0 Prescaler Serial Overflow (UART1) Serial Baudrate Low (UART1) Serial Baudrate High (UART1) UART2 Control UART2 Serial Data Buffer A ddress Notes E0h F0h D0h 81h 82h 83h 80h A0h B8h A8h 89h 88h 8Ch 8Ah 98h 99h 8Eh 90h 9Ah 9Bh C0h C1h S tandard Registers C ustom Registers Revision 1.0, 19-Jun-07 Page 102 of 136 D ata Sheet AS8267 / AS8268 S ymbol S BaudL2 S BaudH2 S OVR2 S QRTIN0 S QRTIN1 S QRTIN2 S QRTIN3 S QRTIN4 R egister Name UART2 Baudrate Low UART2 Baudrate High UART2 Overflow Square Root Input [7:0] Square Root Input [15:8] Square Root Input [23:16] Square Root Input [31:24] Square Root Input [39:32] A ddress Notes C2h C3h B0h E8h E9h EAh EBh ECh EDh EEh EFh Writing to this location triggers the squareroot calculation S QRTOUT0 Square Root Output [7:0] S QRTOUT1 Square Root Output [15:8] S QRTOUT2 Square Root Output [23:16] N otes: 1) Ports P1 and P3 do not exist. 2) Timer 1 is not implemented (and the related SFRs). 3) Ports P0 and P2 are not connected to pins. P0 and P2 can be used as a register in general. However, P2 can be used for X_RAM access, when ‘@Ri’ is used in the register indirect addressing mode (with Ri being either R0 or R1). In that case P2 will form the higher byte of the X_RAM address. 4) IE/IP: The sources for the interrupts are defined in interrupt controller section. 5) TCON, TMOD, TH0, TLO described in section Timer 0. 6) SCON, SBUF, SBaudL, SBaudH, SOVR are related to UART1 described in the UART section. 7) SCON2, SBUF2, SBaudL2, SBaudH2, SOVR2 are related to UART2 described in the UART2 section. Revision 1.0, 19-Jun-07 Page 103 of 136 D ata Sheet AS8267 / AS8268 S quareroot Block (SQRT) T his SQRT block calculates the square root of a 40 bit input value (mapped to 5 eight bit input registers). The output is a 20 bit number which is mapped to 3 eight bit output registers. The calculation starts immediately after the least significant byte has been written (= address E8h). For the square root calculation the Gypsi- or radicand algorithm is used, which produces one bit per clock cycle. Thus after 20 cycles the result is available in the SQRTOUT[2:0] registers. Note: The interrupt s ignal is not connected t o the interrupt controller of the MCU, because the result is available after a defined period of 4 machine cycles. The programmer has to take care for the correct timing. For instance, 4 NOP instructions must be inserted before reading out the result. When writing SQRTIN[39:36] are don’t care. When reading SQRTOUT[23:20] those bits equal zero. D ata Registers SFR-Address E8h E9h EAh EBh ECh EDh EEh EFh Name SQRTIN0 SQRTIN1 SQRTIN2 SQRTIN3 SQRTIN4 SQRTOUT0 SQRTOUT1 SQRTOUT2 Description Input value[7:0] Input value[15:8] Input value[23:16] Input value[31:24] Input value[39:32] Output value[7:0] Output value[15:8] Output value[19:16] 4 MOV SQRT4, #... 3 2 0 MOV SQRT0, #... 4 cyc MOV A, SQRT2, ... square root calculation start calculation F igure 19: Timing diagram result available D uring the time of calculation data must not be overwritten. As soon as the register SQRT0 is written, the calculation sequence is retriggered and the result is calculated from the latest contents of the 5 input registers. Revision 1.0, 19-Jun-07 Page 104 of 136 D ata Sheet AS8267 / AS8268 B oot Loader (BOOTLOAD) A fter power-up the boot loader checks if the program memory (32kB Flash) is blank or if there is a program available. In case there is no program stored (no program length stored at 7FFFh and 7FFEh) the boot loader generates ‘SJMP$’ (Hex code: 80FEh) instruction address 0000h. This guarantees a well defined behaviour after power-on. In case there is a program stored in the Flash memory the boot load block loads also security information from the upmost page of the Flash memory. After the boot load the MCU will start to work. The loaded program will be executed. W atchdog Timer (WDT) A w atchdog timer is provided on-chip to automatically initiate a system reset if a ‘hold-off’ signal is not detected within a predefined timeout period, by the watchdog. The watchdog timer consists of a programmable timer driven either by the Mclk (main oscillator output frequency), or the MCU clock (microcontroller unit clock). The watchdog timer timeout period is dependent upon the programming of the WDTCLK register. When the watchdog times out, a reset signal is generated which is OR-ed with the main system reset. Thus a watchdog timer reset is identical to a power on reset. If the watchdog timer function is required, the watchdog is enabled by setting the WDTE register LSB (Bit 0). As soon as this bit is enabled, the program must periodically access the WDTCLK register (either read or write) to prevent the watchdog timer from timeout and thus resetting the device. R egister Name W DTE W DTCLK[1:0] x ........Don’t care A ddress 9180h 9181h R eset Value xxxx.xxx0b xxxx.xxx00b D escription Enables or disables the watchdog timer function 0: watchdog disabled 1: watchdog enabled A read or write access clears the watchdog timer. Writing bits [1:0] selects the clock source. W atchdog Timer Enable Register (WDTE) MSB - LSB WDTE0 Bit 7 6 5 4 3 2 Symbol Function N ot used N ot used N ot used N ot used N ot used N ot used Revision 1.0, 19-Jun-07 Page 105 of 136 D ata Sheet AS8267 / AS8268 Bit 1 0 Symbol Function N ot used WDTE0 Disables and enables the watchdog timer function 0: watchdog disabled 1: watchdog enabled T he watchdog timer has a selectable counter length of 18 bit, 20 bit or 22 bit for the Mclk and 18 bits for the mcu_clk. It should be noted that while the Mclk has a fixed frequency, depending on the crystal frequency, the MCU clock is programmable, being divisible by 1 to 128, in binary steps (see MCUCLKDIV Register (‘mcu_clk’)). The timeout periods below assume the Mclk = 3.579545MHz (fixed crystal frequency). W atchdog Timer Clock Register (WDTCLK) MSB WDTCLK1 LSB WDTCLK0 Bit 7 6 5 4 3 2 1 Symbol WDTCLK1 Function Not used Not used Not used Not used Not used N ot used Clock Source Watchdog timeout period (Mclk = 3.579545MHz) 0 WDTCLK0 Mclk – default after reset Mclk Mclk Mcu_clk (div=1) Mcuclk (div=128) Timeout Period (ms) 73.2 292.8 1171.2 73.2 9300 Bit1 0 0 1 1 Bit0 0 1 0 1 2 nd U ART (UART2) A n additional serial interface, UART2 is provided for debugging purposes. UART2 is accessible via two of the multi-purpose I/Os (MPIO). The UART2 is functionally identical to UART1. The SFR addresses are defined as follows: R egister Name S CON2 S BUF2 S BAUDL2 S BAUDH2 S OVR2 A ddress C0h C1h C2h C3h B0h D escription Serial port control register – see Serial Interface – UART1 for details. Serial port buffer register – see Serial Interface – UART1 for details. Baudrate reload register – Low address Baudrate reload register – High address ‘Serial overflow’ register, which indicates when data in SBUF has been overwritten before being read. The flag is the LSB with the other 7 bits all being 0. B elow is an example how to configure the ports IO7 and IO6 as UART2s txd2 (IO7) and rxd2 (IO6) pins. Revision 1.0, 19-Jun-07 Page 106 of 136 D ata Sheet AS8267 / AS8268 ;------------------------------------------------------------------------------; Configure UART2 to the pins IO6 and IO7 with the Baudrate of 19200 Baud: ;------------------------------------------------------------------------------; map txd2 = IO7 ; map rxd2 = IO6 ;------------------------------------------------------------------------------xdata mem: OUTMUX1 (9503h)