1.1
2
AS8500 U niversal multi pupose data aquisition system
3
D ata Sheet
D ATA SHEET
1
Features
16 bits resolution differential inputs Single + 5V supply Low power 15 mW SOIC16 package 16 kHz maximum sampling frequency internal temperature measurement internal reference programmable current sources digital comparator active wake-up PGA gains 6, 24, 50, 100 Zero offset Zero offset TC Extremely low noise Internal oscillator with comparator for active wake up 3-wire serial interface, !P compatible temperature range – 40 to + 125 °C
INTERNAL TEMPERATURE
REF
AGND
VDDA
VSSA
1.26 V REFERENCE CALIBRATION DATA
VDDD VSSD
ETR
BUF INPUT MUX CHOPPER PROTECTION 16 BIT - CONVERTER
ETS VBAT RSHH
DSP CONTROLLER FILTER INT. CLOCK TIMER
CLK EZPRG
RSHL
PGA and LEVEL SHIFT
COMPARATOR
CURRENT SOURCES
SERIAL INTERFACE / CONTROL REGISTERS
SCLK
SDAT
INTN
Figure 1: Functional Block Diagram
the high internal chopping frequency the system is free of 1/f-noise down to DC.The 0-10 Hz noise is typical below 1 µ V i.e. as good or better than any other available chopper amplifier. For high speed synchronous measurements the chip can run in an automatic switching mode between two input channels with preprogrammed parameter sets. The circuit has been optimised for the application in battery management systems in automotive systems. As a front end data acquisition system it allows an high quality measurement of current, voltage and temperature of the battery. With a high quality 100 !" resistor the system can handle the starter current of up to 1500 A, a continuous current of # 300 A as well as the very low idle current of a few mA in the standby mode. For external temperature measurement the chip can use a wide variety of different temperature sensors such as RTD, PTC, NTC, thermocouples or even diodes or transistors. A built-in programmable current source can be switched to any input and activate these sensors without the need of other external components. The measurement of the chip temperature with the integrated internal temperature sensor allows in addition the temperature compensation of sensitive parameters which increases the total accuracy considerably. The flexibility of the system is further increased by a digital comparator that can be assigned to any measured property (current, voltage, temperature) and an active wake-up in the sleep-mode. All analog input-terminals can be checked for wire break via the SDIinterface.
2
Applications
battery management for automotive systems power management mV/µ V-meter thermocouple temperature measurement RTD precision temperature measurement high-precision voltage and current measurement
3
General description
The AS8500 is a complete, low power data acquisition system for very small signals (i.e. voltages from shunt resistors, thermocouples) that operates on a single 5 V power supply. The chip powers up with a set of default conditions at which time it can be operated as a read-only-converter. Reprogramming is at any time possible by just writing into two internal registers via the serial interface. The AS8500 has four ground refering inputs which can be switched separately to the internal PGA. Two input channels can also be operated as a fully differential ground free input. The system can measure both positive and negative input signals. The PGA amplification ranges from 6 to 100 which enables the system to measure signals from 7mV to 120 mV full scale range with high accuracy, linearity and speed. The chip contains a high precision bandgap reference and an active offset compensation that makes the system offset free (better than 0,5 !V) and the offset-TC value negligible. The builtin programmable digital filter allows an effective noise suppression if the high speed is not necessary in the application. The input noise density is only 35 nV / Hz and due to
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CONTENTS
1 2 3 4 5 6 7 7.1 7.2 FEATURES ........................................................................................................................................................................................ 1 APPLICATIONS................................................................................................................................................................................. 1 GENERAL DESCRIPTION ................................................................................................................................................................ 1 PIN FUNCTION DESCRIPTION FOR SOIC 16 PACKAGE.............................................................................................................. 3 ABSOLUTE MAXIMUM RATINGS.................................................................................................................................................... 4 ELECTRICAL CHARACTERISTICS ................................................................................................................................................. 5
FUNCTIONAL DESCRIPTION .......................................................................................................................................................... 9 POWER ON RESET ........................................................................................................................................................................... 9 ANALOG PART, GENERAL DESCRIPTION ............................................................................................................................................ 9 7.2.1 Reference voltage ............................................................................................................................................................ 10 7.2.2 Current sources ................................................................................................................................................................ 12 7.2.3 Internal temperature sensor ............................................................................................................................................. 13 7.3 DIGITAL PART ................................................................................................................................................................................ 13 7.3.1 Sampling rate ................................................................................................................................................................... 13 7.3.2 Calibration ........................................................................................................................................................................ 13 7.4 MODES OF OPERATION .................................................................................................................................................................. 15 7.5 REGISTER DESCRIPTION ................................................................................................................................................................ 16 7.5.1 OPM operation mode register ( 4 bits ) ............................................................................................................................ 17 7.5.2 CRG general configuration register ( 28 bits ) .................................................................................................................. 17 7.5.3 CRA measurement channel A configuration register ( 17 bits ) ..................................................................................... 18 7.5.4 CRB measurement channel B configuration register ( 17 bits ) ...................................................................................... 20 7.5.5 ZZR Zener-Zap register (188 bits ):................................................................................................................................. 21 7.5.6 CAR calibration register ( 110 bits )................................................................................................................................. 23 7.5.7 TRR trimming register ( 20 bits ) ...................................................................................................................................... 23 7.5.8 THR alarm (Wake-up) threshold register ( 17 bits )......................................................................................................... 26 7.5.9 MSR measurement result register ( 18 bits )................................................................................................................... 26 8 DIGITAL INTERFACE DESCRIPTION............................................................................................................................................ 26 8.1 CLK ............................................................................................................................................................................................. 26 8.2 INTN............................................................................................................................................................................................ 26 8.3 SDI BUS OPERATION...................................................................................................................................................................... 27 8.4 DATA TRANSFERS .......................................................................................................................................................................... 28 8.5 SDI BUS TIMING............................................................................................................................................................................. 29 8.6 SDI ACCESS TO OTP MEMORY ....................................................................................................................................................... 30 8.6.1 ZZR register bit mapping .................................................................................................................................................. 30 8.6.2 Stored ZZR-register mapping ........................................................................................................................................... 34 9 GENERAL APPLICATION HINTS................................................................................................................................................... 35 9.1 GROUND CONNECTION, ANALOG COMMON....................................................................................................................................... 35 9.2 THERMAL EMF.............................................................................................................................................................................. 35 9.3 NOISE CONSIDERATIONS ................................................................................................................................................................ 35 9.4 SHIELDING, GUARDING ................................................................................................................................................................... 36 10 TYPICAL PERFORMANCE CHARACTERISTICS.......................................................................................................................... 37 11 12 13 14 PACKAGE DIMENSIONS................................................................................................................................................................ 39 REVISION HISTORY ....................................................................................................................................................................... 39 ORDERING INFORMATION............................................................................................................................................................ 39 CONTACT........................................................................................................................................................................................ 40 14.1 HEADQUARTERS ...................................................................................................................................................................... 40 14.2 SALES OFFICES ....................................................................................................................................................................... 40
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4
PIN 1 2 3
PIN function description for SOIC 16 package
Name RSHL RSHH ETS description anlalog input from shunt resistor low side anlalog input from shunt resistor high side analog input with reference to RSHL analog input for differential input ETS-VBAT analog output for current-source Comment analog common for VBAT, ETS and ETR; return for internal current source
4
VBAT
analog input with reference to RSHL analog input for differential input ETS-VBAT analog output for current-source
5 6 7 8 9 10 11 12 13 14 15 16
VSS EZPRG VSSD CLK SCLK SDAT INTN VDDD VDDA REF AGND ETR
0V-power supply for analog part digital power input for programming Zener fuses. 0V-power supply and ground reference point for digital part digital input for external clock, master clock input serial port clock input for SDI-port serial data in- and output Digital I/O for interrupt from comparator + 5V digital power supply + 5V analog power supply reference input/output analog ground, ground reference for ADC analog input with reference to RSHL analog output for current-source must be connected to VSS with a 30 nF capacitor this PIN must be connected with a 50-100nF-capacitor to VSS; no direct connection to VSSD/VSS allowed signal wake-up to external µ C conversion ready flag for external interupt and synchronisation in normal mode external clock typical 8.192 MHz; during MWU-mode (see 7.4) external connection must be high impedance or connected to VDDD to reduce current consumption the user must provide a serial clock on this input This input must be open or connected to VDDD. It is not intended, that OTP content is modified by the user.
Table 1: Pin Description
Figure 2: Schematic Package outline SOIC 16
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5
Absolute Maximum Ratings
Stress beyond those listed under “Absolute Maximum Ratings“ may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are defined with respect to VSS and VSSD. Positive currents flow into the IC. Absolute maximum ratings (TA = -40°C to 125°C unless otherwise specified) Nr. 0 1 2 3 4 5 6 7 8 9 PARAMETER Supply voltage Analogue VDDA and digital VDDD Input pin voltage Input current (latch-up immunity) Electrostatic discharge Ambient temperature Storage temperature Soldering conditions Humidity, non-condensing Thermal resistance Power dissipation SYMBOL VDD Vin ISCR ESD TA TSTRG TLEAD RthJA PTOT MIN -0.3 -0.3 -100 -2 -40 -55 5 TYP MAX 7.0 VDD +0.3 100 2 125 150 260 85 75 350 UNIT V V mA kV
OC OC
NOTE Polarity inversion externally protected JEDEC 17
1)
(Tj = 150°C)
2)
°C % K/W mW
Notes: 1) MIL 883 E method 3015, HBM: R =1.5 k", C =100pF. 2) Jedec Std – 020C, lead free
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6
Electrical characteristics
VDDA=5V +/-0.1 V, fclk=8.192 MHz, chopping ratio MM=4 (see 7.5.3), oversampling frequency=2.048 MHz, oversampling ratio=128 temperature range : -40 to 125°C if not otherwise noted symbol parameter conditions min typ max units input characteristics for gain 1 the input signal is connected directly to th input of the converter, this is not possible for the RSHH-RSHL G1 input Gain gains of PGA 6, 24, 50, 100 AC_g6 Accuracy at gain 6 0 to 85 °C 0.4 % @-120mV -40 to 125°C 1.0 % @-120mV AC_g24 Accuracy at gain 24 0 to 85 °C 0.2 % @+-20mV -40 to 125°C 0.6 % @+-20mV AC_g50 Accuracy at gain 50 0 to 85 °C 1 % @+-10mV AC_g100 Accuracy at gain 100 0 to 85 °C 1 % @+-5mV Vin input voltage ranges G1 -300 to + 800 mV (with reference to RSHL) G6 +/- 120 mV G24 +/- 30 mV G50 +/- 15 mV G100 +/- 7.5 mV
1) 2) 2),3) 2) 2) 3) 2)4) 2)4) 5) 6) 6) 7) 7)
Notes: 1) the absolute gain values are subjected to a manufacturing spread of +/-30% 2) Accuracy relies on bandgap characteristic, on the gain variation over temperature and on the trimm information. To achieve optimum performance, the circuit may be trimmed by the user for best temperature stability by writting aproporiate data to the TRR register (see sections 7.4 and 7.5) Default content of TRR register is 17. 3) due to a nonlinear behaviour of the gain and reference voltage over temperature the accuracy is lower for the extended temperature range. 4) It is recommended to use these gain settings only for applications in the temperature range 0 t0 85°C therefore it is recommended to use these gain settings only for applications in the temperature range 0 to 85°C. 5) this gain range is not using the internal PGA, the input is directely connected to the AD-converter. Therefore the input resistance is lower then for other gain ranges. It has been designed mainly for positive input voltages up to 0.8 V i.e. for measurements of temperature with transistors and diodes. The limitation for negative input voltages is due to the onset of conduction of the input protection diodes. 6) the ASSP is optimised for G6 and G24 concerning linearity, speed and TC, therefore these ranges are recommended whenever possible. 7) because of higher TC value at elevated temperature G50 and G100 are recommended for applications in the temperature range 0 to 85°C
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AS8500 - Data Sheet Electrical characteristics (continued)
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VDDA=5V +/-0.1 V, fclk=8.192 MHz, chopping ratio MM=4 (see 7.5.3), oversampling frequency=2.048 MHz, oversampling ratio=128 temperature range : -40 to 125°C if not otherwise noted symbol cal_err parameter calibration error for 30 000 digits output at full range nonlinearity conditions min G1, 720 mV G6, 120 mV G24, 30 mV G50, 15 mV G100, 7.5 mV gain 6 @ room temp gain 24 @ room temp gain 50 @ room temp gain 100 @ room temp all gains -40 to 125°C -40 to 85°C 85 to 125°C -40 to 85 °C room temperature f=0 to 1 kHz -1000 -0.5 -2 -4 typ Device is not factory calibrated 0.1 0.03 0.05 0.05 1 0.2 0.5 1 0.002 0.2 35 20 3 1 1.5 100 100 -90 -60 1000 50 max units %
1)
lin_err
lin_errTC Vos
TC of linearity error offset voltage: RSHH_RSHL offset voltage: ETS, ETR, VBAT Offset voltage drift: RSHHRSHL input bias/leakage current, all channels voltage noise density (G=24) current noise density (G=24) voltage noise, peak (G=24)
5 0.5 1 2
% or 30 digits % or 10 digits % or 15 digits % or 20 digits ppm/K µV µV µV µ V/K nA nV//Hz fA//Hz µV µV µV dBmin dBmin dBmax dBmax
2) 2) 2) 2) 3) 4) 4) 4)
dVos/dT Ib Vndin Indin en p_p en_RMS SNR SDR CCI PSRR
5) 6) 6) 6) 6) 6)
f=10 Hz 0 to 100 Hz 0 to 10 Hz voltage noise, RMS (G=24) 1000 Hz signal to noise (G=24, G=6) room temperature signal to distortion (G=24, G=6) room temperature chanel to chanel insulation room temperature power supply rejection ratio 4.9 to 5.1 V
Notes: 1) The output response might be calibrated by the user by writing appropriate calibration constants to the CAR register (see 7.5. ). The default values are 1548 dec 2) whatever is lower 3) max limit is derived fromdevice characterization and not tested 4) Min/Maximum limits over temperature range are derived from device characterization and not etsted. In normal operation a termperature independent digital offset of -0.7 digits is present due to internal raunding. 5) Typical leakage current is valid for all gain settings except G=1 for positive input voltages below 200 mV. In the temperature range 85-125°C it may be as high as 5 nA. In normal operation a temperature independent digital offset of -0.7 digits is present due to internal rounding. 6) This parameter is not measured directly. It is measured indirectly via gain measurement of the whole path at room temperature
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AS8500 - Data Sheet Electrical characteristics (continued)
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VDDA=5V +/-0.1 V, fclk=8.192 MHz, chopping ratio MM=4 (see 7.5.3), oversampling frequency=2.048 MHz, oversampling ratio =128 temperature range : -40 to 125°C if not otherwise noted symbol parameter conditions min typ max units data conversion RES resolution all channels 16 bits Vref reference voltage room temperature 1.21 V 0-85°C,box Vref_TC temperature coefficient of Vref method 20 ppm/K Vref_Ri internal resistance of Vref Rload > 50 kOhm 200 Ohm fovs clock frequency 4.096 MHz R1 oversamplig ratio 64 128 MM conversions during chopper cycle 4 8 BW bandwidth 7.8 1000 16000 Hz av internal averaging 1 4 1024 cycles fclk external clock frequency 0.05 8.192 10 MHz CLK_extdiv clock division factor 2 4 DR_clk duty ratio of external clock 50 % int_fclk internal clock frequency 180 250 330 kHz analog inputs RSHH, VBAT, ETS, ETS Rin input resistance Ue < 150 mV 50 100 MOhm Cin input capacitance at gain 24 8 15 30 pF internal temperature sensor T_out20 output at 23°C G 6, typical 23 000 digits T_sl slope -20 to 100°C 75 digits/degC current source output to RSHH, RSHL Icurr_rshh 2 µA
1) 2)
3)
4)
Notes: 1) with external averaging the resolution can be increased up to 21 bits with an effective sampling rate below 10 Hz 2) the system works in overflow condition without degradation of accuracy up to 1.4 * range width. This means that the overflow bit can work as bit no.17 in this range. 3) TC- value of the reference voltage may be set through trimm bits intentionally higher to minimize TC of the entire measurement path for gain 24 4) in the temperature range 0 - 85°C the clock frequency can be increased to 12 MHz
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AS8500 - Data Sheet Electrical characteristics (continued)
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VDDA=5V +/-0.1 V, fclk=8.192 MHz, chopping ratio MM=4 (see 7.5.3), oversampling frequency=2.048 MHz, oversampling ratio=128 temperature range : -40 to 125°C if not otherwise noted symbol parameter conditions min typ max units programmable current source output to Vbat, ETS, or ETR Icurr_ON current level 0 248 µA I_steps current steps 6 8 10 µA TC_CS temperature coefficient 900 ppm/K Icurr_OFF current when off room temperature 0.001 µA Icurr_Ri internal resistance of current source Ua < 2 V 10 MOhm digital CMOS inputs with pull up and schmidt-trigger input PINs CLK and SCLK Vih high level input voltage VDDD=5V 3.5 V Vil low level input voltage VDDD=5V 1.5 V Iih current level VDDD=5V, Vih=5V -1 1 µA Iil current level VDDD=5V, Vil=0 30 120 µA digital CMOS outputs output PINs SDAT and INTN Voh high level output voltage VDDD=5V, -633uA 4.5 V Vol low level output voltage VDDD=5V, 564uA 0.4 V Cl capacitive load 20 pF Tristate digital I/O Voh high level output voltage VDDD=5V, -633uA 4.5 V Vol low level output voltage VDDD=5V, 564uA 0.4 V tristate leakage current to Ioz VDDD,VSSD VDDD=5V -1 1 µA Vih high level input voltage VDDD=5V 3.5 V Vil low level input voltage VDDD=5V 1.5 V supply current Isup normal operation VDDD=VDDA=5V 3 5 mA Iaw active wake-up VDDD=VDDA=5V 40 100 µA supply voltage VDDA positive analog supply voltage 4.7 5.0 5.3 V VDDD positive digital supply voltage 4.5 5.0 5.5 V VSS, VSSD negative supply voltage 0 V Power On Reset Vporhi Power on reset Hi 3.1 V Vhyst Hysteresis 0.2 V Notes: 1) the average current is dependent on the on-time of the measurement system i.e. it can be programed via the CRA register 2) dynamic stability of analog supply should be within +/- 0.1 V
1)
2)
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7
7.1
Functional Description
Power on Reset
The power on reset is iniciated during each power up of the ASSP and can be triggered purpously by reducing the analog supply voltage (VDDA) to a value lower than Vporlo for a time interval longer than 0.5 µ sec. During power on reset sequence the following steps are performed automatically: The chip goes to mode MZL (see 7.4) Internal clock is enabled The calibration constants are loaded from Zener-zap memory to the appropriate registers (ZTR=>TRR, ZCL=>CAR). The load procedure is directed by the internal clock and can be monitored on INTN pin. 188 clock pulses are generated from the internal oscillator source. Pulse period is equal to internal clock period. After the power-on reset sequence is finished: the operation continues with internal clock if no external clock is detected. In this case the ASSPs switches to mode MWU with default value of threshold register ( 214 ) If external clock is available the ASSP switches to mode current measurement MMS (default measurement with default configuration: gain=100, fovs=4.096MHz, R1=64, MM=4, R2=1, NTH=214). The microcontroller can communicate via SDI interface whenever appropriate, i.e. CAR and TRR register can be rewritten from the µ C if necessary. Because the automatic selected calibration factor (CGI4) is loaded with zeros, the ASSP delivers constant zero at the output to allow the µ C to check for an unwanted POR. To bring the ASSP back into normal operation for current measurement with gain100 the µ C has to copy the CAU4 default content or a customer specific calibration factor into the CAR-register. (see also 7.5.5 and 8.6.2) 7.2 Analog part, general description
The input signals are level shifted to AGND (+ 2.5 V) then switched by the special high quality MUX- which contains also the chopper – to the input of the programmable gain amplifier (PGA). This low noise amplifier is optimised for best linearity, TC- value and speed at gain 24. The systems contains an internal bandgap reference with high stability, low noise and low TC-value. The output of a programmable current source can be switched to the analog inputs VBAT, ETS and ETR for testing the sensor connections or for external activation of resistors, bridges or sensors (RTD, NTC). The voltage drop generated by the current is measured at the corresponding input/output PIN. For the wire break test of the RSHH and RSHL inputs special low noise current sources are implemented. The integrated temperature sensor can also be switched to the PGA by the MUX and measured any time. The chip temperature can be used for the temperature compensation of the gain of the different channels in the external µ C, which increases the absolute accuracy considerably. The offset of the amplifier itself is already fairly low, but to guarantee the full dynamic range it can be trimmed via the digital interface to nearly zero independent of the autozero chopping function. In the same way the manufacturing spread of the absolute value of the reference voltage can be eliminated and the TC-value set to nearly zero by a trimming process via the SDI interface. For more details of the input multiplexer see the following schematic. The position of all switches is defined by writing into the registers CRA, CRB and CRG via the SDI bus, which is explained in 7.5.2 through 7.5.4.
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M6 ETR M8 ETS
M7
CURRENT SOURCE
INTERNAL TEMPERATURE
M9 M 15
M 14 VBAT M 10
M2
M3 RSHH RSHL M 12
AUXILIARY CURRENT SOURCE
M4 M5 M1
PGA ADCONVERTER
M 13
Figure 3: Multiplexer
7.2.1
Reference voltage
The ASSP contains a highly sophisticated precision reference voltage. Its typical temperature dependence is a slight parabola shaped curve and is shown in figure 14. This reference voltage is used mainly for the internal AD-converter, but can also be used for external purposes if the impedance of the external circuitry is high enough.
reference voltage as function of resistance load 1,26 1,24 reference voltage in V 1,22 1,20 1,18 1,16 1,14 1,12 10 20 30 40 50 60 70 80 90 100 110 resistance load in kOhm
measurement open loop value
The absolute value and its temperature coefficient (TC) is given by the content of the TRR register. This opens the possibility to calibrate the reference voltage to the optimum absolute value (i.e. 1.28 V) and the TC value to zero thus eliminating fully the production spread.
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Writing into subregister TRIMBV of TRR changes the absolute value linearly by 5.1 mV per digit as shown in the following graph and described in full detail in 7.5.7
as function of temperature
1,36 1,32 75 °C 1,28 1,24 1,20 1,16 0 5 10 15 20 25 30 content of TRIMBV in bits 24 °C
Trimming the TC value is similarly done by writing into subregister TRIMBTC. Since the TC trimming is also changing the absolute value it is important to trim the TC first and then the absolute value.
reference voltage in V
temperature coefficient as function of TRIMBTC setting
200
temperature coefficient in ppm/K
150 100 50 0 -50 -100 -150 -200 -250 0 5 10 15 20 25 30 35
change 12.7 ppm/K per step
setting of subregister TRIMBTC of TRR
The TC trimming also opens the unique possibility to change the TC-value within the time of reprogramming of the TRR-register (i.e. within µ sec) to allow the compensation of different TC-values of the external circuitry for different channels. In addition it can be used for very fast autocalibration of the total TC of a given channel. An external reference voltage is applied to the channel to be checked. Then all numbers from 0 to 31 are written into subregister TRIMBTC and a reading is done for the input voltage and the internal temperature as well. The same is repeated at any temperature above RT. From these data the TRIMBTC setting for a minimum drift can be easily calculated.
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7.2.2 Current sources
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The AS8500 contains several current sources which can be used for checking all input lines for wire brake, to control external circuitry or to activate external sensors. Main current source The main current source can be digitally controlled via the content of the CRG register in 31 steps of 8 µ A in the range of 0 to 248 µ A. Its absolute value can be calibrated by writing in the subregister TRIMC of TRR. The current source can be switched to the inputs VBAT, ETR or ETS to activate external sensors like RTDs, NTCs or resistance briges and strain gages. It can also be used to detect a wire breake of external connected sensors. Performing a measurement with a high and a low (or zero) current opens the possiblity to eliminate thermal EMF voltages in external sensors. Secondary current sources The ASSP contains two other high quality current sources supplying a current of approx. 2µ A at the inputs RSHL and RSHH. These current sources can be switched on and off at any time to check the correct connection of both terminals. During off state they must not interfere with the high sensitive voltage inputs, especially the noise level should not be increased. If one of the terminals is an open connection the amplifier goes into saturation and the overflow bit is set.
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7.2.3
Internal temperature sensor
The ASSP contains a high sensitive precision temperature sensor which can be used at any time. The sensor supplies a very linear voltage with temperature. The voltage can be measured using the internal circuitry with gain 6, with free selection of all other parameters defining the sampling rate.
measurement of internal temperature sensor over oil bath temperature
35000 100 75
internal temperature in digits inearity deviation in digits
30000
50 25
25000
0 -25
20000
output signal linearity deviation cubic fit
-50 -75 -100 -50 -25 0 25 50 75 100 125 150 175
15000
temperature in deg C
The slope of the curve is approx. 75 digits per degC. The calculation of the temperature has to be done in the external µ C acc. to the following simple formula: Tint=( Uint(T)-Uint(23) ) / 75 + 23°C Uint(T) is the measured result and Uint(23) is the reference value at 23°C, which is stored as an 11 bit-word in the ZZR-register.
7.3
Digital part
In the digital part the result of the AD-converter is processed, i.e. calibration, active offset cancellation and filtering is done. In addition the communication via the serial SDI interface is handled and all circuit functions (like voltage and current path settings, chopping, dechopping) are controlled. Whenever the power supply line returns from below POR threshold a power-up circuitry is activated which loads the internal calibration registers from the Zener-Zap memory into the working register and starts the chip in a special default mode. 7.3.1 Sampling rate the sampling rate (SR) is defined by the setting of parameters in register CRA or CRB. The oversampling frequency (OSF), the oversampling ratio (OSR), the chopping ratio (MM) and the averaging number (AV). The sampling rate can be calculated acc. to the following formula: SR= OSF/(OSR*MM*AV) For an clock frequency of 8.192 MHz it can vary between 16 000 Hz and 1.95 Hz.
In the dual mode (see 7.4 mode 2) the ASSP is switching automatically between the two channels and it needs at least one measurement for each polarity to get a valid measurement. In addition the ASSP needs some time to reprogram the internal registers and switches. Therefore the maximum sampling frequency is limited to 7.5 kHz for the above given clock frequency. The internal averaging is not working in the dual mode, but the sampling frequency can be different for each channel. 7.3.2 Calibration The calibration of the ASSP is done by a test setup as follows: room temperature calibration of the internal temperature sensor absolute input-output calibration for all gain settings TC calibration for the measurement path for gain 24
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The absolute input-output calibration of the gain ranges can be done that way that for a given input voltage 30 000 digits at the output are produced:
Table 7.2.2
gain
1 6 24 50 100
input/mV
720 120 30 15 7.5
output/digits
30 000 30 000 30 000 30 000 30 000
The TC-value of the output (total measurement path) for G24 can be trimmed to a minimum value by selecting the best setting of the TRIMBTC subregister of the TRR register (see 7.5.7). A factory calibration is done for the amplifier offset (TRIMA). This data is stored in the ZZR register. ZZR-register mapping is given in 8.6.2
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AS8500 - Data Sheet
7.4 Modes of operation
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The AS8500 can run in different operation modes, which are selected and activated via the serial interface. Detailed description: Mode 0: MZL In power-on reset sequence, which is initiated by the on-chip power-on reset circuit whenever the power is connected , the registers are loaded from the Zener-Zap memory. Mode 1: MMS Measurement mode where the definition is taken from the registers CRA and CRG defined later on. The measurements are continuous and measured results are available after the ready flag (INTN pin) is set to LO. The result can be read by the µ C any time after this bit is set to LO. However, to obtain the best noise performances the result should be read when INTN pin is at LO state. All modules are in power-up. Mode 2: MMD Dual channel measurement mode. Two consecutive different measurements are performed according to the settings in the configuration registers CRA, CRB and CRG defined later (usually CRA defining current measurements and CRB voltage measurement). One complete measurement is performed with each setting. CRG register holds common settings. The measurements are continuous (A,B,A,B). The 17th bit in the output register defines, which measurement has been executed according to the definition LO=A, HI=B. The number of consecutive measurements with equal configuration is defined in register CRG (bits s3,s2,s1,s0). All modules are in power-up. Mode 3: MWU In this wake-up mode the internal clock finclk=256kHz is running and one complete measurement is performed in the period from 1 to 1.5 s with the parameter settings of the CRA register. Before the actual measurement is performed the logic powers up all internal circuits especially the AGND and the Vref. If the external load is higher than 70 kOhms both signals can be used for external triggering or even as interrupt for the µ C. If the external clock is not running, this input should be high impedance. To achieve a stable low idle current the oversampling ratio should be set to R1=128 and the CFG register must be programmed to x00003, see also 7.4 ‘Register description’. It is assumed that the threshold level in the THR register is defined within the 16 bit range, if not the default value is 210 After one measurement is finished all modules except the on- board oscillator and divider are switched into power down condition to save power. The MSR register is updated with the last measurement result. Whenever this value exceeds the digital threshold the (wake-up) INTN pin goes LO for one clock cycle to trigger the wake-up event in the external µ C. After that the circuit returns in power-down for approximately 1s. During this time the last measurement (MSR register) is available on the SDI interface. In this intermediate sleep-mode all modules except internal oscillator and divider are in power-down mode. The SDI interface works independent which means that the measurement result is available by reading the MSR register. At any time the microprocessor can start any other mode via SDI. In such a case the external clock must be switched on first. The chip goes in MWU mode (mode 3) after it received the command for that. After that command 6 or more additional CLK pulses are needed before external clock may go to power down mode (no CLK pulses, high level because of internal pull-up resistors). This 6 CLK pulses are needed for synchronisation. On the way back to normal mode this restriction is not needed. Mode 4: MAM In this alarm mode the measurement defined in CRA is going on. The channel bit in the THR register must be cleared (channel A). The threshold value may be positive or negative. Whenever the measured value exceeds the digital threshold value in the THR register the pin INTN (in this mode its function is to signal alarm-condition) goes LO for one clock cycle. For negative threshold value the signed measurement result must be more negative than the THR value to activate the alarm. During measurements the signal INTN is high. All modules are in power-up, measurements are continuously going on. Mode 5: MZP Zener-Zap programming/reading. This mode for factory programming only and should not be used by the customer. Mode 6: MPD Power down mode. Individual analog blocks can be disabled/enabled. The data acquisition system is not running during this mode is activated. Mode 7: MSI The operation in this mode is exactly the same as in MMS mode except that the internal clock is used. The SDI interface signals can become active whenever appropriate. This mode can be used if no external clock CLK is available. The measuring speed is reduced by a factor of 16. Modes 8-15: These modes are reserved for testing purposes and should not be used by the customer. Reading and writing of some registers is only possible in these higher modes. Write to registers CAR (calibration register) and TRR (trimming register) is allowed only in test modes.
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Modes of operation, register OPM Mode 0 1 2 3 4 5 6 7 8-15 Name MZL MMS MMD MWU MAM MZP MPD MSI Reserved for testing
1)
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Description Power on, loading from Zener-Zap memory Single measurement Double measurement (A,B,A,B …) Wake-up Alarm Zener program/read Power down
mo3 0 0 0 0 0 0 0 0 1
mo2 0 0 0 0 1 1 1 1 x
mo1 0 0 1 1 0 0 1 1 x
mo0 0 1 0 1 0 1 0 1 x
Notes: 1) Register addresses 12, 13, 14 and 15 are reserved for testing and future options; operations on these registers must be avoided 7.5 Register description
In the following sections the register contents and their functions are described in detail. Since the length of some registers is too long to present clearly, the registers are logically subdivided according to their functions and described separately. All internal functions are controlled by the contents of these registers which can be reloaded via the serial SDI interface at any time. The AS8500 contains the following registers: REGISTER OPM CRA CRB CRG MSR ZZR CAR TRR THR CFG reserved Note:
1)
ADDRESS 0 1 2 3 4 5 6 7 8 9 10-12
SIZE 4 17 17 28 18 188 110 20 17 20
Contents Operating mode register Measurement A configuration register Measurement B configuration register General configuration register Measurement result register Zener-Zap register Calibration register Trimming register Alarm or wake-up threshold register Test and special configuration register Test registers
Detailled description see 7.5.1 7.5.3 7.5.4 7.5.2 7.5.9 7.5.5 7.5.6 7.5.7 7.5.8
1)
This register is reserved for testing modes. Writing is possible only in mode 8. In order to assure stable conditions in power-down modes MWU(3), MPD(6), TMSS(8) and MSI(13) the default setting of the CFG register must be changed to x00003. It is not necessary to change this value during normal operation.
Write commands not supported in a certain mode can be released immediately after the register address. The ASSP will resume operation with the next start condition. Registers CAR and TRR are not buffered. Any read operation of the CAR or TRR register may generate transients in the analog circuitry; further accurate measurements require a delay time for settling.
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7.5.1 no. 0 1) 7.5.2 no. 0
OPM operation mode register ( 4 bits ) Bit default mo3 0 mo2 0 mo1 0 mo0 0 Note
1)
This register has been described in detail under 7.4 CRG general configuration register ( 28 bits ) CRG bits 27-22 CRS 21-11 CRI 10-7 CRV 6-0 CRP NOTE
subregister CRS: Sequence length, dechop and chop ( 6 bits ) Nr. 0 1 Bits CRS bit names Default 5 s3 0 4 s2 0 3 s1 0 2 s0 1 1 d 1 0 c 1 NOTE
1)
2)
Notes: 1) This register defines the sequence length, chopping (c) and dechopping (d) of the input signal 2) Default power-up state before any setting Sequence length bits ( 4bits) Nr. 0 1 … 14 15 No. of measurements 16 1 … 14 15 s3 0 0 … 1 1 s2 0 0 … 1 1 s1 0 0 … 1 1 s0 0 1 … 0 1 NOTE
1)
default
Notes: 1)Number of consecutive measurements of A and B with settings defined in CRA,CRB and other settings in CRG register. This setting is used only for mode MMD.
DECHOPPING BIT
Nr. 0 1
CHOPPING BIT
Dechopping No dechopping Dechopping
d 0 1
NOTE
Nr. 0 1
Chopping No chopping chopping
c 0 1
NOTE
subregister CRI: Current configuration ( 11 bits ) Nr. 0 1 2 Bits CRI bit names Default output 10 M14 0 VBAT 9 M13 0 RSHL 8 M12 0 RSHH 7 M11 0 no 6 M8 0 ETS 5 M6 0 ETR 4 i4 0 3 i3 0 2 I2 0 1 i1 0 0 i0 0 NOTE
1),3)
2)
Notes: 1) whenever M1=1 in (CRA,CRB) it is good practice to set all M6 to M14 to zero, but it is not mandatory 2) default logic state after power up and before any setting 3) All bits with names M14 to M1 represent control signals of the multiplexer with positive logic (for example M14=1 means that corresponding switch is closed).
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Current source setting bits (5 bits) Nr. 0 1 2 3 4 … 31 Current [uA] 0 8 16 24 32 … 248 1 i4 0 0 0 0 0 i3 0 0 0 0 0 … 1 i2 0 0 0 0 1 … 1 i1 0 0 1 1 0 … 1 i0 0 1 0 1 0 … 1 NOTE
subregister CRV: Voltage configuration (4 bits ) Nr. 0 1 2 Bits CRV bit names Defaults channel 3 M15 0 VBATRSHL 2 M10 0 VBAT-ETS differential 1 M9 0 ETS-RSHL 0 M7 0 ETRRSHL NOTE
1),3)
2)
Notes: 1) This register defines the connection of the analog voltage- bus to the input-PINs and to the A/D converter 2) Default logic state after power-up and before any setting subregister CRP: Power down configuration ( 7 bits ) Nr. 0 1 2 Bits CRP bit names Defaults block p6 pdosc 0 p5 pda 0 p4 pdm 0 modulator p3 pdb 0 ref. bias p2 pdc 1 current source p1 pdi 0 internal temp. p0 pdg 0 analog GND NOTE
1),3)
2)
oscillator amplifier
Notes: 1) This register defines the power-down signals of the building blocks 2) Default power-up state before any setting 3) The logic is positive (pdosc=1 means the corresponding block is in power-down) 7.5.3 Nr. 0 1 2 CRA measurement channel A configuration register ( 17 bits ) Bits CRA bit names Defaults subreg. 16 cu2 0 15 cu1 0 CRU 14 cu0 0 13 M5 0 12 M4 0 11 M3 0 CRM 10 M2 0 9 M1 1 8 g1 1 GN 7 g0 1 6 f 1 OSF 5 r 0 OSR 4 32 mm n3 n2 0 MM 0 0 1 n1 0 CRN 0 n0 0 NOTE
1), 3)
2)
Notes: 1) This register defines the measurement channel A configuration 2) Default power-up state before any setting 3) Bit M1 is control signal of the multiplexer for current input (for example M1=1 means that corresponding switch is closed).
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subregister CRU: calibration constant selection for voltage path ( 3 bits) in registers CRA,CRB Nr. 0 1 2 3 4 5 6 7 Calibration const. U CAU0 CAU1 CAU2 CAU3 CAU4 CAU5 1548 1548 cu2 cu1 cu0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 NOTE
subregister CRM: measurement path for registers CRA,CRB Nr. Bits CRA bit names Defaults 13 M5 0 0 0 0 1 1 1 12 M4 0 1 1 1 0 0 0 11 M3 0 0 0 1 0 0 1 10 M2 0 0 1 0 0 1 0 9 M1 1 0 0 0 0 0 0 NOTE
1), 2)
1 2 3 4 5 6 7
measurement RSHH-RSHL voltage bus voltage bus, internal temperature voltage bus, reference low=RSHL voltage bus, gain=1 voltage bus,gain=1, internal temperature voltage bus, gain=1, reference low=RSHL
Notes: 1) these bits define the inner part of the voltage path settings 2) only the listed combinations are allowed subregister GN: gain definition bits, Registers CRA,CRB Nr. 0 1 2 3 GAIN 6 24 50 100 g1 0 0 1 1 g0 0 1 0 1 NOTE
subregister OSF: oversampling frequency bit, Registers CRA,CRB Nr. 0 1 Fovs (fclk=8MHz) 2.048MHz 4.096MHz Fovs (internal osc) 132kHz 264kHz f 0 1 NOTE
1) 1)
Notes: 1) For internal oscillator typical values subregister OSR: oversampling ratio bit, Registers CRA, CRB Nr. 0 1 R1 64 128 r 0 1 NOTE
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subregister MM: chopping ratio bit, Registers CRA, CRB Nr. 0 1 2 MM 4 8 1 mm 0 1 x
1)
NOTE
Notes: 1) For c=0 and d=0 , chopping and dechopping is switched off and every cycle is active regardless of mm, i.e. the sampling frequenzy is higher by a factor of 4 subregister CRN: averaging bits ( 4 bits), registers CRA,CRB Nr. 0 1 2 3 4 5 6 7 8 9 10 11-14 15 R2 1 2 4 8 16 32 64 128 256 512 1024 Reserved for test raw mode n3 0 0 0 0 0 0 0 0 1 1 1 1 1 n2 0 0 0 0 1 1 1 1 0 0 0 x 1 n1 0 0 1 1 0 0 1 1 0 0 1 x 1 n0 0 1 0 1 0 1 0 1 0 1 0 x 1
1) 2)
NOTE
Note: 1) combinations from B to E are reserved for test 2) this mode delivers the AD-values without calibration and averaging but multiplied by a factor which is dependent on the setting of the oversampling ratio. It can be used for high resolution measurements of very low signals since it eliminates the internal rounding error. The ratio between raw result (Nr) and normal result (Nn) is given by: Nr/Nn = 2^(11+x)/CAL where x=6 for R=128 and x=3 for R=64. CAL is the calibration constant used. 7.5.4 Nr. 0 1 2 CRB measurement channel B configuration register ( 17 bits ) Bits CRB bit names Defaults subreg. 16 cu2 0 15 cu1 0 CRU 14 cu0 0 13 M5 0 12 M4 1 11 M3 1 CRM 10 M2 0 9 M1 0 8 g1 0 GN 7 g0 1 6 f 1 OSF 5 r 0 OSR 4 mm 0 MM 3 n3 0 2 n2 0 CRN 1 n1 0 0 n0 0 NOTE
1), 3)
2)
Notes: 1) This register defines the measurement channel B configuration, the functions of the subregisters are the same as described above for measurement channel A 2) Default power-up state before any setting 3) In this mode the chip cannot measure the current sensing input RSHH-RSHL, therefore M1=0 for all settings
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7.5.5
ZZR Zener-Zap register (188 bits ):
For the AS8500 the zener zap registers are set to a predefined default value. As an exception the TRIMA bits in the ZTR subregister is factory adjusted for minimum amplifier offset to ensure optimum linearity over input range.
Nr. 0 ZZR bits 183-187 ZLO 163-182 ZTR 53-162 ZCL 0-52 ZTC1) NOTE
2)
Notes: 1) 5 bits are reserved for:
- 1 bit eventually destroyed during testing, - 2 bits for testing programmed 0 and 1 - 2 bits reserved for locking 2) due to a limited driving capability of the ZZR-cells the maximum reading speed is limited to 500 kHz subregister ZLO: Zener spare bits ( 5 bits ) Nr. 1 Name Reserved bits SYMBOL ZLO WORD WIDTH 5 Default Hex F
subregister ZTR: trimming bits (20 bits) Nr. 0 1 2 3 4 PARAMETER TC of reference absolute value of reference amplifier offset current source for external temperature ∑ trim bits SYMBOL TRIMBTC TRIMBV TRIMA TRIMC TRIMREG WORD WIDTH 5 5 5 5 20 UNIT Bits Bits Bits Bits Bits
subregister ZCL: calibration bits ( 110 bits ) Nr. 0 1 2 3 4 5 6 7 8 9 10 PARAMETER Calibration G=6, I Calibration G=24, I Calibration G=50, I Calibration G=100, I Calibration U0 Calibration U1 Calibration U2 Calibration U3 Calibration U4 Calibration U5 ∑ cal. Bits SYMBOL CGI1 CGI2 CGI3 CGI4 CAU0 CAU1 CAU2 CAU3 CAU4 CAU5 ZCL WORD WIDTH 11 11 11 11 11 11 11 11 11 11 110 UNIT Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits
Calibration constants are selected dependent on state of M1 ( see table below). For M1=1 one of CGI1 to CGI4 is selected according to selected gain of amplifier. For M1=0 the selection of the calibration constants is defined by bits (cu2,cu1,cu0), which are part of CRA and CRB registers and are defined via SDI interface independently of any other selection.
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Calibration constant selection truth table Nr. cu2 cu1 cu0 M1 g1 x x x 1 0 0 1 2 3 4 5 6 7 8 9 10 11 x x x 0 0 0 0 1 1 1 1 x x x 0 0 1 1 0 0 1 1 x x x 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 x x x x x x x x
g0 0 1 0 1 x x x x x x x x
CAL CONST CGI1 CGI2 CGI3 CGI4 CAU0 CAU1 CAU2 CAU3 CAU4 CAU5 1548 1548
NOTE
1) 1) 1) 1) 2) 2) 2) 2) 2) 2)
Notes: 1) CGIx calibration constants are selected when M1=1 according to selected gain 2) CGUx calibration constants are selected when M1=0 according to bits cu2 to cu0 defined via SDI in CRA and/or CRB registers. subregister ZTC: These bits are spare bits and can be used on special request (e.g. ID number).
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7.5.6
CAR calibration register ( 110 bits )
The aim of the calibration register is to hold the calibration constants that are used by the internal DSP for the correction of each measurement (for the factory calibrated version AS8501). At power-up sequence the Zener-Zap subregister ZCL default setting is copied into the CAR register. The register can be read or written in mode 8 via the SDI bus at any time. In particular for the AS8500, which is not factory calibrated it is intended to overwrite the default setting with external data defined by the user. Nr. 0 1 CAR bits 109-99 98-88 Subregister CGI1 CGI2 default 1548 1548 87-77 CGI3 1548 76-66 CGI4 0 65-55 CAU0 1548 54-44 CAU1 2047 43-33 CAU2 2047 32-22 CAU3 1548 21-11 CAU4 1548 10-0 CAU5 1548 NOTE
1) 2)
Notes: 1) Calibration register is composed of the following constants each having 11 bits: CGI1, CGI2, CGI3, CGI4, CAU0, CAU1, CAU2, CAU3, CAU4, CAU5 2) Decimal default value of the calibration constant for voltage and current is calculated using formula: CGdef=Nmax/NADdef=(Vref*1024)/(Vin*Gmax)=1548 7.5.7 TRR trimming register ( 20 bits )
In the TRR register the calibration constants for the reference voltage, for the amplifier-offset trim and for the current source setting are stored. At power-up sequence the Zener-Zap subregister ZTR is loaded into the TRR register. This register can be read or written in mode 8 via the SDI bus. In particular it is possible to write preliminary calibration constants into TRR or overwrite the loaded ZTR data, if a calibration has been changed. The trimming of the TRR-registors is usually done at the factory before supplying the part. Nr. 0 1 TRR bits Subregister default 19-15 TRIMC 4 14-10 TRIMA typ 0 or 1 9-5 TRIMBV 16 4-0 TRIMBTC 17 NOTE
1)
Notes: 1)writing into TRR register is done as usual with the MSB first subregister TRIMC change of current source output with TRIMC bits Nr. 0 1 2 .. 14 15 16 17 18 .. 30 31 trimcs 0 0 0 .. 0 0 1 1 1 .. 1 1 trimc3 0 0 0 .. 1 1 0 0 0 .. 1 1 trimc2 0 0 0 .. 1 1 0 0 0 .. 1 1 trimc1 0 0 1 .. 1 1 0 0 1 .. 1 1 trimc0 0 1 0 .. 0 1 0 1 0 .. 0 1 dI/Io % 0 -1*2.3 -2*2.3 .. –14*2.3 –15*2.3 16*2.3 15*2.3 14*2.3 .. 2*2.3 1*2.3
1),2) 1),2) 1),2) 1),2)
Notes
1),2) 1),2) 1),2)
1),2)
Notes: 1) Io is the current in µ A at TRIMC = 00000 2) The output current of the internal current source can be controlled in a wide range via the bit setting in CRG. In some applications it may be necessary to trim the current in the rang of +/- 30% for an optimum result of the external temperature measurement. This trimming is achieved with writing into subregister TRIMC of the TRR register. The trimming is done in % for all ranges selected in CRG register.
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subregister TRIMA
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The offset of the PGA is factory trimmed to a mimimum absolute value to guarantee the full dynamic range with all gain settings. change of amplifier offset with TRIMA bits
Nr. 0 1 2 .. 14 15 16 17 18 .. 30 31 trimas 0 0 0 .. 0 0 1 1 1 .. 1 1 trima3 0 0 0 .. 1 1 0 0 0 .. 1 1 trima2 0 0 0 .. 1 1 0 0 0 .. 1 1 trima1 0 0 1 .. 1 1 0 0 1 .. 1 1 trima0 0 1 0 .. 0 1 0 1 0 .. 0 1 Voffset mV Uos Uos -1*1.34 Uos -2*1.34 .. Uos –14*1.34 Uos –15*1.34 Uos Uos +1*1.34 Uos +2*1.34 .. Uos +14*1.34 Uos +15*1.34
1),2) 1),2) 1),2) 1),2)
Notes
1),2) ,3) 1),2) 1),2)
1),2)
Notes: 1) Uos is the input offset voltage in mV at TRIMA = 00000 2) Every step of TRIMA settings brings $offset=1.34 mV change in absolute value of the input offset voltage. If the measured value is Uos then the number that should be written into the TRIMA for minimum final absolute value is calculated as TRIMA=int((Uos)/1.34) for Uos above zero and TRIMA=16+int(-Uos)/1.34) for Uos below zero. 3) The input offset voltage can be measured with chopping and dechopping bits being cleared in register CRG. Any input channel as well as gain settings can be used. The input should be shorted to avoid any external voltages to interfere with the measurement. If the measured output voltage is Va then the offset voltage is calculated acc. Vos = Va/gain. subregister TRIMBV
change of reference voltage Uo with TRIMBV bits
Nr. 0 1 2 .. 14 15 16 17 18 .. 30 31 trimbvs 0 0 0 .. 0 0 1 1 1 .. 1 1 trimbv3 0 0 0 .. 1 1 0 0 0 .. 1 1 trimbv2 0 0 0 .. 1 1 0 0 0 .. 1 1 trimbv1 0 0 1 .. 1 1 0 0 1 .. 1 1 trimbv0 0 1 0 .. 0 1 0 1 0 .. 0 1 VREF mV Ua Ua -1*5.1 Ua -2*5.1 .. Ua –14*5.1 Ua –15*5.1 Ua Ua +1*5.1 Ua +2*5.1 .. Ua +14*5.1 Ua +15*5.1
1),2) 1),2) 1),2) 1),2)
Notes
1),2) 1),2) 1),2)
1),2)
Notes: 1) Ua is the reference voltage in mV at TRIMBTC = 00000, the optimum value is 1.232V. 2) Every step of TRIMBV settings brings $BV=5.1 mV change in absolute value of the reference voltage. For trimming the TC value and absolute value of the reference voltage it is recommended to trim the TC value first and then trim the absolute value since TRIMBTC is changing both TC and absolute value, whereas TRIMBV is changing only the absolute value. If the measured absolute value is Uam then the number that should be written into the TRIMBV for optimum final absolute value is calculated as TRIMBV=int((Uam-1.231)/0.0051) for Uam above the ideal value and
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TRIMBV=16+int(-(Uam-1.232)/0.0051) for Uam below the ideal value. subregister TRIMBTC change of reference voltage Uo and TC-value with TRIMBTC bits Nr. 0 1 2 .. 14 15 16 17 18 .. 30 31 trimbtcs 0 0 0 .. 0 0 1 1 1 .. 1 1 trimbtc3 0 0 0 .. 1 1 0 0 0 .. 1 1 trimbtc2 1 0 0 0 .. 1 1 0 0 0 .. 1 1 trimbtc1 1 0 0 1 .. 1 1 0 0 1 .. 1 1 trimbtc0 0 1 0 .. 0 1 0 1 0 .. 0 1 VREF mV Uo Uo -1*5.2 Uo -2*5.2 .. Uo –14*5.2 Uo –15*5.2 Uo Uo +1*5.2 Uo +2*5.2 .. Uo +14*5.2 Uo +15*5.2 TCo -14*12.7 TCo -15*12.7 TCo +1*12.7 TCo -2*12.7 .. TCo -14*12.7 TCo -15*12.7
1),2) 1),2) 1),2) 1),2) 1),2)
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TC ppm/K TCo TCo -1*12.7 TCo -2*12.7
Notes
1),2) 1),2) 1),2)
Notes: 1) Uo is the reference voltage in mV and TCo is the TC value in ppm/K at TRIMBV = 00000 2) Every step of TRIMBTC settings brings $BTC=5.2 mV change in absolute value of the reference voltage and S=12.7 ppm/K change in the slope of temperature dependence. So for trimming the temperature coefficient of the band-gap reference 2 measurements are recommended ( at T1=25oC and at T2=125oC ). If the measured TC value is TCm then the number that should be written into the TRIMBTC for minimum final TC is calculated as trimBTC=int(TCM/12.7) for positive values and trimBTC=16+int(-TCM/12.7) for negative values. The absolute voltage is also changed in this way, which must be compensated by bringing back the absolute value by changing the TRIMBV register. Usually the TRIMBVx=-TRIMBTCx+1 is sufficient. If further accuracy or change of absolute value is necessary it can be adjusted by making some more measurements and adjustments.
ZZR REGISTER: ZLO 5 ZTR 20 ZCL 110 ZTC 53 188
R/W
TRR reg.7 bit0 bit0 CAR
CAR reg.6
data in
TRR
ZLO
bit0
bit0
Figure 4 Copying of ZCL and ZTR registers into CAR and TRR registers
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7.5.8 Nr. 0 default THR alarm (Wake-up) threshold register ( 17 bits ) MR16 A/B 0 MR15 s 0 MR14 Msb 1 0 0 MR13 MR12 MR11 … MR1 MR0 lsb 0
1)
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NOTE
Notes: 1) _ All measurements are performed in channel A therefore MR16 must be set to zero. When channel B is selected no interrupt will be generated. - The signed value is used. For positive THR values the ASSP will initiate an interrupt whenever the measured value is bigger than the THR value. For negtive THR values the interrupt will be generated for a negative result with an absolute value bigger than the absolute value of the THR register. 7.5.9 Nr. MSR measurement result register ( 18 bits ) MR17 Overflow/un derflow MR16 A/B MR15 S MR14 msb MR13 MR12 MR11 … MR1 MR0 lsb
1)
NOTE
Notes: 1) - Result word length is 16 bits because of calibration accuracy and to maintain all possible resolutions ( different setting ). - A/B bit signifies which measurement was performed: the one defined in CRA or CRB: MR16=0 -> A MR16=1 -> B - Overflow/underflow bit is set whenever the result after multiplication by calibration constant is bigger than 32767 or smaller than –32767. In Wake-up or Alarm mode the overflow/underflow always sets INTN signal to LO.
8
Digital interface description
The digital interface of the AS8500 consists of two input pins (CLK and SCLK) and two I/O pins (INTN and SDAT). The SCLK and SDAT pins are used as universal serial data interface (SDI). SDI operates only if external clock signal (CLK) is running. 8.1 CLK
In all operating modes except the Wake-up mode this pin must be connected to 8 MHz clock signal. In the Wake-up mode (MWU) the CLK pin must be connected to logic HI or float. 8.2 INTN
The INTN pin is used to signal various conditions to the microcontroller, depending on the operating mode. application modes of the INTN pin Mode 0 1, 2,7 3 4 5 6,8,9 10 10 Signal Load clock (internal) SDI clock disable idle / wake-up not idle / alarm not PW1 Logic ‘0’ t12 t18 Direction Output Output Output Output Input Output Output Output Purpose Indicates progress of the Zener-Zap load process Signals new result and suggests when to disable SCLK in high-precision measurement phase Signals the wake-up condition Signals the alarm condition Shows the programming pulse width No purpose Test mode Test mode Note
1) 2)
Notes: 1) 188 clock pulses are generated from the internal oscillator source during the loading time. 2) In measurement modes (MMS and MMD) the INTN pin is used to synchronize the SDI bus operations (see figure 5).
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The trailing edge of INTN signals the start of a new measurement.
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i-1
start measurement i Tcnv
i+1
INTN
available results on SDI
i-2
i-1 Tres
i
Figure 5: INTN pin in modes 1 and 2
The determination of Tcnv and Tres from the parameter settings is: Tcnv % R1/(fovs*2) 8.3 SDI bus operation Tres = MM*Tcnv*R2*2 with R1=OSR and R2=number of averages
SDI bus is a 2-line bi-directional interface between one master and one slave unit. Typically the master unit is a microcontroller with softwareimplemented SDI protocol. The ASSP is always the slave unit. SDI bus operation is presented on figure 6. During data transfers the sdat signal changes while sclk is low. The sdat signal can change while sclk is high only to generate start or exception conditions.
Direction
Address
Register data
sclk
SDAT
Start
Data transfer
Exception
Figure 6: SDI bus operation
The master unit always generates the sclk signal.
Strobe ASSP
The master unit generates the sdat signal in start, direction, address, master-write data and exception conditions. The master sdat pin is in high-impedance state in master-read data condition.
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The slave unit drives the sdat signal only in master-read data condition. In all other cases the slave sdat pin is in high-impedance state. During data transfer in read condition the internal AD-conversion in continuing but the data in the MSR-register is not updated and the output of the INTN signal is suppressed. Only after the completion of the reading cycle the ASSP returns to the normal condition and updates the MSRregister immediately if a new AD-conversion has been finished during data transfer. The master unit does not detect any bus conditions since it generates them. Data transfer conditions (direction, register address and register data) must not be changed until the current condition is over. The slave unit does not detect start and exception condition when master-read is in progress. The exception condition is reserved for future use and should be avoided. 8.4 Data transfers
Generally the SDI interface is active in all ASSP modes. For security reasons some write operations are restricted to certain modes. Read operations are never disabled in order to keep consistent sdat driving conditions. Writing to the result, trimming and calibration registers (MSR, CAR and TRR) is allowed only in test modes. Writing to the Zener-Zap register is allowed only in mode MZP. The first data bit after the start condition in each data transfer defines the data direction: sdat=high is used for master-read data (mr) condition and sdat=low for master-write data (mw) condition. Data is transferred with the most significant bit (MSB) first. Data bits are composed of register address and register data bits. Register address is transmitted first, followed by the register data bits. The register address is always 4 bits long. The number of register data bits (see 7.5) is implied by the register address.
sclk mr sdat mw a3 a2 a1 a0 MSB LSB
Direction
Figure 7: SDI Data transfer
Register address
Register data
The ASSP supports the data transfers presented in the following table: master read-write operations REGISTER ADDRESS Contents read write allowed in allowed in modes modes All All All All All All All All All All All >7 5 >7 page
OPM CRA CRB CRG MSR ZZR CAR
0 1 2 3 4 5 6
operating mode measurement set-up A measurement set-up B general measurement conditions measurement result Zener-Zap data calibration register
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TRR THR 7 8 trimming register alarm or wake-up threshold register All All >7 All
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8.5
SDI bus timing
Timing definitions for SDI bus are based on software-implemented master unit protocol
MDE
DV_m
PW_sclk
DV_m
TS_m
LO_sclk
TS_m
sclk
(uP)
master sdat
(uP)
HI - Z
slave sdat
(ASIC)
HI - Z
TS_s
DV_s CDD
TS_S
strobe ASSP
strobe µC
Figure 8: SDI Bus timing
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SDI bus timing Nr. 0 1 2 3 4 5 6 7 PARAMETER SCLK pulse width SCLK low Master SDAT exception after SCLK Master SDAT valid before/after SCLK Slave SDAT not valid after SCLK Master 3-state ON/OFF Slave 3-state ON/OFF Bus condition detection disabled in slave unit SYMBOL PW_sclk LO_sclk MDE DV_m DV_s TS_m TS_s CDD TS_s TSW 120 MIN 120 120 120 120 TSW 120 TYP MAX Unit ns ns ns ns ns ns ns ns Conditions All All All All Master read Master read Master read Master read
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NOTE
5), 6)
1)
3)
Notes: 1)TSW is typical time required by the microcontroller program to change or to read the state of the I/O pin 3) Start detection is disabled when slave unit transmits data 5) LO_sclk>300ns and PW_sclk> 2µ sec required to read ZZR. 6) LO_sclk > (3/2)*TCLK = (3/2)/f CLK = (3/2)/8MHz=187.5ns required for results synchronisation in MSR. 8.6 8.6.1 SDI access to OTP memory ZZR register bit mapping 0 pos A 1) ZLO 187 (msb) 1 pos B 2) ZLO 186 2 pos C 3) ZLO 185 3 lock A ZLO 184 4 lock B 5) ZLO 183 5 trimcs ZTR 182 6 trimc3 ZTR 181 7 trimc2 ZTR 180
SDI can read the OTP memory in any mode by reading the register ZZR.
Cell index Purpose ZZR field ZZR bit
1) Always 2) Always
4)
programmed to '0' during the production test programmed to '0' during the production test 3) Always programmed to '1' during the production test 4) Reserved 5) Reserved
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Cell index Purpose ZZR field ZZR bit Cell index Purpose ZZR field ZZR bit Cell index Purpose ZZR field ZZR bit Cell index Purpose ZZR field ZZR bit Cell index Purpose ZZR field ZZR bit Cell index Purpose ZZR field ZZR bit
8 trimc1 ZTR 179 16 trimbv3 ZTR 171 24 trimbtc0 ZTR 163 32 cgi1_3 ZCL 155 40 cgi2_6 ZCL 147 48 cgi3_9 ZCL 139
9 trimc0 ZTR 178 17 trimbv2 ZTR 170 25 cgi1_10 ZCL 162 33 cgi1_2 ZCL 154
10 trimas ZTR 177 18 trimbv1 ZTR 169 26 cgi1_9 ZCL 161 34 cgi1_1 ZCL 153 42 cgi2_4 ZCL 145 50 cgi3_7 ZCL 137
11 trima3 ZTR 176 19 trimbv0 ZTR 168 27 cgi1_8 ZCL 160 35 cgi1_0 ZCL 152 43 cgi2_3 ZCL 144 51 cgi3_6 ZCL 136
12 trima2 ZTR 175 20 trimbtcs ZTR 167 28 cgi1_7 ZCL 159 36 cgi2_10 ZCL 151 44 cgi2_2 ZCL 143 52 cgi3_5 ZCL 135
13 trima1 ZTR 174 21 trimbtc3 ZTR 166 29 cgi1_6 ZCL 158 37 cgi2_9 ZCL 150 45 cgi2_1 ZCL 142 53 cgi3_4 ZCL 134
14 trima0 ZTR 173 22 trimbtc2 ZTR 165 30 cgi1_5 ZCL 157 38 cgi2_8 ZCL 149 46 cgi2_0 ZCL 141 54 cgi3_3 ZCL 133
15 trimbvs ZTR 172 23 trimbtc1 ZTR 164 31 cgi1_4 ZCL 156 39 cgi2_7 ZCL 148 47 cgi3_10 ZCL 140 55 cgi3_2 ZCL 132
41 cgi2_5 ZCL 146 49 cgi3_8 ZCL 138
Cell index Purpose ZZR field ZZR bit Cell index Purpose ZZR field ZZR bit
56 cgi3_1 ZCL 131 64 cgi4_4 ZCL 123
57 cgi3_0 ZCL 130 65 cgi4_3 ZCL 122
58 cgi4_10 ZCL 129 66 cgi4_2 ZCL 121
59 cgi4_9 ZCL 128 67 cgi4_1 ZCL 120
60 cgi4_8 ZCL 127 68 cgi4_0 ZCL 119
61 cgi4_7 ZCL 126 69 cau0_10 ZCL 118
62 cgi4_6 ZCL 125 70 cau0_9 ZCL 117
63 cgi4_5 ZCL 124 71 cau0_8 ZCL 116
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Cell index Purpose ZZR field ZZR bit Cell index Purpose ZZR field ZZR bit Cell index Purpose ZZR field ZZR bit Cell index Purpose ZZR field ZZR bit Cell index Purpose ZZR field ZZR bit Cell index Purpose ZZR field ZZR bit Cell index Purpose ZZR field ZZR bit Cell index Purpose ZZR field ZZR bit
72 cau0_7 ZCL 115 80 cau1_10 ZCL 107 88 cau1_2 ZCL 99 96 cau2_5 ZCL 91 104 cau3_8 ZCL 83 112 cau3_0 ZCL 75 120 cau4_3 ZCL 67 128 cau5_6 ZCL 59
73 cau0_6 ZCL 114 81 cau1_9 ZCL 106 89 cau1_1 ZCL 98 97 cau2_4 ZCL 90 105 cau3_7 ZCL 82 113 cau4_10 ZCL 74 121 cau4_2 ZCL 66 129 cau5_5 ZCL 58
74 cau0_5 ZCL 113 82 cau1_8 ZCL 105 90 cau1_0 ZCL 97 98 cau2_3 ZCL 89 106 cau3_6 ZCL 81 114 cau4_9 ZCL 73 122 cau4_1 ZCL 65 130 cau5_4 ZCL 57
75 cau0_4 ZCL 112 83 cau1_7 ZCL 104 91 cau2_10 ZCL 96 99 cau2_2 ZCL 88 107 cau3_5 ZCL 80 115 cau4_8 ZCL 72 123 cau4_0 ZCL 64 131 cau5_3 ZCL 56
76 cau0_3 ZCL 111 84 cau1_6 ZCL 103 92 cau2_9 ZCL 95 100 cau2_1 ZCL 87 108 cau3_4 ZCL 79 116 cau4_7 ZCL 71 124 cau5_10 ZCL 63 132 cau5_2 ZCL 55
77 cau0_2 ZCL 110 85 cau1_5 ZCL 102 93 cau2_8 ZCL 94 101 cau2_0 ZCL 86 109 cau3_3 ZCL 78 117 cau4_6 ZCL 70 125 cau5_9 ZCL 62 133 cau5_1 ZCL 54
78 cau0_1 ZCL 109 86 cau1_4 ZCL 101 94 cau2_7 ZCL 93 102 cau3_10 ZCL 85 110 cau3_2 ZCL 77 118 cau4_5 ZCL 69 126 cau5_8 ZCL 61 134 cau5_0 ZCL 53
79 cau0_0 ZCL 108 87 cau1_3 ZCL 100 95 cau2_6 ZCL 92 103 cau3_9 ZCL 84 111 cau3_1 ZCL 76 119 cau4_4 ZCL 68 127 cau5_7 ZCL 60 135 tcu1_8 ZTC 52
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Cell index Purpose ZZR field ZZR bit Cell index Purpose ZZR field ZZR bit Cell index Purpose ZZR field
136 tcu1_7 ZTC 51 144 tcu0_8 ZTC 43 152 tcu0_0 ZTC 35 160 trt0_3 ZTC 27 168 tcn3_3 ZTC 19 176 tcn2_3 ZTC 11 184 tcn1_3 ZTC 3
137 tcu1_6 ZTC 50 145 tcu0_7 ZTC 42 153 trt0_10 ZTC 34 161 trt0_2 ZTC 26 169 tcn3_2 ZTC 18 177 tcn2_2 ZTC 10 185 tcn1_2 ZTC 2
138 tcu1_5 ZTC 49 146 tcu0_6 ZTC 41 154 trt0_9 ZTC 33 162 trt0_1 ZTC 25 170 tcn3_1 ZTC 17 178 tcn2_1 ZTC 9 186 tcn1_1 ZTC 1
139 tcu1_4 ZTC 48 147 tcu0_5 ZTC 40 155 trt0_8 ZTC 32 163 trt0_0 ZTC 24 171 tcn3_0 ZTC 16 179 tcn2_0 ZTC 8 187 tcn1_0 ZTC 0
140 tcu1_3 ZTC 47 148 tcu0_4 ZTC 39 156 trt0_7 ZTC 31 164 tcn3_7 ZTC 23 172 tcn2_7 ZTC 15 180 tcn1_7 ZTC 7
141 tcu1_2 ZTC 46 149 tcu0_3 ZTC 38 157 trt0_6 ZTC 30 165 tcn3_6 ZTC 22 173 tcn2_6 ZTC 14 181 tcn1_6 ZTC 6
142 tcu1_1 ZTC 45 150 tcu0_2 ZTC 37 158 trt0_5 ZTC 29 166 tcn3_5 ZTC 21 174 tcn2_5 ZTC 13 182 tcn1_5 ZTC 5
143 tcu1_0 ZTC 44 151 tcu0_1 ZTC 36 159 trt0_4 ZTC 28 167 tcn3_4 ZTC 20 175 tcn2_4 ZTC 12 183 tcn1_4 ZTC 4
ZZR bit
Cell index Purpose ZZR field ZZR bit Cell index Purpose ZZR field ZZR bit Cell index Purpose ZZR field ZZR bit Cell index Purpose ZZR field ZZR bit
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8.6.2 Stored ZZR-register mapping
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ZZR ZLO ZTR
subreg
bitno in subregister 10 9 8 7 6 msb
ZZR bits 5 4 x 0 x 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 3 x 0 x 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 2 x 1 x 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 x 0 x 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 lsb x 0 x 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 187 182 177 172 167 162 151 140 129 118 107 96 85 74 63 52 43 34 23 15 7 183 178 173 168 163 152 141 130 119 108 97 86 75 64 53 44 35 24 16 8 0
Remarks
ZCL
TRIMC TRIMA TRIMBV TRIMBTC CGI1 CGI2 CGI3 CGI4 CAU0 CAU1 CAU2 CAU3 CAU4 CAU5
1 1 1 0 1 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1
ZTC
0 0 0 0 0 1 1 0 0 0 1 1 1
0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1
0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1
0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1
current souce PGA offset voltage reference reference TC gain 6 current gain 24 current gain 50 current gain 100 current gain 24 gain 1 gain 100 inernal temperature spare bits
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9
General application hints
Since the AS8500 is optimised for low voltage applications extreme care should be taken that the signal is not disturbed by influences like bad ground reference, external noise pick-up, thermal EMFs generated at the transition of different materials or ground loops. The influence of these error sources can be quite high and they may completely shadow the excellent properties of the device if not handled properly. The following sections are supposed to supply additional informations to the design engineer how to get around some of these problems. 9.1 Ground connection, analog common
The analog common terminal where all voltages are referring to is RSHL. All ground lines of the external circuitry of VBAT, ETS and ETR as well as the voltage sense line of the low ohmic current sensing resistor should be connected to each other in a star like ground point. It is recommended that this point is as close as possible situated to the low side sense terminal of the current sensing resistor. It should also be connected to the VSS and VSSD terminal, but the return line of both must leave this point separately. Also the power decoupling capacitors should be connected to the analog common. To give an example of the magnitude of possible errors consider that the ground return of the power supply is not connected properly and 5 mm of a copper track 35µ m thick and 0.1 mm wide are within the measuring circuit with a current flow of 5 mA. This will result in an offset of 120 µ V which is more than 500 times higher than the typical offset of the ASSP. In addition the current fluctuations will act as an extra noise voltage which is also way above that of the device itself. 9.2 Thermal EMF
another major source of error for low level measurements are thermal voltages (electromotive force, thermal EMF) or Seebeck voltages which are principally produced by any junction of two dissimilar materials. On PC-boards pairs of dissimilar materials may consist of the copper tracks and the solder, the leads of different components or different materials used in the construction within the components. Any temperature difference between two connection produces a voltage which is superimposed to the measuring voltage. A number of strategies are known to detect or minimise their influence on the measuring result: in cases were a current has to be measured directly or a current is to be used to activate a resistive sensor (like Ohm-meter or temperature measurement with RTDs, NTC or PTC) a switch in the circuit could be used to interrupt or invert the current thus producing a current change dI. In the difference of the two voltage states dU the EMFs as well as the Offset voltages of the amplifier are fully eliminated. For resistance measurements this method is known as ‘true Ohm’ measurement. in applications were this is not possible and the problematic device (i.e. the input resistor of an amplifier) can be located it may help to place a dummy device of the same type in the circuit as close and thermally connected as good as possible to compensate the influence of the first one. Since the thermal EMFs are proportional to the temperature difference it is important to maintain a homogeneous temperature distribution in the vicinity of the sensitive area. This is possible by keeping this area as small as possible, by avoiding any heat sources nearby or by increasing the heat conductivity of the substrate, i.e. wide and thick copper tracks, multilayer board or even metal substrate. The best solution of all however is to avoid the thermal EMFs by using only components which are matched to the copper world which means that their thermo-electrical power against copper is zero. This is specially important for current measurements in the range of 10- 1000A. In this case the resistance value has to be very low (down to 100µ Ohms) to limit the measuring power and avoid an overheating of the sensing resistor. On the other hand the voltages to be detected are extremely low if a high resolution is required. If for instance a current of 10 mA has to be measured with a 100µ Ohm resistor, the resolution of the measuring system must be better than 1µ V and the error voltages due to thermal EMFs must be below this limit. Quite often people are trying to use the well known Konstantan (CuNi44) for current sensing resistors. This is a bad choice since the thermal EMF versus copper is very high. With –40µ V/deg already a temperature difference of 2.5 K is enough to produce an error which is 100 times lager than the required resolution. Or vice versa a temperature fluctuation of only 1/100 K produces a ‘thermal noise’ which is equivalent to the required resolution. With such materials and high currents of 10A and above the other thermoelectric effect, the so called Peltier-effect, can also play an important role. Under current flow this effect generates heat in one junction and destroys the same amount of heat in the other junction. The amount of heat is proportional to the current and its direction. The result is a temperature difference which in turn generates a thermal EMF proportional to it. Finally this means that such a resistor produces its own error voltage and it is never possible to measure better than 1-2% with such badly matched materials. The precision resistance materials Manganin, Zeranin and Isaohm are perfectly matched to the copper world and resistors made from these materials can achieve the high quality that is necessary for low level measurements and high resolution. 9.3 Noise considerations
-
-
for every low level measuring system it is essential to know the origin of noise and to accept the limitations given by it. Three major sources of noise have to be considered. The input voltage noise and the input current noise of the amplifier and the thermal noise (Johnson noise) of resistors in the external circuitry around the amplifier. Due to the fact that these three sources are not correlated they can be added in the well known square root equation. In most applications the input resistor or input divider is low ohmic (i.e. below 10 kOhms) which mean that the noise voltage produced by the input current noise is negligible compared to the input voltage noise. The input noise density (En) of the AS8500 is with only 35 nV/sqr(Hz) extremely low. This could be achieved with a special internal analog and digital chopper circuitry which eliminates the CMOS typical 1/f-noise completely. Even though the overall noise will be dominated by the input amplifier as long as the external resistors are below 10 kOhm.
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The total noise voltage generated at a given frequency resp. in a given frequency band (BW) is given by: Un= En*sqr(BW)
a ustria micro systems
This square root dependence can be seen very nicely in fig. 9.10. The typical square-root shaped dependence is found for both the peak to peak noise as well as for the equivalent RMS noise. The bandwidth resp. the sampling frequency of the AS8500 can be adapted to the requirements of the application by programming the internal digital filter via the SDI bus. For a sampling frequency of 16kHz the input voltage RMS noise is less than 5µ V, whereas at 500 Hz already 1µ V (or 1LSB) is reached. If the customer needs even higher resolution at a lower measuring speed the internal integration time can be further increased but due to the limitation of the digital noise ( 1LSB) it is better to perform an external averaging in the attached µ C. In this way the resolution of the system can be considerably increased to less than 0.1 µ V for sampling rates of 5 Hz and below which corresponds to an effective AD-converter width of more than 20 bits. (see fig. 9.10) 9.4 Shielding, guarding
In many applications it is difficult to gain full benefit from the AS8500 performance since a number of external error sources can disturb the measurement. To achieve the maximum performance the design engineer has to take care specially of the layout of the PC-board and the sense connections to the external components. To avoid noise pick-up from external magnetic fields all tracks on the PC-board should be parallel strip lines and they should be traced as close as possible to each other. External sensing cables should be twisted and kept away from current carrying cables as far as possible. For longer cables a shielding is sometimes helpful but care should be taken that the shield is not connected to one of the sense leads. For an optimum performance it should be open on one side, the other side should be connected to the central (star like) analog common point. In very sensitive applications it may be wise to use a guard ring around both inputs and it should be connected again to the analog common point. This procedure minimises leakage currents and parasitic capacitances between different terminals and components on the PC-board. EMV interferences can be affectively avoided in most cases by using standard SMD-type high frequency filters in the analog input lines as well as in the digital output lines.
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10
Typical performance characteristics
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Thermal Resistance junction / ambient.: 66 K/W (typ.) in still air 11 Revision History
R evision 1.0 1.1 1.2 D ate Feb.10, 2006 March 23, 2006 June 8th, 2006 Initial Revision TRIMA 8.6.2, RthJA Remove preliminary D escription
12
Ordering Information
Delivery: Tape and Reel (1 reel = 1500 devices) = MOQ Order AS8500
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13
13.1
Contact
Headquarters
austriamicrosystems AG A 8141 Schloss Premstätten, Austria Phone: +43 3136 500 0 Fax: +43 3136 525 01 industry.medical@austriamicrosystems.com www.austriamicrosystems.com
13.2 Sales Offices
austriamicrosystems USA, Inc. 8601 Six Forks Road Suite 400 Raleigh, NC 27615, USA Phone: Fax: +1 919 676 5292 +1 509 696 2713
austriamicrosystems Germany GmbH Tegernseer Landstrasse 85 D-81539 München, Germany Phone: Fax: +49 89 69 36 43 0 +49 89 69 36 43 66
austriamicrosystems Italy S.r.l. Via A. Volta, 18 I-20094 Corsico (MI), Italy Phone: Fax: +39 02 4586 4364 +39 02 4585 773
austriamicrosystems USA, Inc. 4030 Moorpark Ave Suite 116 San Jose, CA 95117, USA Phone: Fax: +1 408 345 1790 +1 509 696 2713
austriamicrosystems France S.A.R.L. 124, Avenue de Paris F-94300 Vincennes, France Phone: Fax: +33 1 43 74 00 90 +33 1 43 74 20 98
austriamicrosystems AG Suite 811, Tsimshatsui Centre East Wing, 66 Mody Road Tsim Sha Tsui East, Kowloon, Hong Kong Phone: Fax: +852 2268 6899 +852 2268 6799
austriamicrosystems Switzerland AG Rietstrasse 4 CH 8640 Rapperswil, Switzerland Phone: Fax: +41 55 220 9008 +41 55 220 9001
austriamicrosystems AG AIOS Gotanda Annex 5th Fl., 1-7-11, Higashi-Gotanda, Shinagawa-ku Tokyo 141-0022, Japan Phone: Fax: +81 3 5792 4975 +81 3 5792 4976
austriamicrosystems UK, Ltd. 88, Barkham Ride, Finchampstead, Wokingham Berkshire RG40 4ET, United Kingdom Phone: Fax: +44 118 973 1797 +44 118 973 5117
austriamicrosystems AG #805, Dong Kyung Bldg., 824-19, Yeok Sam Dong, Kang Nam Gu, Seoul Korea 135-080 Phone: Fax: +82 2 557 8776 +82 2 569 9823
austriamicrosystems AG Klaavuntie 9 G 55 FI 00910 Helsinki, Finland Phone: Fax: +358 9 72688 170 +358 9 72688 171
austriamicrosystems AG Bivägen 3B S 19163 Sollentuna, Sweden Phone: +46 8 6231 710
austriamicrosystems AG Singapore Representative Office 83 Clemenceau Avenue, #02-01 UE Square 239920, Singapore Phone: Fax: +65 68 30 83 05 +65 62 34 31 20
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Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent identification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
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Copyright
Devices sold by austriamicrosystems are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems for current information. This product is intended for use in normal commercial applications. Copyright © 2004 austriamicrosystems. Trademarks registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. To the best of its knowledge, austriamicrosystems asserts that the information contained in this publication is accurate and correct. However, austriamicrosystems shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems rendering of technical or other service
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