AS8510

D atas hee t AS8510 D a t a A cq u is i t io n D ev ic e f o r B a t t e r y S e n s o r s 1 General Description The AS8510 is a virtually offset free, low noise, two channel measurement device. It is tailored to accurately measure battery current from mA range up to kA range in conjunction with a 100 µΩ shunt resistor in series with the battery rail. Through the second measurement channel it enables capture of, either battery voltage synchronous with the current measurement, or, measure the analog output of an internal or external temperature sensor. Both channels are matched and can either measure small signals up to ±160 mV versus ground, through programmable gain amplifier or larger signals in the 0 to 1V range without the amplifier. After analog to digital conversion and digital filtering, the resulting 16-bit digital words are accessible through 4-wire standard serial interface.The device includes a number of additional features explained in the next section. Option for multiplexing either one differential input, or two single ended inputs or the internal temperature sensor on one channel Programmable current source for external temperature sensor connectable to any of the inputs High precision and high stability 1.2V reference voltage source Digital signal processing with filter options for both channels Four operating modes providing - Continuous data acquisition (or) - Periodic single-shot acquisition, (or) - Continuous acquisition on threshold crossing of programmed current levels (or) - A combination of the above On chip high-precision 4MHz RC oscillator or option for external clock -40ºC to +125ºC ambient operation AEC - Q100 automotive qualified Internal chip ID for full traceability SSOP-20 pin package 2 Key Features 3.3V supply voltage Two High resolution 16 bit Σ−Δ A/D converters Programmable sampling to enable data throughputs from less than 1Hz to 8kHz Zero Offset for both channels Independent control of data rate on both channels Precision, low noise, programmable gain amplifiers for both channels with gains 5, 25, 40, 100 to support wide dynamic ranges. Figure 1. AS8510 Block Diagram AVDD Internal Temperature Sensor Prog-Cur Source MUX and Chopper PGA 3 Applications The AS8510 is ideal for shunt based batteries sensor. For high-side current sensing, the input signal may be conditioned using austriamicrosystems device AS8525 before applying to this device. REF Bandgap Reference DVDD Oscillators ETR ETS VBAT_IN VBAT_GND 16-bit Sigma-Delta ADC MEN FIR / MA AS8510 RSHH RSHL Chopper PGA 16-bit Sigma-Delta ADC CHOP_CLK INT CLK Analog Common Mode Serial Interface AVSS VCM SCLK CS SDI SDO DVSS www.austriamicrosystems.com/AS8510 Revision 3.4 1 - 46 AS8510 Datasheet - C o n t e n t s Contents 1 General Description .................................................................................................................................................................. 2 Key Features............................................................................................................................................................................. 3 Applications............................................................................................................................................................................... 4 Pin Assignments ....................................................................................................................................................................... 4.1 Pin Descriptions.................................................................................................................................................................................... 1 1 1 4 4 5 Absolute Maximum Ratings ...................................................................................................................................................... 6 Electrical Characteristics........................................................................................................................................................... 6.1 Operating Conditions............................................................................................................................................................................ 6.2 DC/AC Characteristics for Digital Inputs and Outputs .......................................................................................................................... 6.3 Detailed System and Block Specifications ........................................................................................................................................... 6.4 Current Measurement Ranges (across 100µΩ shunt resistor)............................................................................................................ 6.4.1 Differential Input Amplifier for Current Channel ......................................................................................................................... 6.4.2 Differential Input Amplifier for Voltage Channel......................................................................................................................... 6.4.3 Sigma Delta Analog to Digital Converter ................................................................................................................................... 6.4.4 Bandgap Reference Voltage...................................................................................................................................................... 6.4.5 Internal (Programmable) Current Source for External Temperature Measurement .................................................................. 6.4.6 CMREF Circuit (VCM) ............................................................................................................................................................... 6.4.7 Internal AVDD Power-on Reset ................................................................................................................................................. 6.4.8 Internal DVDD Power-on Reset................................................................................................................................................. 6.4.9 Low Speed Oscillator................................................................................................................................................................. 6.4.10 High Speed Oscillator .............................................................................................................................................................. 6.4.11 External Clock.......................................................................................................................................................................... 6.4.12 Internal Temperature Sensor................................................................................................................................................... 6.5 System Specifications ........................................................................................................................................................................ 6 7 7 7 8 9 10 11 12 12 13 14 14 14 14 15 15 15 16 6.3.1 Electrical System Specifications .................................................................................................................................................. 8 7 Detailed Description................................................................................................................................................................ 7.1 Current Measurement Channel .......................................................................................................................................................... 7.2 Voltage/Temperature Measurement Channel ..................................................................................................................................... 7.3 Digital Implementation of Measurement Path..................................................................................................................................... 7.4 Modes of Operation ............................................................................................................................................................................ 7.4.1 7.4.2 7.4.3 7.4.4 Normal Mode 1 (NOM1) ............................................................................................................................................................ Normal Mode 2 (NOM2) ............................................................................................................................................................ Standby Mode1 (SBM1) ............................................................................................................................................................ Standby Mode2 (SBM2) ............................................................................................................................................................ 17 17 17 18 18 19 20 21 21 22 22 22 22 23 23 24 25 26 7.5 Reference-Voltage.............................................................................................................................................................................. 7.6 Oscillators........................................................................................................................................................................................... 7.7 Power-On Reset ................................................................................................................................................................................. 7.8 4-Wire Serial Port Interface ................................................................................................................................................................ 7.8.1 7.8.2 7.8.3 7.8.4 7.8.5 SPI Frame.................................................................................................................................................................................. Write Command......................................................................................................................................................................... Read Command......................................................................................................................................................................... Timing ........................................................................................................................................................................................ SPI Interface Timing .................................................................................................................................................................. www.austriamicrosystems.com/AS8510 Revision 3.4 2 - 46 AS8510 Datasheet - C o n t e n t s 7.9 Control Register.................................................................................................................................................................................. 7.9.1 7.9.2 7.9.3 7.9.4 7.9.5 Standby Mode - Power Consumption ........................................................................................................................................ Initialization Sequence at Power ON ......................................................................................................................................... Soft-reset Using Bit D[7] of Reset Register 0x09....................................................................................................................... Reconfiguring Gain Setting of PGA .......................................................................................................................................... Configuring the Device During Normal Mode ............................................................................................................................ 27 38 38 39 40 40 41 7.10 Low Side Current Measurement Application .................................................................................................................................... 8 Package Drawings and Markings ........................................................................................................................................... 8.1 Recommended PCB Footprint............................................................................................................................................................ 42 43 9 Ordering Information............................................................................................................................................................... 45 www.austriamicrosystems.com/AS8510 Revision 3.4 3 - 46 AS8510 Datasheet - P i n A s s i g n m e n t s 4 Pin Assignments Figure 2. Pin Assignments (Top View) RSHH RSHL REF VCM AVDD AVSS ETR ETS VBAT_IN VBAT_GND 1 2 20 19 INT CLK SDI MEN CHOP_CLK DVDD DVSS SDO SCLK CS 3 4 18 17 5 6 7 8 9 10 AS8510 16 15 14 13 12 11 4.1 Pin Descriptions Table 1. Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 Pin Name RSHH RSHL REF Analog output VCM AVDD AVSS ETR ETS VBAT_IN VBAT_GND CS SCLK SDO Digital input Digital output Analog input Supply pad Pin Type Analog input Description Positive Differential input for current channel Negative differential input for current channel Internal reference voltage to sigma-delta ADC; connect 100nF to AVSS from this pin. Common Mode voltage to the internal measurement path; connect 100nF to AVSS from this pin. +3.3V Analog Power-supply 0V Power-supply analog Voltage channel single ended input Battery voltage (high) input Battery voltage (low) input Digital input with pull-up Chip select with an internal pull-up resistor (SPI Interface) Clock signal (SPI Interface) Serial Data Input (SPI Interface) www.austriamicrosystems.com/AS8510 Revision 3.4 4 - 46 AS8510 Datasheet - P i n A s s i g n m e n t s Table 1. Pin Descriptions Pin Number 14 15 Pin Name DVSS DVDD Pin Type Supply pad 0V Digital Ground +3.3V Digital Supply Chop Clock used in High side measurements to synchronize external chopper. (As an example, when AS8525 is used to condition the input signal to the input range of AS8510, the chop clock is used by AS8525.) Digital output issued during the Standby Mode (SBM) to signal the short duration of data sampling. This signal is useful in the case of a High Side Measurement application. (For example: This signal is used by AS8525 device to wake-up and enable the measurement path.) Data signal (SPI Interface) By default this pin is the internal clock output which can be used by a Microcontroller. The internal clock may also be disabled as an output by programming Register 08. To use an external Clock, Register 08 has to be programmed. Active High Interrupt to indicate data is ready Description 16 CHOP_CLK Digital output 17 MEN 18 19 20 SDI CLK INT Digital input Digital I/O Digital output www.austriamicrosystems.com/AS8510 Revision 3.4 5 - 46 AS8510 Datasheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 7 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter Electrical Parameters DC supply voltage (AVDD and DVDD) Input voltage (VIN) Input current (latchup immunity) (ISCR) Electrostatic Discharge Electrostatic discharge (ESD) all pins Continuous Power Dissipation Total power dissipation (all supplies and outputs) (Pt) Temperature Ranges and Storage Conditions Storage temperature (TSTRG) Junction temperature (TJ) Thermal resistance (RthJC) -50 125 130 80 ºC ºC K/W JEDEC standard test board, 0 air velocity Norm: IPC/JEDEC J-STD-020 The reflow peak soldering temperature (body temperature) is specified according IPC/ JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices”. The lead finish for Pb-free leaded packages is matte tin (100% Sn). 50 mW SSOP20 in still air, soldered on JEDEC standard board @ 125º ambient, static operation with no time limit ±2 kV AEC - Q100 - 002 -0.3 -0.3 -100 5 AVDD + 0.3 DVDD + 0.3 100 V V mA AEC - Q100 - 004 Min Max Units Notes Package body temperature (TBODY) 260 ºC Humidity non-condensing 5 85 % www.austriamicrosystems.com/AS8510 Revision 3.4 6 - 46 AS8510 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics 6.1 Operating Conditions Table 3. Operating Conditions Symbol AVDD AVSS A-D DVDD DVSS TAMB ISUPP fCLK Parameter Positive analog supply voltage 0V Ground Difference in analog and digital supplies Positive digital supply 0V Digital Ground Ambient temperature Supply current System clock frequency 1 Conditions Min 3.0 0 2.97 0 -40 Max 3.6 0 0.1 3.63 0 125 5.5 4.096 Units V V V V V ºC mA MHz 1. Nominal clock frequency from external or internal oscillator. 6.2 DC/AC Characteristics for Digital Inputs and Outputs All pull-up and pull-down have been implemented with active devices. SDO has been measured with 10pF load. Table 4. INT Symbol ILEAK VOH VOL IO Table 5. CS Input Symbol VIH VIL ILEAK Ipu Table 6. SDI Symbol VIH VIL ILEAK Parameter High level input voltage Low level input voltage Input leakage current -1 Conditions Min 2.0 0.8 +1 Typ Max Units V V µA Parameter High level input voltage Low level input voltage Input leakage current Pull up current CS pulled to DVDD = 3.3V -1 -150 Conditions Min 2.0 0.8 +1 -15 Typ Max Units V V µA µA Parameter Tri-state leakage current High level output voltage Low level output voltage Output Current Conditions Min -1 2.5 0.4 4 Typ Max +1 Units µA V V mA www.austriamicrosystems.com/AS8510 Revision 3.4 7 - 46 AS8510 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 7. SDO Output Symbol VOH VOL Io Table 8. CHOP_CLK Output Symbol VOH VOL Io Parameter High level output voltage Low level output voltage Output Current Conditions Min 2.5 0.4 4 Typ Max Units V V mA Parameter High level output voltage Low level output voltage Output Current Conditions Isource = 8mA Isink = 8mA Min 2.5 0.4 8 Typ Max Units V V mA Table 9. CLK I/O with Input Schmitt Trigger and Output Buffer Symbol VIH VIL ILEAK IPD Io VOH VOL Parameter High level input voltage Low level input voltage Input leakage current Pull down current Output Current High level output voltage Low level output voltage 2.5 0.4 CLK pulled to DVSS Conditions DVDD = 3.3V DVDD = 3.3V -1 10 Min 2.4 1.0 +1 100 4 Typ Max Units V V µA µA mA V V Table 10. SCLK with Input Schmitt Trigger Symbol VIH VIL ILEAK Table 11. MEN Output Symbol VOH VOL IO Parameter High level output voltage Low level output voltage Output Current Conditions Min 2.5 0.4 2 Typ Max Units V V mA Parameter High level input voltage Low level input voltage Input leakage current Conditions DVDD = 3.3V DVDD = 3.3V -1 Min 2.4 1.0 +1 Typ Max Units V V µA www.austriamicrosystems.com/AS8510 Revision 3.4 8 - 46 AS8510 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.3 Detailed System and Block Specifications 6.3.1 Electrical System Specifications Symbol IDDNOM IDDSBM Parameter Current consumption normal mode Current consumption standby mode Min Typ 3 40 Max 5.5 Units mA µA Average of NORMAL Mode Power consumption over a period of 10sec when the device is in STANDBY Mode Notes Table 12. Electrical System Specifications 6.4 Current Measurement Ranges (across 100µΩ shunt resistor) Table 13. Current Measurement Ranges Symbol I10 I200 I400 I1500 I1 I10 I200 Parameter Input current range of 10A in NOM Input current range of 200A in NOM Input current range of 400A in NOM Input current range of 1500A in NOM Input current range of 1A in SBM 3 3 3 Imax [A] ±10 ±200 ±400 ±1500 ±1 ±10 ±200 Vsh [mV] ±1 ±20 ±40 ±150 ±0.1 ±1 ±20 PGA Gain Nominal 100 40 25 5 100 100 40 Data Rate (fOUT) @ 1 kHz @ 1 kHz @ 1 kHz @ 1 kHz @ 1 Hz @ 1 Hz @ 1 Hz VINADC [mV] ±100 ±800 1 PSR [dB] 60 60 60 60 60 60 60 2 ±1000 ±750 ±10 ±100 ±800 Input current range of 10A in SBM Input current range of 200A in SBM 1. VINADC = Vsh * Gain, gain deviations to be considered according to Table 15 and Table 16. 2. AVDD, DVDD of 3.3V with ±5% variation. 3. For low power current monitoring, single shot measurement is performed with internal oscillator. Note: The Data Rate at the output can be calculated according to the formula: fsout=2*fchop /R2 (R2 is down sampling ratio taking values 1, 2, 4 up to 32768 as powers of 2) Table 14. Valid Combinations of the Chopper Clock, Oversampling Clock and Decimation Ratios Over Sampling Frequency 1MHz 2MHz 2MHz 2MHz Chopper Frequency 2kHz 2kHz 2kHz 4kHz Decimation Ratio 64 64 128 64 www.austriamicrosystems.com/AS8510 Revision 3.4 9 - 46 AS8510 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.4.1 Differential Input Amplifier for Current Channel Parameter Input voltage range Input current 1, 11 Table 15. Differential Input Amplifier for Current Channel Symbol VIN_AMP IIN_AMP ICM G = G1 G = G2 G = G3 G = G4 e fP_AMP εT1 VOSDRIFT Vos Vos_ch VNdin THD Notes: 1. Leakage test accuracy is limited by tester resource accuracy and tester hardware. 2. For gain 100 PGA input common mode is 0V and the minimum supply is 3.15V. 3. The measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are programmed independently. 4. This parameter is not measured directly in production. It is measured indirectly via gain measurements of the whole path. It is guaranteed by design. 5. Pole frequency of input amplifier changes with GAIN. The number is valid for the gain at G1, while the bandwidth will be higher for other ranges. This parameter is not measured in production. 6. Based on device evaluation. Not tested. 7. These offsets are cancelled if chopping enabled (default). 8. Noise density calculated by taking system bandwidth as 150Hz. 9. Refer to Measurement Ranges shown in Table 13. 10. No impact on the measurement path. If the chopping is enabled, both the offset and offset drift will be eliminated. 11. For negative input voltages up to -160mV below ground, Input leakage is typically -20nA @ 65ºC due to forward conductance of protection diode. Noise density 4, 8 Conditions RSHH and RSHL RSHH and RSHL@ +160mV input voltage at 125ºC with PGA 2 Min -160 -50 Typ Max +160 Units mV nA mV 2 -160 +300 50 Absolute input voltage range Gain1 Gain2 Gain3 Gain4 3, 4, 9 3, 4, 9 3, 4, 9 3, 4, 9 I10 I200 I400 I1500 i = 1, 2, 3, 4 0.9 * Gi 15 6 100 40 25 5 1.1 * Gi kHz ±0.3 350 % µV 350 0 25 µV LSB nV/√Hz dB Gain deviation Pole frequency 4, 5 Gain drift with temperature Offset drift with temperature Input referred offset 7, 10 -20ºC to +65ºC Gain 5, 25, referenced to room temperature 7, 10 After trim, for temperature range -20 to +65ºC Chopping enabled Total harmonic distortion For 150 Hz input signal 70 www.austriamicrosystems.com/AS8510 Revision 3.4 10 - 46 AS8510 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.4.2 Differential Input Amplifier for Voltage Channel Parameter Input voltage range Input current 1, 10 Table 16. Differential Input Amplifier for Voltage Channel Symbol VIN_AMP IIN_AMP ICM G = G1 G = G2 G = G3 G = G4 e fP_AMP VNDIN THD εT1 VOS Vos_ch VOSDRIFT Notes: 1. Input for the voltage channel can be as high as 1220mV, in this high input case PGA will be bypassed. 2. Leakage test accuracy is limited by tester resource accuracy and tester hardware, especially at low temperatures due to condensing moisture. 3. For gain 100 PGA input common mode is 0V and the minimum supply is 3.15V. 4. The measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are programmed independently. 5. This parameter is not measured directly in production. It is measured indirectly via gain measurements of the whole path. It is guaranteed by design. 6. Pole frequency of input amplifier changes with changing the GAIN. The number is valid for the gain at G1, while the bandwidth will be higher for other ranges. This parameter is not measured in production. 7. Noise density calculated by taking system bandwidth as 150Hz. 8. Based on device evaluation. Not tested. 9. No impact on the measurement path. If the chopping is enabled, both the offset and offset drift will be eliminated. 10. For negative input voltages up to -160mV below ground, Input leakage is typically -20nA @ 65ºC due to forward conductance of protection diode. Conditions Min -160 VBAT_IN, ETR, ETS @ +160mV input voltage at 125ºC with PGA 3 Typ Max +160 Units mV nA mV 2, 10 -50 2 -160 +300 100 40 25 5 50 Absolute input voltage range Gain1 Gain2 Gain3 Gain4 4, 5 4, 5 4, 5 4, 5 Gain deviation Pole frequency Noise density 5, 6 i = 1, 2, 3, 4 0.9 * Gi 15 25 1.1 * Gi kHz nV/√Hz dB ±0.3 350 0 350 % µV LSB µV 5, 7 Total harmonic distortion Gain drift with temperature 9 8 For 150Hz input signal -20ºC to +65ºC Gain 5, 25, referenced to room temperature After trim at +65ºC Chopping enabled 9 70 Input referred offset Offset drift with temperature www.austriamicrosystems.com/AS8510 Revision 3.4 11 - 46 AS8510 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.4.3 Sigma Delta Analog to Digital Converter Parameter Reference voltage Input range 1 2 6 Table 17. Sigma Delta Analog to Digital Converter Symbol VREF VINADC R1 fovs RES BW S/N Notes: Production test at ±800mV. Maximum VIN can be 1.22V with VREF=1.225V. Programmable. It is defined with respect to the first decimator in the ΣΔ ADC. Programmable: Internal clock is 1024/2048 kHz; external clock max is 8192 kHz. Dependent on fovs, R1 and R2. The bandwidth is calculated according to the formula: BW=fovs/(2*R1*R2); the sampling frequency at the output of the A/D converter is 2*BW. 5. Defined at maximum input signal, BW=500 Hz (1Hz to 500 Hz), fovs=1024 kHz, R1=64, fchop=2 kHz and R2=2. 6. Reference voltage might be forced from external. 1. 2. 3. 4. Conditions Min Typ 1.225 At Vref = 1.22V 0 64 128 1024/ 2048 16 1 5 Max Units V ±1.22 128 V Oversampling ratio/Decimation Ratio Oversampling frequency Number of bits Bandwidth 4 3 kHz bits Hz dB 500 90 Signal to noise ratio 6.4.4 Bandgap Reference Voltage Parameter Reference Voltage after trim 1, 2 1, 2 Table 18. Bandgap Reference Voltage Symbol VREFTRIM VREFACC Conditions Trim at 65ºC At 65ºC Temperature range (see note 4) -20 to 65 ºC Temperature range -40 to 125 ºC +0.4/ -0.6 80 3 3 Min Typ 1.225 Max Units V Reference Voltage Initial Accuracy ±3.5 ±0.4 mV % % dB ms VREFDRIFT Reference Voltage Temperature drift PSRRREF SUTAVDD SUTPD RNDVREF VNDVREF CLVREF ESRVREF Notes: PSR @ dc Start Up Time with supply ramp Start Up Time from power down Output resistance of band gap Bandgap reference thermal noise density Output Capacitor (Ceramic) 3 5 1 200 500 300 100 0.02 1 ms Ω nV/√Hz nF Ω 1. Accuracy at 65ºC. 2. No DC current is allowed from this pin. 3. This is a design parameter and not production tested. www.austriamicrosystems.com/AS8510 Revision 3.4 12 - 46 AS8510 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.4.5 Internal (Programmable) Current Source for External Temperature Measurement Parameter 5-bit current source enabled 1 Table 19. External Temperature Measurement Symbol ICURON ICUROFF TK_CS VMAXETR VMAXETRMOD VMAXETS VMAXETSMOD Conditions 5-bit programmable current source Limited by leakage 2 Min 0 Typ 270 10 1000 Max 320 Units µA nA ppm / ºK 5-bit current source disabled Temperature coefficient of current source Voltage on pin ETR 3 1000/G 1.22 1000/G 1.22 mV V V V Max voltage on pin ETR when PGA is 4 bypassed Voltage on pin ETS for resistor sensor 3 Max. Voltage on pin ETS when PGA is 5 bypassed Notes: 1. Current value can be programmed in steps of 8mAmps from 0 to 256 mA with a process error of 30%. 2. Temperature coefficient is not important since external temperature measurement is a 2 step measurement. The value specified is guaranteed by design and will not be tested in production. 3. Maximum voltage on pin ETR (reference) can be calculated by given formula, where G is the gain of PGA (G=100). 4. Maximum voltage on pin ETR, if PGA is bypassed. 5. Maximum voltage on pin ETS, if PGA is bypassed. www.austriamicrosystems.com/AS8510 Revision 3.4 13 - 46 AS8510 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.4.6 CMREF Circuit (VCM) Symbol VVCM CL Parameter Output voltage Load capacitance Min 1.6 Typ 1.7 100 Max 1.8 Units V nF Table 20. CMREF Circuit 6.4.7 Internal AVDD Power-on Reset Parameter Power On Reset Threshold POR time - The duration from Power ON till the time, internal Power On Reset signal 1 goes HIGH Current consumption in POR block 2 Table 21. Internal AVDD Power-on Reset Symbol VPORHIA tPORA IPORA Min 2.2 1 1.5 Typ 2.4 Max 2.6 Units V µs µA 1. POR pulse is always longer than tPORA whatever the slope of the supply. 2. IPORA can not be switched off. 6.4.8 Internal DVDD Power-on Reset Symbol VPORHID VHYST tPORD IPORD Parameter Power On Reset Threshold Hysteresis 1 Table 22. Internal DVDD Power-on Reset Min 2.2 0.2 1 1.5 Typ 2.4 0.25 Max 2.7 0.4 Units V V µs µA POR time - The duration from Power ON till the time, internal Power On Reset signal goes 2 HIGH Current 3 1. VPORLO = VPORHI - VHYST where VPORLO is the lower threshold of POR. 2. VPORLO = VPORHI - VHYST where VPORLO is the lower threshold of POR. 3. IPORD can not be switched off. 6.4.9 Low Speed Oscillator Symbol fLS fLS_ACC ILS Parameter Frequency Accuracy Supply current Min Typ 262.144 ±7 5 Max Units kHz % µA Table 23. Low Speed Oscillator www.austriamicrosystems.com/AS8510 Revision 3.4 14 - 46 AS8510 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.4.10 High Speed Oscillator Table 24. High Speed Oscillator Symbol fHS fHSACC IHS Notes: 1. Accuracy after trimming. 2. Accuracy for limited temperature range of -20 to 65 ºC. Parameter Frequency Accuracy 1, 2 Min Typ 4.096 ±4 300 Max Units MHz % µA Supply current 6.4.11 External Clock Table 25. External Clock Symbol fCLKEXT DIVCLKEXT DCCLKEXT Parameter Clock frequency Clock division factor Duty Cycle of external clock to be programmed in Register 08 CLK_REG through the serial bus SPI. 40 Conditions Min Typ 2048/ 4096/ 8192 2/4/8 60 % Max Units kHz 6.4.12 Internal Temperature Sensor Table 26. Internal Temperature Sensor Symbol TINTRNG ΔTIN TINTSLP TINT65G5 Parameter Temperature sensor range Temperature measurement accuracy Temperature sensor slope Temperature sensor output at gain 5 Guaranteed by design; at PGA gain 5 which is the recommended Gain for internal temperature measurement. 40660 Conditions Min -40 3 27 41807 43012 Typ Max 125 Units ºC ºC Digits/C Digits www.austriamicrosystems.com/AS8510 Revision 3.4 15 - 46 AS8510 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.5 System Specifications Table 27. System Specifications Symbol IS At Ph Parameter Channel to channel isolation 1 Min Typ Max -90 3 5 Units dB dB Deg Difference in channel to channel attenuation 1, 2 @600Hz Difference in phase shift between the two 1, 2 channels @600Hz System Measurement Error Budget for Voltage and Current Channel. Temperature Range: -20ºC to +65ºC; Output data rate is 1kHz, VCC = 3.3V, chopping enabled. Table 28. System Measurement Error Budget for Gains 5 and 25 Symbol Err Parameter System measurement error 3, 4 Conditions Min Typ ±0.5 Max ±0.8 ±0.3 ±0.4 Units % % % % Measurement error due to PGA gain drift Measurement error due to VREF drift6 Measurement error due to non-linearity of PG Notes: 1. 2. 3. 4. From device evaluation Tested by distortion measurements ±0.025 These specifications are defined by taking one channel as reference and measured on the other channel. Guaranteed by design. System measurement error due to noise, individual block parameter drifts and non linearity. Based on evaluation, not tested. System error due to offset is neglected because of chopper architecture. www.austriamicrosystems.com/AS8510 Revision 3.4 16 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n 7 Detailed Description The AS8510 consists of two independent high resolution 16-bit SD analog to digital conversion channels. The measurement path of these two channels integrates a programmable gain amplifier, chopper and de-chopper, sigma-delta modulator, decimator and a digital filter for simultaneous measurement of Current and Voltage/Temperature. The two measurement channels, namely the Current and Voltage/Temperature measurement channels have identical data path. The input signal is amplified in the Programmable Gain Amplifier (PGA) with any of the selected gains of 1, 5, 25, 40 and 100 facilitating measurement of a wide range of Current, voltage and temperature levels. Gain Settings for different input ranges and any associated restrictions are explained in the Table 13. Offset in the measurement path is minimized with the use of a chopper and a de-chopper at appropriate stages in the data path. By default the chopper/de-chopper is ON in the measurement path. It may be disabled by programming the appropriate register. The amplified input signal is converted into a single-bit pulse-density modulated stream by the Σ-Δ Modulator. A decimator acting as a low-pass filter filters out the quantization noise and generates 16-bit data corresponding to the input signal. The decimation ratios of 64, 128 may be selected in the first filter stage. For reducing data rate further, the second stage decimation can be used. An optional FIR Filter is provided to offer matched low pass filter response typically required in lead acid battery sensor systems. 7.1 Current Measurement Channel The voltage across a Shunt Resistor, connected in series with the Battery negative terminal, forms the input signal to the Current Measurement channel. RSHH and RSHL are the Current measurement input pins. Offset in the input signal is nullified with the use of a chopper and a dechopper at appropriate stages in the data path. The programmable gain amplifier in the data path with programmable settings of 1, 5, 25, 40 and 100 enables measurement of current ranges from ±1A to ±1500A. The sampled input signal is converted into a single-bit pulse-density modulated stream by the Σ-Δ Modulator. A decimator acting as a low-pass filter filters out the quantization noise and generates 16-bit data equivalent to the input current signal. The programmable input sampling rate and the decimation ratio determine the output data rates. The data path can be programmed to provide 1Hz to 2 kHz rates in the various modes available. An optional FIR filter is provided to offer matched low pass filter response typically required in lead acid battery sensor systems. After enabling the current measurement channel, the delay for the availability of the first sample is two conversion cycles. 7.2 Voltage/Temperature Measurement Channel The other two parameters of the Battery for measurement are Voltage and its Temperature. The second channel accepts signals from four independent sources through a Multiplexer as listed below: An attenuated battery voltage obtained through appropriate external resistor divider, (or) A signal from the external temperature sensor, (or) A signal from external reference, (or) A signal from the internal temperature sensor. Apart from this difference in the multiplexing of four input signals, the rest of the data path is identical to the Current measurement channel. RSHH and RSHL are the Current measurement input pins The Battery Voltage which can go up to 18V is attenuated through a Resistor Divider externally and is applied to the Voltage Channel. For Automotive Battery measurement, the Gain of the PGA should be restricted to 5 and 25. The latency for the first result from the voltage measurement channel is two conversion cycles. A second option on this measurement channel is to measure Temperature. Internally generated constant current is pumped through the Temperature Sensor with positive temperature coefficient, and, a high- precision resistor. The voltages across the sensor and the resistor form the inputs to the measurement channel one at a time. The difference between the two voltages which is independent of the magnitude of the current is used to determine the temperature accurately. The Voltage across the sensor is applied between the ETS and VSS pins and, the voltage across the high-precision resistor is applied between ETR and VSS. External Temperature measurement involves the acquisition of two signals one after the other using the same constant current source. The latency for the first result from the temperature measurement channel is two conversion cycles. A third option on the measurement channel is to measure the internal temperature. Hence, one of the three options for measurement of Battery Voltage, External Temperature and, internal temperature may be carried out by selection of appropriate inputs through the internal multiplexer selection. www.austriamicrosystems.com/AS8510 Revision 3.4 17 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n 7.3 Digital Implementation of Measurement Path Figure 3. Block Diagram of Digital Implementation R1 fmod / R1 fchop * 2 R2 fchop * 2 / R2 FIR_MA_SEL fchop * 2 / R2 MOD_IN CIC1 64 / 128 fmod Dechopper CIC2 FIR/MA DATAOUT MOD_CLK fchop CHP_CLK R1 R1 = First decimation ratio (64 or 128) R2 = Second decimation ratio (1 to 32768) CLK DIVISION BLOCK MOD_CLK Figure 3 shows the digital implementation of the decimator and filter to process the 1-bit output of the Modulator. This block receives a 1-bit pulse density modulated output (MOD_IN) from the second order sigma delta modulator along with the oversampling frequency clock (MOD_CLK). The MOD_CLK directly goes to a clock division block, which generates chopper clock (CHOP_CLK). The CHOP_CLK can be one of 2kHz or 4kHz selected by Register CLK_REG in Table 33. The MOD_CLK can be either 1MHz or 2MHz. The Decimation is a two phase process. In the first phase, the R1 down sampling rate can be obtained by selecting either 64 or 128 in Registers DECREG_R1_I, DECREG_R1_V in Table 33. The 16-bit CIC1 output is dechopped with respect to CHOP_CLK. The output of Dechopper is passed through the CIC2 filter with a decimation ratio of 1to 32768 in steps of power of 2. This output is then processed through a FIR or Moving Average (MA) filter. FIR Filter is provided to offer matched low pass filter response typically required in lead acid battery sensor systems. MA filter is used to provide averaged output and the number of samples for averaging can be any integer value from 1 to 15. 7.4 Modes of Operation The device operates in four different modes, namely, Normal Mode 1 (NOM1), Normal Mode 2 (NOM2), Standby Mode 1 (SBY1), and, Standby Mode 2 (SBY2). The Normal Modes are full-power modes with the exception that in Normal Mode 2, sampling is normally at a programmed lower frequency and is increased to a higher rate only when a measured input signal level crosses the programmed threshold in the current measurement channel. The Standby Modes are lower power modes. Sampling is normally at a very low frequency interval. In Standby Mode 2, data sampling can be carried out only when the internal comparator detects the input current to be greater than the programmed threshold and it generates interrupt on the INT pin. The device enters into the “Stop” state on Power On. This is a state where in the data path is inactive and can be entered into from any of the four Modes. The State transition Diagram involving the state of Stop and the four Modes is illustrated in the Figure 4. www.austriamicrosystems.com/AS8510 Revision 3.4 18 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n Figure 4. State Transition Diagram RESET !por_avdd por_avdd OTP_INT otp_load Wait for otp_load Completes in 32 cycles of lp_clk stop rt STOP sta Analog Stablization period Wait for 1.5msec A_STB 1.5msec & NORM NORM NORM or stop 1.5msec & SBM p sto NO RM Wait for x number of conversions SBM_ON SBM stop SBM SBM_OFF Wait for TT1 timeout 7.4.1 Normal Mode 1 (NOM1) On Power-on-reset of the device, AS8510 goes into STOP State. Transition to Normal mode1 (NOM1) occurs when the “START BIT” D0 of Mode Control Register MOD_CTL_REG in Table 33 is set to “1” through the serial port SPI. Data Rate of voltage and current channels can be independently programmed and both the channels generate interrupts for every output available from ADC. The interrupt signal is generated on the INT pin. The width of the interrupt pulse is eight cycles of lp_clk. The data is stable up to the next interrupt. If the data rate is different for the two channels, the interrupt rate would follow the higher rate among the two channels. Data update can be known by reading the status register. The functionality is explained in the waveform shown in Figure 5. When the device is configured to NOM1 Mode from any mode the configuration should be through the STOP state only. www.austriamicrosystems.com/AS8510 Revision 3.4 !por_dvdd ti 1_ TT me t ou 19 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n Figure 5. Normal Mode 1 IDATA Sampling with f1 I t V,TDATA Sampling with f2 V,T t STOP START Current Channel DATA Register Voltage Channel DATA Register INT at f1 rate from current channel Interrupt from the current channel is at f1 rate which is integer multiple of f2 rate from voltage channel TINT 7.4.2 Normal Mode 2 (NOM2) NOM2 differs from NOM1 in such a way that it allows for a relaxed data rate at a period of TMC by programming the corresponding register as long as the amplitude of current is less than a programmed threshold ITHC. However, when, the measured input signal exceeds the programmed threshold, the data rate is changed to the rate of NOM1 mode. Transition to NOM2 occurs when the “START BIT” D0 of Mode Control register MOD_CTL_REG in Table 33 is set to 1 and mode control bits to 01 through SPI. In this mode the data rate should be programmed with the time of TMC. An interrupt signal is generated on INT at the rate of TMC secs with a pulse width of eight cycles of lp_clk. The data is stable up to the next interrupt. The data sample is compared against the programmed threshold and when it is exceeded, the data sampling rate is changed to provide data at the data rate of NOM1 mode. However, as soon as the data sample amplitude falls below the programmed threshold, the sampling rate is restored to provide data at the rate of TMC. The functionality is illustrated in the waveform Figure 6. Figure 6. Normal Mode 2 I I < I THS I DD ITHS V,I,T TMC TMC V,I,T V,I,T V,I,T V,I,T Sampling with f I > I THS t INT T INT www.austriamicrosystems.com/AS8510 Revision 3.4 20 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n 7.4.3 Standby Mode1 (SBM1) The low-power Standby Mode can be entered only through the STOP state. Transition to SBM1 mode occurs when the “START BIT” D0 of Mode Control register MOD_CTL_REG in Table 33 is set to “1” and Mode Control Bits to “10” through SPI. In this mode the date rate is programmable with the time of Ta. An interrupt signal is generated on INT at the rate of Ta secs., and with a pulse width of eight cycles of lp_clk. The data is stable up to the next interrupt. The functionality is illustrated in Figure. During the period of Ta, only one data sample is made available and, during the rest of the period, the device is maintained in STOP state to reduce power consumption. The microcontroller which receives the data on the Interrupt, is also expected to be processing the data for a short time as shown clearly in the Figure 7 to ensure the overall low-power consumption of the data acquisition and processing system. Figure 7. Standby Mode 1 I DD MCU V, I, T ADC MCU V, I, T MCU t Ta Start SBM1 sec. Tconv Ta sec. Tconv Ta sec. Tconv DATA – A3 Channel DATA Register INT DATA – A0 DATA – A1 DATA – A2 TINT 7.4.4 Standby Mode2 (SBM2) Standby Mode 2 is an extension of the Standby Mode1 to achieve even a lower power in the data acquisition system by providing interrupt to the microcontroller only when the data sample exceeds the set current threshold. The Standby Mode can be entered only through the STOP state. Transition to SBM2 mode occurs when the “START BIT” D0 of Mode Control register MOD_CTL_REG in Table 33 is set to “1” and Mode Control Bits D7,D6 to “1,1” through SPI. In this mode the date rate is programmable with the time of Ta in the Ta control registers B, C. The data sample is made available and an interrupt signal is generated on INT pin only when the input signal exceeds the threshold set in Current Threshold Registers D,E. It should be noted here that the data is stable for Ta secs. The functionality is illustrated in Figure 8. Figure 8. Standby Mode 2 I DD ADC I MCU |I| > I Threshold I Ta Start SBM2 sec. Tconv Ta sec. Tconv Ta sec. t Tconv DATA – A3 Channel DATA Register INT DATA – A0 DATA – A1 DATA – A2 TINT www.austriamicrosystems.com/AS8510 Revision 3.4 21 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n 7.5 Reference-Voltage Band gap-reference voltage is used for the ADC as a reference and for the generation of the current for external temperature measurement. 7.6 Oscillators A High-speed oscillator (HS) generates the oversampling clock. For internal state machine and Interrupt generation, a low-speed Oscillator (LS) is also available. 7.7 Power-On Reset The AS8510 has PORs, APOR and DPOR on analog and digital power supplies respectively. On PORs of both supplies, initialization sequence happens and the system status is shown in state diagram (see Figure 4). As shown in the state diagram, the system is in RESET state until DPOR output goes to logic HIGH and subsequently until APOR output goes to logic HIGH. Once analog power supply is available, the system goes into OTP_INT state and loads the default values into the control and data registers and goes into STOP state. If analog POR, APOR goes low at any time, the system goes into RESET state. In the STOP state, the AS8510 can be programmed and by giving start command it starts working following the state machine. 7.8 4-Wire Serial Port Interface The SPI interface is used as interface between the AS8510 and an external micro-controller to configure the device and access the status information. The micro-controller begins communication with the SPI which is configured as a slave. The SPI protocol is simple and the length of each frame is an integer multiple of bytes except when a transmission is started. Each frame has 1 command bit, 7 address/configuration bits, and one or more data bytes. The edge of CS and the level of SCLK during the start of a SPI transaction, determine the edge on which the data is transferred from the SPI and the edge on which the data is sampled by the slave. Table 29 describes the setting of the transfer and sampling edges of SCLK. Figure 9 shows the falling edge and rising edge for data transfer and data sampling respectively, when SCLK is HIGH on the falling edge of CS. Table 29. CS and SCLK CS FALL FALL ANY SCLK LOW HIGH ANY Description Serial data transferred on rising edge of SPI clock. Sampled at falling edge of SPI clock. Serial data transferred on falling edge of SPI clock. Sampled at rising edge of SPI clock. Serial data transfer edge is unchanged. Figure 9. Protocol for Serial Data Write with Length = 1 CS SCLK SDI 0 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDO Data D7 – D0 is moved to Address A4..A0 here Transfer edge Sampling edge www.austriamicrosystems.com/AS8510 Revision 3.4 22 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n 7.8.1 SPI Frame A frame is formed by a first byte for command and address/configuration and a following bit stream that can be formed by an integer number of bytes. Command is coded on the 1 first bit, while address is given on LSB 7 bits (see Table 30). Table 30. Command Bits Command Bits C0 Table 31. Command Bits C0 0 1 Command WRITE READ ADDRESS ADDRESS Description Writes data byte on the given starting address. Read data byte from the given starting address. A6 A5 Register Address or Transmission Configuration A4 A3 A2 A1 A0 If the command is read or write, one or more bytes follow. When the micro-controller sends more bytes (keeping CS LOW and SCLK toggling), the SPI interface increments the address of the previous data byte and writes/reads data to/from consecutive addresses. 7.8.2 Write Command For write command, C0=0. After the command code C0 is transferred, the address of register to be written is provided from MSB to LSB. Subsequently one or more data bytes can be transferred from MSB to LSB. For each data byte following the first one, used address is the incremented value of the previously written address. Each bit of the frame has to be driven by the SPI master on the SPI clock transfer edge. The SPI slave samples it on the next clock edge. These edges are determined by the level of SCLK as shown in Table 29. Figure 10 and Figure 11 are examples of write command without and with address self-increment. Figure 10. Protocol for Serial Data Write with Length = 1 CS SCLK SDI 0 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDO Data D7 – D0 is moved to Address A4..A0 here www.austriamicrosystems.com/AS8510 Revision 3.4 23 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n Figure 11. Protocol for Serial Data Write with Length = 4 CS SCLK SDI 0 AA A A A A A DD D D D D D D DD D D D D D D DD D D D D D D DD D D D D D D DD D D D D D D 65 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 76 5 4 3 2 1 0 76 5 4 3 2 1 0 SDO Data D7-D0 is moved to Address A4-A0 here Data D7-D0 is moved to Address A4-A0 +1 here Data D7-D0 is moved to Address A4-A0 +2 here Data D7-D0 is moved to Address A4-A0 +3 here Data D7-D0 is moved to Address A4-A0 +4 here 7.8.3 Read Command For Read command C0=1. After the command code C0, the address of register to be read is provided from MSB to LSB. Then one or more data bytes can be transferred from the SPI slave to the master, always from MSB to LSB. To transfer more bytes from consecutive addresses, SPI master keeps CS signal LOW and SPI clock active as long as it desires to read data from the slave. Each bit of the command and address of the frame is to be driven by the SPI master on the SPI clock transfer edge where SPI slave samples it on the next SPI clock edge. Each bit of the data section of the frame is driven by the SPI slave on the SPI clock transfer edge and SPI master samples it on the next SPI clock edge. These edges are determined as per Table 29 and examples of read command without and with address self-increment. Figure 12. Protocol for Serial Data Read with Length = 1 CS SCLK SDI 1 A6 A5 A4 A3 A2 A1 A0 SDO D7 D6 D5 D4 D3 D2 D1 D0 Data D7 – D0 at Address A4..A0 is read here www.austriamicrosystems.com/AS8510 Revision 3.4 24 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n Figure 13. Protocol for Serial Data Read with Length = 4 CS SCLK SDI 1 AA AAAAA 6543210 SDO D D D D D D D D D D D D D D D D D D D D D D D D D D D DD D D D D D D D D D D D 7 6 543 210 76 5 432 10 76 5432 10 76 5 43 21 0 76 543 21 0 Data D7-D0 at Data D7-D0 at Data D7-D0 at Data D7-D0 at Data D7-D0 at Address A4-A0 Address A4-A0 +1 Address A4-A0 +2 Address A4-A0 +3 Address A4-A0 +4 is read here is read here is read here is read here is read here 7.8.4 Timing In the following timing waveforms and parameters are exposed. Figure 14. Write Timing for Writing CS ... t CPS t CPHD t SCLKH tSCLKL ... tDIS tDIH DATAI DATAI ... DATAI t CSH SCLK CLK polarity SDI SDO ... www.austriamicrosystems.com/AS8510 Revision 3.4 25 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n Figure 15. Read Timing for Reading CS t SCLKH tSCLKL SCLK SDI DATAI DATAI tDOD t DOHZ SDO DATAO (D7 ) DATAO (D0 ) 7.8.5 SPI Interface Timing Parameter Bit rate Clock high time Clock low time Data in setup time Data in hold time CS hold time Data out delay Data out to high impedance delay Time for the SPI to release the SDO bus Setup time of SCLK with respect to CS falling edge Hold time of SCLK with respect to CS falling edge 400 400 20 20 20 80 80 Conditions Min Typ Max 1 Units Mbps ns ns ns ns ns ns ns Table 32. SPI Interface Timing Symbol General BRSPI TSCLKH TSCLKL Write timing tDIS tDIH TCSH Read timing tDOD tDOHZ Timing parameters when entering 4-Wire SPI mode (for determination of CLK polarity) tCPS tCPHD Clock setup time (CLK polarity) Clock hold time (CLK polarity) 20 20 ns ns www.austriamicrosystems.com/AS8510 Revision 3.4 26 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n 7.9 Control Register This section describes the control registers used in AS8510. Registers can be broadly classified into the following categories. Data access registers Status Registers Digital signal path control registers Digital Control registers Analog Control Registers Table 33. Control Registers Addr in HEX Register Name POR Value R/W 8-bit Control / Status Data Data Access Registers 00 01 02 03 DREG_I1 (ADC Data Register for Current) DREG_I2 (ADC Data Register for Current) DREG_V1 (ADC Data Register for Voltage) DREG_V2 (ADC Data Register for Voltage) 0000_0000 0000_0000 0000_0000 0000_0000 R R R R D[7:0] D[7:0] D[7:0] D[7:0] Denotes the Current ADC MSB Byte (ADC_I[15:8]) Denotes the Current ADC LSB Byte (ADC_I[7:0]) Denotes the Voltage ADC MSB Byte (ADC_V[15:8]) Denotes the Voltage ADC LSB Byte (ADC_V[7:0]) Status Registers D[7] D[6] D[5] 04 STATUS_REG 0000_0000 R D[4] D[3] D[2] D[1] D[0] NOM1/NOM2 Data Ready NOM2 Threshold Crossover SBM1 Data Ready SBM2 Threshold Crossover APOR status Data from current channel updated Data from voltage channel updated Reserved www.austriamicrosystems.com/AS8510 Revision 3.4 27 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n Table 33. Control Registers Addr in HEX Register Name POR Value R/W 8-bit Control / Status Data Digital Signal Path Control Registers for Current Channel D[7] This bit selects decimation rate is used for current channel. Default is 0 (Down Sampling Rate is 64) 0 1 Down Sampling Rate is 64 Down Sampling Rate is 128 These two bits select division ratio of oversampling frequency clock MOD_CLK to be used as chopper clock, CHOP_CLK. Default is “10” (divide by 512) D[6:5] 00 01 10 11 Chopper Clock Always High Divide by 256 Divide by 512 Divide by 1024 These four bits select the decimation ratio of second CIC stage. Default is “0010” (equal to 4) 0000 0001 0010 05 DEC_REG_R1_I 0100_ 0101 R/W 0011 0100 0101 0110 D[4:1] 0111 1000 1001 1010 1011 1100 1101 1110 1111 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 CIC1 Saturation Interrupt Mask Control. Default is 1 D[0] 0 1 Unmask Mask www.austriamicrosystems.com/AS8510 Revision 3.4 28 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n Table 33. Control Registers Addr in HEX Register Name POR Value R/W D[7] D[6] D[5] 0 1 8-bit Control / Status Data I-Channel Enable, Default 1=enable V-Channel Enable, Default 1=enable Interrupt polarity Active high Active low . Interrupt Mask Control for Current Channel Data Ready Interrupt on INT pin (Default is 0) D[4] 0 1 06 DEC_REG_R2_I 1100_0101 R/W D[3:2] Unmasked Masked These two bits select the source of output 16-bit data in Normal mode from Current channel. Default is 01 00 01 10 11 FIR / MA Output CIC2 Output Dechop/Demod Output CIC1 Output These two bits select the source of output 16-bit data in SBM mode from Current channel. Default is 01 00 D[1:0] 01 10 11 FIR / MA Output CIC2 Output Dechop/Demod Output CIC1 Output www.austriamicrosystems.com/AS8510 Revision 3.4 29 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n Table 33. Control Registers Addr in HEX Register Name POR Value R/W 8-bit Control / Status Data This bit selects FIR / MA Filter in Current channel. Default is 0 (FIR) D[7] 0 1 FIR MA Filter These bits select the number of data samples for averaging in MA filter in Current channel. Default is 0000 (bypass) 0000 D[6:3] 0001 0011 07 FIR CTL_REG_I 0000_0100 R/W 0111 1111 bypass 1 3 7 15 These two bits select the Measurement Path architecture in both Current and Voltage channels. Default is 10 (Dechopper after CIC) 00 D[2:1] 01 10 11 D[0] Demodulator after CIC1 Demodulator before CIC1 Dechopper after CIC1 (preferred and suggested) Demodulator before CIC1 with settled sample Reserved. Default 0. Do not change www.austriamicrosystems.com/AS8510 Revision 3.4 30 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n Table 33. Control Registers Addr in HEX Register Name POR Value R/W 8-bit Control / Status Data Digital Control Registers Oversampling frequency clock selection. Default is 00 (high speed (HS) internal Clock) D[7:6] 00 01 10 Internal HS Clock with No Clock Output Internal HS Clock with Clock Output External Clock These two bits select the division ratio for HS clock/ external clock. Default is 10 (division by 4) 00 D[5:4] 01 10 08 CLK_REG (Clock Control Register) 0010_0000 R/W 11 No division Divide by 2 Divide by 4 Divide by 8 These two bits select the division ratio of HS clock, by which it should be divided before providing it on CLK pin. Default is 00 (No Division) D[3:2] 00 01 10 11 D[1] D[0] D[7] 0 1 No Division Divide by 2 Divide by 4 Divide by 8 LS _CLK undivided (Low Speed clock) LS _CLK divide by 2 Reserved Entire device can be soft reset by writing “0” into this register bit. This bit will take a default 1 value on coming out of Reset Measurement Path can be soft reset by writing “0” into this register bit. This bit will take a default 1 value after Measurement Path is reset. Reserved This bit selects the division ratio of LS clock 09 RESET_REG (Reset Control Register) 1100_0000 R/W D[6] D[5:0] www.austriamicrosystems.com/AS8510 Revision 3.4 31 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n Table 33. Control Registers Addr in HEX Register Name POR Value R/W 8-bit Control / Status Data These two bits select the operating mode of the Device. Default is 00 (Normal Mode 1) 00 D[7:6] 01 10 11 Normal Mode 1 Normal Mode 2 Standby Mode 1 Standby Mode 2 These three bits select the number of cycles to be ignored before comparison with the set threshold in Standy Mode. Default is 000 (3 cycles of data) 000 001 D[5:3] 010 011 100 0A MOD_CTL_REG (Mode Control Registers) 101 0000_0000 R/W 110 111 3 cycles of data 4 cycles of data 5 cycles of data 6cycles of data 7 cycles of data 8 cycles of data 9 cycles of data 10 cycles of data D[2] This bit controls the CHOP_CLK availability on CHOP_CLK pin. Default is 0 0 1 Disabled Enabled Enabling the MEN pin to indicate transition from Standy to Normal Mode. D[1] 0 1 Disabled Enabled This bit is used to take the device from STOP state to any of the Modes based on D[7:6] selection of this register. D[0] 0 1 Retain in STOP state Enables transition to Normal or Standby Modes. Unit of Ta in SBM1/SBM2. Default is 1 0B MOD_Ta_REG1 (Ta Control Register) 1000_0000 D[7] D[6:0] 0C 0D 0E MOD_Ta_REG2 (Ta Control Register) MOD_ITH_REG1 (Current Threshold Register) MOD_ITH_REG2 (Current Threshold Register) 0000_0000 0000_0000 0000_0000 R/W R/W R/W D[7:0] D[7:0] D[7:0] 0 1 Unit is in milliseconds Unit is in seconds MSB value of Ta Unit of Ta in SBM1/SBM2 LSB value of Ta MSB bits of 16 bits SBM2 threshold register LSB bits of 16 bits SBM2 threshold register www.austriamicrosystems.com/AS8510 Revision 3.4 32 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n Table 33. Control Registers Addr in HEX 0F 10 11 12 Register Name MOD_TMC_REG1 (TMC Control Registers) MOD_TMC_REG2 (TMC Control Register) NOM_ITH_REG1 NOM_ITH_REG2 POR Value 0000_0000 0000_0000 0000_0000 0000_0000 R/W R/W R/W R/W R/W D[7:0] D[7:0] D[7:0] D[7:0] 8-bit Control / Status Data MSB value of number of data samples to be dropped from ADC before sending Interrupt in NOM2 LSB value of number of data samples to be dropped from ADC before sending Interrupt in NOM2 Eight MSB bits of NOM2 current threshold register Eight LSB bits of NOM2 current threshold register Setting of Gain G of Current Channel PGA. Default is 01 (G = 25) 00 D[7:6] 01 10 11 13 PGA_CTL_REG (PGA Control Registers) 0101_0000 R/W 5 25 40 100 Analog Control Registers Setting of Gain G in Voltage channel. Default is 01 (G = 25) 00 D[5:4] 01 10 11 D[3:0] 0 1 0 1 5 25 40 100 Reserved Disable Chopper clock to Current channel Enable Chopper clock to Current channel Disable Chopper clock to Voltage channel Enable Chopper clock to Voltage channel Reserved Reserved 0 1 0 1 0 1 0 1 Disable Current channel PGA Enable Current channel PGA Disable Current channel ΣΔ Modulator Enable Current channel ΣΔ Modulator Disable Voltage channel PGA Enable Voltage channel PGA Disable Voltage channel ΣΔ Modulator Enable Voltage channel ΣΔ Modulator D[7] D[6] D[5] D[4] 14 PD_CTL_REG_1 (Power Down Control Register) 1100_1111 R/W D[3] D[2] D[1] D[0] www.austriamicrosystems.com/AS8510 Revision 3.4 33 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n Table 33. Control Registers Addr in HEX Register Name POR Value R/W D[7] D[6] D[5] D[4] 15 PD_CTL_REG_2 (Power Down Control Register) 1111_0011 R/W D[3] 0 1 0 1 0 1 0 1 0 1 D[2] 0 1 D[1] D[0] D[7] D[6] D[5] 16 PD_CTL_REG_3 (Power Down Control Register) 1111_1000 D[4] D[3] 0 D[2] D[1] D[0] 1 0 1 0 1 0 1 0 1 0 1 8-bit Control / Status Data Disable CIC1 of both channels Enable CIC1 of both channels Disable CIC2 of both channels Enable CIC2 of both channels Disable Dechopper in both channels Enable Dechopper in both channels Disable FIR in both channels Enable FIR in both channels Do not bypass PGA in Current Channel Default 0 Bypass PGA in Current Channel Do not bypass PGA in Voltage Channel Default 0 Bypass PGA in Voltage Channel Disable Current Channel Chopper Enable Current Channel Chopper Disable Voltage Channel Chopper Enable Voltage Channel Chopper Disable Common Mode Reference Enable Common Mode Reference Disable Internal Current Source Enable Internal Current Source Disable Internal temperature sensor Enable Internal temperature sensor Reserved. (Default 1) Do not change Reserved. (Default 1) Do not change Data Output in binary numbering system Data Output in 2’s complement numbering system Reserved. (Default 0) Do not change Reserved www.austriamicrosystems.com/AS8510 Revision 3.4 34 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n Table 33. Control Registers Addr in HEX Register Name POR Value R/W 8-bit Control / Status Data These bits specify the selection of voltage/temperature in Voltage Channel Default is 00 (Voltage Channel) D[7:6] 00 01 10 11 D[5] Voltage Channel External Temperature Channel ETR External Temperature Channel ETS Internal Temperature Channel Reserved. (Default 0) Do not change Internal current source switch enable. Default is 0 Note: D4 bit is used for Enabling current source to the channel selected by bits D[7,6] of this register. 0 1 Disabled Enabled 17 ACH_CTL_REG (Analog Channel Selection Register) 0000_0000 R/W D[4] Enable/disable Internal current source to RSHH pin of Current channel D[3] 0 1 Disabled Enabled Enable/disable current source switch to RSHL pin of Current channel D[2] 0 1 D[1:0] Disabled Enabled Reserved These three bits specify the selection of magnitude of current from the Internal current source. Default is 00000 (0µA). 00000 00001 18 ISC_CTL_REG (Current Source Setting Register) 0000_0000 R/W D[7:3] 00010 00100 01000 10000 11111 D[2:0] 19 OTP_EN_REG 0000_0000 R/W D[7] D[6:0] D[7] 44 STATUS_REG_2 0000_0000 R D[6] D[5:0] 1 0µA 8.5µA 17µA 34.5µA 68µA 135µA 270µA Reserved Reserved (default = 1) Do not change Reserved Status indicating data saturation in Current channel Status indicating data saturation in Voltage channel Reserved www.austriamicrosystems.com/AS8510 Revision 3.4 35 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n Table 33. Control Registers Addr in HEX Register Name POR Value R/W 8-bit Control / Status Data Digital Signal path control registers for Voltage Channel Selection of Decimation ratio for Voltage/Temperature channel. Default is 0 (Down Sampling Rate is 64) 0 1 Down Sampling Rate is 64 Down Sampling Rate is 128 D[7] Division of oversampling clock, which is used as Chopper Clock. Default is 10 (divide by 512) 00 D[6:5] 01 10 11 0000 0001 0010 0011 45 DEC_REG_R1_V 0100_ 0101 R/W 0100 0101 0110 D[4:1] 0111 1000 1001 1010 1011 1100 1101 1110 1111 Chopper Clock Always High Divide by 256 Divide by 512 Divide by 1024 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 CIC1 Saturation Interrupt Mask Control. Default is 1 D[0] 0 1 Unmasked Masked Decimation ratio of CIC2. Default is 0010 (4) www.austriamicrosystems.com/AS8510 Revision 3.4 36 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n Table 33. Control Registers Addr in HEX Register Name POR Value R/W D[7:5] 8-bit Control / Status Data Reserved Interrupt Mask Control for Voltage channel data Ready Interrupt on INT pin (Default is 0) D[4] 0 1 46 DEC_REG_R2_V 0000_0100 R/W D[3:2] Unmasked Masked These two bits select the source of output 16-bit data in Normal mode from Voltage channel. Default is 01 00 01 10 11 D[1:0] FIR / MA Output CIC2 Output Dechop/Demod Output CIC Output Reserved This bit selects FIR / MA Filter in Voltage channel. Default is 0 (FIR) D[7] 0 1 FIR MA Filter 47 FIR CTL_REG_V 0000_0000 R/W D[6:3] These bits select the number of data samples for averaging in MA filter in Voltage channel. Default is 0000 (bypass) 0000 0001 0011 0111 1111 D[2:0] Reserved bypass 1 3 7 15 Note: All the registers from address 0x19 to 0x2C are read-only. 7.9.1 Standby Mode - Power Consumption In Standby Mode 1 there is a timer based accurate measurement every Ta seconds. The device itself stays in idle-mode as long as it does not get a different command from the SPI interface. Internal oscillator frequency is typically foscint=262 kHz to reduce power consumption as long as the timer runs. After every time out of Ta secs, it performs accurate measurement of current, voltage/ temperature. Data ready is signaled to microcontroller through an interrupt signal on INT and goes into STOP state. In the SBM the following equations hold: Tsbm1 = Ta= 10s (default value is 10secs); the power consumption is valid for this setting. This is the period of the repetition rate in SBM 1 and SBM2. Tsett ≈ 2ms (depending on external capacitors). This is the time required by the analog part to settle when the new measuring period is started. Any measurements performed during Tsett produce invalid results. T1 = 3ms (by default setting, every third measurement is sent to microcontroller in the SBM mode 1) is the time needed to perform the first measurement. Tmeas =Tsett +T1 is the total active time needed to get a valid result. DRSBM = Tmeas/Tsbm ≈ 5ms/10s. This is the ratio of repetition time versus the active time (Device in NOM mode). Power consumption = (DRSBM*NOM mode power consumption) + ((10s-5ms)/10s)*Stop mode power consumption) www.austriamicrosystems.com/AS8510 Revision 3.4 37 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n 7.9.2 Initialization Sequence at Power ON Figure 16. AS8510 Device Initialization Sequence at Power ON VPORHID/VPORHIA DVDD/AVDD POR_N INT 500µS Start ADC 1.5mS TADC D1 D2 D3 D4 D1 D2 D3 D4 D1 D2 D3 D4 CHOP_CLK Channel Data Register Configure Device 0x0000 TDATA_STATUS_RD DATA1 TDATA_VALID TDATA_INVALID DATA2 Device initialization starts if the DVDD and AVDD supplies are switched ON and DVDD > VPORHID. The duration period of Initialization is 500µsec, and, during this period, INT pin toggles at the rate of internal low power oscillator. Toggling on INT during the period of initialization should be ignored in the system. Device configuration and activation should be carried out only after the initialization period. On ADC start, device enters into analog stabilization state and takes 1.5msec for oscillator and Reference to settle. After this 1.5msec period, the first interrupt will occur after a time period of TADC. TDATA_STATUS_RD is the time period during which the micro-controller should complete reading of data and status from the device. If reading is carried out beyond this time period, then, ADC performance will degrade for next sample generation. Status register gets cleared automatically only when micro-controller reads this register. Data in the channel registers is changed after TDATA_VALID duration. Ensure that data channel registers and status registers are not read during the TDATA_INVALID duration. Example: Configuration registers are set as follows: CLK_REG = 8’b0010_0000 DEC_REG_R1_I = 0100_0101 DEC_REG_R2_I = 1100_0101 FIR_CTL_REG_I = 0000_0100 ADC is configured to a data rate of 1KHz, CHOP_CLK to 2KHz, and Modulator clock to 1MHz, Decimation ratio of CIC1 = 64, and Decimation ratio of CIC2 = 4. With these settings the various time periods as shown in the Figure 16 are as follows: TDATA_STATUS_RD = 100 µsec (TDATA_STATUS_RD = (1/mod_clk) * R1 * [((mod_clk/(2*chop_clk))*(1/R1)) - 2.5) TDATA_INVALID = 8 µsec TADC = 1msec TDATA_VALID = TADC - TDATA_INVALID = 1msec - 8 µsec CHOP_CLK and POR_N are internal signals of the device. www.austriamicrosystems.com/AS8510 Revision 3.4 38 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n Table 34 provides valid combinations of Modulator clock, Chopper clock and Decimation R1 and the corresponding values of TDATA_STATUS_RD and TADC. Table 34. Valid Combinations of Modulator Clock, Chopper Clock and Decimation Ratio R1 Modulator Clock 1MHz 2MHz 2MHz 2MHz Chopper Frequency CHOP_CLK 2KHz 2KHz 2KHz 4KHz Decimation Ratio R1 64 64 128 64 TDATA_STATUS_RD 1usec * 64 * [4 - 2.5] = 96usec 0.5usec * 64 * [8 - 2.5] = 176usec 0.5usec * 128 * [4 - 2.5] = 96usec 0.5usec * 64 * [4 - 2.5] = 48usec TADC R2/(2*CHOP_CLK) for R2=4 1mSec 1mSec 1mSec 0.5mSec 7.9.3 Soft-reset Using Bit D[7] of Reset Register 0x09 It is possible to soft-reset the device by writing “0” into D[7] bit of Reset Register at 0x09. On applying soft-reset, the device enters into initialization state and D[7] bit changes back to “1”. The duration period of Initialization is 500µsec, and, during this period, INT pin toggles at the rate of internal low power oscillator. Toggling on INT during the period of initialization should be ignored in the system. Device configuration and activation should be carried out only after the initialization period. See Figure 17 for the timing details of the sequence of device initialization on soft-reset. Figure 17. AS8510 Device Initialization Sequence at Soft-reset Start ADC 1.5mS INT D4 D1 D2 D3 D4 D1 Soft Reset Using D7 500µS Re-Configure Device D1 D2 D3 D4 D1 D2 D3 D4 D1 D2 D3 D4 CHOP_CLK Channel Data Register DATA-N DATA-N+1 0x0000 DATA1 DATA2 TDATA_STATUS_RD TDATA_VALID TDATA_INVALID TDATA_STATUS_RD TDATA_VALID TDATA_INVALID www.austriamicrosystems.com/AS8510 Revision 3.4 39 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n 7.9.4 Reconfiguring Gain Setting of PGA Only PGA gain settings can be changed dynamically while ADC conversions are in progress. When PGA gain settings are changed, the first sample from the ADC is invalid. Ignore the first interrupt after the gain re-configuration. Valid data starts from the second interrupt onwards. Figure 18. AS8510 - Reconfiguration of Gain Setting of PGA Read Channel data in this slot Gain Re-Configuration can be carried out in this slot, skip next interrupt and Channel Data. TDATA_STATUS_RD VALID DATA INT D4 D1 D2 D3 D4 D1 D2 D3 D4 D1 D2 D3 D4 D1 D2 D3 D4 CHOP_CLK Channel Data Register DATA-N TDATA_STATUS_RD TDATA_VALID DATA-N+1 TDATA_INVALID DATA1 TDATA_STATUS_RD TDATA_VALID DATA2 TDATA_INVALID 7.9.5 Configuring the Device During Normal Mode Following registers can be programmed dynamically when the device is in operational mode (Normal mode). ACH_CTL_REG address is 0x17 PGA_CTL_REG address is 0x03 During the operation (Normal mode) of the device, if any of the registers need to be programmed or changed other than the above mentioned registers, then it is required to STOP the device by writing into MOD_CTL_REG “STOP” bit and configure the device as per the requirements and start the device. www.austriamicrosystems.com/AS8510 Revision 3.4 40 - 46 AS8510 Datasheet - D e t a i l e d D e s c r i p t i o n 7.10 Low Side Current Measurement Application Figure 19. Application Diagram RSHH RSHL REF 100nF VCM 100nF 3.3V 1µF AVSS +12V 481R ETR ETS VBAT_IN VBAT_GND AVDD INT CLK SDI MEN CHOP_CLK DVDD DVSS SDO SCLK CS 3.3V 1µF AS8510 20 pin (SSOP20) R 100µohm + 12V Battery - Load Note: On ETR connect constant resistor (temp co = 0) On ETS connect PT100 µC www.austriamicrosystems.com/AS8510 Revision 3.4 41 - 46 AS8510 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 8 Package Drawings and Markings The product is available in a 20-pin SSOP package. Figure 20. Drawings and Dimensions Symbol A A1 A2 b c D E E1 e L L1 L2 R θ N Min 0.05 1.65 0.22 0.09 6.90 7.40 5.00 0.55 0.09 0º Nom 1.75 7.20 7.80 5.30 0.65 BSC 0.75 1.25 REF 0.25 BSC 4º 20 Max 2.00 1.85 0.38 0.25 7.50 8.20 5.60 0.95 8º YYWWIXX AS8510 www.austriamicrosystems.com/AS8510 Revision 3.4 42 - 46 AS8510 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s Notes: 1. Dimensions & tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. Angles are in degrees. Marking: YYWWIXX. YY Last two digits of the current year WW Manufacturing week I Assembly plant identifier XX Assembly traceability code 8.1 Recommended PCB Footprint Figure 21. PCB Footprint Recommended Footprint Data Symbol mm A 9.02 B 6.16 C 0.46 D 0.65 E 6.31 www.austriamicrosystems.com/AS8510 Revision 3.4 43 - 46 AS8510 Datasheet - R e v i s i o n H i s t o r y Revision History Revision 1.1 Date Jun 22, 2009 Dec 02, 2009 1.2 Owner mbr ss2, rad Description Initial version Updated the datasheet according to 1.8 specification Following modifications carried out in Table 27: 1) Deleted Max value for parameter ‘Temperature upper limit’ 2) Added Footnote 2 3) Added new parameter ‘Temperature Sensor Output (without gain calibration) Updated Table 15 with PGA information 1.3 Feb 19, 2010 mbr Updated Voltage Measurement Updated VREFand VIN values in Table 17 and VREF in Table 18 Inserted new Table 28 - System Measurement Error Budget Changed the pin name AGND to VCM Current source added in the block diagram 2.0 June 01, 2010 mbr Added application diagram Updated Electrical Characteristics on page 7 Updated Detailed System and Block Specifications on page 9 Updated Standby Mode - Power Consumption on page 37 3.0 3.1 3.2 3.3 Oct 29, 2010 Nov 02, 2010 Nov 14, 2010 Nov 26, 2010 Dec 03, 2010 ss2 ss2 ss2 vel ss2 Updates carried out across the datasheet Updated Ref Voltage Offset in Table 18 Added sections 7.9.2, 7.9.3, 7.9.4 Formatted figures 17, 18 in portrait mode. Index modified from page 39 Added Configuring the Device During Normal Mode on page 40 Updated General Description, Key Features, Applications, Pin Descriptions, Current Measurement Ranges, Differential Input Amplifier for Current Channel, Differential Input Amplifier for Voltage Channel, Sigma Delta Analog to Digital Converter, Bandgap Reference Voltage, System Measurement Error Budget for Gains 5 and 25, Package Drawings and Markings. Deleted Voltage Measurement. Dec 08, 2009 ss2 3.4 Mar 01, 2011 mbr / ss2 Note: Typos may not be explicitly mentioned under revision history. www.austriamicrosystems.com/AS8510 Revision 3.4 44 - 46 AS8510 Datasheet - O r d e r i n g I n f o r m a t i o n 9 Ordering Information The devices are available as the standard products shown in Table 35. Table 35. Ordering Information Ordering Code AS8510-ASST Description Data Acquisition Device for Battery Sensors Delivery Form Tape and Reel Package 20-pin SSOP Note: All products are RoHS compliant and Pb-free. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect Technical Support is available at http://www.austriamicrosystems.com/Technical-Support For further information and requests, please contact us mailto: sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor www.austriamicrosystems.com/AS8510 Revision 3.4 45 - 46 AS8510 Datasheet - C o p y r i g h t s Copyrights Copyright © 1997-2011, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. 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No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com/AS8510 Revision 3.4 46 - 46