Product
Document
Published by
ams OSRAM Group
AS7265x
Smart 18-Channel VIS to NIR Spectral_
ID 3-Sensor Chipset with Electronic
Shutter
General Description
The AS7265x chipset consists of three sensor devices AS72651
with master capability, AS72652 and AS72653. The multispectral sensors can be used for spectral identification in a range
from visible to NIR. Every of the three sensor devices has 6 independent on-device optical filters whose spectral response is
defined in a range from 410nm to 940nm with FWHM of 20nm.
The AS72651, combined with the AS72652 (spectral response
from 560nm to 940nm) and the AS72653 (spectral response
from 410nm to 535nm) form an AS7265x 18-channel
multi-spectral sensor chip-set. Using the AS7265x chipset
requires the use of firmware. It must be loaded into a serial flash
via a UART interface. The list of ams tested serial flash memories
can be found in Figure 56. The components AS72651, AS72652
and AS72653 are pre-calibrated with a specific light source. The
information about the conditions of the performed calibration
(for example light source, gain, integration time) can be found
in the table of optical characteristics of the respective component. Any operation other than these conditions might require
a new calibration in the application.
Each AS7265x device has two integrated LED drivers with
programmable current and can be timed for electronic shutter
applications.
The device family integrates Gaussian filters into standard
CMOS silicon via nano-optic deposited interference filter technology in LGA packages that also provide built-in apertures to
control the light entering the sensor array.
Ordering Information and Content Guide appear at end of
datasheet.
Key Benefits & Features
The benefits and features of AS7265x, Smart 18-Channel VIS to
NIR Spectral_ID 3-Sensor Chipset with Electronic Shutter are
listed below:
ams Datasheet
[v1-04] 2018-Jul-09
Page 1
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AS7265x − General Description
Figure 1:
AS7265x Chip-Set Benefits and Features
Benefits
Features
• 3 chip set including master device delivering 18
visible and NIR channels from 410nm to 940nm
each with 20nm FWHM
• Compact 18-channel spectrometry chip-set
solution
• UART or I²C slave digital Interface
• Visible filter set realized by silicon interference
filters
• 16-bit ADC with digital access
• No additional signal conditioning required
• Programmable LED drivers
• 2.7V to 3.6V with I²C interface
• Small, robust package, with built-in aperture
• 20-pin LGA package 4.5mm x 4.7mm x 2.5mm
-40°C to 85°C temperature range
Applications
The AS7265x applications include:
• Product/Brand authentication
• Anti-counterfeiting
• Portable spectroscopy
• Product safety/adulteration detection
• Horticultural and specialty lighting
• Material analysis
Page 2
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ams Datasheet
[v1-04] 2018-Jul-09
AS7265x − General Description
Block Diagram
The functional blocks of this device are shown below:
Figure 2:
AS7265x Chip-Set Block Diagram
VDD2
VDD1
AS72651
Communication
Spectral_ID
Sensor
VDD
VDD
LED Drivers
LED_IND
I2C_ENB
Micro
Controller
Unit (MCU)
RX / SCL_S
TX / SDA_S
UART or
I2C Slave
INT
Current
Control
R
S
T
U
V
W
VDD
Firmware Interface
SDA_M
SCL_M
LED_DRV
I2C Master
VDD
°C
MISO
OSC
16MHz
SLV1_RESN
SLV2_RESN
RESN
SPI
Master
Serial Flash
Memory
MOSI
SCK
CSN
GND
VDD2
VDD1
VDD2
VDD1
AS72652
AS72653
Spectral_ID
Sensor
Spectral_ID
Sensor
Communication
Communication
LED Drivers
VDD
LED Drivers
VDD
VDD
VDD
LED_IND
SCL_S
I2C Slave
SDA_S
RESN
G
H
I
J
K
L
Current
Control
LED_IND
SCL_S
LED_DRV
SDA_S
I2C Slave
A
B
C
D
E
F
°C
°C
OSC
16MHz
OSC
16MHz
RESN
GND
Current
Control
LED_DRV
GND
Note(s):
1. Refer to the Application Diagram in Figure 60.
ams Datasheet
[v1-04] 2018-Jul-09
Page 3
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AS7265x − Pin Assignments
Pin Assignments
The device pin assignments are described below.
Figure 3:
Pin Diagram of AS7265x (Top View)
20
16
1
15
5
11
6
10
Figure 4:
AS72651 Pin Description
Pin No.
Pin Name
1
SLV1_RESN
2
Pin Type
Description
Digital Input and Output
Reset pin for Slave 1 e.g. AS72652, active low
RESN
Digital Input
Reset pin, active low (with internal pull-up to
VDD)
3
SCK
Digital Output
SPI serial clock
4
MOSI
Digital Input and Output
SPI MOSI
5
MISO
Digital Input and Output
SPI MISO
6
CSN
Digital Output
Chip select for external flash
7
NC
8
I2C_ENB
9
10
Not functional, no connect
Digital Input
Selects UART (low) or I²C (high) operation
SCL_M
Digital Output
I²C master clock for communication with
AS72652 and AS72653
SDA_M
Digital Input and Output
I²C master data for communication with AS72652
and AS72653
Page 4
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ams Datasheet
[v1-04] 2018-Jul-09
AS7265x − Pin Assignments
Pin No.
Pin Name
Pin Type
Description
11
RX / SCL_S
Digital Input and Output
RX (UART) or SCL_S (I²C slave) depending on
I2C_ENB setting
12
TX / SDA_S
Digital Input and Output
TX (UART) or SDA_S (I²C slave) depending on
I2C_ENB setting
13
INT
Digital Output
INT is active low
14
VDD2
Voltage Supply
Voltage supply
15
LED_DRV
Analog Output
LED driver output for driver LED, current sink
16
GND
Supply
Ground
17
VDD1
Voltage Supply
Voltage supply
18
LED_IND
Analog Output
LED driver output for indicator LED, current sink
19
NC
20
SLV2_RESN
Not functional, no connect
Digital Output
Reset pin for slave 2 e.g. AS72653, active low
Note(s):
1. Pin out is valid for firmware versions from 11 and later.
Figure 5:
AS72652 and AS72653 Pin Description
Pin No.
Pin Name
1
NC
2
RESN
3
NC
Not functional, no connect
4
NC
Not functional, no connect
5
NC
Not functional, no connect
6
NC
Not functional, no connect
7
NC
Not functional, no connect
8
NC
Not functional, no connect
9
SCL_S
Digital Input and Output
I²C slave clock for communication with master
AS72651
10
SDA_S
Digital Input and Output
I²C slave data for communication with master
AS72651
ams Datasheet
[v1-04] 2018-Jul-09
Pin Type
Description
Not functional, no connect
Digital Input
Reset pin, active low (with internal pull-up to
VDD)
Page 5
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AS7265x − Pin Assignments
Pin No.
Pin Name
11
NC
Not functional, no connect
12
NC
Not functional, no connect
13
INT
Digital Output
INT is active low
14
VDD2
Voltage Supply
Voltage supply
15
LED_DRV
Analog Output
LED driver output for driver LED, current sink
16
GND
Supply
Ground
17
VDD1
Voltage Supply
Voltage supply
18
LED_IND
Analog Output
LED driver output for indicator LED, current sink
19
NC
Not functional, no connect
20
NC
Not functional, no connect
Page 6
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Pin Type
Description
ams Datasheet
[v1-04] 2018-Jul-09
AS7265x − Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings
of AS7265x may cause permanent damage to the device. These
are stress ratings only. Functional operation of the device at
these or any other conditions beyond those indicated under
Electrical Characteristics is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. The device is not designed for high energy UV
(ultraviolet) environments, including upward looking outdoor
applications, which could affect long term optical performance.
Figure 6:
Absolute Maximum Ratings of AS7265x
Symbol
Parameter
Min
Max
Unit
Comments
Electrical Parameters
VDD1_MAX
Supply Voltage VDD1
-0.3
5
V
Pin VDD1 to GND
VDD2_MAX
Supply Voltage VDD2
-0.3
5
V
Pin VDD2 to GND
Input/Output Pin Voltage
-0.3
VDD+0.3
V
Input/Output Pin to GND
VDD_IO
ISCR
Input Current (latch-up
immunity)
± 100
mA
JESD78D
Electrostatic Discharge
ESDHBM
Electrostatic Discharge HBM
±1000
V
JS-001-2014
ESDCDM
Electrostatic Discharge CDM
±500
V
JESD22-C101F
Temperature Ranges and Storage Conditions
TSTRG
Storage Temperature Range
TBODY
Package Body Temperature
RHNC
Relative Humidity
(non-condensing)
MSL
Moisture Sensitivity Level
ams Datasheet
[v1-04] 2018-Jul-09
-40
85
5
3
°C
260
°C
85
%
IPC/JEDEC J-STD-020. The
reflow peak soldering
temperature (body
temperature) is specified
according IPC/JEDEC
J-STD-020 “Moisture/Reflow
Sensitivity Classification for
Non-hermetic Solid State
Surface Mount Devices”
Represents a 168 hour max.
floor lifetime
Page 7
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AS7265x − Electrical Characteristics
Electrical Characteristics
All limits are guaranteed with VDD = VDD1 = VDD2 = 3.3V,
T AMB = 25°C. The parameters with min and max values are
guaranteed with production tests or SQC (Statistical Quality
Control) methods.
VDD1 and VDD2 should be sourced from the same power supply
output.
Figure 7:
Electrical Characteristics of AS7265x
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
General Operating Conditions
VDD1
/VDD2
Voltage Operating
Supply
UART Interface
2.97
3.3
3.6
V
VDD1
/VDD2
Voltage Operating
Supply
I²C Interface
2.7
3.3
3.6
V
-40
25
85
°C
5
mA
16.3
MHz
1.2
ns
-8.5
8.5
°C
1
8
mA
-30
30
%
0.3
VDD
V
TAMB
Operating Temperature
IVDD
Operating Current
Internal RC Oscillator
FOSC
tJITTER(1)
Internal RC Oscillator
Frequency
Internal Clock Jitter
15.7
@25°C
16
Temperature Sensor
DTEMP
Absolute Accuracy of the
Internal Temperature
Measurement
Indicator LED
IIND
LED Current
IACC
Accuracy of Current
VLED
Voltage Range of
Connected LED
Vds of current sink
LED_DRV
ILED1
LED Current
12.5
100
mA
IACC
Accuracy of Current
-10
10
%
VLED
Voltage Range of
Connected LED
0.3
VDD
V
Page 8
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Vds of current sink
ams Datasheet
[v1-04] 2018-Jul-09
AS7265x − Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-1
1
μA
Digital Inputs and Outputs
IIH, IIL
Logic Input Current
Vin=0V or VDD
VIH
CMOS Logic High Input
0.7*
VDD
VDD
V
VIL
CMOS Logic Low Input
0
0.3*
VDD
V
VOH
CMOS Logic High Output
I=1mA
VDD0.4
V
VOL
CMOS Logic Low Output
I=1mA
0.4
V
tRISE(1)
Current Rise Time
C(Pad)=30pF
5
ns
tFALL(1)
Current Fall Time
C(Pad)=30pF
5
ns
Note(s):
1. Guaranteed by design, not tested in production.
ams Datasheet
[v1-04] 2018-Jul-09
Page 9
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AS7265x − Electrical Characteristics
Timing Characteristics
Figure 8:
AS7265x I²C Slave Timing Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
400
kHz
I²C Interface
fSCLK
SCL Clock Frequency
tBUF
Bus Free Time Between a STOP and
START
1.3
μs
Hold Time (Repeated) START
0.6
μs
tLOW
LOW Period of SCL Clock
1.3
μs
tHIGH
HIGH Period of SCL Clock
0.6
μs
tSU:STA
Setup Time for a Repeated START
0.6
μs
tHS:DAT
Data Hold Time
0
tSU:DAT
Data Setup Time
100
tR
Rise Time of Both SDA and SCL
20
300
ns
tF
Fall Time of Both SDA and SCL
20
300
ns
tSU:STO
Setup Time for STOP Condition
0.6
tHS:STA
CB
Capacitive Load for Each Bus Line
CI/O
I/O Capacitance (SDA, SCL)
Page 10
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0
CB - total
capacitance of one
bus line in pF
0.9
μs
ns
μs
400
pF
10
pF
ams Datasheet
[v1-04] 2018-Jul-09
AS7265x − Electrical Characteristics
Figure 9:
I²C Slave Timing Diagram
tR
tF
tLOW
SCL
P
tHIGH
S
tHD:STA
S
tSU:DAT
tHD:DAT
P
t SU:STA
tSU:STO
VIH
SDA
tBUF
Stop
VIL
Start
Figure 10:
AS72651 SPI Timing Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
16
MHz
SPI Interface
fSCK
Clock Frequency
0
tSCK_H
Clock High Time
40
ns
tSCK_L
Clock Low Time
40
ns
tSCK_RISE
SCK Rise Time
5
ns
tSCK_FALL
SCK Fall Time
5
ns
tCSN_S
CSN Setup Time
Time between CSN high-low
transition to first SCK high
transition
50
ns
tCSN_H
CSN Hold Time
Time between last SCK
falling edge and CSN
low-high transition
100
ns
tCSN_DIS
CSN Disable Time
100
ns
tDO_S
Data-Out Setup Time
5
ns
tDO_H
Data-Out Hold Time
5
ns
tDI_V
Data-In Valid
10
ns
ams Datasheet
[v1-04] 2018-Jul-09
Page 11
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AS7265x − Electrical Characteristics
Figure 11:
SPI Master Write Timing Diagram
t CS N_DIS
CSN
tSCK_RISE
tCSN_S
tCSN_H
tSCK_FALL
SCK
t DO_S
MOSI
tDO_H
MSB
LSB
HI-Z
HI-Z
MISO
Figure 12:
SPI Master Read Timing Diagram
CSN_xx
tSCK_H
tSCK_L
SCK
tDI_V
Dont care
MOSI
MISO
Page 12
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MSB
LSB
ams Datasheet
[v1-04] 2018-Jul-09
AS7265x − Typical Operating Characteristics
Typical Operating
Characteristics
Optical Characteristics
All optical characteristics are optimized for diffused light. When
using a point light source or collimated light on the sensor, the
sensor opening must be covered by a lambertian diffuser with
achromatic characteristics. Diffusor of Tsujiden like D121UP
have been successfully tested at ams. If in the application
diffused light, e.g. used by a reflective surface, no additional
diffuser is required.
Figure 13:
AS7265x LGA Average Field of View
Diffused Light
A=0.75mm
β = 20.5°
20 5°
5
Lens
Sensor
ns
sor
H=2.5mm
α = 12°
DIE
E
LGA Package Substrate
Figure 14:
AS7265x 18-Channel Spectral Responsivity
18 Channel Spectral Response
AS72651 + AS72652 + AS72653
410nm
1
435nm
0.9
460nm
485nm
0.8
Normalized Responsivity
510nm
535nm
0.7
560nm
0.6
585nm
610nm
0.5
645nm
680nm
0.4
705nm
0.3
730nm
760nm
0.2
810nm
860nm
0.1
900nm
0
350
372
394
416
438
460
482
504
526
548
570
592
614
636
658
680
702
724
746
768
790
812
834
856
878
900
922
944
966
988
940nm
A
B
C
D
E
F
G
H
R
I
S
J
T
U
V
W
K
L
Wavelength (λ, nm)
ams Datasheet
[v1-04] 2018-Jul-09
Page 13
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AS7265x − Typical Operating Characteristics
Figure 15:
AS72651 Spectral Responsivity
AS72651, 6-Channel Spectral Response
1.2
R
610
S
680
T
U
730 760
V
810
W
860
Normalized Responsivity
1
0.8
0.6
0.4
0.2
350
370
390
410
430
450
470
490
510
530
550
570
590
610
630
650
670
690
710
730
750
770
790
810
830
850
870
890
910
930
950
970
990
0
Wavelength (λ, nm)
Figure 16:
Optical Characteristics of AS72651 (Pass Band) (1)
Symbol
Parameter
Test Conditions
Channel
(nm)
Min
Typ
Max
Unit
R
Channel R
Incandescent(2),(4)
610
35(3),(4)
counts/
(μW/cm2)
S
Channel S
Incandescent(2),(4)
680
35(3),(4)
counts/
(μW/cm2)
T
Channel T
Incandescent(2),(4)
730
35(3),(4)
counts/
(μW/cm2)
U
Channel U
Incandescent(2),(4)
760
35(3),(4)
counts/
(μW/cm2)
V
Channel V
Incandescent(2),(4)
810
35(3),(4)
counts/
(μW/cm2)
W
Channel W
Incandescent(2),(4)
860
35(3),(4)
counts/
(μW/cm2)
20
nm
FWHM
Wacc
Full Width Half
Max
Wavelength
Accuracy
Page 14
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+10
-10
nm
ams Datasheet
[v1-04] 2018-Jul-09
AS7265x − Typical Operating Characteristics
Symbol
Parameter
dark
Dark Channel
Counts
AFOV
Average Field
of View
Test Conditions
Channel
(nm)
Min
Typ
Max
Unit
5
counts
GAIN=64,
TAMB=25°C
tint=165ms
±20.5
deg
Note(s):
1. Calibration and measurements are made using diffused light.
2. Each channel is tested with GAIN = 16x, Integration Time (INT_T) = 166ms and VDD = VDD1 = VDD2 = 3.3V, TAMB =25°C.
3. The accuracy of the channel counts/μW/cm 2 is ±12%.
4. The light source is an incandescent light with an irradiance of ~1500μW/cm2 (300-1000nm).
Figure 17:
AS72652 Spectral Responsivity
AS72652, 6-Channel Spectral Response
(w/AS72651 as Controller)
1.2
G H
560 585
I
645
J
705
K
900
L
940
Normalized Responsivity
1
0.8
0.6
0.4
0.2
350
368
386
404
422
440
458
476
494
512
530
548
566
584
602
620
638
656
674
692
710
728
746
764
782
800
818
836
854
872
890
908
926
944
962
980
998
0
Wavelength (λ, nm)
ams Datasheet
[v1-04] 2018-Jul-09
Page 15
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AS7265x − Typical Operating Characteristics
Figure 18:
Optical Characteristics of AS72652 (Pass Band) (1)
Symbol
Parameter
Conditions
Channel
(nm)
Min
Typ
Max
Unit
G
Channel G
3300K White LED(2)
560
35(3)
counts/
(μW/cm2)
H
Channel H
3300K White LED(2)
585
35(3)
counts/
(μW/cm2)
I
Channel I
3300K White LED(2)
645
35(3)
counts/
(μW/cm2)
J
Channel J
3300K White LED(2)
705
35(3)
counts/
(μW/cm2)
K
Channel K
Incandescent(2)
900
35(3)
counts/
(μW/cm2)
L
Channel L
940nm LED(2)
940
35(3)
counts/
(μW/cm2)
FWHM
Full Width
Half Max
20
nm
Wacc
Wavelength
Accuracy
dark
Dark
Channel
Counts
AFOV
Average
Field of View
-10
GAIN=64, TAMB=25°C
tint = 165ms
+10
nm
5
counts
±20.5
deg
Note(s):
1. Calibration and measurements are made using diffused light.
2. Each channel is tested with GAIN = 16x, Integration Time (INT_T) = 166ms and VDD = VDD1 = VDD2 = 3.3V, TAMB =25°C.
3. The accuracy of the channel counts/μW/cm 2 is ±12%.
Page 16
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ams Datasheet
[v1-04] 2018-Jul-09
AS7265x − Typical Operating Characteristics
Figure 19:
AS72653 Spectral Responsivity
AS72653, 6-Channel Spectral Response
(w/AS72651 as controller)
Normalized Responsivity
1.2
D E
B C
F
A
410 435 460 485 510 535
1
0.8
0.6
0.4
0.2
350
368
386
404
422
440
458
476
494
512
530
548
566
584
602
620
638
656
674
692
710
728
746
764
782
800
818
836
854
872
890
908
926
944
962
980
998
0
Wavelength (λ, nm)
ams Datasheet
[v1-04] 2018-Jul-09
Page 17
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AS7265x − Typical Operating Characteristics
Figure 20:
Optical Characteristics of AS72653 (Pass Band)(1)
Conditions
Channel
(nm)
Symbol
Parameter
A
Channel A
410
35(3)
counts/
(μW/cm2)
B
Channel B
435
35(3)
counts/
(μW/cm2)
C
Channel C
460
35(3)
counts/
(μW/cm2)
D
Channel D
485
35(3)
counts/
(μW/cm2)
E
Channel E
510
35(3)
counts/
(μW/cm2)
F
Channel F
535
35(3)
counts/
(μW/cm2)
FWHM
Full Width
Half Max
20
nm
Wacc
Wavelength
Accuracy
dark
Dark Channel
Counts
AFOV
Average Field
of View
LED:(2)
395nm
415nm
428nm
5600K white
Min
Typ
-10
GAIN=64, TAMB=25°C
tint = 165ms
Max
Unit
+10
nm
5
counts
±20.5
deg
Note(s):
1. Calibration and measurements are made using diffused light.
2. Each channel is tested with GAIN = 16x, Integration Time (INT_T) = 166ms and VDD = VDD1 = VDD2 = 3.3V, TAMB =25°C.
3. The accuracy of the channel counts/μW/cm 2 is ±12%.
Page 18
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ams Datasheet
[v1-04] 2018-Jul-09
AS7265x − Detailed Description
Detailed Description
AS7265x 18-Channel Spectral_ID Detector
Overview
Each of the three AS7265x Spectral_ID devices are next-generation digital 6-channel spectral sensor devices. Each of the 6
channels has a Gaussian filter characteristic with a full width
half maximum (FWHM) bandwidth of 20nm. The filters use an
interference topology design providing high stability in terms
of drift in time and temperature. The drifts are so small that it
is undetectable in the measurement. The temperature drift of
the device is largely determined by the drift of the sensor and
the electronics. To compensate for the temperature drift in the
application, every device of the AS7265x chipset includes an
integrated temperature sensor.
Filter accuracy will be affected by the angle of incidence which
itself is limited by integrated aperture and internal micro-lens
structure. The aperture-limited average field of view is ±20.5°
to deliver specified accuracy. All optical characteristics are
optimized for using diffused light.
Each device contains an analog-to-digital converter (16-bit resolution ADC) which integrates the current from each channel’s
photodiode. Upon completion of the conversion cycle, the integrated result is transferred to the corresponding data registers. The transfers are double-buffered to ensure data integrity
is maintained.
The external MCU interface control via I²C registers or AT commands, transparently controls the AS72652 and/or AS72653.
A serial flash is a required operating companion for this device
and enables factory calibration/normalization of the filters.
Supported device types are noted in
Ordering & Contact Information at the end of this document.
Required operating code can be downloaded at
download.ams.com.
Channel Data Conversion of the AS7265x
Devices
All three of these 6 channel devices use conversion implemented via two photodiode banks in each device. Refer to
Figure 21and Figure 22. Bank 1 consists of register data from 4
of the 6 photodiodes, with 2 registers zeroed and Bank 2 consists of data from a different set of 4 of the 6 photodiodes, with
2 different registers zeroed. Spectral conversion requires the
integration time (IT in ms) set to complete. If both photodiode
banks are required to complete the conversion, the 2 nd bank
requires an additional IT ms. Minimum IT for a single bank conversion is 2.8 ms. If data is required from all 6 photodiodes then
the device must perform 2 full conversions (2 x Integration
Time).
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AS7265x − Detailed Description
This spectral data conversion process operates continuously,
new data is available after each IT ms period.
The conversion process is controlled with BANK Mode settings
in the AS72651 as follows:
BANK Mode 0 Registers:
AS72651 data will be in S, T, U & V registers (R & W will be zero)
AS72652 data will be in G, H, K & I registers (J & L will be zero)
AS72653 data will be in A, B, E & C registers (D & F will be zero)
BANK Mode 1 Registers:
AS72651 data will be in R, T, U & W registers (S & V will be zero)
AS72652 data will be in G, H, J & L registers (I & K will be zero)
AS72653 data will be in F, A, B & D registers (C & E will be zero)
BANK Mode 2 Registers:
AS72651 data will be in S, T, U, V, R & W registers
AS72652 data will be in G, H, K, I, J & L registers
AS72653 data will be in A, B, C, D, E & F registers
For BANK Mode 2, care should be taken to assure prompt interrupt servicing so integration values from both banks are all derived from the same spectral conversion cycle.
Figure 21:
AS7265x Photo Diode Arrays
AS72651 Photo Diode Array
AS72652 Photo Diode Array
AS72653 Photo Diode Array
T
U
S
G
H
I
A
B
C
R
V
W
J
K
L
D
E
F
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AS7265x − Detailed Description
Figure 22:
Bank Mode and Data Conversion
BANK Mode 0
One Conversion
S, T, U, V, I, G, H, K, C, A, B, E
Integration Time
BANK Mode 1
One Conversion
R, T, U, W, L, G, H, J, F, A, B, D
Integration Time
BANK Mode 2
1st Conversion
S, T, U, V, I, G, H, K, C, A, B, E
2nd Conversion
Integration Time
R, T, U, W, L, G, H, J, F, A, B, D
Integration Time
RC Oscillator
The timing generation circuit consists of on-chip 16MHz, temperature compensated oscillators, which provide the individual
master clocks of the AS7625x devices
Temperature Sensor
The AS7265x internal temperature sensors are constantly measuring on-chip temperature to enable temperature compensation procedures, and can be read via I²C registers or AT commands in the AS72651.
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AS7265x − Detailed Description
Reset
Pulling down the RESN pin for longer than 100ms resets the
AS72651 which proceed to reset the AS72562 and the same
RESN signal shown below can be used directly to reset the
AS72653.
Figure 23:
Reset Circuit
VDD
Spectral_ID
Engine
Reset
AS72651
RESN
Push > 100ms
AS7265x LED_IND Controls
There are LED_IND pins on all AS7265x devices. An LED connected to LED_IND can be used as a general power indicator
and will automatically be used to indicate a Flash firmware update is occurring.
The LED_IND can then be setup as needed. Each AS7265x LED_
IND source can be turned on/off via AT commands or I²C register
control, and LED_IND sink current is programmable to 1mA,
2mA, 4mA or 8mA. This LED_IND control can also be used in
applications just like the LED_DRV control (described below), if
the lower current sink of the LED_IND control is appropriate.
Electronic Shutter with AS7265x LED_DRV
Driver Control
There are LED_DRV pins on all AS7265x devices. The LED_DRV
pin can be used to control external LED sources as needed for
sensor applications. LED_DRV can sink a programmable current
of 12.5mA, 25mA, 50mA or 100mA. The control can be turned
on/off via I²C registers or AT commands, and as such it provides
the AS7265x device with an electronic shutter.
Interrupt Operation
Interrupt operation is only needed for AS72651 as it transparently controls data collection from the AS72652 (if used) or
AS72653 (if used).
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AS7265x − Detailed Description
If BANK is set in the AS72651 to Mode 0 or Mode 1, data is ready
after the 1 st integration time. If BANK is set to Mode 2, data is
ready after two integration times.
For interrupt operation using I²C registers, if interrupts are enabled and data is ready, the INT pin is set low and DATA_RDY is
set to 1. Reading the raw or calibration data releases (returns
high) the interrupt. For multi-byte sensor data (2 or 4 bytes),
after the 1st byte is read the remaining bytes are shadow protected in case an integration cycle completes just after the 1st
byte is read. The sensors continue to gather information at the
rate of the integration time, hence if the sensor registers are not
read when the interrupt line goes low, it will stay low and the
next cycle’s sensor data will be available in the registers at the
end of the next integration cycle.
For interrupt operation using AT Commands, if interrupts are
enabled and data is ready the INT pin is set low and is released
(returns high) after any sensor data is read.
Required Flash Memory
Serial flash is a required operating companion for this device,
and enables the I²C and UART interfaces, as well as enabling
calibrated data results. Supported device types are noted in
Ordering & Contact Information at the end of this document.
Required operating code can be downloaded at
download.ams.com.
I²C Slave Interface
If selected by the I2C_ENB pin setting, interface and control can
be accomplished through an I²C compatible slave interface to
a set of registers that provide access to device control functions
and output data. These registers on the AS72651 are, in reality,
implemented as virtual registers in software. The actual I²C slave
hardware registers number only three and are described in the
table below. The steps necessary to access the virtual registers
defined in the following are explained in pseudocode for external I²C master writes and reads below.
I²C Feature List
• Fast mode (400kHz).
• 7+1-bit addressing mode.
• Write format: Byte.
• Read format: Byte.
• SDA input delay and SCL spike filtering by integrated
RC-components.
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AS7265x − Detailed Description
Figure 24:
I²C Slave Device Address and Physical Registers
Entity
Description
Note
8-bit slave address
Byte = 1001001x (device address = 49 hex)
• x= 1 for Master Read (byte = 93 hex)
• x= 0 for Master Write (byte = 92 hex)
I²C slave interface STATUS
register. Read-only.
Register Address = 0x00
Bit 1: TX_VALID
• 0 - New data may be written to WRITE register
• 1 -WRITE register occupied. Do NOT write.
Bit 0: RX_VALID
• 0 -No data is ready to be read in READ register.
• 1 -Data byte available in READ register.
WRITE Register
I²C slave interface WRITE
register. Write-only.
Register Address = 0x01
• 8-Bits of data written by the I²C Master
intended for receipt by the I²C slave. Used for
both virtual register addresses and write data.
READ Register
I²C slave interface
READ register. Read-only.
Register Address = 0x02
• 8-Bits of data to be read by the I²C Master.
Device Slave Address
STATUS Register
I²C Virtual Register Write Access
I²C Virtual Resister Byte Write, detailed below, shows the
pseudocode necessary to write virtual registers on the
AS72651. Note that, because the actual registers of interest are
realized as virtual registers, a means of indicating whether there
is a pending read or write operation of a given virtual register
is needed. To convey this information, the most significant bit
of the virtual register address is used as a marker. If it is 1, then
a write is pending, otherwise the slave is expecting a virtual
read operation. The pseudocode illustrates the proper technique for polling of the I²C slave status register to ensure the
slave is ready for each transaction.
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AS7265x − Detailed Description
I²C Virtual Register Byte Write
Pseudocode
Poll I²C slave STATUS register;
If TX_VALID bit is 0, a write can be performed on the interface;
Send a virtual register address and set the MSB of the register address to 1 to indicate the pending write;
Poll I²C slave STATUS register;
If TX_VALID bit is 0, the virtual register address for the write has been received and the data may now be written;
Write the data.
Sample Code:
#define I2C_AS72XX_SLAVE_STATUS_REG
0x00
#define I2C_AS72XX_SLAVE_WRITE_REG
0x01
#define I2C_AS72XX_SLAVE_READ_REG
0x02
#define I2C_AS72XX_SLAVE_TX_VALID
0x02
#define I2C_AS72XX_SLAVE_RX_VALID
0x01
void i2cm_AS72xx_write(uint8_t virtualReg, uint8_t d)
{
volatile uint8_tstatus;
while (1)
{
// Read slave I²C status to see if the write buffer is ready.
status = i2cm_read(I2C_AS72XX_SLAVE_STATUS_REG);
if ((status & I2C_AS72XX_SLAVE_TX_VALID) == 0)
// No inbound TX pending at slave. Okay to write now.
break ;
}
// Send the virtual register address (enabling bit 7 to indicate a write).
i2cm_write(I2C_AS72XX_SLAVE_WRITE_REG, (virtualReg | 0x80)) ;
while (1)
{
// Read the slave I²C status to see if the write buffer is ready.
status = i2cm_read(I2C_AS72XX_SLAVE_STATUS_REG) ;
if ((status & I2C_AS72XX_SLAVE_TX_VALID) == 0)
// No inbound TX pending at slave. Okay to write data now.
break ;
}
// Send the data to complete the operation.
i2cm_write(I2C_AS72XX_SLAVE_WRITE_REG, d) ;
}
I²C Virtual Register Read access
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AS7265x − Detailed Description
I²C Virtual Register Byte Read, detailed below, shows the
pseudocode necessary to read virtual registers on the AS72651.
Note that in this case, reading a virtual register, the register
address is not modified.
I²C Virtual Register Byte Read
Pseudocode
Poll I²C slave STATUS register;
If TX_VALID bit is 0, the virtual register address for the read may be written;
Send a virtual register address;
Poll I²C slave STATUS register;
If RX_VALID bit is 1, the read data is ready;
Read the data.
Sample Code
uint8_t i2cm_AS72xx_read(uint8_t virtualReg)
{
volatile uint8_t status, d;
while (1)
{
// Read slave I²C status to see if the read buffer is ready.
status = i2cm_read(I2C_AS72XX_SLAVE_STATUS_REG) ;
if ((status & I2C_AS72XX_SLAVE_TX_VALID) == 0)
// No inbound TX pending at slave. Okay to write now.
break;
}
// Send the virtual register address (disabling bit 7 to indicate a read).
i2cm_write(I2C_AS72XX_SLAVE_WRITE_REG, virtualReg);
while (1)
{
// Read the slave I²C status to see if our read data is available.
status = i2cm_read(I2C_AS72XX_SLAVE_STATUS_REG);
if ((status & I2C_AS72XX_SLAVE_RX_VALID)!= 0)
// Read data is ready.
break;
}
// Read the data to complete the operation.
d = i2cm_read(I2C_AS72XX_SLAVE_READ_REG) ;
return d;s
}
The details of the i2cm_read() and i2cm_write() functions in
previous figures are dependent upon the nature and implementation of the external I²C master device.
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AS7265x − Detailed Description
4-Byte Floating-Point (FP) Registers
Several 4 byte registers (hex) are used by the AS72651. Here is
an example of how these registers are used to represent floating
point data (based on the IEEE 754 standard).
Figure 25:
Example of the IEEE 754 Standard
byte 3
byte 2
byte 1
byte 0
3E (hex)
20 (hex)
00 (hex)
00 (hex)
0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24 23
16 15
8 7
0
31
sign
exponent (8 bits)
fraction (23 bits)
0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = 0.15625
31 30
23 22
0
The floating point (FP) value assumed by 32 bit binary32 data
with a biased exponent e (the 8 bit unsigned integer) and a 23
bit fraction is (for the above example):
(EQ1)
FPvalue = ( – 1 )
sign
23
–i
( e – 127 )
⋅ 1 + b 23 – i ⋅ 2 ⋅ 2
i–1
23
0
–i
( 124 – 127 )
FPvalue = ( – 1 ) ⋅ 1 + b 23 – i ⋅ 2 ⋅ 2
i–1
–2
–3
FPvalue = 1 ⋅ ( 1 + 2 ) ⋅ 2 = 0.15625
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AS7265x − Detailed Description
I²C Virtual Register Set
The figure below provides a summary of the AS72651 I²C register set for the AS72651 which serves as the master interface of
the 3 device AS7265x set. Figures after that provide additional
register details. All register data is hex, and all multi-byte entities are Big Endian (most significant byte is situated at the lowest register address).
Multiple byte registers (2 byte integer, or, 4 byte floating point)
must be read in the order of ascending register addresses (low
to high) and if capable of being written to, must also be written
in the order ascending register addresses.
Figure 26:
AS72651 I²C Master Device Virtual Register Set Overview
Addr
Name
0x00
HW Version H
HW Version
0x01
HW Version L
0x02
FW Version H
FW Version
0x03
FW Version L
0x04
Configuration
0x05
Integration Time
Integration Time
0x06
Temperature
Temperature
0x07
LED
Configuration
0x08
RAW value R, G, A
RAW value H
0x09
RAW value R, G, A
RAW value L
0x0A
RAW value S, H, B
RAW value H
0x0B
RAW value S, H, B
RAW value L
0x0C
RAW value T, I, C
RAW value H
0x0D
RAW value T, I, C
RAW value L
0x0E
RAW value U, J, D
RAW value H
0x0F
RAW value U, J, D
RAW value L
0x10
RAW value V, K, E
RAW value H
0x11
RAW value V, K, E
RAW value L
0x12
RAW value W, L, F
RAW value H
0x13
RAW value W, L, F
RAW value L
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SRST
READ_
ERR
INT
LED_
DRV
GAIN
BANK
ENABLELED
_DRV
DATA_RDY
FRST
LED_INT
ENABL
E LED_
INT
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AS7265x − Detailed Description
Addr
Name
0x14
Calibrated value
channel R, G, A
CAL CHAN0_0
0x15
Calibrated value
channel R, G, A
CAL CHAN0_1
0x16
Calibrated value
channel R, G, A
CAL CHAN0_2
0x17
Calibrated value
channel R, G, A
CAL CHAN0_3
0x18
Calibrated value
channel S, H, B
CAL CHAN0_0
0x19
Calibrated value
channel S, H, B
CAL CHAN0_1
0x1A
Calibrated value
channel S, H, B
CAL CHAN0_2
0x1B
Calibrated value
channel S, H, B
CAL CHAN0_3
0x1C
Calibrated value
channel T, I, C
CAL CHAN0_0
0x1D
Calibrated value
channel T, I, C
CAL CHAN0_1
0x1E
Calibrated value
channel T, I, C
CAL CHAN0_2
0x1F
Calibrated value
channel T, I, C
CAL CHAN0_3
0x20
Calibrated value
channel U, J, D
CAL CHAN0_0
0x21
Calibrated value
channel U, J, D
CAL CHAN0_1
0x22
Calibrated value
channel U, J, D
CAL CHAN0_2
0x23
Calibrated value
channel U, J, D
CAL CHAN0_3
0x24
Calibrated value
channel V, K, E
CAL CHAN0_0
0x25
Calibrated value
channel V, K, E
CAL CHAN0_1
0x26
Calibrated value
channel V, K, E
CAL CHAN0_2
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AS7265x − Detailed Description
Addr
Name
0x27
Calibrated value
channel V, K, E
CAL CHAN0_3
0x28
Calibrated value
channel W, L, F
CAL CHAN0_0
0x29
Calibrated value
channel W, L, F
CAL CHAN0_1
0x2A
Calibrated value
channel W, L, F
CAL CHAN0_2
0x2B
Calibrated value
channel W, L, F
CAL CHAN0_3
0x48
FW control
0x49
FW byte count
FW_BYTE_COUNT_H
0x4A
FW byte count
FW_BYTE_COUNT_L
0x4B
FW payload
HW version H
0x4F
DEV SEL
0x50
COEF DATA
COEF_DATA_0
0x51
COEF DATA
COEF_DATA_1
0x52
COEF DATA
COEF_DATA_2
0x53
COEF DATA
COEF_DATA_3
0x54
COEF READ
COEF_READ
0x55
COEF WRITE
COEF_WRITE
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START
STOP
BYTES_
TRANSF
ERRED
Second
Slave
LOCK
SWITC
H
First
Slave
BANK1
ERROR
CHKSU
M
SELECT DATA
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AS7265x − Detailed Description
Detailed Register Descriptions
Figure 27:
HW Version Registers
Addr: 0x00,0x01
HW Version
Bit
Bit Name
Default
Access
Bit Description
15:8
HW version H
0x40
R
Device type
7:0
HW version L
0x41
R
HW version
Figure 28:
FW Version Registers
Addr: 0x02,0x03
FW Version
Bit
Bit Name
Default
Access
15:8
FW version H
0
R/W
7:0
FW version L
0
R/W
Bit Description
Set register 0x02, 0x03 to 0x01 to 0x03 to get
each firmware positions high byte
0x01: MAJOR version [15..8]
0x02: PATCH version [15..8]
0x03: BUILD version [15..8]
Figure 29:
Configuration Register
Addr: 0x04
Configuration
Bit
Bit Name
Default
Access
Bit Description
7:0
SRST
0
W
6
INT
0
R/W
Enable interrupt pin
5:4
GAIN
01
R/W
Gain configuration: b00=1x; b01=3.7x; b10=16x;
b11=64x
Measurement mode:
b00=Mode 0: 4 channels
b01=Mode 1: 4 channels
b10=Mode 2: All 6 channels
b11=Mode 3: One-Shot operation of mode 2
[W] software reset [R] gain error
3:2
BANK
10
R/W
1
DATA_RDY
0
R
Data ready to read
0
FRST
0
W
Factory reset
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AS7265x − Detailed Description
The maximum sensitivity value depends on the integration
time. For every 2.78ms of integration time, the maximum
sensitivity value increases by 1024 counts. This means that to
be able to reach the full sensitivity scale, the sensitivity has to
be at least 64*2.78ms.
Figure 30:
Integration Time Register
Addr: 0x05
Bit
Bit Name
Integration Time
Default
Access
Bit Description
Integration time = * 2.8ms (applies to all
channels); value: 1-255;Return 0 - read error
7:0
INTEGRATION_
TIME
20
R/W
Value
Integration
Cycles
Integration
Time
Maximum
ADC
Value
0x00
1
2.78ms
1023
0x01
2
5.56ms
2047
...
...
...
...
0x11
18
50ms
18431
0x40
65
181ms
65535
...
...
...
...
0xFF
256
711ms
65535
Figure 31:
Temperature Register
Addr: 0x06
Bit
7:0
Bit Name
Temperature
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Temperature
Default
-
Access
Bit Description
R
Temperature of the device in °C
Read value from every device in dependency of
register DEV_SEL
From -127 to 127
Return -128: Means error
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AS7265x − Detailed Description
Figure 32:
LED Configuration Register
Addr: 0x07
LED Configuration
Bit
Bit Name
Default
Access
Bit Description
7
READ_ERR
0
R
5:4
LED_DRV
00
R/W
LED_DRV current limit: b00=12.5mA; b01=25mA;
b10=50mA; b11=100mA
Device depends on register DEV_SEL
3
ENABLE LED_
DRV
0
R/W
Enable LED DRV
Device depends on register DEV_SEL
2:1
LED_INT
01
R/W
Current limit: b00=1mA; b01=2mA; b10=4mA;
b11=8mA
Device depends on register DEV_SEL
0
ENABLE LED_
INT
0
R/W
Enable LED IND
Device depends on register DEV_SEL
Error while reading status
Figure 33:
RAW Value Channel R,G,A Register
Addr: 0x08,0x09
RAW Value Channel R,G,A
Bit
Bit Name
Default
Access
15:8
RAW value H
-
R
7:0
Raw value L
-
R
Bit Description
Channel R or J or D depends on register DEV_SEL
Figure 34:
RAW Value Channel S,H,B Register
Addr: 0x0A,0x0B
RAW Value Channel S,H,B
Bit
Bit Name
Default
Access
15:8
RAW value H
-
R
7:0
Raw value L
-
R
Bit Description
Channel S or I or C depends on register DEV_SEL
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AS7265x − Detailed Description
Figure 35:
RAW Value Channel T,I,C Register
Addr: 0x0C/0x0D
RAW Value Channel T,I,C
Bit
Bit Name
Default
Access
15:8
RAW value H
-
R
7:0
Raw value L
-
R
Bit Description
Channel T or G or A depends on register DEV_
SEL
Figure 36:
RAW Value Channel U,J,D Register
Addr: 0x0E,0x0F
RAW Value Channel U,J,D
Bit
Bit Name
Default
Access
15:8
RAW value H
-
R
7:0
Raw value L
-
R
Bit Description
Channel U or H or B depends on register DEV_
SEL
Figure 37:
RAW Value Channel V,K,E Register
Addr: 0x10,0x011
RAW Value Channel V,K,E
Bit
Bit Name
Default
Access
15:8
RAW value H
-
R
7:0
Raw value L
-
R
Bit Description
Channel V or K or E depends on register DEV_SEL
Figure 38:
RAW Value Channel W,L,F Register
Addr: 0x12,0x013
RAW Value Channel W,L,F
Bit
Bit Name
Default
Access
15:8
RAW value H
-
R
7:0
Raw value L
-
R
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Bit Description
Channel W or L or F depends on register DEV_
SEL
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AS7265x − Detailed Description
Figure 39:
Calibrated Value Channel R,G,A Register
Addr:
0x17,0x016,0x15,0x014
Calibrated Value Channel R,G,A
Bit
Bit Name
Default
Access
31:24
CAL CHAN0_3
FF
R
23:16
CAL CHAN0_2
FF
R
15:8
CAL CHAN0_1
FF
R
7:0
CAL CHAN0_0
FF
R
Bit Description
Channel R or J or D depends on register DEV_
SEL
Figure 40:
Calibrated Value Channel S, H, B Register
Addr:
0x1B,0x01A,0x19,0x018
Calibrated Value Channel S,H,B
Bit
Bit Name
Default
Access
31:24
CAL CHAN1_3
FF
R
23:16
CAL CHAN1_2
FF
R
15:8
CAL CHAN1_1
FF
R
7:0
CAL CHAN1_0
FF
R
Bit Description
Channel S or I or C depends on register DEV_
SEL
Figure 41:
Calibrated Value Channel T, I, C Register
Addr:
0x1F,0x01E,0x1D,0x01C
Calibrated Value Channel T,I,C
Bit
Bit Name
Default
Access
31:24
CAL CHAN2_3
FF
R
23:16
CAL CHAN2_2
FF
R
15:8
CAL CHAN2_1
FF
R
7:0
CAL CHAN2_0
FF
R
ams Datasheet
[v1-04] 2018-Jul-09
Bit Description
Channel T or G or A depends on register DEV_
SEL
Page 35
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AS7265x − Detailed Description
Figure 42:
Calibrated Value Channel U, J, D Register
Addr:
0x23,0x022,0x21,0x20
Calibrated Value Channel U,J,D
Bit
Bit Name
Default
Access
31:24
CAL CHAN3_3
FF
R
23:16
CAL CHAN3_2
FF
R
15:8
CAL CHAN3_1
FF
R
7:0
CAL CHAN3_0
FF
R
Bit Description
Channel U or H or B depends on register DEV_
SEL
Figure 43:
Calibrated Value Channel V, K, E Register
Addr:
0x27,0x026,0x25,0x24
Calibrated Value Channel V,K,E
Bit
Bit Name
Default
Access
31:24
CAL CHAN4_3
FF
R
23:16
CAL CHAN4_2
FF
R
15:8
CAL CHAN4_1
FF
R
7:0
CAL CHAN4_0
FF
R
Bit Description
Channel V or K or E depends on register DEV_
SEL
Figure 44:
Calibrated Value Channel W, L, F Register
Addr:
0x2B,0x02A,0x29,0x28
Calibrated Value Channel W,L,F
Bit
Bit Name
Default
Access
31:24
CAL CHAN5_3
FF
R
23:16
CAL CHAN5_2
FF
R
15:8
CAL CHAN5_1
FF
R
7:0
CAL CHAN5_0
FF
R
Page 36
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Bit Description
Channel W or L or F depends on register DEV_
SEL
ams Datasheet
[v1-04] 2018-Jul-09
AS7265x − Detailed Description
Figure 45:
FW Control Register
Addr: 0x48
FW Control
Bit
Bit Name
Default
Access
Bit Description
7
START
R/W
6
STOP
W
Reset firmware update state machine
5
BYTES_
TRANSFERRED
R
All 56kbytes are transferred
4
LOCK
R/W
3
SWITCH
W
Switch between both firmware
2
BANK1
R
Set if bank 1 is active, else bank 2
1
ERROR
R
Error occurred while firmware update
0
CHKSUM
R
Checksum of other bank is valid
Set bit once to configure the device update
Lock this firmware for the next start
Figure 46:
FW Byte Count Register
Addr: 0x49,0x4A
FW Byte Count
Bit
Bit Name
Default
Access
15:8
FW_BYTE_
COUNT_H
0
R
7:0
FW_BYTE_
COUNT_L
Bit Description
Byte counter of transferred image
R
Figure 47:
FW Payload Register
Addr:0x4B
FW Payload
Bit
Bit Name
Default
Access
7:0
HW version H
0
R/W
ams Datasheet
[v1-04] 2018-Jul-09
Bit Description
Transfer of firmware byte
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AS7265x − Detailed Description
Figure 48:
DEV SEL Register
Addr: 0x4F
DEV SEL
Bit
Bit Name
Default
Access
Bit Description
5
SECOND
SLAVE
0
R
Second slave Available
5
FIRST SLAVE
0
R
First slave available
1:0
SELECT DATA
00
R/W
0x00: Select master data
0x01: Select first slave data
0x02: Select second slave data
Figure 49:
COEF DATA Register
Addr:
0x53,0x52,0x51,0x50
COEF DATA
Bit
Bit Name
Default
Access
31:24
COEF_DATA_
3
R/W
23:16
COEF_DATA_
2
R/W
15:8
COEF_DATA_
1
R/W
7:0
COEF_DATA_
0
R/W
Bit Description
Data heap to read and write calibration data
Figure 50:
COEF READ Register
Addr:0x54
Bit
Bit Name
7:0
COEF_READ
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COEF READ
Default
Access
R/W
Bit Description
Set sub addresses to read different calibration
data from COEF_DATA register
ams Datasheet
[v1-04] 2018-Jul-09
AS7265x − Detailed Description
Figure 51:
COEF WRITE Register
Addr:0x55
Bit
Bit Name
7:0
COEF_WRITE
COEF WRITE
Default
Access
R/W
Bit Description
Set sub addresses to write different calibration
data from COEF_DATA register to persistent
memory
AS72651 I 2 C Firmware (FW) Update Procedure
• In the FW Update Control register set the Start_XFR bit to
1.
• Write 56k of data to the FW Download register starting
with the first byte in the ams file, then proceed the end of
the ams 56k file with consecutive writes.
• If desired read the FW Byte Count registers to see which
byte is expected to be written next into the FW Download
register.
• When the download file is completely written, confirm the
action by using the FW Update Control register bit XFR_
56k (should =1 if 56k has been downloaded).
• In the FW Update Control register, set the Toggle bit to 1
which will reboot the AS72651 with the new FW after
checking the new FW for correct CRC. If the CRC is incorrect
the toggle bit will not change and the new FW will not be
used.
Figure 52:
Firmware Byte Count High Byte
Addr: 0x60/0xE0
Control_Setup
Bit
Bit Name
Default
Access
7
Start_XFR
0
R/W
Set to 1 to start firmware update
6
Kill_XFR
0
R/W
Set to 1 to stop firmware update.
5
XFR_56K
0
R
4
Reserved
3
Toggle
2:0
Reserved
ams Datasheet
[v1-04] 2018-Jul-09
Bit Description
Set to 1 when 56k bytes have been downloaded.
Reserved, do not use.
0
R/W
Set to 1 to toggle firmware image partition.
Reserved, do not use.
Page 39
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AS7265x − Detailed Description
Figure 53:
Firmware Byte Count, High Byte Register
Addr: 0x61/0xE1
Bit
Bit Name
7:0
FWBC_HIGH
Firmware Byte Count, High Byte
Default
Access
Bit Description
R
Firmware byte address to be downloaded next, High
Byte
Figure 54:
Firmware Byte Count, Low Byte Register
Addr: 0x62/0xE2
Bit
Bit Name
7:0
FWBC_LOW
Firmware Byte Count, Low Byte
Default
Access
R
Bit Description
Firmware byte address to be downloaded next, Low
Byte
Figure 55:
Firmware Download Register
Addr: 0x63/0xE3
Bit
Bit Name
7:0
FWLOAD
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Firmware Download
Default
Access
R/W
Bit Description
Firmware byte to be downloaded
ams Datasheet
[v1-04] 2018-Jul-09
AS7265x − Detailed Description
UART Command Interface
If selected by the I2C_ENB pin setting, the UART module implements the TX and RX signals as defined in the RS-232 / V.24
standard communication protocol. Serial flash EPROM is a required operating companion device to enable the UART command interface.
Figure 56:
Flash Memory Overview
Serial Flash
Manufacturer
AT25SF041xx
Adesto Technologies
AT25DF041xx
Adesto Technologies
MX25L4006ExxI-12G
Macronix
SST25PF040C
Microchip Technology
W25X40CLSNIG
Winbond Electronics
LE25U40CMD
ON Semiconductor
Note(s):
1. Where xx= alternative packages.
UART Feature List
• Full duplex operation (independent serial receive and
transmit registers).
• Factory set to 115.2k Baud
• Supports serial frames with 8 Data Bits, no Parity and 1
Stop Bit.
Operation
Transmission
If data is available in the transmit FIFO, it will be moved into the
output shift register and the data will be transmitted at the
configured Baud Rate, starting with a Start Bit (logic zero) and
followed by a Stop Bit (logic one).
Reception
At any time, with the receiver being idle, if a falling edge of a
start bit is detected on the input, a byte will be received and
stored in the receive FIFO. The following Stop Bit will be checked
to be logic one.
ams Datasheet
[v1-04] 2018-Jul-09
Page 41
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AS7265x − Detailed Description
Figure 57:
UART Protocol
Data Bits
TX
D0
D1
Start Bit
D2
D3
D4
D5
D6
D7
Stop Bit
Tbit=1/Baude Rate
Always Low
RX
D0
Next Start
Always High
D0
D1
D2
D3
D4
D5
D6
D7
D0
Start Bit detected
After Tbit/2: Sampling of Start Bit
After Tbit: Sampling of Data
Sample Points
AT Command Interface
The microprocessor interface to control the AS72651 Spectral_
ID sensor(s) is via AT Commands across the UART interface. The
AS72651 provides a text-based serial command interface borrowed from the “AT Command” model used in early Hayes modems.
For example:
Read DATA value:
ATDATA →
OK
Set the gain of the sensor to 1x:
ATGAIN=0→
OK
The AT Command Interface, shown below provides access to
the Spectral_ID engine’s control and configuration functions.
Figure 58:
AT Command Interface Block Diagram
RX
MCU
AT Commands
TX
AT
Command
Interface
Spectral_ID
Engine
AT Command Interface
AS72651
Page 42
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ams Datasheet
[v1-04] 2018-Jul-09
AS7265x − Detailed Description
In the AT Commands figure below, numeric values may be specified with no leading prefix, in which case they will be interpreted as decimals, or with a leading “0x” to indicate that they are
hexadecimal numbers. The commands are loosely grouped into
functional areas. Texts appearing between angle brackets
(‘‘) are commands or response arguments. A carriage
return character, a linefeed character, or both may terminate
commands and responses. Note that any command that encounters an error will generate the “ERROR” response shown,
for example, in the NOP command at the top of the first table,
but has been omitted elsewhere in the interest of readability
and clarity.
Note(s): The Figure 59 shows the complete list of all AS7265x
AT commands.
Figure 59:
AS7265x AT Commands
Commands
Direction
Description
Format
Value Range
Default
-
-
-
Status
AT
R
ATVERSW
R
Return the current
software version
number
DEC
ATVERHW
R
Returns the system
hardware as a HEX
value of the form
PRDTx where
P=PartID and
R=ChipRevision and
DT= DeviceType
HEX
PR = 40
DT = 15
ATTEMP
R
Read the current
device temperature
in degrees Celsius
DEC
Send three temperature values (Format:
A, B, C)
-
ATDATA
R
Read all six raw vales
per device(
-
R
Read all six calibrated
values per device.
Returns commaseparated 32-bit
floating point values.
DEC
< R, S, T, U, V, W, G, H,
I, J, K, L, A, B, C, D, E,
F>
-
ATCDATA
ams Datasheet
[v1-04] 2018-Jul-09
NOP
-
0x4041
Page 43
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AS7265x − Detailed Description
Commands
Direction
Description
Format
Value Range
Default
Control
ATINTTIME
R/W
Set sensor
integration time.
Integration time =
* ~2.8ms.
ATGAIN
R/W
Set sensor gain: 0=1x
gain, 1=3.7x, 2=16x,
3=64x
DEC
0-3
1
ATINTRP
R/W
Enable/Disable
interrupt pin
DEC
0 - Disable
1 - Enable Interrupt
pin functionality
0
2
1
ATTCSMD
ATINTRVL
Page 44
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DEC
1-255
20
R/W
Set measurement
mode
DEC
0: Captures bank0 (1
integration period)
1: Captures bank1 (1
integration period)
2: Captures bank0+
bank1(2 integration
period)
3:Captures bank0+
bank1 in one shot
mode (2 integration
period)
R/W
Set the sampling
interval as an integer
multiple of the
integration time. The
is an integer
between [1...255].
A sampling
interval=1 implies a
sampling rate of 1x
the current
integration time.
A sampling
interval=255 implies
a slow sampling rate
of 255 times the
current integration
time
DEC
1…255
ams Datasheet
[v1-04] 2018-Jul-09
AS7265x − Detailed Description
Commands
ATBURST
Direction
R/W
Description
Format
Value Range
Default
Sends a number of
calibrated data
without separate
requests second
parameter for the
burst mode is
optionally format:
Send: ATBURST=10,0
or ATBURST=10
Read: ATBURST ≥
10,0 OK
DEC
BURST NUMBER:
0 - Burst mode is
deactivated
1-254 - Number of
burst transfers
255 - Send unlimited
bursts (stops with
ATBURST=0)
0
BURST MODE:
0 - Raw values
(default, like
ATDATA)
1 - Calibrated values
(like ATCDATA)
ATLED0
R/W
Enables or disables
the indication LED
DEC
0 - LED off
1 - LED on
1
ATLED1
R/W
Enables or disables
the driver LED
DEC
0 - LED off
1 - LED on
0
ATLED2
R/W
Enables or disables
the indication LED for
first I2C slave
DEC
0 - LED off
1 - LED on
1
ATLED3
R/W
Enables or disables
the driver LED for first
I2C slave
DEC
0 - LED off
1 - LED on
0
ATLED4
R/W
Enables or disables
the indication LED for
second I2C slave
DEC
0 - LED off
1 - LED on
1
R/W
Enables or disables
the driver LED for
second I2C slave
DEC
0 - LED off
1 - LED on
0
HEX
[1...0] LED_IND:
b00=1mA;
b01=2mA;
b10=4mA; b11=8mA
[5...4] LED_DRV:
b00=12.5mA;
b01=25mA;
b10=50mA;
b11=100mA
ATLED5
ATLEDC
ams Datasheet
[v1-04] 2018-Jul-09
R/W
Sets LED_IND and
LED_DRV current
(for master only)
0x00
Page 45
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AS7265x − Detailed Description
Commands
Format
Value Range
Default
HEX
[1...0] LED_IND:
b00=1mA;
b01=2mA;
b10=4mA; b11=8mA
[5...4] LED_DRV:
b00=12.5mA;
b01=25mA;
b10=50mA;
b11=100mA
0x00
R/W
Sets LED_IND and
LED_DRV current for
second I2C slave
HEX
[1...0] LED_IND:
b00=1mA;
b01=2mA;
b10=4mA; b11=8mA
[5...4] LED_DRV:
b00=12.5mA;
b01=25mA;
b10=50mA;
b11=100mA
0x00
ATFRST
W
Factory Reset. Stored
values are reset to
‘Factory’ defaults.
Afterwards a software
reset is started.
-
-
-
ATSRST
W
Software reset
-
-
-
ATLEDD
ATLEDE
Direction
R/W
Description
Sets LED_IND and
LED_DRV current for
first I2C slave
Calibration Values
ATSCLx
R/W
Read/Write scalar for
the raw values
(x=0...17)
p2ram
value
DEC
Firmware Update
ATFWU
ATFW
Page 46
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W
Starts firmware
update process and
transfer the bin file
checksum
-
-
-
W
Download new
firmware.
Up to 7 bytes of FW
image at a time (14
hex bytes with no
leading or trailing 0x).
Repeat command till
all 56kBytes of
firmware are
downloaded
-
HEX STRING
(without 0x), max. 7
bytes
-
ams Datasheet
[v1-04] 2018-Jul-09
AS7265x − Detailed Description
Commands
ATFWS
ATFWL
ATFWC
ATFWA
ams Datasheet
[v1-04] 2018-Jul-09
Direction
Description
Format
Value Range
Default
W
Tests the checksum
on the non-active FW
partition and, if
correct, switches
active partition. This
is a toggle and used
to toggle between
the 2 FW partitions.
Note: The first 5 bytes
in page 0 are not
touched. It is only a
temporary switch
and must be used to
check the new
firmware whether the
communication
works!
-
-
-
W
This command locks
the current firmware
to starts on power
cycles. It rewrites the
first five bytes in
page0!
-
-
-
R
This command gives
information about
the current firmware
state
-
Bit0 - Checksum of
non-active firmware
OK
Bit1 - Error occurred
Bit2 - Bank 1 active
Bit3 - Not used
Bit4 - Current
firmware is locked
Bit5 - 56kBytes
transferred
Bit6 - Not used
Bit7 - Firmware
update active
-
W
Only for backward
compatibility to
support old firmware,
update mechanism.
Always returns with
OK. Because of flash
devices, it is not
possible to increment
the address
separately (page
erase necessary!)
-
-
-
Page 47
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AS7265x − Application Information
Application Information
Figure 60:
Typical AS7265x 18-Channel Application Circuit
3V3
U3
+5V
3V3
D9
LED
17
C7
100nF
C8
1u0
14
RESN TP9
R10
10k
GND
2
RESN
16
R11
200R
D11
3V3
CSN
VDD2
MISO
RESN
MOSI
GND
SCK
AS72651
GND
LED_651
15
LED_IND
18
I2C_ENB
LED_DRV
LED_IND
NC
GRN
SLV2_RESN
--->
COMM_RX
11
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