ACD2202S8P0

ACD2202 CATV/TV/Video Downconverter with Dual Synthesizer Data Sheet - Rev 2.1 FEATURES • • • • • • • • • • • Integrated Downconverter Integrated Dual Synthesizer 256 QAM Compatibility Single +5 V Power Supply Operation Low Power Consumption: A, Divide ratios less than 3 are prohibited. Table 12: Main Divider A Counter Bits VALUE OF A COUNTER 0 1 127 Notes: B > A, A < P Table 13: Variable Definitions A 1 0 1 1 A 7 0 0 1 A 6 0 0 1 A 5 0 0 1 A 4 0 0 1 A 3 0 0 1 A 2 0 0 1 VAR fVCO B A fOSC R P DEFINITION Desired output frequency of external voltage controlled oscillator (VCO) Divide ratio of B counter (3 to 2047) Divide ratio of A counter (0 < A < P, A < B) Frequency of external reference crystal or oscillator Divide ratio of R counter (3 to 32767) Preset modulus of prescalar (P = 64) 12 Data Sheet - Rev 2.1 12/2003 ACD2202 Programmable Modes Each register contains bits set aside for programming different modes of operation in the synthesizers. Currently, the only programmable mode is the polarity of the phase detector in each of the synthesizers. Bit D1 in each reference divider register controls this feature. Bits D2 through D5 in the reference divider registers and bits C1 and C2 in the main divider registers are reserved for future use, and have no current function. They can be set Table 14: Phase Detector Polarity Bit either high or low without affecting synthesizer performance. Setting Phase Detector Polarity Table 14 shows how bit D1 of each reference divider register controls the polarity of the phase detector associated with each PLL. The correct setting is determined by using Table 15 and Figure 21. Figure 21: VCO Characteristics S 2 0 1 S 1 0 0 D 1 PLL2 Phase Detector Polarity PLL1 Phase Detector Polarity VCO OUTPUT FREQUENCY (1) Table 15: Phase Detector Polarity Selection D 1 0 1 PHASE DETECTOR POLARITY Negative Positive VC O CHARACTERISTICS (SEE FIGURE 12) curve (2) curve (1) (2) VCO INPUT VOLTAGE Synthesizer Programming Example The following example for programming the two synthesizers in the ACD2202 details the calculations used to determine the required value of each bit in all four registers: Requirements Desired CATV input channel: “HHH” - 499.25 MHz picture carrier (501 MHz digital channel center frequency) (Second) IF picture carrier output frequency: 45.75 MHz (44 MHz digital channel center frequency) First IF frequency: 1087.75 MHz Phase detector comparison frequency for down converter (also tuning increment): 62.5 KHz Phase detector comparison frequency for up converter: 250 KHz Crystal reference oscillator frequency: 4 MHz Calculation of Reference Divider Values The value for each reference divider is calculated by dividing the reference oscillator frequency by the desired phase detector comparison frequency: R = fOSC / fPD For the down converter, the 4 MHz crystal oscillator frequency and the 62.5 KHz phase detector comparison frequency are used to yield RPLL2 = 4 MHz / 62.5 KHz = 64, and so the bit values for the down converter R counter are RPLL2 = 000000001000000. Data Sheet - Rev 2.1 12/2003 13 ACD2202 For the up converter, the 4 MHz crystal oscillator frequency and the 250 KHz phase detector comparison frequency are used to yield RPLL1 = 4 MHz / 250 KHz = 16, and so the bit values for the up converter R counter are RPLL1 = 000000000010000. Calculation of Main Divider Values The values for the A and B counters are determined by the desired VCO output frequency for the local oscillator and the phase detector comparison frequency: N = fVCO / f PD B = trunc(N / P) A = N - (B x P) The down converter local oscillator frequency will be 1087.75 MHz - 45.75 MHz = 1042 MHz in this example. The main divider ratio for the down converter, then, is NPLL2 = 1042 MHz / 62.5 KHz = 16672. Since P = 64 in the ACD2202, BPLL2 = trunc(16672 / 64) = 260, and APLL2 = 16672 - (260 x 64) = 32. These results give bit values of BPLL2 = 00100000100 and APLL2 = 0100000 for the B and A counters. The up converter local oscillator frequency will be 499.25 MHz + 1087.75 MHz = 1587 MHz in this example. Therefore, NPLL1 = 1587 MHz / 250 KHz = 6348, BPLL1 = trunc(6348 / 64) = 99, and APLL1 = 6348 - (99 x 64) = 12. These results give bit values of BPLL1 = 00001100011 and APLL1 = 0001100 for the B and A counters. Phase Detector Polarity Assuming the VCO for the up converter has a negative slope, the phase detector polarity for PLL1 should be negative, and D1PLL1 = 1. If the VCO for the down converter has a positive slope, the phase detector polarity for PLL2 should be positive, and D1PLL2 = 0. In summary, for this example, the four register programming words are shown in Tables 16 and 17: Table 16: PLL1 and PLL2 Reference Divider Register Bits for Synthesizer Programming Example MSB LSB 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Program Mode D 5 0 0 D 4 0 0 D 3 0 0 D 2 0 0 D 1 1 0 R 15 0 0 R 14 0 0 R 13 0 0 R 12 0 0 Reference Divider R Counter R 11 0 0 R 10 0 0 R 9 0 0 R 8 0 0 R 7 1 0 R 6 0 0 R 5 0 1 R 4 0 0 R 3 0 0 R 2 0 0 R 1 0 0 Select S 2 0 1 S 1 0 0 MSB Table 17: PLL1 and PLL2 Main Divider Register Bits for Synthesizer Programming Example 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 LSB 22 1 Program Mode C 2 0 0 C 1 0 0 B 11 0 0 B 10 0 0 B 9 1 0 Main Divider B Counter B 8 0 0 B 7 0 1 B 6 0 1 B 5 0 0 B 4 0 0 B 3 1 0 B 2 0 1 B 1 0 1 A 7 0 0 Main Divider A Counter A 6 1 0 A 5 0 0 A 4 0 1 A 3 0 1 A 2 0 0 A 1 0 0 Select S 2 0 1 S 1 1 1 14 Data Sheet - Rev 2.1 12/2003 ACD2202 APPLICATION INFORMATION VSYN 20 kW VSYN pins 16,19 AV~ -1000 VSS VSS pins 17,18 VSYN 200 W pin 13 VSS VSYN pin 14 VSS 300 kW pin 1 pin 2 5 kW pin 4 GND 5 kW GND VSUP 10 W 15 W 5W GND 10 pF OSCGND pin 27 5 pF pin 28 5 pF 5W GND pin 24 pin 5 Figure 22: Equivalent Circuits Data Sheet - Rev 2.1 12/2003 15 ACD2202 Figure 23: PC Board Layout Top View Figure 24: PC Board Layout Mid View RF RF IF Balun AFC Out 4M Hz Xtal ACD2202 J1 LO In 1 Figure 25: PC Board Layout Bottom View Table 18: J1 Header Pinout PIN 1 2 3 4 5 6 16 FUNCTION Clock Data Ground Enable +5 V DC +30 V DC Data Sheet - Rev 2.1 12/2003 Figure 26 Evaluation Fixture Table 19: Fixture Pinout PIN RF RF IF AFC Out LO In FU N C TION D ownconverter RF Input D ownconverter RF Input IF Output (Si ngle Ended) To Upconverter Osci llator Tuni ng C i rcui t Synthesi zer RFU LO Input IF L3 C24 DT1 +5V 1 RF RF C1 C2 2 RFIN+ RFINGND ISET TCKT OSCGND OSCGND VSS VSS EN DATA CLK REFIN REFOUT ACD2202 R8 L2 C13 C12 C11 C10 C9 C14 RFU VSYN CPU 17 16 15 VIF + IFOUT+ VIF + IFOUTGND 26 VSUP OSC OUT GND GND VSS VSS RFD CPD 18 19 20 21 22 23 24 25 27 28 C21 C22 C23 R1 4 5 3 R13 C18 C16 C20 C17 R11 Q1 C19 +30V J1 7 D1 L1 8 9 10 C3 6 6 +30V 5 +5V 4 R5 R3 11 Figure 27: Evaluation Fixture Schematic R12 R4 12 13 14 Data Sheet - Rev 2.1 12/2003 R6 X1 +5V 3 R2 2 1 AFCOUT LOIN C4 R7 C5 C6 R9 R10 C15 C7 C8 ACD2202 17 ACD2202 Table 20: Evaluation Fixture Parts List ITEM # C 1, C 2, C 20 C3 C 7, C 8 C 12 C9, C11, C 14, C 21, C 22 C 10, C 23 C 15, C 17 C 16 C 18 C 19 C 24 C 13 C 4, C 5, C6 R8 R5 R2, R3, R4 R12 R11 R7 R13 R10 R1 VALUE 100pF 9pF 30pF 220uF .1uF SIZE 0603 0603 0603 DESCRIPTION Chip-capacitor Chip-capacitor Chip-capacitor PART # GRM39COG101J50V GRM39COG090C50V GRM39COG300J50V PCE2040CT-ND GRM39Y5V104Z16V QTY 3 VENDOR Murata Murata Murata DIGI-KEY Murata 1 2 1 10V VA Capacitor Series 0603 Chip-capacitor 5 1000pF 4700pF 1uF .01uF 10uF 15pF 5600pF 33pF 51 10K 2K 1K 2.7K 3K 22K 8.2K 10 0603 0603 0603 0603 35 V TANT 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 Chip-capacitor Chip-capacitor Radial-lead Chip-capacitor Chip-capacitor GRM39X7R102K50V GRM39X7R472K25V RPE113-X7R-105-K-050 GRM39X7R103K25V 2 2 1 Murata Murata Murata Murata DIGI-KEY Murata Murata Murata Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic 1 1 TE Series Cap. PCS6106CT-ND Chip-capacitor Chip-capacitor Chip-capacitor Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor GRM39COG150J50V GRM39X7R562K50V GRM39COG330J50V ERJ-3GSYJ510 ERJ-3GSYJ103 ERJ-3GSYJ202 ERJ-3GSYJ102 ERJ-3GSYJ272 ERJ-3GSYJ302 ERJ-3GSYJ223 ERJ-3GSYJ822 1 1 3 1 1 3 1 1 1 1 1 1 ERJ-3GSYJ100 18 Data Sheet - Rev 2.1 12/2003 ACD2202 Table 20: Evaluation Fixture Parts List continued ITEM # R6, R9 L1 L2 L3 D1 DT1 Q1 X1 VALUE 0 5.6nH 68nH 270nH 1S V 245 4:1 30V SMD 4MHZ SOT-23 SIZE 0603 0805 0805 0805 DESCRIPTION Chip Resistor Inductor Inductor Inductor Varactor diode Transformer Transistor NPN Darl. Crystal PART # ZC0603 0805CS-050X-BC 0805CS-680X-BC 0805CS-271X-BC 1SV245 ETC4-1-2 FMMTA13CT-ND SE2618CT-ND QTY 2 1 1 1 1 1 VENDOR RCD Coilcraft Coilcraft Coilcraft Toshiba M/A-COM, Inc. North America DIGI-KEY DIGI-KEY 1 1 Data Sheet - Rev 2.1 12/2003 19 ACD2202 PACKAGE OUTLINE Figure 28: S8 Package Outline - 28 Pin SSOP 20 Data Sheet - Rev 2.1 12/2003 ACD2202 NOTES Data Sheet - Rev 2.1 12/2003 21 ACD2202 NOTES 22 Data Sheet - Rev 2.1 12/2003 ACD2202 NOTES Data Sheet - Rev 2.1 12/2003 23 ACD2202 ORDERING INFORMATION ORDER NUMBER A C D 2202S 8P 1 A C D 2202S 8P 0 TEMPERATURE RANGE -40°C to +85°C -40°C to +85°C PACKAGE DESCRIPTION 28 Pin SSOP 28 Pin SSOP COMPONENT PACKAGING Tape & Reel, 3500 pieces per reel Tubes, 50 pieces per tube ANADIGICS, Inc. 141 Mount Bethel Road Warren, New Jersey 07059, U.S.A Tel: +1 (908) 668-5000 Fax: +1 (908) 668-5132 URL: http://www.anadigics.com E-mail: Mktg@anadigics.com IMPORTANT NOTICE ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders. WARNING ANADIGICS products are not intended for use in life support appliances, devices, or systems. Use of an ANADIGICS product in any such application without written consent is prohibited. 24 Data Sheet - Rev 2.1 12/2003