AAT3215IJS-3.3-T1

150mA CMOS High Performance LDO General Description The AAT3215 MicroPower™ low dropout (LDO) linear regulator is ideally suited for portable applications where low noise, extended battery life, and small size are critical. The AAT3215 has been specifically designed for very low output noise performance, fast transient response, and high power supply rejection ratio (PSRR), making it ideal for powering sensitive RF circuits. Other features include low quiescent current, typically 95µA, and low dropout voltage which is typically less than 140mV at full output current. The device is output short-circuit protected and has a thermal shutdown circuit for additional protection under extreme conditions. The AAT3215 also features a low-power shutdown mode for extended battery life. A reference bypass pin has been provided to improve PSRR performance and output noise by connecting an external capacitor from the AAT3215's reference output to ground. The AAT3215 is available in a Pb-free, space-saving 5-pin SOT23 or 8-pin SC70JW package in ten factory-programmed voltages: 2.5V, 2.6V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0V, 3.1V, 3.3V, or 3.6V. AAT3215 Features • • • • • • • • • • • • • • • PowerLinear ™ SmartSwitch™ Low Dropout: 140mV at 150mA Guaranteed 150mA Output High Accuracy ±1.5% 95µA Quiescent Current High Power Supply Ripple Rejection — 70dB at 1kHz — 50dB at 10kHz Very Low Self Noise: 45µVrms Fast Line and Load Transient Response Short-Circuit Protection Over-Temperature Protection Uses Low Equivalent Series Resistance (ESR) Ceramic Capacitors Noise Reduction Bypass Capacitor Shutdown Mode for Longer Battery Life Low Temperature Coefficient Ten Factory-Programmed Output Voltages SOT23 5-Pin or SC70JW 8-Pin Package Applications • • • • • • Bluetooth™ Headsets Cellular Phones Digital Cameras Notebook Computers Personal Portable Electronics Portable Communication Devices Typical Application VIN IN OUT VOUT AAT3215 ON/OFF 1μF EN GND 10nF 2.2μF BYP GND GND 3215.2006.05.1.6 1 150mA CMOS High Performance LDO Pin Descriptions Pin # SOT23-5 SC70JW-8 AAT3215 Symbol IN GND EN Function Input voltage pin; should be decoupled with 1µF or greater capacitor. Ground connection pin. Enable pin. When pulled low, the PMOS pass transistor turns off and all internal circuitry enters low-power mode, consuming less than 1µA. This pin should not be left floating. Bypass capacitor connection. To improve AC ripple rejection, connect a 10nF capacitor to GND. This will also provide a softstart function. Output pin; should be decoupled with 2.2µF capacitor. 1 2 3 5, 6 8 7 4 1 BYP 5 2, 3, 4 OUT Pin Configuration SOT23-5 (Top View) SC70JW-8 (Top View) IN GND EN 1 5 OUT 2 3 4 BYP BYP OUT OUT OUT 1 2 3 4 8 7 6 5 GND EN IN IN 2 3215.2006.05.1.6 150mA CMOS High Performance LDO Absolute Maximum Ratings1 TA = 25°C, unless otherwise noted. Symbol VIN VENIN(MAX) IOUT TJ AAT3215 Description Input Voltage Maximum EN to Input Voltage DC Output Current Operating Junction Temperature Range Value 6 0.3 PD/(VIN-VO) -40 to 150 Units V V mA °C Thermal Information2 Symbol ΘJA PD Description Maximum Thermal Resistance (SOT23-5, SC70JW-8) Maximum Power Dissipation (SOT23-5, SC70JW-8) Rating 190 526 Units °C/W mW Recommended Operating Conditions Symbol VIN T Description Input Voltage Ambient Temperature Range Rating (VOUT + 0.3) to 5.5 -40 to +85 Units V °C 1. Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum Rating should be applied at any one time. 2. Mounted on a demo board. 3215.2006.05.1.6 3 150mA CMOS High Performance LDO Electrical Characteristics VIN = VOUT(NOM) + 1V, IOUT = 1mA, COUT = 2.2µF, CIN = 1µF, CBYP = 10nF, TA = -40°C to +85°C, unless otherwise noted. Typical values are TA = 25°C. Symbol VOUT IOUT VDO ISC IQ ISD ΔVOUT/VOUT*ΔVIN ΔVOUT(line) ΔVOUT(load) VEN(L) VEN(H) IEN PSRR TSD THYS eN TC AAT3215 Description Output Voltage Tolerance Output Current Dropout Voltage1 Short-Circuit Current Ground Current Shutdown Current Line Regulation Dynamic Line Regulation Dynamic Load Regulation Enable Threshold Low Enable Threshold High Leakage Current on Enable Pin Power Supply Rejection Ratio Over-Temperature Shutdown Threshold Over-Temperature Shutdown Hysteresis Output Noise Output Voltage Temperature Coefficient Conditions IOUT = 1mA to TA = 25°C 150mA TA = -40 to 85°C VOUT > 1.2V IOUT = 150mA VOUT < 0.4V VIN = 5V, No Load, EN = VIN VIN = 5V, EN = 0V VIN = VOUT + 1 to 5.5V VIN = VOUT + 1V to VOUT + 2V, IOUT = 150mA, TR/TF = 2µs IOUT = 1mA to 150mA, TR < 5µs Min Typ -1.5 -2.5 150 140 600 95 Max 1.5 2.5 250 150 1 0.07 Units % mA mV mA µA µA %/V mV mV V V µA dB °C °C µVrms ppm/°C 1 30 0.6 1.5 VEN = 5V IOUT = 10mA, CBYP = 10nF 1kHz 10kHz 1MHz 70 50 47 150 10 45 22 1 1. VDO is defined as VIN - VOUT when VOUT is 98% of nominal. 4 3215.2006.05.1.6 150mA CMOS High Performance LDO Typical Characteristics Unless otherwise noted, VIN = 5V, TA = 25°C. AAT3215 Dropout Voltage vs. Temperature 200 Dropout Characteristics 3.1 Dropout Voltage (mV) 160 140 120 100 80 60 40 20 0 -40 -20 Output Voltage (V) 180 IL = 150mA IL = 100mA IL = 50mA 3.0 IOUT = 10mA IOUT = 0mA IOUT = 150mA 2.9 IOUT = 100mA 2.8 IOUT = 50mA 2.9 3.0 3.1 3.2 3.3 2.7 0 20 40 60 80 100 120 Temperature (°C) Input Voltage (V) Dropout Voltage vs. Output Current 200 Ground Current vs. Input Voltage 120 Dropout Voltage (mV) Ground Current (μA) 180 160 140 120 100 80 60 40 20 0 0 50 100 150 100 80 60 40 20 0 2 VOUT = 3.0V IOUT = 5mA IOUT = 150mA IOUT = 0 3 4 5 Output Current (mA) Input Voltage (V) Ground Current vs. Temperature (VOUT = 3.0V) 105 3.014 Output Voltage vs. Temperature Ground Current (μA) Output Voltage (V) 0 50 100 150 100 95 90 85 80 -50 3.013 3.012 3.011 3.01 3.009 3.008 3.007 -50 0 50 100 150 Temperature (°C) Temperature (°C) 3215.2006.05.1.6 5 150mA CMOS High Performance LDO Typical Characteristics Unless otherwise noted, VIN = 5V, TA = 25°C. AAT3215 On/Off Transient Response (No CBYP Capacitor) On/Off Transient Response (CBYP = 10nF) EN (2V/div) VOUT (1V/div) EN (2V/div) VOUT (1V/div) 10mA 10mA 150mA 150mA Time (100µs/div) Time (5ms/div) Line Transient Response 3.04 6 3.10 Load Transient Response 500 Output Current (mA) Output Voltage (V) 3.02 3.01 3.00 2.99 2.98 4 3 2 1 0 Output Voltage (V) 3.03 5 3.05 3.00 2.95 2.90 2.85 2.80 400 300 200 100 0 -100 Input Voltage (V) Time (5µs/div) Time (100µs/div) Short-Circuit Current Short-Circuit Current (A) 1.2 1 Power Supply Rejection Ratio vs. Frequency 90 80 IOUT = 150mA COUT = 10μF 4.7μF 2.2μF PSRR (dB) 0.8 0.6 0.4 0.2 0 70 60 50 40 30 20 10 0 10 1.0μF 100 1k 10k 100k 1m 10m Time (10ms/div) Frequency (Hz) 6 3215.2006.05.1.6 150mA CMOS High Performance LDO Typical Characteristics Unless otherwise noted, VIN = 5V, TA = 25°C. AAT3215 Output Self Noise Noise Amplitude in nVrms/√Hz (50nVrms/√Hz per div) 500 0 10 100 1k 10k 100k 1m 10m Frequency (Hz) 3215.2006.05.1.6 7 150mA CMOS High Performance LDO Functional Block Diagram AAT3215 IN Over-Current Protection Over-Temperature Protection OUT Error Amplifier EN BYP Voltage Reference GND Functional Description The AAT3215 is intended for LDO regulator applications where output current load requirements range from no load to 150mA. The advanced circuit design of the AAT3215 provides excellent input-to-output isolation, which allows for good power supply ripple rejection characteristics. To optimize for very low output self noise performance, a bypass capacitor pin has been provided to decrease noise generated by the internal voltage reference. This bypass capacitor will also enhance PSRR behavior. The two combined characteristics of low noise and high PSRR make the AAT3215 a truly high performance LDO regulator especially well suited for circuit applications which are sensitive to their power source. The LDO regulator output has been specifically optimized to function with low-cost, low-ESR ceramic capacitors. However, the design will allow for operation over a wide range of capacitor types. The device enable circuit is provided to shut down the LDO regulator for power conservation in portable products. The enable circuit has an additional output capacitor discharge circuit to assure sharp application circuit turn-off upon device shutdown. This LDO regulator has complete short-circuit and thermal protection. The integral combination of these two internal protection circuits gives the AAT3215 a comprehensive safety system during extreme adverse operating conditions. Device power dissipation is limited to the package type and thermal dissipation properties. Refer to the Thermal Considerations section of this datasheet for details on device operation at maximum output current loads. 3215.2006.05.1.6 8 150mA CMOS High Performance LDO Applications Information To assure the maximum possible performance is obtained from the AAT3215, please refer to the following application recommendations. greater for COUT. If desired, COUT may be increased without limit. In low output current applications where output load is less than 10mA, the minimum value for COUT can be as low as 0.47µF. AAT3215 Input Capacitor Typically, a 1µF or larger capacitor is recommended for CIN in most applications. A CIN capacitor is not required for basic LDO regulator operation. However, if the AAT3215 is physically located more than three centimeters from an input power source, a CIN capacitor will be needed for stable operation. CIN should be located as closely to the device VIN pin as practically possible. CIN values greater than 1µF will offer superior input line transient response and will assist in maximizing the highest possible power supply ripple rejection. Ceramic, tantalum, or aluminum electrolytic capacitors may be selected for CIN. There is no specific capacitor ESR requirement for CIN. However, for 150mA LDO regulator output operation, ceramic capacitors are recommended for CIN due to their inherent capability over tantalum capacitors to withstand input current surges from low impedance sources such as batteries in portable devices. Bypass Capacitor and Low Noise Applications A bypass capacitor pin is provided to enhance the very low noise characteristics of the AAT3215 LDO regulator. The bypass capacitor is not necessary for operation of the AAT3215. However, for best device performance, a small ceramic capacitor should be placed between the bypass pin (BYP) and the device ground pin (GND). The value of CBYP may range from 470pF to 10nF. For lowest noise and best possible power supply ripple rejection performance, a 10nF capacitor should be used. To practically realize the highest power supply ripple rejection and lowest output noise performance, it is critical that the capacitor connection between the BYP pin and GND pin be direct and PCB traces should be as short as possible. Refer to the PCB Layout Recommendations section of this document for examples. There is a relationship between the bypass capacitor value and the LDO regulator turn-on time. In applications where fast device turn-on time is desired, the value of CBYP should be reduced. In applications where low noise performance and/ or ripple rejection are less of a concern, the bypass capacitor may be omitted. The fastest device turnon time will be realized when no bypass capacitor is used. DC leakage on this pin can affect the LDO regulator output noise and voltage regulation performance. For this reason, the use of a low leakage, high quality ceramic (NPO or C0G type) or film capacitor is highly recommended. Output Capacitor For proper load voltage regulation and operational stability, a capacitor is required between pins VOUT and GND. The COUT capacitor connection to the LDO regulator ground pin should be made as direct as practically possible for maximum device performance. The AAT3215 has been specifically designed to function with very low ESR ceramic capacitors. Although the device is intended to operate with these low ESR capacitors, it is stable over a very wide range of capacitor ESR, thus it will also work with higher ESR tantalum or aluminum electrolytic capacitors. However, for best performance, ceramic capacitors are recommended. Typical output capacitor values for maximum output current conditions range from 1µF to 10µF. Applications utilizing the exceptionally low output noise and optimum power supply ripple rejection characteristics of the AAT3215 should use 2.2µF or Capacitor Characteristics Ceramic composition capacitors are highly recommended over all other types of capacitors for use with the AAT3215. Ceramic capacitors offer many advantages over their tantalum and aluminum electrolytic counterparts. A ceramic capacitor typically has very low ESR, is lower cost, has a smaller PCB 9 3215.2006.05.1.6 150mA CMOS High Performance LDO footprint, and is non-polarized. Line and load transient response of the LDO regulator is improved by using low ESR ceramic capacitors. Since ceramic capacitors are non-polarized, they are not prone to incorrect connection damage. Equivalent Series Resistance: ESR is a very important characteristic to consider when selecting a capacitor. ESR is the internal series resistance associated with a capacitor that includes lead resistance, internal connections, size and area, material composition, and ambient temperature. Typically, capacitor ESR is measured in milliohms for ceramic capacitors and can range to more than several ohms for tantalum or aluminum electrolytic capacitors. Ceramic Capacitor Materials: Ceramic capacitors less than 0.1µF are typically made from NPO or C0G materials. NPO and C0G materials generally have tight tolerance and are very stable over temperature. Larger capacitor values are usually composed of X7R, X5R, Z5U, or Y5V dielectric materials. Large ceramic capacitors (i.e., greater than 2.2µF) are often available in low-cost Y5V and Z5U dielectrics. These two material types are not recommended for use with LDO regulators since the capacitor tolerance can vary more than ±50% over the operating temperature range of the device. A 2.2µF Y5V capacitor could be reduced to 1µF over temperature; this could cause problems for circuit operation. X7R and X5R dielectrics are much more desirable. The temperature tolerance of X7R dielectric is better than ±15%. Capacitor area is another contributor to ESR. Capacitors that are physically large in size will have a lower ESR when compared to a smaller sized capacitor of an equivalent material and capacitance value. These larger devices can improve circuit transient response when compared to an equal value capacitor in a smaller package size. Consult capacitor vendor datasheets carefully when selecting capacitors for LDO regulators. age on the EN pin falls below 0.6 volts. If the enable function is not needed in a specific application, it may be tied to VIN to keep the LDO regulator in a continuously on state. When the LDO regulator is in shutdown mode, an internal 1.5kΩ resistor is connected between VOUT and GND. This is intended to discharge COUT when the LDO regulator is disabled. The internal 1.5kΩ has no adverse effect on device turn-on time. AAT3215 Short-Circuit Protection The AAT3215 contains an internal short-circuit protection circuit that will trigger when the output load current exceeds the internal threshold limit. Under short-circuit conditions, the output of the LDO regulator will be current limited until the short-circuit condition is removed from the output or LDO regulator package power dissipation exceeds the device thermal limit. Thermal Protection The AAT3215 has an internal thermal protection circuit which will turn on when the device die temperature exceeds 150°C. The internal thermal protection circuit will actively turn off the LDO regulator output pass device to prevent the possibility of overtemperature damage. The LDO regulator output will remain in a shutdown state until the internal die temperature falls back below the 150°C trip point. The combination and interaction between the shortcircuit and thermal protection systems allows the LDO regulator to withstand indefinite short-circuit conditions without sustaining permanent damage. No-Load Stability The AAT3215 is designed to maintain output voltage regulation and stability under operational noload conditions. This is an important characteristic for applications where the output current may drop to zero. Enable Function The AAT3215 features an LDO regulator enable/ disable function. This pin (EN) is active high and is compatible with CMOS logic. To assure the LDO regulator will switch on, the EN turn-on control level must be greater than 2.0V. The LDO regulator will go into the disable shutdown mode when the volt10 Reverse Output-to-Input Voltage Conditions and Protection Under normal operating conditions, a parasitic diode exists between the output and input of the LDO regulator. The input voltage should always remain greater than the output load voltage, main3215.2006.05.1.6 150mA CMOS High Performance LDO taining a reverse bias on the internal parasitic diode. Conditions where VOUT might exceed VIN should be avoided since this would forward bias the internal parasitic diode and allow excessive current flow into the VOUT pin, possibly damaging the LDO regulator. In applications where there is a possibility of VOUT exceeding VIN for brief amounts of time during normal operation, the use of a larger value CIN capacitor is highly recommended. A larger value of CIN with respect to COUT will effect a slower CIN decay rate during shutdown, thus preventing VOUT from exceeding VIN. In applications where there is a greater danger of VOUT exceeding VIN for extended periods of time, it is recommended to place a Schottky diode across VIN to VOUT (connecting the cathode to VIN and anode to VOUT). The Schottky diode forward voltage should be less than 0.45V. where TA = 85°C, under normal ambient conditions TA = 25°C. Given TA = 85°C, the maximum package power dissipation is 211mW. At TA = 25°C, the maximum package power dissipation is 526mW. The maximum continuous output current for the AAT3215 is a function of the package power dissipation and the input-to-output voltage drop across the LDO regulator. Refer to the following simple equation: AAT3215 IOUT(MAX) < PD(MAX) (VIN - VOUT) Thermal Considerations and High Output Current Applications The AAT3215 is designed to deliver a continuous output load current of 150mA under normal operating conditions. The limiting characteristic for the maximum output load current safe operating area is essentially package power dissipation and the internal preset thermal limit of the device. In order to obtain high operating currents, careful device layout and circuit operating conditions need to be taken into account. The following discussions will assume the LDO regulator is mounted on a printed circuit board utilizing the minimum recommended footprint as stated in the Layout Considerations section of this datasheet. At any given ambient temperature (TA), the maximum package power dissipation can be determined by the following equation: For example, if VIN = 5V, VOUT = 3V, and TA = 25°C, IOUT(MAX) < 264mA. If the output load current were to exceed 264mA or if the ambient temperature were to increase, the internal die temperature would increase. If the condition remained constant, the LDO regulator thermal protection circuit would activate. To determine the maximum input voltage for a given load current, refer to the following equation. This calculation accounts for the total power dissipation of the LDO regulator, including that caused by ground current. PD(MAX) = (VIN - VOUT)IOUT + (VIN · IGND) This formula can be solved for VIN to determine the maximum input voltage. VIN(MAX) = PD(MAX) + (VOUT · IOUT) IOUT + IGND The following is an example for an AAT3215 set for a 2.5 volt output: VOUT IOUT IGND = 2.5V = 150mA = 150µA PD(MAX) = TJ(MAX) - TA θJA VIN(MAX) = Constants for the AAT3215 are TJ(MAX), the maximum junction temperature for the device which is 125°C, and ΘJA = 190°C/W, the package thermal resistance. Typically, maximum conditions are calculated at the maximum operating temperature 526mW + (2.5V · 150mA) 150mA + 150μA VIN(MAX) = 6.00V From the discussion above, PD(MAX) was determined to equal 526mW at TA = 25°C. 3215.2006.05.1.6 11 150mA CMOS High Performance LDO Thus, the AAT3215 can sustain a constant 2.5V output at a 150mA load current as long as VIN is ≤ 6.00V at an ambient temperature of 25°C. 6.0V is the absolute maximum voltage where an AAT3215 would never be operated, thus at 25°C, the device would not have any thermal concerns or operational VIN(MAX) limits. This situation can be different at 85°C. The following is an example for an AAT3215 set for a 2.5V output at 85°C: Voltage Drop (V) AAT3215 For a 150mA output current and a 2.7V drop across the AAT3215 at an ambient temperature of 85°C, the maximum on-time duty cycle for the device would be 85.54%. The following family of curves show the safe operating area for duty-cycled operation from ambient room temperature to the maximum operating level. Device Duty Cycle vs. VDROP (VOUT = 2.5V @ 25°C) 3.5 3 2.5 2 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 90 100 VOUT IOUT IGND = 2.5V = 150mA = 150µA 200mA VIN(MAX) = 211mW + (2.5V · 150mA) 150mA + 150μA VIN(MAX) = 3.90V From the discussion above, PD(MAX) was determined to equal 211mW at TA = 85°C. Higher input-to-output voltage differentials can be obtained with the AAT3215, while maintaining device functions within the thermal safe operating area. To accomplish this, the device thermal resistance must be reduced by increasing the heat sink area or by operating the LDO regulator in a duty-cycled mode. For example, an application requires VIN = 4.2V while VOUT = 2.5V at a 150mA load and TA = 85°C. VIN is greater than 3.90V, which is the maximum safe continuous input level for VOUT = 2.5V at 150mA for TA = 85°C. To maintain this high input voltage and output current level, the LDO regulator must be operated in a duty-cycled mode. Refer to the following calculation for duty-cycle operation: IGND = 150µA IOUT = 150mA VIN = 4.2V VOUT = 2.5V Duty Cycle (%) Device Duty Cycle vs. VDROP (VOUT = 2.5V @ 50°C) 3.5 Voltage Drop (V) 3 2.5 2 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 90 100 200mA 150mA Duty Cycle (%) Device Duty Cycle vs. VDROP (VOUT = 2.5V @ 85°C) 3.5 Voltage Drop (V) PD(MAX) %DC = 100 (VIN - VOUT)IOUT + (VIN · IGND) %DC = 100 211mW (4.2V - 2.5V)150mA + (4.2V · 150μA) 3 2.5 2 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 100mA 200mA 150mA %DC = 85.54% PD(MAX) was assumed to be 211mW. 90 100 Duty Cycle (%) 12 3215.2006.05.1.6 150mA CMOS High Performance LDO High Peak Output Current Applications Some applications require the LDO regulator to operate at continuous nominal level with short duration, high-current peaks. The duty cycles for both output current levels must be taken into account. To do so, first calculate the power dissipation at the nominal continuous level, then factor in the additional power dissipation due to the short duration, high-current peaks. For example, a 2.5V system using a AAT3215IGV2.5-T1 operates at a continuous 100mA load current level and has short 150mA current peaks. The current peak occurs for 378µs out of a 4.61ms period. It will be assumed the input voltage is 4.2V. First, the current duty cycle in percent must be calculated: % Peak Duty Cycle: X/100 = 378µs/4.61ms % Peak Duty Cycle = 8.2% The LDO regulator will be under the 100mA load for 91.8% of the 4.61ms period and have 150mA peaks occurring for 8.2% of the time. Next, the continuous nominal power dissipation for the 100mA load should be determined then multiplied by the duty cycle to conclude the actual power dissipation over time. PD(MAX) PD(100mA) PD(100mA) = (VIN - VOUT)IOUT + (VIN · IGND) = (4.2V - 2.5V)100mA + (4.2V · 150µA) = 170.6mW mine the total true power dissipation under the varied load. PD(total) = PD(100mA) + PD(150mA) PD(total) = 156.6mW + 21mW PD(total) = 177.6mW The maximum power dissipation for the AAT3215 operating at an ambient temperature of 85°C is 211mW. The device in this example will have a total power dissipation of 177.6mW. This is well within the thermal limits for safe operation of the device. AAT3215 Printed Circuit Board Layout Recommendations In order to obtain the maximum performance from the AAT3215 LDO regulator, careful consideration should be given to the printed circuit board (PCB) layout. If grounding connections are not properly made, power supply ripple rejection, low output self noise, and transient response can be compromised. Figure 1 shows a common LDO regulator layout scheme. The LDO regulator, external capacitors (CIN, COUT, and CBYP), and the load circuit are all connected to a common ground plane. This type of layout will work in simple applications where good power supply ripple rejection and low self noise are not a design concern. For high performance applications, this method is not recommended. The problem with the layout in Figure 1 is the bypass capacitor and output capacitor share the same ground path to the LDO regulator ground pin, along with the high current return path from the load back to the power supply. The bypass capacitor node is connected directly to the LDO regulator internal reference, making this node very sensitive to noise or ripple. The internal reference output is fed into the error amplifier, thus any noise or ripple from the bypass capacitor will be subsequently amplified by the gain of the error amplifier. This effect can increase noise seen on the LDO regulator output, as well as reduce the maximum possible power supply ripple rejection. There is PCB trace impedance between the bypass capacitor connection to ground and the LDO regulator ground connection. When the high load current returns through this path, a small ripple voltage is created, feeding into the CBYP loop. PD(91.8%D/C) = %DC · PD(100mA) PD(91.8%D/C) = 0.918 · 170.6mW PD(91.8%D/C) = 156.6mW The power dissipation for 100mA load occurring for 91.8% of the duty cycle will be 156.6mW. Now the power dissipation for the remaining 8.2% of the duty cycle at the 150mA load can be calculated: PD(MAX) PD(150mA) PD(150mA) = (VIN - VOUT)IOUT + (VIN · IGND) = (4.2V - 2.5V)150mA + (4.2V · 150mA) = 255.6mW PD(8.2%D/C) = %DC · PD(150mA) PD(8.2%D/C) = 0.082 · 255.6mW PD(8.2%D/C) = 21mW The power dissipation for 150mA load occurring for 8.2% of the duty cycle will be 21mW. Finally, the two power dissipation levels can summed to deter- 3215.2006.05.1.6 13 150mA CMOS High Performance LDO Figure 2 shows the preferred method for the bypass and output capacitor connections. For low output noise and highest possible power supply ripple rejection performance, it is critical to connect the bypass and output capacitor directly to the LDO regulator ground pin. This method will eliminate any load noise or ripple current feedback through the LDO regulator. AAT3215 Evaluation Board Layout The AAT3215 evaluation layout follows the recommend printed circuit board layout procedures and can be used as an example for good application layouts (see Figures 3, 4, and 5). Note: Board layout shown is not to scale. VIN IIN ILOAD VIN EN LDO Regulator GND IGND VOUT BYP DC INPUT CIN CBYP CBYP GND LOOP COUT RLOAD IRIPPLE IBYP + noise GND RTRACE RTRACE RTRACE RTRACE ILOAD return + noise and ripple Figure 1: Common LDO Regulator Layout with CBYP Ripple Feedback Loop. IIN ILOAD VIN EN VIN LDO Regulator GND VOUT BYP DC INPUT CIN IRIPPLE IGND CBYP IBYP only COUT RLOAD GND RTRACE RTRACE RTRACE RTRACE ILOAD return + noise and ripple Figure 2: Recommended LDO Regulator Layout. 14 3215.2006.05.1.6 150mA CMOS High Performance LDO AAT3215 Figure 3: Evaluation Board Component Side Layout. Figure 4: Evaluation Board Solder Side Layout. Figure 5: Evaluation Board Top Side Silk Screen Layout / Assembly Drawing. 3215.2006.05.1.6 15 150mA CMOS High Performance LDO Ordering Information Output Voltage 2.5V 2.6V 2.7V 2.8V 2.85V 2.9V 3.0V 3.1V 3.3V 3.6V 2.5V 2.6V 2.7V 2.8V 2.85V 2.9V 3.0V 3.3V AAT3215 Package SOT23-5 SOT23-5 SOT23-5 SOT23-5 SOT23-5 SOT23-5 SOT23-5 SOT23-5 SOT23-5 SOT23-5 SC70JW-8 SC70JW-8 SC70JW-8 SC70JW-8 SC70JW-8 SC70JW-8 SC70JW-8 SC70JW-8 Marking1 BQXYY GKXYY CHXYY BSXYY CIXYY DVXYY BTXYY GJXYY BUXYY DVXYY BQXYY GKXYY CHXYY BSXYY CIXYY DVXYY BTXYY BUXYY Part Number (Tape and Reel)2 AAT3215IGV-2.5-T1 AAT3215IGV-2.6-T1 AAT3215IGV-2.7-T1 AAT3215IGV-2.8-T1 AAT3215IGV-2.85-T1 AAT3215IGV-2.9-T1 AAT3215IGV-3.0-T1 AAT3215IGV-3.1-T1 AAT3215IGV-3.3-T1 AAT3215IGV-3.6-T1 AAT3215IJS-2.5-T1 AAT3215IJS-2.6-T1 AAT3215IJS-2.7-T1 AAT3215IJS-2.8-T1 AAT3215IJS-2.85-T1 AAT3215IJS-2.9-T1 AAT3215IJS-3.0-T1 AAT3215IJS-3.3-T1 All AnalogicTech products are offered in Pb-free packaging. The term “Pb-free” means semiconductor products that are in compliance with current RoHS standards, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. For more information, please visit our website at http://www.analogictech.com/pbfree. 1. XYY = assembly and date code. 2. Sample stock is generally held on part numbers listed in BOLD. 16 3215.2006.05.1.6 150mA CMOS High Performance LDO Package Information SOT23-5 2.85 ± 0.15 1.90 BSC 0.95 BSC AAT3215 1.575 ± 0.125 1.10 ± 0.20 0.60 REF 2.80 ± 0.20 1.20 ± 0.25 0.15 ± 0.07 4° ± 4° GAUGE PLANE 10° ± 5° 0.40 ± 0.10 0.075 ± 0.075 0.60 REF 0.45 ± 0.15 0.10 BSC SC70JW-8 0.50 BSC 0.50 BSC 0.50 BSC 1.75 ± 0.10 0.225 ± 0.075 2.00 ± 0.20 2.20 ± 0.20 0.048REF 0.85 ± 0.15 1.10 MAX 0.15 ± 0.05 0.100 7 ° ± 3° 0.45 ± 0.10 2.10 ± 0.30 4° ± 4° All dimensions in millimeters. 0.05 ± 0.05 3215.2006.05.1.6 17 150mA CMOS High Performance LDO AAT3215 © Advanced Analogic Technologies, Inc. AnalogicTech cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an AnalogicTech product. No circuit patent licenses, copyrights, mask work rights, or other intellectual property rights are implied. AnalogicTech reserves the right to make changes to their products or specifications or to discontinue any product or service without notice. Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. AnalogicTech warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with AnalogicTech’s standard warranty. Testing and other quality control techniques are utilized to the extent AnalogicTech deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed. AnalogicTech and the AnalogicTech logo are trademarks of Advanced Analogic Technologies Incorporated. All other brand and product names appearing in this document are registered trademarks or trademarks of their respective holders. Advanced Analogic Technologies, Inc. 830 E. Arques Avenue, Sunnyvale, CA 94085 Phone (408) 737-4600 Fax (408) 737-4611 18 3215.2006.05.1.6