APL158115GC-TRL

APL1581 DUAL INPUT LOW DROPOUT REGULATOR Features • • • • • • • • Adjustable or Fixed Output 520mV typ. Dropout at 5A in Dual Power Voltage Mode Remote Sense Pin Available 2% Accuracy Over Temperature Range Build-in Over Temperature Protection Build-in Current Limit 5 Pin TO-220 and TO-263, TO-252, SOP-8-P Packages Lead Free and Green Devices Available (RoHS Compliant) General Description The APL1581 series of high performance positive voltage regulators are designed for use in applications requiring very low dropout voltage at 5Amp. The APL1581 can provide a output voltage at the range of 1.25V to 2.55V where both 5V and 3.3V voltage supplies are available. The superior dropout characteristics result in reducing heat dissipation compared to regular LDOs. The APL1581 also provides excellent regulation over line, load, and temperature variations. Current limit is trimmed to ensure specified output current and controlled short-circuit current. On-chip thermal limiting provides protection against any combination of overload that would create excessive junction temperature. The APL1581 is available in both the through-hole and surface mount versions of the industry standard 5-Pin TO-220 and TO-263, TO-252, SOP-8P power packages. Applications • • • • Microprocessor Supplies Chip Set Supplies VGA Card Power LCD Monitor Power Ordering and Marking Information APL1581 Assembly Material Handling Code Temperature Range Package Code Voltage Code Package Code F : TO-220-5 G : TO-263-5 U :TO-252-5 KA : SOP-8P Temperature Range C : 0 to 70° C Handling Code TR : Tape & Reel Voltage Code : 15 : 1.5V 18 : 1.8V 25 : 2.5V Blank : Adjustable Version Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APL1581-15 F/G/U : 15 APL1581 XXXXX - Date Code XXXXX APL1581 KA : APL1581 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright © ANPEC Electronics Corp. Rev. B.5 - Mar., 2008 1 www.anpec.com.tw APL1581 Pin Configuration 5 4 TAB is VOUT VIN 5 VIN VCNTL VOUT ADJ(or GND) VSENSE VCNTL VOUT ADJ (or GND) VSENSE TAB is VOUT 4 3 2 1 3 2 1 Front View of TO-220-5 5 4 TAB is VOUT 3 2 1 VIN VCNTL VOUT ADJ (or GND) VSENSE Front View of TO-252-5 VSENSE ADJ (or GND) VCNTL VIN 1 2 3 4 8 7 6 5 VOUT VOUT VOUT VOUT SOP-8-P (Top View) NC = No internal connection Front View of TO-263-5 = Thermal Pad (connected to VOUT plane for better heat dissipation) Pin 5~8 must be connected together by a shortest wide track or plane. Pin Description PIN Name VSENSE I/O I Description Positive side of the reference voltage, which allows remote sensing to obtain excellent load regulation. Negative side of the reference voltage, which allows to use resistor divider to set an expect output voltage. A small bypass capacitor can be connected from this pin to ground to improve PSRR performance. For fixed voltage devices this is the bottom of the resistor divider that sets the output voltage. Output pin of the regulator, which connects to the TAB. A minimum of 10µF capacitor must be connected from this pin to ground to ensure the stability. Supply pin of the control circuitry, which must be always higher than VOUT for the device to regulate. (See electrical characteristics) Power input pin of the regulator, which must be always higher than VOUT for the device to regulate. (See electrical characteristics) 2 www.anpec.com.tw ADJ O GND O VOUT VCNTL VIN O I I C opyright © A NPEC Electronics Corp. Rev. B.5 - Mar., 2008 APL1581 Block Diagram VIN VOUT VCNTL Current Limit VSENSE Thermal Protection Voltage Regulation ADJ/GND Absolute Maximum Ratings Symbol VIN VCNTL PD TJ TSTG TSDR Input Voltage Control Voltage Power Dissipation Junction Temperature Storage Temperature Range Parameter (Note 1, 2) Rating 7 7 Internally Limited 150 -65 to +150 260 Unit V V W °C °C °C Maximum Lead Soldering Temperature, 10 Seconds Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: The maximum allowable power dissipation at any TA (ambient temperature) is calculated using: PD (max) = (TJ – TA) / θJA; TJ = 125°C. Exceeding the maximum allowable power dissipation will result in excessive die temperature. Thermal Characteristics Symbol Parameter Junction-to-Ambient Resistance in free air TO-263-5 (Toplayer plane size : 15mm x 15 mm) TO-252-5 (Toplayer plane size : 10mm x 10 mm) SOP-8-P (Toplayer plane size : 10mm x 10 mm) (Note 4) Junction-to-Case Resistance TO-220-5 TO-263-5 TO-252-5 (Note 3) Typical Value Unit θJA 28 42 68 3 4 5 o C/W θJC o C/W Note 3: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The sizes of the rectangular plane, where the devices are mounted, are shown in the table. Note 4: The case temperature is measured on the TAB of the device mounted on the test board described in Note 3 except the package TO-220-5. The case temperature of the TO-220-5 is measured on the bottom of the case directly below the die. C opyright © A NPEC Electronics Corp. Rev. B.5 - Mar., 2008 3 www.anpec.com.tw APL1581 Electrical Characteristics Unless otherwise noted , these specifications apply over CIN = 1 0µF, CCNTL = 1µF, COUT = 10µF, and TA = 0 to 70°C. Typical values refer to TA = 25°C. VOUT = VSENSE. Symbol VREF Parameter Test Conditions MIN 1.225 1.470 1.764 2.450 APL1581 TYP 1.250 1.500 1.800 2.500 MAX 1.275 1.530 1.836 2.550 UNIT VOUT Reference Voltage APL1581 Output Voltage APL1581-15 APL1581-18 APL1581-25 Line Regulation APL1581 APL1581-15 APL1581-18 APL1581-25 Load Regulation (Note 5) APL1581 APL1581-15 APL1581-18 APL1581-25 Dropout Voltage (Note 6) APL1581 APL1581-15 APL1581-18 APL1581-25 Dropout Voltage (Note 6) APL1581 APL1581-15 APL1581-18 APL1581-25 Current Limit Minimum Load Current (Note7) REGLINE REGLOAD VCNTL-VOUT VIN-VOUT ILIMIT ILMIN REGTHERMAL VCNTL=2.75~5.5V, VIN=2.05~5.5V, IO =10mA~5A, VADJ=0V (IO =0~5A for fixed versions) VCNTL=3~5.5V , VIN=2.3~5.5V VCNTL=3.3~5.5V , VIN=2.6~5.5V VCNTL=4~5.5V , VIN=3.3~5.5V (IO =0A for fixed versions) VCNTL=2.75~5.5V, VIN=1.75~5.5V, IO =10mA, VADJ=0V VCNTL=3~5.5V, VIN=2.3~5.5V VCNTL=3.3~5.5V, VIN=2.6~5.5V VCNTL=4~5.5V, VIN=3~5.5V (IO =0~5A for fixed versions) VCNTL=2.75V, VIN=2.1V, VADJ =0V, IO =10mA~5A VCNTL=3V, VIN=2.35V VCNTL=3.3V, VIN=2.65V VCNTL=4V, VIN=3.35V IO =5A for all versions VIN=2.05V, VADJ =0V VIN=2.3V VIN=2.6V VIN=3.3V IO =5A for all versions VCNTL=2.75V, VADJ =0V VCNTL=3V VCNTL=3.3V VCNTL=4V VCNTL-VOUT=1.5V, VIN-VOUT=0.6V VCNTL=5V, VIN=3.3V, VADJ =0V 30ms Pulse VRIPPLE=1VPP at 120Hz, IO=5A VCNTL=5V, VIN=5V, VADJ =0V VCNTL=5.25V, VIN=5.25V VCNTL=5.55V, VIN=5.55V VCNTL=6.25V, VIN=6.25V VCNTL-VOUT=1.5V, VIN-VOUT=0.8V, IO =5A VCNTL =3V, VIN =2.3V VCNTL =3.3V, VIN =2.6V VCNTL =4V, VIN =3.3V VCNTL=2.75V, VIN=2.05V , VADJ =0V V V 3 mV 5 mV 1.20 1.35 V 0.52 0.75 V 5 0.8 0.01 10 A mA %/W PSRR APL1581 Thermal Regulation Power Supply Ripple Rejection APL1581 APL1581-15 APL1581-18 APL1581-25 CNTL Pin Current Ground Pin Current APL1581-15 APL1581-18 APL1581-25 Adjust Pin Current APL1581 60 70 dB ICNTL 45 120 mA IGND 8 13 mA IADJ 50 120 µA Note 5 : Low duty cycle pulse test with Kelvin connections are required to maintain data accuracy . Note 6 : Dropout voltage is defined as the minimum difference between VIN and VOUT required to maintain 1% VOUT regulation. Note 7 : Minimum load current is defined as the minimum current required at the output to maintain VOUT regulation. C opyright © A NPEC Electronics Corp. Rev. B.5 - Mar., 2008 4 www.anpec.com.tw APL1581 Application Circuit (1) Adjustable Output Voltage Device VIN +3.3V VIN VOUT APL1581 (Adj.) VOUT +2.5V/5A VCNT L +5V CCNTL 10uF VCNTL VSENSE ADJ V REF R1 120 COUT 470uF CIN 100uF R2 120 GND GND * VOUT = VREF ( 1+ R2 / R1 ) + IADJ * R2 where VREF =1.25V (typical) IADJ=50µA (typical) * R1 is typically in range of 100Ω to 125Ω to satisfy the minimum load current requirement. (2) Fixed Output Voltage Device V IN +3.3V VIN VOUT APL1581-25 V OUT +2.5V/5A V CNT L +5V CCNTL 10uF VCNTL VSENSE GND COUT 470uF CIN 100uF GND GND (3) With Enable Control Application VIN +3.3V Q1 VIN VOUT APL1581 (Adj.) VOUT +2.5V/5A VCNT L +5V VCNTL 10k Q2 10k CCNTL 10uF CIN 100uF VSENSE ADJ V REF R1 120 COUT 470uF Enable R2 120 GND Q1 : APM2301A Q2 : APM2300A GND C opyright © A NPEC Electronics Corp. Rev. B.5 - Mar., 2008 5 www.anpec.com.tw APL1581 Typical Characteristics Reference Voltage vs. Junction Temperature 1.275 1.270 Adjust Pin Current vs. Junction Temperature 80 70 Reference Voltage (V) 1.265 1.260 1.255 1.250 1.245 1.240 1.235 1.230 1.225 -50 -25 0 25 50 75 100 125 150 Adjust Pin Current (uA) 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 150 Junction Temperature (°C) Junction Temperature (°C) Minimum Load Current vs. Junction Temperature 1 .2 VIN-VOUT Dropout Voltage vs. Output Current 700 VIN-VOUT Dropout Voltage (mV) Minimum Load Current (mA) 1 .0 600 500 400 300 TJ=125°C VCNTL-VOUT=10.75V 0 .8 VCNTL-VOUT=1.45V 0 .6 TJ=25°C 0 .4 TJ=-50°C 200 100 0 0 .2 0 .0 -5 0 -25 0 2 5 5 0 7 5 100 125 150 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Junction Temperature (°C) Output Current (A) C opyright © A NPEC Electronics Corp. Rev. B.5 - Mar., 2008 6 www.anpec.com.tw APL1581 Typical Characteristics Short-Circuit Current vs. Junction Temperature 1 4 VCONTROL-VOUT Dropout Voltage vs. Output Current 1.4 VCNTL-VOUT Dropout Voltaage (V) VIN=5.0V TJ=-50°C 1.3 1.2 1.1 1.0 0.9 Short-Circuit Current (A) 1 2 1 0 TJ=0°C VIN=3.3V 8 6 4 2 0 -5 0 TJ=25°C TJ=125°C 0.8 0.7 -2 5 0 2 5 5 0 7 5 10 0 15 2 10 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Junction Temperature (°C) Output Current (A) Control Pin Current vs. Output Current VIN-VOUT=0.6V 160 Control Pin Current vs. Output Current VIN-VOUT=0.8V 80 VCNTL Pin Current (mA) VCNTL Pin Current (mA) 140 120 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 TJ=125°C 70 60 50 40 30 20 10 0 TJ=-50°C TJ=0°C TJ=25°C TJ=75°C TJ=25°C TJ=0°C TJ=-50°C TJ=75°C TJ=125°C 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Output Current (A) Output Current (A) C opyright © A NPEC Electronics Corp. Rev. B.5 - Mar., 2008 7 www.anpec.com.tw APL1581 Typical Characteristics Control Pin Current vs. Output Current VIN-VOUT=1.0V 80 70 Control Pin Current vs. Output Current VIN-VOUT=4.25V 70 TJ=-50°C TJ=0°C TJ=25°C TJ=75°C VCNTL Pin Current (mA) 60 50 40 30 20 VCNTL Pin Current (mA) 60 50 40 TJ=-50°C TJ=0°C TJ=25°C TJ=75°C 30 20 10 0 TJ=125°C 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 TJ=125°C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Output Current (A) Output Current (A) Application Information General The APL1581 (adjustable or fixed) regulator is a 5 terminal device designed specifically to provide extremely low dropout voltages comparable to the PNP type without the disadvantage of the extra power dissipation due to the base current associated with PNP regulators. This is done by bringing out the control pin of the regulator that provides the base current to the power NPN and connecting it to a voltage that is greater than the voltage present at the VIN pin. This flexibility makes APL1581 ideal for applications where dual inputs are available, such as a computer motherboard with an ATX power supply that provides 5V and 3.3V to the board. APL1581 is equipped with a 1.25V reference, precision and fast voltage regulations, on-chip current and thermal limits, and remote sensing capability to reduce system total cost. C opyright © A NPEC Electronics Corp. Rev. B.5 - Mar., 2008 8 APL1581 is available in SOP-8P, TO-252-5, TO-263-5, and TO-220-5 packages to meet different power dissipation applications. Output Voltage Setting See Figure 1 Adjustable APL1581 develops a 1.25V reference voltage between the VSENSE pin and the ADJ pin. Placing a resistor between these two terminals causes a constant current to flow through R1 and down through R2 to set the overall output voltage. In general, R1 is chosen so that this current is the specified minimum load current of 10mA.The current out of the ADJ pin is small, typically 50µA and itadds to the current from R1. Because IADJ is very small, it needs to be considered only when very precise output voltage setting is required. For best regulation, the top of the resistor divider should be connected directly to the SENSE pin. The adjustable APL1581 can be pro- www.anpec.com.tw APL1581 Application Information (Cont.) Output Voltage Setting (Cont.) grammable to any voltages in the range of 1.25V to 5.5V according to the following formula: VIN VOUT VIN VOU T APL1581 regardless of whether they are inside or outside the regulation loop. VOUT = VREF x (1+ R2 ) + IADJ x R2 R1 VCNTL VCN TL VSENSE AD J R1 Load where VREF = 1.25V (typical) IADJ = 50µA (typical) The recommended R1 is in range of 100Ω to125Ω to satisfy the minimum load current requirement. Proper sizes of R2 and R1 are also concerned for power dissipation. VCNTL VIN VIN VOU T APL1581 VCN TL VSENSE GN D Load Adjustable Device R2 RP VOUT VIN VCNT L VIN VOU T APL1581 VOUT Fixed Voltage Device VCNTL VSENSE AD J VRE F R1 RP IA DJ=50uA Figure 2 Remote Voltage Sensing R2 Stability and Output Capacitors Figure 1 Setting Output Voltage The circuit design of using the APL1581 series requires an output capacitor as part of the device frequency compensation. The following chart shows a stable region to select output capacitor for APL1581. This region above the curve indicates minimum required ESR and capacitance to maintain stability. However, the output capacitor should have an ESR less than1Ω. 100 80 60 40 20 0 1 10 100 Capacitance(µF) 1000 ESR (m Ω ) ESR (m Ω ) Grounding and Output Sensing The APL1581 allows true Kelvin sensing for both the high and low side of the load. Figure 2 shows the device connected to take advantage of the remote sense feature. The SENSE pin and the top of the resistor divider are connected to the top of the load; the bottom of the resistor divider is connected to the bottom of the load. Typically the load is a microprocessor and parasitic resistance RP is made up of the PC traces and /or connector resistance between the regulator and the processor. RP is now connectedinside the regulation loop of the APL1581 and for reasonable values of RP the load regulation at the load will be negligible. Voltage drops due to RP are not eliminated; they will add to the dropout voltage of the regulator C opyright © A NPEC Electronics Corp. Rev. B.5 - Mar., 2008 9 Stable Region www.anpec.com.tw APL1581 Application Information (Cont.) Stability and Output Capacitors (Cont.) A low-ESR solid tantalum and aluminum electrolytic capacitor (ESR33µF) is recommended. It is not necessary to use low-ESR capacitors. More capacitance reduces the variations of the input voltage at VIN pin. Layout and Thermal Consideration The APL1581 series have internal power and thermal limiting (TJ=150oC typical) circuitry designed to protect the device under overload conditions. However, maximum junction temperature ratings should not be C opyright © A NPEC Electronics Corp. Rev. B.5 - Mar., 2008 10 www.anpec.com.tw S o l d e ri n g a re a (1 4 0 m i l x 110mil) for bottom p a d 1 2 3 4 Vias Vias 8 7 6 5 exceeded under continuous normal load conditions. Careful consideration must be given to all sources of thermal resistance from junction to ambient, including junction-to-case, case-to-heat sink interface, and heat sink resistance itself. See Figure 3 The SOP-8P is a cost-effective package featuring a small size as a standard SOP-8 and a bottom thermal pad to minimize the thermal resistance of the package, being applicable to high current applications. The thermal pad is soldered to the top VOUT plane which may be connected to internal or bottom VOUT plane by vias to reduce the heat sink thermal resistance. Therefore, the printed circuit board (PCB) forms a heat sink and dissipates heat into ambient air. Top layer VOUT plane for Heat Dissi p a t i o n (L a rg e r a re a i s better) C OUT Load CCNTL C IN Figure 3 Recommended SOP-8P Layout APL1581 Package Information TO-220-5 D Q R b E e e1 H1 L A F c J1 Dim A b c D e e1 E F H1 J1 L R Q Millimeters Min. 3.55 0.63 0.35 14.22 1.57 6.68 9.65 1.14 5.84 2.03 13.72 3.53 2.54 Max. 4.83 1.02 0.56 16.51 1.83 6.94 10.67 1.40 6.60 3.05 14.22 4.09 3.43 Min. 0.140 0.025 0.014 0.560 0.062 0.263 0.380 0.045 0.230 0.080 0.540 0.139 0.100 Inches Max. 0.190 0.040 0.022 0.650 0.072 0.273 0.420 0.055 0.260 0.120 0.560 0.161 0.135 C opyright © A NPEC Electronics Corp. Rev. B.5 - Mar., 2008 11 www.anpec.com.tw APL1581 Package Information TO-263-5 A E L1 c2 E1 D b e H c SEE VIEW A 0 GAUGE PLANE 0.25 SEATING PLANE A1 L VIEW A S Y M B O L A A1 b c c2 D D1 E E1 e H L L1 0 TO-263-5 MILLIMETERS MIN. 4.06 0.00 0.51 0.38 1.14 8.38 6.00 9.65 6.22 1.70 BSC 14.61 1.78 15.88 2.79 1.68 0o 8o 0 o INCHES MAX. 4.83 0.25 0.99 0.74 1.65 9.65 9.00 11.43 9.00 MIN. 0.160 0.000 0.020 0.015 0.045 0.330 0.236 0.380 0.245 0.067 BSC 0.575 0.070 0.625 0.110 0.066 8o MAX. 0.190 0.010 0.039 0.029 0.065 0.380 0.354 0.450 0.354 Note : Follow from JEDEC TO-263 BB. C opyright © A NPEC Electronics Corp. Rev. B.5 - Mar., 2008 12 www.anpec.com.tw D1 APL1581 Packaging Information TO-252-5 E b3 A c2 E1 L3 D c b e SEE VIEW A H GAUGE PLANE 0.25 A1 L VIEW A SEATING PLANE S Y M B O L A A1 b b3 c c2 D D1 E E1 e H L L3 0 TO-252-5 MILLIMETERS MIN. 2.18 MAX. 2.39 0.13 0.50 4.32 0.46 0.46 5.33 4.57 6.35 3.81 1.27 BSC 9.40 1.40 0.89 0° 10.41 1.78 2.03 8° 0.370 0.055 0.035 0° 0.89 5.46 0.61 0.89 6.22 6.00 6.73 6.00 0.020 0.170 0.018 0.018 0.210 0.180 0.250 0.150 0.050 BSC 0.410 0.070 0.080 8° MIN. 0.086 INCHES MAX. 0.094 0.005 0.035 0.215 0.024 0.035 0.245 0.236 0.265 0.236 C opyright © A NPEC Electronics Corp. Rev. B.5 - Mar., 2008 13 www.anpec.com.tw D1 0 APL1581 Packaging Information SOP-8-P D SEE VIEW A D1 THERMAL PAD E2 E1 E e b h X 45 ° c 0.25 GAUGE PLANE SEATING PLANE VIEW A 0 A2 A1 A L S Y M B O L A A1 A2 b c D D1 E E1 E2 e h L 0 SOP-8P MILLIMETERS MIN. MAX. 1.60 0.00 1.25 0.31 0.17 4.80 2.25 5.80 3.80 2.00 1.27 BSC 0.25 0.40 0o 0.50 1.27 8o 0.010 0.016 0o 0.51 0.25 5.00 3.50 6.20 4.00 3.00 0.15 0.000 0.049 0.012 0.007 0.189 0.098 0.228 0.150 0.079 0.050 BSC 0.020 0.050 8o 0.020 0.010 0.197 0.138 0.244 0.157 0.118 MIN. INCHES MAX. 0.063 0.006 Note : 1. Follow JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. C opyright © A NPEC Electronics Corp. Rev. B.5 - Mar., 2008 14 www.anpec.com.tw APL1581 Carrier Tape & Reel Dimensions OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B d Application A H H A T1 3 81.0 ± 2.00 6 0 MIN. T O-263-5 P0 4 .0 ± 0.10 A pplication A P1 1 6.0 ± 0.10 H 3 30.0 ± 2.00 5 0 MIN. T O-252-5 P0 4 .0 ± 0.10 A pplication A P1 8 .0 ± 0.10 H 3 30.0 ± 2.00 5 0 MIN. S OP-8-P P0 4 .0 ± 0.10 P1 8 .0 ± 0.10 T1 C 2 4.4+2.00 1 3.0+0.50 - 0.00 - 0.20 P2 D0 1.5+0.10 2 .0 ± 0.10 - 0.00 T1 C 1 6.4+2.00 1 3.0+0.50 - 0.00 - 0.20 P2 D0 1.5+0.10 2 .0 ± 0.05 - 0.00 T1 C 1 2.4+2.00 1 3.0+0.50 - 0.00 - 0.20 P2 D0 1.5+0.10 2 .0 ± 0.05 - 0.00 d 1 .5 MIN. D1 1 .5 MIN. d 1 .5 MIN. D1 1 .5 MIN. d 1 .5 MIN. D1 1 .5 MIN. D 2 0.2 MIN. T 0 .6+0.00 - 0.40 D 2 0.2 MIN. T 0 .6+0.00 - 0.40 D 2 0.2 MIN. T 0 .6+0.00 - 0.40 W W E1 F 2 4.0 ± 0.30 1 .75 ± 0.10 11.5 ± 0.10 A0 B0 K0 1 0.8 ± 0.20 1 6.1 ± 0.20 5 .2 ± 0.20 W E1 F 1 6.0 ± 0.30 1 .75 ± 0.05 0.10 7 .50 ± A0 6 .80 ± 0.20 W B0 K0 1 0.40 ± 2.50 ± 0.20 0.20 E1 F 5 .5 ± 0.05 K0 1 2.0 ± 0.30 1 .75 ± 0.10 A0 B0 6 .40 ± 0.20 5 .20 ± 0.20 2 .10 ± 0.20 ( mm) C opyright © A NPEC Electronics Corp. Rev. B.5 - Mar., 2008 15 www.anpec.com.tw APL1581 Devices Per Unit Package Type TO-252-5 TO-263-5 SOP-8-P Unit Tape & Reel Tape & Reel Tape & Reel Quantity 2500 1000 2500 Reflow Condition (IR/Convection or VPR Reflow) TP tp Critical Zone TL to TP Ramp-up TL Temperature tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25°C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 sec 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA C opyright © A NPEC Electronics Corp. Rev. B.5 - Mar., 2008 16 www.anpec.com.tw APL1581 Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Time 25°C to Peak Temperature Sn-Pb Eutectic Assembly 3°C/second max. 100°C 150°C 60-120 seconds 183°C 60-150 seconds See table 1 10-30 seconds 6°C/second max. 6 minutes max. Pb-Free Assembly 3°C/second max. 150°C 200°C 60-180 seconds 217°C 60-150 seconds See table 2 20-40 seconds 6°C/second max. 8 minutes max. Note: All temperatures refer to topside of the package. Measured on the body surface. Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures Package Thickness