APL3206AQBI-TRG

APL3206/A Li+ Charger Protection IC with Integrated P-MOSFET Features • • • • • • • • Input Over-Voltage Protection Input Over-Current Protection Battery Over-Voltage Protection High Immunity of False Triggering High Accuracy Protection Threshold A Built-In P-MOSFET Thermal Shutdown Protection Compliance to IEC61000-4-2 (Level 4) ± 8kV (Contact Discharge) ± 15kV (Air Discharge) General Description The APL3206/A provides complete Li+ charger protection against input over-voltage, input over-current, and battery over-voltage. When any of the monitored parameters are over the threshold, the IC removes the power from the charging system by turning off an internal switch. All protections also have deglitch time against false triggering due to voltage spikes or current transients. The APL3206/A integrates a P-MOSFET with the body diode reverse protection to replace the external P-MOSFET and Schottky diode for charger function of cell phone’ s PMIC. When the CHRIN voltage drops below VBAT+20mV, the internal power select circuit will reverse the body diode’ terminal to prevent a reverse current flowing from s the battery back to CHRIN pin. The APL3206/A provides complete Li+ charger protections and saves the external MOSFET and Schottky diode for the charger of cell phone’ PMIC. The above features s and small package make the APL3206/A an ideal part for cell phones applications. • • Available in a TDFN2x2-8 and TSOT-23-6A Packages Lead Free and Green Devices Available (RoHS Compliant) Applications • Cell Phones Pin Configuration ACIN 1 8 OUT 7 OUT EP 6 CHRIN 5 GATDRV TDFN2x2-8 (Top View) EP PMIC GATDRV ISENS Simplified Application Circuit 5V Adapter or USB ACIN CHRIN CHRIN ACIN 2 GND 3 VBAT 4 APL3206/A GATDRV OUT = Exposed Pad (connected to ground plane for better heat dissipation) OUT 1 GND VBAT Li+ Battery VBAT 6 VIN 5 GND 4 VBAT TSOT-23-6A (Top View) CHRIN 2 GATDRV 3 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. C opyright © A NPEC Electronics Corp. Rev. A.3 - Jul., 2009 1 www.anpec.com.tw APL3206/A Ordering and Marking Information APL3206 APL3206A Assembly Material Handling Code Temperature Range Package Code L06 X L6A X L06X L6AX Package Code QB : TDFN2x2-8 CT : TSOT-23-6A Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device X - Date Code APL3206 QB: APL3206A QB: APL3206 CT: APL3206A CT: X - Date Code X - Date Code X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Symbol VACIN VCHRIN VGATDRV VBAT VOUT IOUT TJ TSTG TSDR CHRIN to GND Voltage GATDRV to GND Voltage VBAT to GND Voltage OUT to GND Voltage OUT Output Current Maximum Junction Temperature Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds Parameter ACIN Input Voltage (ACIN to GND) Rating -0.3 ~ 30 -0.3 ~ 7 -0.3 ~ VCHRIN -0.3 ~ 7 -0.3 ~ 7 1.5 150 -65 ~ 150 260 Unit V V V V V A o o o C C C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristic Symbol θJA Parameter Junction-to-Ambient Resistance in Free Air (Note 2) TDFN2x2-8 TSOT-23-6A 80 235 o Typical Value Unit C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of TDFN2x2-8 is soldered directly on the PCB. C opyright © A NPEC Electronics Corp. Rev. A.3 - Jul., 2009 2 www.anpec.com.tw APL3206/A Recommended Operating Conditions (Note 3) Symbol VACIN IOUT TA TJ ACIN Input Voltage Output Current Ambient Temperature Junction Temperature Parameter Range 4.5 ~ 5.5 0 ~ 700 -40 ~ 85 -40 ~ 125 Unit V mA o o C C Note 3: Refer to the typical application circuit Electrical Characteristics Unless otherwise specified, these specifications apply over VACIN=5V, VBAT=3.8V and TA= -40 ~ 85 oC. Typical values are at TA=25oC. Symbol Parameter Test Conditions Min. ACIN INPUT CURRENT AND POWER-ON-RESET (POR) IACIN VACIN TB(ACIN) ACIN Supply Current ACIN POR Threshold ACIN POR Hysteresis ACIN Power-On Blanking Time INTERNAL SWITCH ON RESISTANCE ACIN to OUT On Resistance CHRIN Discharge On Resistance INPUT OVER-VOLTAGE PROTECTION (OVP) VOVP Input OVP Threshold Input OVP Hysteresis Input OVP Propagation Delay TON(OVP) Input OVP Recovery Time OVER-CURRENT PROTECTION (OCP) IOCP TB(OCP) OCP Threshold OCP Blanking Time 1 VBAT rising VBAT = 4.4V 4.32 220 176 64 4.35 270 176 1.5 4.38 320 20 A µs ms V mV nA µs VACIN rising APL3206 APL3206A 6 6.6 200 6.17 6.8 300 8 6.35 7 400 1 V mV µs ms IOUT=0.7A 0.5 500 Ω Ω IOUT=0A, ICHRIN=0A VACIN rising 2.4 200 250 250 8 350 2.8 300 µA V mV ms APL3206/A Typ. Max. Unit TON(OCP) OCP Recovery Time BATTERY OVER-VOLTAGE PROTECTION VBOVP IVBAT Battery OVP Threshold Battery OVP Hysteresis VBAT Pin Leakage Current TB(BOVP) Battery OVP Blanking Time INTERNAL P-MOSFET (CHRIN, OUT, AND GATDRV PINS) VCHRIN-VBAT Lockout Threshold OUT Input Current GATDRV Leakage Current OUT Leakage Current VCHRIN from low to high, P-MOSFET is controlled by GATDRV VCHRIN from high to low, P-MOSFET is off VCHRIN=0V, VOUT=4.2V, GATDRV=GND VACIN=VCHRIN= VOUT=5V, VGATDRV=0V VACIN=VCHRIN= VGATDRV =5V, VOUT=0V - 150 20 - 1 1 1 mV µA µA µA C opyright © A NPEC Electronics Corp. Rev. A.3 - Jul., 2009 3 www.anpec.com.tw APL3206/A Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VACIN=5V, VBAT=3.8V and TA= -40 ~ 85 oC. Typical values are at TA=25oC. Symbol Parameter Test Conditions Min. INTERNAL P-MOSFET (CHRIN, OUT, AND GATDRV PINS) (CONT.) P-MOSFET Input Capacitance GATDRV Input Resistance OVER-TEMPERATURE PROTECTION (OTP) TOTP Over-Temperature Threshold Over-Temperature Hysteresis TJ rising 160 40 °C °C 200 15 pF Ω APL3206/A Typ. Max. Unit C opyright © A NPEC Electronics Corp. Rev. A.3 - Jul., 2009 4 www.anpec.com.tw APL3206/A Typical Operating Characteristics Input OVP Threshold vs. Junction Temperature 6.25 OCP Threshold vs. Junction Temperature 1.30 Input OVP Threshold, VOVP (V) 6.15 6.05 5.95 5.85 5.75 5.65 -50 -25 0 25 50 75 100 125 VACIN Increasing OCP Threshold, IOCP (A) 1.25 1.20 1.15 1.10 VACIN Decreasing 1.05 1.00 -50 -25 0 25 50 75 100 125 Junction Temperature ( oC) Junction Temperature (oC) Battery OVP Threshold vs. Junction Temperature ACIN to OUT On Resistance, RDS,ON (mΩ) 4.40 1000 900 800 700 600 500 400 300 -50 ACIN to OUT On Resistance vs. Junction Temperature Battery OVP Threshold, VBOVP (V) 4.35 4.30 4.25 4.20 4.15 4.10 4.05 4.00 -50 -25 0 25 50 75 100 125 VBAT Decreasing VBAT Increasing ACIN to OUT On Resistance -25 0 25 50 75 100 125 Junction Temperature (oC) Junction Temperature ( oC) ACIN Supply Current vs. Junction Temperature 350 POR Threshold vs. Junction Temperature 2.8 VACIN Increasing 2.7 2.6 2.5 2.4 VACIN Decreasing 2.3 ACIN Supply Current, IACIN (µA) 300 250 200 150 -50 -25 0 25 50 75 100 125 POR Threshold, VPOR (V) 2.2 -50 -25 0 25 50 75 100 125 Junction Temperature (oC) Junction Temperature (oC) C opyright © A NPEC Electronics Corp. Rev. A.3 - Jul., 2009 5 www.anpec.com.tw APL3206/A Operating Waveforms The test condition is VACIN=5V, VBAT=3.8V, CACIN=1µF, CCHRIN=1µF, TA= 25oC unless otherwise specified. Normal Power On OVP at Power On VACIN 1 VOUT VACIN 1 VCHRIN 2 VCHRIN 2,3 VOUT IOUT 4 3 VGATDRV = VCHRIN CH1: VACIN, 5V/Div, DC CH2: VOUT, 2V/Div, DC CH3: VCHRIN, 2V/Div, DC CH4: IOUT, 0.2A/Div, DC TIME: 2ms/Div VACIN = 0 to 12V, VGATDRV = VCHRIN CH1: VACIN, 10V/Div, DC CH2: VCHRIN, 2V/Div, DC CH3: VOUT, 2V/Div, DC TIME: 2ms/Div Input Over-Voltage Protection Recovery from Input OVP VACIN VACIN 1 VCHRIN 1 VCHRIN 2 2 VACIN =5V to 12V CH1: VACIN, 5V/Div, AC CH2: VCHRIN, 2V/Div, DC TIME:20µs/Div VACIN= 12V to 5V CH1: VACIN, 5V/Div, AC CH2: VCHRIN, 2V/Div, DC TIME: 2ms/Div C opyright © A NPEC Electronics Corp. Rev. A.3 - Jul., 2009 6 www.anpec.com.tw APL3206/A Operating Waveforms (Cont.) The test condition is VACIN=5V, VBAT=3.8V, CACIN=1µF, CCHRIN=1µF, TA= 25oC unless otherwise specified. Battery Over-Voltage Protection VBAT Battery Over-Voltage Protection VBAT 1 VCHRIN 1 VCHRIN 2 2 VBAT = 3.6V to 4.4V to 3.6V CH1: VBAT, 2V/Div, AC CH2: VCHRIN, 2V/Div, DC TIME: 50ms/Div VBAT = 3.6V to 4.4V CH1: VBAT, 2V/Div, DC CH2: VCHRIN, 2V/Div, DC TIME: 200µs/Div Over-Current Protection Over-Current Protection VCHRIN VACIN 1 VCHRIN 1 2 VOUT 2 VOUT IOUT IOUT 3 3 ROUT=2.5Ω, VBAT = 0V, VGATDRV=0V CH1: VACIN, 5V/Div, DC CH2: VCHRIN, 5V/Div, DC CH3: VOUT, 5V/Div, DC CH4: IOUT, 1A/Div, DC TIME: 200ms/Div Note: OUT pin connected with a resistor to ground. ROUT=10Ω to 2.4Ω, VBAT = 0V, VGATDRV=0V CH1: VCHRIN, 2V/Div, DC CH2: VOUT, 2V/Div, DC CH3: IOUT, 0.5A/Div, DC TIME: 100µs/Div Note: OUT pin connected with a resistor to ground. C opyright © A NPEC Electronics Corp. Rev. A.3 - Jul., 2009 7 www.anpec.com.tw APL3206/A Pin Description PIN NO. 1 2 3 4 5 6 7 8 NAME ACIN ACIN GND VBAT GATDRV CHRIN OUT OUT EP Exposed Thermal Pad. Must be electrically connected to the GND pin. Power Supply Input. Connect this pin to external DC supply. Bypass to GND with a 1µF (minimum) ceramic capacitor. Ground Terminal. Battery Voltage Sense Input. Connect this pin to pack positive terminal through a resistor. Internal P-MOSFET Gate Input. Output Pin. This pin provides supply voltage to the PMIC input. Bypass to GND with a 1µF (minimum) ceramic capacitor. Output Pins. These pins provide supply source current in series with a resistor to battery. FUNCTION Block Diagram ACIN CHRIN POR OUT Charge Pump OCP ACIN OVP Gate Driver and Control Logic 0.5V VBAT OVP 1V GATDRV GND Thermal Shutdown VBAT C opyright © A NPEC Electronics Corp. Rev. A.3 - Jul., 2009 8 www.anpec.com.tw APL3206/A Typical Application Circuit 5V Adapter/USB 1, 2 CACIN 1µF ACIN CHRIN 6 CCHRIN 1 µF 5 7, 8 OUT 3 GND VBAT 0.2Ω 4 RBAT 200kΩ Li+ Battery VBAT CHRIN APL3206/A GATDRV PMIC GATDRV ISENS Designation CACIN CCHRIN Description 1µF, 25V, X5R, 0603 Murata GRM188R61E105K 1µF, 10V, X5R, 0603 Murata GRM188R61A105K Murata website: www.murata.com C opyright © A NPEC Electronics Corp. Rev. A.3 - Jul., 2009 9 www.anpec.com.tw APL3206/A Function Description ACIN Power-On-Reset (POR) The APL3206/A has a built-in power-on-reset circuit to keep the output shutting off until internal circuitry is operating properly. The POR circuit has hysteresis and a deglitch feature so that it will typically ignore undershoot transients on the input. When input voltage exceeds the POR threshold and after 8ms blanking time, the output voltage starts a soft-start to reduce the inrush current. ACIN Over-Voltage Protection (OVP) The input voltage is monitored by the internal OVP circuit. When the input voltage rises above the input OVP threshold, the internal FET will be turned off within 1ms to protect connected system on OUT pin. When the input voltage returns below the input OVP threshold minus the hysteresis, the FET is turned on again after 8ms recovery time. The input OVP circuit has a 300mV hysteresis and a recovery time of TON(OVP) to provide noise immunity against transient conditions. Over-Current Protection (OCP) The output current is monitored by the internal OCP circuit. When the output current reaches the OCP threshold, the device limits the output current at OCP threshold level. If the OCP condition continues for a blanking time of TB(OCP), the internal power FET is turned off. After the recovery time of TON(OCP), the FET will be turned on again. The APL3206/A has a built-in counter. When the total count of OCP fault reaches 16, the FET is turned off permanently, requiring a VACIN POR again to restart. Battery Over-Voltage Protection The APL3206/A monitors the VBAT pin voltage for battery over-voltage protection. The battery OVP threshold is internally set to 4.35V. When the VBAT pin voltage exceeds the battery OVP threshold for a blanking time of TB(BOVP), the internal power FET is turned off. When the VBAT voltage returns below the battery OVP threshold minus the hysteresis, the FET is turned on again. The APL3206/A has a built-in counter. When the total count of battery OVP fault reaches 16, the FET is turned off permanently, requiring a VACIN POR again to restart. Over-Temperature Protection When the junction temperature exceeds 160oC, the internal thermal sense circuit turns off the power FET and allows the device to cool down. When the device’ juncs tion temperature cools by 40 oC, the internal thermal sense circuit will enable the device, resulting in a pulsed output during continuous thermal protection. Thermal protection is designed to protect the IC in the event of over temperature conditions. For normal operation, the junction temperature cannot exceed TJ=+125oC. Internal P-MOSFET The APL3206/A integrates a P-channel MOSFET with the body diode reverse protection to replace the external PMOSFET and Schottky diode for cell phone’ PMIC. The s body diode reverse protection prevents a reverse current flowing from the battery back to CHRIN pin. During poweron, when CHRIN voltage rises above the VBAT voltage by more than 150mV, the body diode of the P-channel MOSFET is forward biased from OUT to CHRIN, and PMOSFET is controlled by the external GATDRV voltage. When the CHRIN voltage drops below VBAT+20mV, the body diode of the P-channel MOSFET is forward biased from CHRIN to OUT and P-channel MOSFET is turned off. When any of input OVP, OCP, battery OVP, is detected, the internal P-channel MOSFET is also turned off. ESD Tests The APL3206/A VIN input pin fully supports the IEC610004-2. That means the VIN pin has immunity of ±15kV ESD discharge in Air condition, and immunity of ±8kV ESD discharge in Contact condition. C opyright © A NPEC Electronics Corp. Rev. A.3 - Jul., 2009 10 www.anpec.com.tw APL3206/A Function Description (Cont.) VOVP VPOR VACIN VCHRIN -VBAT = 150mV VCHRIN -VBAT = 150mV VCHRIN VOUT GATDRV is pulled low P-MOS Gate Control Turn Off Internal P-MOSFET TB(ACIN) Controlled by GATDRV Turn Off Internal P-MOSFET Controlled by GATDRV ACIN OVP TON(OVP) Figure 1. OVP Timing Diagram IOCP IOUT GATDRV is pulled low VCHRIN Count 13 times Controlled by GATDRV Turn Off Internal P-MOSFET Controlled by GATDRV Turn Off Internal PMOSFET Controlled by GATDRV Turn Off Internal PMOSFET Total count 16 times, IC is latched off P-MOS Gate Control TB(OCP) TON(OCP) TB(OCP) TB(OCP) Figure 2. OCP Timing Diagram C opyright © A NPEC Electronics Corp. Rev. A.3 - Jul., 2009 11 www.anpec.com.tw APL3206/A Function Description (Cont.) VBAT VBOVP VCHRIN -VOUT = 150mV VBOVP VCHRIN Count 13 times Turn Off Internal PMOSFET P-MOS Gate Controlled Control by GATDRV Turn Off Internal P-MOSFET Controlled by GATDRV Controlled by GATDRV Turn Off Internal P-MOSFET Total count 16 times, IC is latched off TB(BOVP) TB(BOVP) TB(BOVP) Figure 3. Battery OVP Timing Diagram C opyright © A NPEC Electronics Corp. Rev. A.3 - Jul., 2009 12 www.anpec.com.tw APL3206/A Application Information RBAT Selection Connect the VBAT pin to the positive terminal of battery through a resistor RBAT for battery OVP function. The RBAT limits the current flowing from VBAT to battery in case of VBAT pin is shortened to ACIN pin under a failure mode. The recommended value of RBAT is 200kΩ . In the worse case of an IC failure, the current flowing from the VBAT pin to the battery is: (30V-3V) / 200kΩ =135µA where the 30V is the maximum ACIN voltage and the 3V is the minimum battery voltage. The current is so small and can be absorbed by the charger system. Power Dissipation (W) tion at TA = 25oC can be calculated by following formula : PD(MAX) = (125oC-25oC) / (165oC/W) = 0.606W for TDFN2x2-8 packages PD(MAX) = (125oC-25oC) / (220oC/W)= 0.455W for TSOT-23-6A packages The maximum power dissipation depends on operating ambient temperature for fixed TJ(MAX) and thermal resistance θJA. For APL3206/A packages, the Figure 4 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 25 50 75 oC) Signal Layer PCB TDFN2x2-8 TSOT-23-6A Capacitor Selection The input capacitor is for decoupling and prevents the input voltage from overshooting to dangerous levels. In the AC adapter hot plug-in applications or load current step-down transient, the input voltage has a transient spike due to the parasitic inductance of the input cable. A 25V, X5R, dielectric ceramic capacitor with a value between 1µF and 4.7 µF placed close to the ACIN pin is recommended. The output capacitor of CHRIN is for CHRIN voltage decoupling. And also can be as the input capacitor of the charging circuit. At least, a 1µF, 10V, X5R capacitor is recommended. 100 125 Ambient Temperature ( Figure 4. Derating Curves for APL3206/A Packages Layout Consideration Thermal Considerations The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula: PD(MAX) = (TJ(MAX)-TA) / θJA Where T J(MAX) i s the maximum operation junction temperature, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of APL3206/ A, where TJ(MAX) is 125oC and TA is the operated ambient temperature. The junction to ambient thermal resistance θJA for TDFN2x2-8 package is 165oC/W and TSOT-23-6A package is 220oC/W on the standard JEDEC 51-3 singlelayer thermal test board. The maximum power dissipaC opyright © A NPEC Electronics Corp. Rev. A.3 - Jul., 2009 13 In some failure modes, a high voltage may be applied to the device. Make sure the clearance constraint of the PCB layout must satisfy the design rule for high voltage. The exposed pad of the TDFN2x2-8 performs the function of channeling heat away. It is recommended that connect the exposed pad to a large copper ground plane on the backside of the circuit board through several thermal vias to improve heat dissipation. The input and output capacitors should be placed close to the IC. The high current traces like input trace and output trace must be wide and short. www.anpec.com.tw APL3206/A Package Information TDFN2x2-8 D A E D2 A1 A3 Pin 1 Corner e S Y M B O L A A1 A3 b D D2 E E2 e L 0.30 0.18 1.90 1.00 1.90 0.60 0.50 BSC 0.45 0.012 TDFN2x2-8 MILLIMETERS MIN. 0.70 0.00 0.20 REF 0.30 2.10 1.60 2.10 1.00 0.007 0.075 0.039 0.075 0.024 0.020 BSC 0.018 MAX. 0.80 0.05 MIN. 0.028 0.000 0.008 REF 0.012 0.083 0.063 0.083 0.039 INCHES MAX. 0.031 0.002 Note : 1. Follow from JEDEC MO-229 WCCD-3. C opyright © A NPEC Electronics Corp. Rev. A.3 - Jul., 2009 14 L E2 b www.anpec.com.tw APL3206/A Package Information TSOT-23-6A D e SEE VIEW A E1 b e1 E c A2 A 0.25 GAUGE PLANE SEATING PLANE L VIEW A TSOT-23-6A INCHES MIN. 0.028 0.000 0.028 0.012 0.003 0.106 0.102 0.055 0.037 BSC 0.075 BSC 0.60 8° 0.012 0° 0.024 8° MAX. 0.039 0.004 0.035 0.020 0.008 0.122 0.118 0.071 MAX. 1.00 0.10 0.90 0.50 0.20 3.10 3.00 1.80 S Y M B O L A A1 A2 b c D E E1 e e1 L 0 MILLIMETERS MIN. 0.70 0.01 0.70 0.30 0.08 2.70 2.60 1.40 0.95 BSC 1.90 BSC 0.30 0° Note : Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. C opyright © A NPEC Electronics Corp. Rev. A.3 - Jul., 2009 A1 15 www.anpec.com.tw APL3206/A Carrier Tape & Reel Dimensions OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B d Application A 178.0± 2.00 H 50 MIN. P1 4.0± 0.10 H 50 MIN. P1 4.0± 0.10 H A T1 T1 8.4+2.00 -0.00 P2 2.0± 0.05 T1 8.4+2.00 -0.00 P2 2.0± 0.05 C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00 C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00 d 1.5 MIN. D1 1.5 MIN. d 1.5 MIN. D1 1.0 MIN. D 20.2 MIN. T 0.6+0.00 -0.4 D 20.2 MIN. T 0.6+0.00 -0.40 W 8.0± 0.20 A0 3.35 MIN W 8.0± 0.30 A0 3.20± 0.20 E1 1.75± 0.10 B0 3.35 MIN E1 1.75± 0.10 B0 3.10± 0.20 W F 3.50± 0.05 K0 1.30± 0.20 F 3.5± 0.05 K0 1.50± 0.20 (mm) TDFN2x2-8 P0 4.0± 0.10 Application A 178.0± 2.00 TSOT-23-6A P0 4.0± 0.10 Devices Per Unit Package Type TDFN2x2-8 TSOT-23-6A Unit Tape & Reel Tape & Reel Quantity 3000 3000 C opyright © A NPEC Electronics Corp. Rev. A.3 - Jul., 2009 16 www.anpec.com.tw APL3206/A Taping Direction Information TDFN2x2-8 USER DIRECTION OF FEED TSOT-23-6A USER DIRECTION OF FEED AAAX AAAX AAAX AAAX AAAX AAAX AAAX C opyright © A NPEC Electronics Corp. Rev. A.3 - Jul., 2009 17 www.anpec.com.tw APL3206/A Classification Profile Classification Reflow Profiles Profile Feature Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time (tP)** within 5°C of the specified classification temperature (Tc) Average ramp-down rate (Tp to Tsmax) Time 25°C to peak temperature Sn-Pb Eutectic Assembly 100 °C 150 °C 60-120 seconds 3 °C/second max. 183 °C 60-150 seconds See Classification Temp in table 1 20** seconds 6 °C/second max. 6 minutes max. Pb-Free Assembly 150 °C 200 °C 60-120 seconds 3°C/second max. 217 °C 60-150 seconds See Classification Temp in table 2 30** seconds 6 °C/second max. 8 minutes max. * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. C opyright © A NPEC Electronics Corp. Rev. A.3 - Jul., 2009 18 www.anpec.com.tw APL3206/A Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness