APL431LBAC-TRG

APL431L Low Voltage Adjustable Precision Shunt Regulator Features General Description • Precise Reference Voltage to 1.24V The APL431L is a 3-terminal low voltage adjustable • Guaranteed 0.5%, 1% or 1.5% Reference Voltage precision reference with specified thermal stability Tolerance over applicable commercial temperature ranges. • Sink Current Capability, 80uA to 100mA Output voltage may be set to any value between • Quick Turn-on VREF (1.24 V) and 20 V with two external resistors • Adjustable Output Voltage, VO = VREF to 20V (see Figure 2). When used with an photocoupler, • Low Operational Cathode Current, 80µA Typical the APL431L is an ideal voltage reference in isolated • 0.1Ω Typical Output Impedance feedback circuits for 3V to 12V switching-mode • SOT-23-3, SOT-23-5, TO-92 and SOT-89 power supplies. This device has a typical output Packages impedance of 0.1W. Active output circuitry provides Lead Free and Green Devices Available a very sharp turn-on characteristic, making the (RoHS Compliant) APL431L excellent replacements for zener diodes • in many applications, including on-board regulation Applications and adjustable power supplies. • Linear Regulators • Adjustable Power Supply • Switching Power Supply Pin Configuration Symbol ANODE NC NC 3 5 4 REF 1 Anode Cathode 2 1 REF CATHODE SOT-23-3 (Top View) Functional Diagram 3 REF ANODE CATHODE SOT-23-5 (Top View) 3 CATHODE Cathode 2 ANODE REF 2 + _ 1 2 3 1 REF REF TO-92 (Top View) Vref ANODE CATHODE SOT-89 (Top View) Anode ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright  ANPEC Electronics Corp. Rev. B.10 - Mar., 2008 1 www.anpec.com.tw APL431L Ordering and Marking Information Elec. Grade A : 0.5% Reference Voltage Tolerance B : 1% Reference Voltage Tolerance C : 1.5% Reference Voltage Tolerance Package Code A : SOT-23-3 B : SOT-23-5 D : SOT-89 E : TO-92 Y : Chip Form Temperature Range C : 0 to 70 °C I : -40 to 85 °C Handling Code TR : Tape & Reel TB : Tape & Box Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APL431L Assembly Material Handling Code Temperature Range Package Code Elec. Grade APL431L A/B : 431L APL431L E : APL431L D : APL431L XXXXX XXXXX - Date Code APL 431L XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol Parameter Rating Unit VKA Cathode Voltage 21 V IK Continuous Cathode Current Range 120 mA IREF 3 mA TJ Reference Current Range Thermal Resistance from Junction to Ambient in Free Air SOT-23-3 SOT-23-5 SOT-89 TO-92 Operating Junction Temperature Range 416 357 250 250 -40 to 150 TSTG Storage Temperature Range -65 to 150 °C TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 °C θJA Copyright  ANPEC Electronics Corp. Rev. B.10 - Mar., 2008 2 °C/W °C www.anpec.com.tw APL431L Electrical Characteristics Symbol Parameter TA= 25°C ( unless otherwise noted) VKA=VREF, IK=10mA T A =25°C, (Fig. 1) VREF Reference Voltage T A =full range (see Note1), (Fig.1) VDEF APL431L Test Conditions Typ. Max. APL431LA 1.234 1.240 1.246 APL431LB 1.228 1.240 1.252 APL431LC 1.223 1.240 1.258 APL431LA 1.222 1.240 1.258 APL431LB 1.215 1.240 1.265 APL431LC 1.212 1.240 1.262 5 15 mV -0.2 -1.0 mV/V 0.15 0.5 µA 0.05 0.3 µA VKA=6V 0.01 0.1 VKA=16V 0.01 0.5 0.1 0.4 Ω 80 100 µA T A =full range (see Note1) VKA=VREF, IK=10mA (Fig. 1) VDEF Temp Deviation Unit Min. ∆VREF / Ratio of Change in V REF to IK=10mA, V KA=16V to V REF (Fig. 2) ∆VKA Change in Cathods Votage IREF IK=10mA,R 1 =10kΩ,R 2 =∞ (Fig. 2) Reference Input Current V (Note 1) T K=full range , R 1=10kΩ, R 2=∞, IK=10mA, (Fig. 2) IREF(DEV) IREF Temp Deviation IK(off) Off-State Cathode Current VREF=0V, (Fig. 3) Z KA Dynamic Output Impedance VKA=VREF, IK=1mA to 100mA, f ≤1kHz (Fig. 1) IK(MIN) Minimum Operating Current VKA=VREF (Fig. 1) µA Note 1 : Full temperature range is 0°C to 70°C for APL431LXXC,and -40°C to 85°C for APL431LXXl. Test Figures VIN Vo VIN Vo IK(off) IK VREF Figure 1. Test Circuit for VKA=VREF , VO=VKA=VREF Copyright  ANPEC Electronics Corp. Rev. B.10 - Mar., 2008 Figure 2. Test Circuit for IK(off) 3 www.anpec.com.tw APL431L Test Figures (Cont.) VIN Vo IK R1 IREF R2 VREF Figure 3. Test Circuit for VKA>VREF, VO= VKA= VREF× (1+R1/R2) + IREF × R1 Application Circuits VIN RB VIN Vo Vo RB R1 R1 C1 VREF VREF R2 R2 Precision Voltage Reference Precision High-Current Series Regulator Notes for Application Circuits: 1) For the series regulator applications, add a compensation capacitor C1 between CATHODE and REF is strongly recommended to improve the stability of output voltage . 2) Set VO according to the following equation: VO = VREF(1+R1/R2)+lREF xR1 3) Choose the value for RB as follows: A) The maximum limit for RB should be such that the cathode current (l K) is greater than the minimum operating current (80µA) at VIN(MIN). B) The minimum limit for RB should be such that the cathode current (lK) does not exceed 100mA under all load conditions, and the instantaneous turn-on value for lK does not exceed 150mA. Copyright  ANPEC Electronics Corp. Rev. B.10 - Mar., 2008 4 www.anpec.com.tw APL431L Typical Characteristics Cathode Current vs. Cathode Voltage Cathode Current vs. Cathode Voltage 100 250 VKA=VREF VKA=VREF TA=25°C TA=25°C 150 Cathode Current (mA) Cathode Current (µA) 200 100 50 0 -50 -100 -150 50 0 -50 -200 -250 -1 -0.5 0 0.5 1 -100 -1.5 1.5 -1 0 0.5 1 1.5 Cathode Voltage (V) Cathode Voltage (V) Referemce Voltage vs. Reference Input Current vs. Junction Temperature Junction Temperature 0.18 1.26 Reference Input Current (µA) IKA=10mA Reference Voltage (V) -0.5 1.25 1.24 1.23 1.22 IKA=10mA R1=10kΩ, R2=∞ 0.16 0.14 0.12 0.10 0.08 -50 -25 0 25 50 75 100 125 150 -50 Junction Temperature (°C) Copyright  ANPEC Electronics Corp. Rev. B.10 - Mar., 2008 -25 0 25 50 75 100 125 150 Junction Temperature (°C) 5 www.anpec.com.tw APL431L Typical Characteristics Off State Cathode Current vs. Junction Temperature 0.5 Off State Cathode Current (µA) 0 Delta Cathode Voltage (-mV/V) Ratio of Delta Reference Voltage to ∆VREF/∆VKA vs. Junction Temperature IKA=10mA -0.1 ∆VKA=VREF to 20V -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 VREF =0V VKA =16V 0.4 0.3 0.2 0.1 VKA =6V 0 -1 -50 -25 0 25 50 75 100 125 -50 150 Junction Temperature (°C) -25 0 25 50 75 125 150 Junction Temperature (°C) IKA =1mA 3V 100 IKA =0.1mA TA =25°C 3V TA =25°C Input Input 0 0 1V 1V Output 0 Output 0 0µ S Copyright  ANPEC Electronics Corp. Rev. B.10 - Mar., 2008 5µS 0µS 6 5µ S www.anpec.com.tw APL431L Typical Characteristics Gain vs. Phase Shift vs. Frequency IKA=10mA TA =25°C 50 Gain (dB) 180Ω 0 VIN 50 40 100 30 150 20 200 250 10 Vo 5V Phase Shift (degree) 60 10uF 6.8k Ω 4.3kΩ 300 0 Gain & Phase Test Circuit 350 -10 10 100 1000 10000 100000 1000000 Frequency (Hz) VIN 100 Ω Vo IK CL Stability Boundary Conditions 100 90 Unstable 80 VKA =2.5V 70 Ik (mA) TA =25°C VKA =VREF VKA =3.3V Stability Test Circuit for VKA=VREF 60 100 Ω 50 VIN 40 IK Stable 30 Vo R1 20 CL 10 0 0.0001 0.001 0.01 0.1 R2 1 CL-Load Capacitance (µF) Stability Test Circuit for VKA>VREF, VO= VKA= VREF× (1+R1/R2) + IREF × R1 Use the MLCC for CL Copyright  ANPEC Electronics Corp. Rev. B.10 - Mar., 2008 7 www.anpec.com.tw APL431L Typical Characteristics Zka vs. Frequency 100 IKA=10mA VKA=VREF TA =25°C Zka (Ω) 10 1 0.1 0.01 10 100 1000 10000 100000 1000000 Frequency (Hz) Copyright  ANPEC Electronics Corp. Rev. B.10 - Mar., 2008 8 www.anpec.com.tw APL431L Package Information SOT-23-3 D e E E1 SEE VIEW A c b 0.25 A L GAUGE PLANE SEATING PLANE 0 A1 A2 e1 VIEW A S Y M B O L SOT-23 INCHES MILLIMETERS MIN. MAX. A MIN. MAX. 1.45 0.057 A1 0.00 0.15 0.000 0.006 A2 0.90 1.30 0.035 0.051 b 0.30 0.50 0.012 0.020 c 0.08 0.22 0.003 0.009 D 2.70 3.10 0.106 0.122 E 2.60 3.00 0.102 0.118 E1 1.40 1.80 0.055 e 0.95 BSC e1 0.071 0.037 BSC 1.90 BSC 0.075 BSC L 0.30 0.60 0 0° 8° 0.012 0° 0.024 8° Note : Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. Copyright  ANPEC Electronics Corp. Rev. B.10 - Mar., 2008 9 www.anpec.com.tw APL431L Package Information SOT-23-5 D e E E1 SEE VIEW A b c 0.25 A L 0 GAUGE PLANE SEATING PLANE A1 A2 e1 VIEW A S Y M B O L SOT-23-5 MILLIMETERS MIN. MAX. MIN. MAX. A A1 INCHES 0.057 1.45 0.00 0.15 0.000 0.006 0.051 A2 0.90 1.30 0.035 b 0.30 0.50 0.012 0.020 c 0.08 0.22 0.003 0.009 0.122 D 2.70 3.10 0.016 E 2.60 3.00 0.102 0.118 1.80 0.055 0.071 E1 1.40 e 0.95 BSC e1 0.037 BSC 1.90 BSC 0.075 BSC L 0.30 0.60 0 0° 8° 0.012 0° 0.024 8° Note : 1. Follow JEDEC TO-178 AA. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. Copyright  ANPEC Electronics Corp. Rev. B.10 - Mar., 2008 10 www.anpec.com.tw APL431L Package Information A TO-92 E S D L j e1 b e TO-92 S Y M B O L MIN. MAX. MIN. MAX. A 4.32 5.33 0.170 0.210 b 0.41 0.53 0.016 0.021 D 4.45 5.20 0.175 0.205 E 3.18 4.19 0.125 0.165 e 2.42 2.66 0.095 0.105 e1 1.15 1.39 0.045 0.055 j 3.43 4.00 0.135 0.157 L 12.70 15.00 0.500 0.591 S 2.03 2.66 0.080 0.105 MILLIMETERS INCHES Note : FollowJEDEC TO-92. Copyright  ANPEC Electronics Corp. Rev. B.10 - Mar., 2008 11 www.anpec.com.tw APL431L Package Information SOT-89 A C L H E E1 D D1 e e1 B B1 S Y M B O L A SOT-89 MILLIMETERS INCHES MIN. MAX. MIN. MAX. 1.40 1.60 0.055 0.063 B 0.44 0.56 0.017 0.022 B1 0.36 0.48 0.014 0.019 0.017 C 0.35 0.44 0.014 D 4.40 4.60 0.173 0.181 D1 1.62 1.83 0.064 0.072 E 2.29 2.60 0.090 0.102 E1 2.13 2.29 0.084 0.090 e 1.50 BSC e1 3.00 BSC 0.059 BSC 0.118 BSC H 3.94 4.25 0.155 0.167 L 0.89 1.20 0.035 0.047 Note : Follow JEDEC TO-243 AA. Copyright  ANPEC Electronics Corp. Rev. B.10 - Mar., 2008 12 www.anpec.com.tw APL431L Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SOT-23-3 Application SOT-89 Application SOT-23-5 A H 178.0±2.00 50 MIN. P0 P1 4.0±0.10 4.0±0.10 A H 178.0±2.00 50 MIN. P0 P1 4.0±0.10 8.0±0.10 A H 178.0±2.00 50 MIN. P0 P1 4.0±0.10 4.0±0.10 T1 C 8.4+2.00 13.0+0.50 -0.00 -0.20 d D 1.5 MIN. 20.2 MIN. P2 D0 D1 T 2.0±0.10 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 T1 C d D 8.4+2.00 13.0+0.50 -0.00 -0.20 1.5 MIN. D0 D1 T 2.0±0.10 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 T1 C d D 1.5 MIN. 20.2 MIN. D1 T 1.5 MIN. 0.6+0.00 -0.40 2.0±0.10 1.5+0.10 -0.00 E1 8.0±0.30 1.75±0.10 A0 B0 F 3.5±0.05 K0 3.20±0.20 3.10±0.20 1.50±0.20 W E1 20.2 MIN. 12.0±0.30 1.75±0.10 P2 8.4+2.00 13.0+0.50 -0.00 -0.20 P2 D0 W A0 B0 F 5.50±0.05 K0 4.80±0.20 4.50±0.20 1.80±0.20 W E1 8.0±0.30 1.75±0.10 A0 B0 F 3.5±0.05 K0 3.20±0.20 3.10±0.20 1.50±0.20 (mm) Copyright  ANPEC Electronics Corp. Rev. B.10 - Mar., 2008 13 www.anpec.com.tw APL431L Carrier Tape & Box Dimensions Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Ramp-up Temperature TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25°C to Peak Time Copyright  ANPEC Electronics Corp. Rev. B.10 - Mar., 2008 14 www.anpec.com.tw APL431L Devices Per Unit Package Type Unit Quantity SOT-23-3 Tape & Reel 3000 SOT-89 Tape & Reel 1000 SOT-23-5 Tape & Reel 3000 TO-92 Tape & Box 2000 Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 sec 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Time 25°C to Peak Temperature Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Note: All temperatures refer to topside of the package. Measured on the body surface. Copyright  ANPEC Electronics Corp. Rev. B.10 - Mar., 2008 15 www.anpec.com.tw APL431L Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures 3 3 Package Thickness Volume mm