APL5325BI-TRG

APL5325 Adjustable Low Dropout 300mA Linear Regulator Features • • • • • • • • • Wide Operating Voltage: 3~6V Low Dropout Voltage: 300mV(Typical) @ 300mA Guaranteed 300mA Output Current Adjustable Output Voltage: 0.8~5.5V Current-Limit Protection with Foldback Current Over-Temperature Protection Stable with Low ESR Ceramic Capacitor SOT-23-5 Package Lead Free and Green Devices Available (RoHS Compliant) General Description The APL5325 is a P-channel low dropout linear regulator which needs only one input voltage from 3 to 6V, and delivers current up to 300mA to set output voltage. It also can work with low ESR ceramic capacitors and is ideal for using in the battery-powered applications such as notebook computers and cellular phones. Typical dropout voltage is only 300mV at 300mA loading. Current limit with current foldback and thermal shutdown functions protect the device against current over-loads and over temperature. The APL5325 is available in a SOT23-5 package. Pin Configuration Applications • • • Cellular Phones SHDN 1 GND 2 VIN 3 SOT-23-5 5 SET 4 VOUT Portable and Battery-Powered Equipment Notebook and Personal Computers Simplified Application Circuit APL5325 VIN CIN 3 1 VIN VOUT 4 VOUT COUT SHDN SET 5 GND 2 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright © ANPEC Electronics Corp. Rev. A.1 - Nov., 2008 1 www.anpec.com.tw APL5325 Ordering and Marking Information APL5325 Assembly Material Handling Code Temperature Range Package Code Package Code B: SOT-23-5 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device XXXXXX - Date Code APL5325 B: 25RX Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol VIN VSHDN PD TJ TSTG TSDR VIN Supply Voltage (VIN to GND) SHDN Input Voltage (SHDN to GND) Power Dissipation Junction Temperature Storage Temperature (Note 1) Rating -0.3 ~ 6.5 -0.3 ~ 6.5 Internally Limited -40 ~ 150 -65 ~ 150 260 Unit V V W o o o Parameter C C C Maximum Lead Soldering Temperature, 10 Seconds Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA θJC Parameter Thermal Resistance-Junction to Ambient Thermal Resistance-Junction to Case SOT-23-5 (Note 2) Typical Value SOT-23-5 240 130 Unit o C/W C/W o Note 2 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions Symbol VIN VOUT IOUT CIN COUT TJ VIN Supply Voltage Output Voltage VOUT Output Current Input Capacitor Output Capacitor Junction Temperature 2 Parameter Range 3~6 0.8 ~ 5.5 0 ~ 300 0.22 ~ 100 1.5 ~ 100 -40 ~ 125 Unit V V mA µF µF o C C opyright © A NPEC Electronics Corp. Rev. A.1 - Nov., 2008 www.anpec.com.tw APL5325 Electrical Characteristics Unless otherwise specified, these specifications apply over VIN = VOUT+1V, IOUT=0~300mA, CIN = 1µF, COUT = 2.2µF, TA = -40 to 85oC. Typical values are at TA = 25oC. Symbol VIN VOUT IQ VREF Input Voltage Parameter Test Conditions Min. 3 0.8 IOUT =10mA ~300mA Measured on SET, VIN=3V, IOUT=10mA IOUT=10mA ∆VOUT%/∆VIN, IOUT=10mA ∆VOUT%/∆IOUT VOUT = 2.5V, IOUT = 300mA VOUT = 3.3V, IOUT = 300mA -2 -0.06 -0.2 450 VOUT = 0V 1.6 SHDN = Low SHDN = Low, VIN = 6V VSET=0.8V -100 APL5325 Typ. 135 0.8 500 300 45 160 550 80 60 0.1 3 160 40 Max. 6 5.5 160 +2 +0.06 +0.2 650 Unit V V µA V % %/V %/A mV 400 V 0.4 1 100 Ω µA MΩ o o Output Voltage Range Quiescent Current Reference Voltage Output Voltage Accuracy REGLINE Line Regulation REGLOAD Load Regulation VDROP Dropout Voltage PSRR Power Supply Ripple Rejection Ratio Noise f = 10kHz, IOUT = 300mA f = 80Hz to 100kHz, IOUT = 300mA dB µVRMS mA mA ILIMIT ISHORT Current Limit Foldback Current SHDN Input Voltage High SHDN Input Voltage Low VOUT Discharge MOSFET RDS(ON) Shutdown VIN Supply Current SHDN Pull Low Resistance Over Temperature Threshold Over Temperature Hysteresis SET Input Bias Current C C nA C opyright © A NPEC Electronics Corp. Rev. A.1 - Nov., 2008 3 www.anpec.com.tw APL5325 Typical Operating Characteristics Quiescent Current vs. Supply Voltage 160 140 Quiescent Current, IQ (µA) 120 100 80 60 40 20 0 0 1 2 3 4 5 6 7 Supply Voltage, V IN (V) 126 -50 -25 0 25 50 75 100 125 Quiescent Current vs. Junction Temperature 138 IOUT= 0mV Quiescent Current, IQ (µA) 136 134 132 130 128 Junction Temperature, T J (o C) PSRR vs. Frequency 0 Dropout Voltage vs. Output Current 400 Dropout Voltage, VDROP(mV) -10 -20 VIN=3.3V, VOUT=1.2V, COUT=2.2µF,IOUT=300mA 350 300 250 200 150 100 50 0 VOUT=3.3V o TJ=125oC TJ=75 C PSRR(dB) -30 -40 -50 -60 -70 -80 1000 10000 100000 TJ=-50oC TJ=25oC 0 100 200 300 Frequency(Hz) Output Current, I OUT(mA) Dropout Voltage vs. Output Current 700 Dropout Voltage, VDROP(mV) 600 500 400 300 200 100 0 0 100 200 300 Output Current, IOUT(mA) C opyright © A NPEC Electronics Corp. Rev. A.1 - Nov., 2008 4 TJ=-50 C TJ=25oC o Current Limit vs. Junction Temperature 600 VIN=5V Current Limit, ILIMIT(mA) VOUT=2.5V TJ=125oC TJ=75oC 550 500 VIN=3.3V 450 400 -50 -25 0 25 50 75 100 125 Junction Temperature, T J(oC) www.anpec.com.tw APL5325 Typical Operating Characteristics (Cont.) Loop Gain vs. Frequency 50 40 30 Loop Gain (dB) 20 10 0 -10 -20 -30 -40 1000 10000 100000 1000000 IOUT=300mA 160 Phase vs. Frequency 140 VIN=3.3V, VOUT=1.2V, CIN=1µF, COUT=2.2µF IOUT=300mA VIN=3.3V, VOUT=1.2V, CIN=1µF, COUT=2.2µF IOUT=100mA Phase (degree) 120 100 80 60 40 20 0 1000 10000 IOUT=100mA 100000 1000000 Frequency (Hz) Frequency (Hz) C opyright © A NPEC Electronics Corp. Rev. A.1 - Nov., 2008 5 www.anpec.com.tw APL5325 Operating Waveforms Enable Shutdown CH1 SHDN VIN SHDN CH1 VIN CH2 CH2 CH3 VOUT CH3 VOUT IOUT CH4 CH4 I OUT CH1 : SHDN , 5V/div CH2 : VIN , 5V/div CH3 : VOUT , 2V/div CH4 : IOUT , 100mA/div Time : 200µs/div CH1 : SHDN , 5V/div CH2 : VIN , 5V/div CH3 : VOUT , 2V/div CH4 : IOUT , 100mA/div Time : 10µs/div Load Transient V IN=5V ; C I N=1µF ; C OUT =2.2µF ; T R =1µ s CH1 Line Transient C IN=1 µF ; C OUT =2.2µF ; T R =5µs ; I OUT =10mA V IN VOUT I OUT VOUT CH2 CH2 CH1 CH1 : VOUT , 50mV/div AC CH2 : IOUT , 100mA/div Time : 20µs/div CH1 : VIN , 1V/div DC CH2 : VOUT , 50mV/div AC Time : 20µs/div C opyright © A NPEC Electronics Corp. Rev. A.1 - Nov., 2008 6 www.anpec.com.tw APL5325 Operating Waveforms (Cont.) Power On Power Off VIN CH1 VOUT CH2 I OUT CH1 VIN CH2 VOUT CH3 CH3 IOUT CH1 : VIN , 2V/div CH2 : VOUT , 2V/div CH3 : IOUT , 100mA/div Time : 2ms/div CH1 : VIN , 2V/div CH2 : VOUT , 2V/div CH3 : IOUT , 100mA/div Time : 10ms/div Pin Description PIN NO. 1 2 3 4 5 NAME SHDN GND VIN VOUT SET FUNCTION Shutdown control pin, logic high: enable; logic low: shutdown. Ground pin. Voltage supply input pin. Regulator output pin. Connect this pin to an external resistor divider to adjust output voltage. C opyright © A NPEC Electronics Corp. Rev. A.1 - Nov., 2008 7 www.anpec.com.tw APL5325 Block Diagram UVLO & Shutdown Logic SHDN VIN Thermal Shutdown 0.8V + Foldback Current Limit 3MΩ VOUT SET GND Typical Application Circuit VIN 3 1 VIN SHDN GND 2 VOUT SET 4 5 R1 VOUT CIN 1µF COUT 2.2µF Enable R2 Shutdown R1   VOUT = 0.8 ⋅  1 +   R2  Designation CIN CIN COUT COUT Supplier Murata Murata Murata Murata Part Number GRM185R61A105KE36 GRM188R71A105KA61 GRM188R61A225KE34 GRM188R71A225KE15 Specification 0603, X5R, 10V, 1µF 0603, X7R, 10V, 1µF 0603, X5R, 10V, 2.2µF 0603, X7R, 10V, 2.2µF Reference: www.murata.com C opyright © A NPEC Electronics Corp. Rev. A.1 - Nov., 2008 8 www.anpec.com.tw APL5325 Function Description Output Voltage Regulation The APL5325 is an adjustable low dropout linear regulator. The output voltage set by the resistor-divider is determined by: R1   VOUT = 0.8 ⋅  1 +   R2    Where R1 is connected from VOUT to SET with Kelvin sensing and R2 is connected from SET to GND. The recommended value of R2 is in the range of 100 to100kΩ . An error amplifier works with a temperature compensated 0.8V reference and an output PMOS regulates the output to the presetting voltage. The error amplifier is designed with high bandwidth and DC gain provides very fast transient response and less load regulation. It compares the reference with the feedback voltage and amplifies the difference to drive the output PMOS which provides load current from VIN to VOUT. Thermal Shutdown A thermal shutdown circuit limits the junction temperature of APL5325. When the junction temperature exceeds +160οC, a thermal sensor turns off the output PMOS, allowing the device to cool down. The regulator regulates the output again through initiation of a new soft-start cycle after the junction temperature is cooled down by 40oC. The thermal shutdown is designed with a 40oC hysteresis to lower the average junction temperature during continuous thermal overload conditions, extending lifetime of the device. For normal operation, device power dissipation should be externally limited so that junction temperature will not exceed 125oC. Shutdown Control The APL5325 has an active-low shutdown function. Force SHDN high (>1.6V) enables the VOUT; force SHDN low ( 2KV, VMM > 200V 10ms, 1tr > 100mA www.anpec.com.tw C opyright © A NPEC Electronics Corp. Rev. A.1 - Nov., 2008 APL5325 Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Time 25°C to Peak Temperature Sn-Pb Eutectic Assembly 3°C/second max. 100°C 150°C 60-120 seconds 183°C 60-150 seconds See table 1 10-30 seconds 6°C/second max. 6 minutes max. Pb-Free Assembly 3°C/second max. 150°C 200°C 60-180 seconds 217°C 60-150 seconds See table 2 20-40 seconds 6°C/second max. 8 minutes max. Note: All temperatures refer to topside of the package. Measured on the body surface. Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures Package Thickness