APL5331
3A Bus Termination Regulator
Features
General Description
•
Provide Bi-direction Current
The APL5331 linear regulator is designed to provide a
- Sourcing or Sinking Current up to 3A
regulated voltage with bi-directional output current for
•
1.25V/0.9V Output for DDR I/II Applications
DDR-SDRAM termination. The APL5331 integrates
•
Fast Transient Response
two power transistors to source or sink current up to
High Output Accuracy
3A. It also incorporate current-limit, thermal shutdown
•
- ±20mV over Load, VOUT Offset and Temperature
•
and shutdown control functions into a single chip.
•
Adjustable Output Voltage by External Resistors Current-limit circuit limits the short-circuit current. Onchip thermal shutdown provides protection against any
Current-Limit Protection
•
On-Chip Thermal Shutdown
•
Shutdown for Standby or Suspend Mode
junction temperature. The output voltage of APL5331
Simple SOP-8, SOP-8-P with thermal pad,
tracks the voltage at VREF pin. A resistor divider
•
combination of overload that would create excessive
connected to VIN, GND and VREF pins is used to
TO-252- 5 and TO-263-5 Packages
•
provide a half voltage of VIN to VREF pin. In addition,
Lead Free Available (RoHS Compliant)
an external ceramic capacitor and an open-drain
Applications
transistor connected to VREF pin provide soft-start
and shutdown control respectively. Pulling and holding
•
DDR I/II SDRAM Termination
•
SSTL-2/3 Termination Voltage
output of APL5331 will be high impedance in shut-
Applications Requiring the Regulator with
down condition.
•
the VREF voltage to 0V shuts off the output. The
Bi-direction 3A Current Capability
GND
2
7
VCNTL
VREF
3
6
VCNTL
VOUT
4
5
VCNTL
TAB is VCNTL
SOP-8 (Top View)
VIN
1
8
NC
GND
2
7
NC
VREF
3
6
VCNTL
VOUT
4
5
NC
5
VCNTL
VOUT
VREF
3
8
VCNTL
2
1
GND
1
VIN
4
Pin Configuration
VIN
TO-252-5 (Top View)
TAB is VCNTL
SOP-8-P (Top View)
5
4
3
2
1
VOUT
VREF
VCNTL
GND
VIN
TO-263-5 (Top View)
NC = No internal connection
= Thermal Pad (connected to GND plane for better heat dissipation)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
1
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APL5331
Ordering and Marking Information
Package Code
K : SOP-8
KA : SOP-8-P
U5 : TO-252-5
G5 : TO-263-5
Operating Ambient Temp. Range
C : 0 to 70 oC
Handling Code
TR : Tape & Reel
Lead Free Code
L : Lead Free Device Blank : Original Device
APL5331
Lead Free Code
Handling Code
Temp. Range
Package Code
APL5331KC-TR :
APL5331KAC-TR :
APL5331U5C-TR :
APL5331G5C-TR :
APL5331
XXXXX
XXXXX - Date Code
APL5331
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate
termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering
operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C
for MSL classification at lead-free peak reflow temperature.
Pin Description
PIN NAME
I/O
DESCRIPTION
VIN
I
Main power input pin. Connect this pin to a voltage source and an input
capacitor. The APL5331 sources current to VOUT pin by controlling the
upper NPN pass transistor, providing a current path from VIN pin.
GND
O
Power and signal ground. Connect this pin to system ground plane with
shortest traces. The APL5331 sinks current from VOUT pin by controlling the
lower NPN pass transistor, providing a current path to GND pin. This pin is
also the ground path for internal control circuitry.
VCNTL
I
Power input pin for internal control circuitry. Connect this pin to a voltage
source, providing a bias for the internal control circuitry. A bypass capacitor
is usually connected near this pin.
I
Reference voltage input and active-low shutdown control pin. Apply a
voltage to this pin as a reference voltage for the APL5331. Connect this pin
to a resistor divider, between VIN and GND, and a capacitor for soft-start
and filtering noise purposes. Applying and holding this VREF voltage low by
an open-drain transistor to shut down the output.
O
Output pin of the regulator. Connect this pin to load. The output capacitors
connected to this pin improve stability and transient response. The output
voltage tracks the reference voltage and is capable of sourcing or sinking
current up to 3A.
VREF
VOUT
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
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APL5331
Block Diagram
VCNTL
VREF
VIN
Voltage
Regulation
Thermal
Limit
Current
Limit
VOUT
Shutdown
GND
Absolute Maximum Ratings
Symbol
VCNTL
Parameter
VCNTL Supply Voltage, VCNTL to GND
VIN
VIN Supply Voltage, VIN to GND
PD
Power Dissipation
TJ
Junction Temperature
Rating
Unit
-0.2 ~ 7
V
-0.2 ~ 3.9
V
Internally Limited
W
150
o
-65 ~ 150
o
o
TSTG
Storage Temperature
TSDR
Soldering Temperature, 10 Seconds
300
VESD
Minimum ESD Rating (Human Body Mode)
±3
C
C
C
kV
Thermal Characteristics
Symbol
θJA
θJC
Parameter
Value
Junction-to-Ambient Thermal Resistance in Free Air
SOP-8
SOP-8-P
TO-252-5
TO-263-5
Junction-to-Case Thermal Resistance
SOP-8
SOP-8-P
TO-252-5
TO-263-5
75
55
42
34
28
20
12
11
Unit
o
C/W
o
C/W
Note : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The
exposed pad of SOP-8-P is soldered directly on the PCB.
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
3
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APL5331
Recommended Operating Conditions
Symbol
VCNTL
VIN
Parameter
VCNTL Supply Voltage
VIN Supply Voltage
Unit
3.1 ~ 6
V
1.2 ~ 3.5
V
VREF ± 0.02
V
-3 ~ +3
A
(Note 1)
(Note 2)
VOUT Output Voltage
(Note 3)
IOUT
VOUT Output Current
(Note 4,5)
TJ
Junction Temperature
VOUT
Range
o
0 ~ 125
C
Notes :
1. Please refer to the VCNTL-to-VIN Dropout Voltage in the “Typical Characteristics” section for the minimum supply
voltage on VCNTL.
2. Please supply enough voltage to VIN for sourcing desired maximum output current. Please refer to the VIN. Dropout
Voltage vs Output Current in the Typical Characteristics.
3. The VOUT is regulated to the VREF with additional voltage offset and load regulation except over-load conditions.
4. The symbol “+” means the VOUT sources current to load; the symbol “-“ means the VOUT sinks current to to GND.
5. The max. IOUT varies with the TJ and the voltages of VIN-VOUT and VOUT. Please refer to the Typical Characteristics.
Electrical Characteristics
Refer to the typical application circuit. These specifications apply over, VCNTL=3.3V, VIN=2.5V/1.8V, VREF=0.5VIN
and TA = 0 to 70°C, unless otherwise specified. Typical values refer to TA = 25°C.
Parameter
Symbol
Test Conditions
APL5331
Min
Typ
Max
Unit
OUTPUT VOLTAGE
VOUT
VOUT Output Voltage
System Accuracy
VOS
VOUT Offset Voltage
(VOUT–VREF)
Load Regulation
IOUT = 0A
Over temperature, VOUT offset,
and load regulation
IOUT = +10mA
VREF
-20
-15
IOUT = -10mA
IOUT = +10mA to +3A
20
-8
6
-8
14
-3
1
IOUT = -10mA to -3A
V
6
mV
mV
mV
PROTECTION
ILIM
TSD
Sourcing Current
(VIN = 2.5V)
Sourcing Current
(VIN = 2.5V)
Current Limit
Sourcing Current
(VIN = 1.8V)
Sourcing Current
(VIN = 1.8V)
Thermal Shutdown Temperature Rising TJ
Thermal Shutdown Hysteresis
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
+3.3
TJ = 25°C
TJ = 125°C
-3.3
TJ = 25°C
TJ = 125°C
+2.9
TJ = 25°C
TJ = 125°C
-2.9
TJ = 25°C
°
TJ = 125 C
+3.6
+3.1
-3.6
-3.1
+3.2
+2.6
-3.2
-2.6
183
42
4
A
o
C
o
C
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APL5331
Electrical Characteristics (Cont.)
Refer to the typical application circuit. These specifications apply over, VCNTL=3.3V, VIN=2.5V/1.8V, VREF=0.5VIN
and TA = 0 to 70°C, unless otherwise specified. Typical values refer to TA = 25°C.
Parameter
Symbol
APL5331
Test Conditions
Unit
Min
Typ
Max
2
3.9
6
50
110
mA
INPUT CURRENT
IOUT = 0A
ICNTL
VCNTL Supply Current IOUT = ±3A (Normal Operation)
VREF Bias Current
(The current flows out
of VREF)
SHUTDOWN CONTROL
Shutdown Threshold
Voltage
IVREF
VREF = GND (Shutdown)
2.0
VREF = 1.25V/0.9V (Normal operation)
200
500
nA
VREF = GND (Shutdown)
20
40
µA
0.35
0.65
V
0.2
Typical Application Circuit
1. VOUT=1.25V/0.9V Application
VCNTL
+3.3V
VIN
+2.5V/1.8V
VIN
R1
1k
CIN
470uF
VREF
VCNTL
GND VOUT
VREF
Shutdown
Q1
R2
1k
CSS
0.1uF
CCNTL
47uF
GND
VOUT
+1.25V/0.9V
-3~+3A
COUT
470uF
GND
COUT : 470µF, ESR=25mΩ
R1, R2 : 1kΩ, 1%
Q1 : APM2300 AC
Note : Since R1 and R2 are very small, the voltage offset
caused by the bias current of VREF can be ignore.
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
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APL5331
Typical Application Circuit
2. VOUT=1.4V Application
VCNTL
+5V
VIN
+2.8V
VIN
R1
1k
CIN
470µF
VCNTL
VOUT
+1.4V/
-3~+3A
VREF GND VOUT
VREF
R2
1k
CSS
0.1µF
CCNTL
47µF
COUT
470µF
GND
GND
3. General Application
VCNTL
+5V
VIN
VIN
+1.8V
VREF
VCNTL
VREF
R1
VREFIN
+1.8V
1k
R2
2k
CSS
0.1uF
CIN
22uF
GND VOUT
CCNTL
1uF
VOUT
1.2V/-2~+1.8A
COUT
100uF
GND
GND
V OUT = V REFIN ⋅
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
R2
R1 + R2
(V)
6
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APL5331
Typical Characteristics
Sourcing Current-Limit
vs Junction Temperature
Sinking Current-Limit
vs Junction Temperature
5.0
-2.0
VCNTL=5V,VIN=2.5V
4.0
3.5
3.0
VCNTL=5V,VIN=1.8V
VCNTL=3.3V,VIN=1.8V
2.5
VCNTL=3.3V,VIN=1.8V
-3.0
-3.5
VCNTL=3.3V,VIN=2.5V
-4.0
VCNTL=5V,VIN=2.5V
-4.5
2.0
-5.0
-50
-25
0
25
50
75
100
125
-50
25
50
75
100
VREF Bias Current
vs Junction Temperature
VREF Shutdown Threshold
vs Junction Temperature
125
0.6
VREF=1.25V/0.9V
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-50
0
Junction Temperature (°C)
VREF Shutdown Threshold (V)
0.40
-25
Junction Temperature (°C)
0.45
VREF Bias Current, IVREF (µA)
VCNTL=5V,VIN=1.8V
-2.5
VCNTL=3.3V,VIN=2.5V
Current-Limit, ILIM (A)
Current-Limit, ILIM (A)
4.5
0.5
VCNTL=5V
0.4
0.3
VCNTL=3.3V
0.2
0.1
-25
0
25
50
75
100
125
-50
0
25
50
75
100
125
Junction Temperature (°C)
Junction Temperature (°C)
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
-25
7
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APL5331
Typical Characteristics (Cont.)
VOUT Offset Voltage
vs Junction Temperature
Quiescent VCNTL Current
vs Junction Temperature
6.0
VREF=1.25V/0.9V
Quiescent VCNTL Current (mA)
VOUT Offset Voltage, VOS (mV)
14
10
6
IOUT=-10mA
2
-2
-6
IOUT=+10mA
-10
-14
IOUT=0A
5.5
5.0
VCNTL=5V
4.5
4.0
3.5
VCNTL=3.3V
3.0
2.5
2.0
-50
-25
0
25
50
75
100
125
-50
Junction Temperature (°C)
-25
0
25
50
75
100
125
Junction Temperature (°C)
VREF Bias Current
vs VREF Supply Voltage
VREF Bias Current, IVREF (µA)
22
20
TJ=25°C
18
16
14
12
10
8
6
4
2
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VREF Supply Votage, VREF (V)
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
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APL5331
Typical Characteristics (Cont.)
VIN Dropout Voltage vs. Output Current
VIN Dropout Voltage vs. Output Current
1.2
1.2
VREF=0.9V
VCNTL=5.0V
VREF=0.9V
VCNTL=3.3V
1.0
TJ=25°C
TJ=75°C
TJ=125°C
0.8
Dropout Voltage (V)
Dropout Voltage (V)
1.0
0.6
TJ=-50°C
0.4
TJ=25°C
TJ=75°C
TJ=125°C
0.8
0.6
TJ=-50°C
0.4
0.2
0.2
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.0
3.0
0.5
Output Current (A)
2.0
2.5
3.0
VCNTL-to-VOUT Dropout Voltage vs
VCNTL Input Current
120
3.8
Minimum VCNTL - VOUT Voltage (V)
IOUT = 1A
VCNTL Input Current, ICNTL (mA)
1.5
Output Current (A)
VCNTL Input Current vs
VIN - VOUT Voltage at IOUT=1A
100
TJ=125°C
80
TJ=75°C
TJ=25°C
TJ=-25°C
60
40
20
0
0.2
1.0
0.3
0.4
0.5
0.6
0.7
0.8
0.9
TJ=-25°C
TJ=125°C
3.0
2.6
2.2
TJ=25°C
1.8
1.4
TJ=75°C
1.0
0
1.0
20
40
60
80
100
120
VCNTL Input Current, ICNTL (mA)
VIN - VOUT Voltage (V)
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
IOUT = 1A
3.4
9
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APL5331
Typical Characteristics (Cont.)
VCNTL Input Current vs
VCNTL-to-VOUT Dropout Voltage vs
VCNTL Input Current
VCNTL Input Current, ICNTL (mA)
IOUT = 1.5A
100
TJ=125°C
80
TJ=75°C
TJ=25°C
TJ=-25°C
60
40
20
0
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
Minimum VCNTL - VOUT Voltage (V)
VIN - VOUT Voltage at IOUT=1.5A
120
3.8
IOUT = 1.5A
3.4
TJ=-25°C
TJ=125°C
3.0
2.6
2.2
TJ=25°C
1.8
1.4
TJ=75°C
1.0
0
60
80
100
120
VCNTL Input Current vs
VCNTL-to-VOUT Dropout Voltage vs
VIN - VOUT Voltage at IOUT=2A
VCNTL Input Current
3.8
120
100
Minimum VCNTL - VOUT Voltage (V)
IOUT = 2A
VCNTL Input Current, ICNTL (mA)
40
VCNTL Input Current, ICNTL (mA)
VIN - VOUT Voltage (V)
TJ=125°C
TJ=75°C
TJ=25°C
80
TJ=-25°C
60
40
20
0
0.4
20
0.5 0.6
0.7
0.8 0.9
1.0 1.1
TJ=-25°C
TJ=125°C
3.0
2.6
2.2
TJ=25°C
1.8
1.4
TJ=75°C
1.0
0
1.2
VIN - VOUT Voltage (V)
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
IOUT = 2A
3.4
20
40
60
80
100
120
VCNTL Input Current, ICNTL (mA)
10
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APL5331
Operating Waveforms
1. Load Transient Response : IOUT = +10mA -> +3A -> +10mA
- VIN = 2.5V, VCNTL = 3.3V
- VREF is 1.250V supplied by a regulator
- COUT = 470µF/10V, ESR = 30mΩ
- IOUT slew rate = ±3A/µS
IOUT = +10mA -> +3A
IOUT = +10mA -> +3A -> +10mA
IOUT = +3A -> +10mA
Load Regulation = -2.8mV
V OUT
IOUT
V OUT
V OUT
IOUT
IOUT
+3A
+10mA
Ch1 : VOUT, 20mV/Div, DC,
Offset = 1.250V
Ax1 : IOUT, 1A/Div
Time : 1µS/Div
Ch1 : VOUT, 20mV/Div, DC,
Offset = 1.250V
Ax1 : IOUT, 1A/Div
Time : 20µS/Div
Ch1 : VOUT, 20mV/Div, DC,
Offset = 1.250V
Ax1 : IOUT, 1A/Div
Time : 1µS/Div
2. Load Transient Response : IOUT = -10mA -> -3A -> -10mA
- VIN = 2.5V, VCNTL = 3.3V
- VREF is 1.250V supplied by a regulator
- COUT = 470µF/10V, ESR = 30mΩ
- IOUT slew rate = ±3A/µS
IOUT = -10mA -> -3A
IOUT = -10mA -> -3A -> -10mA
IOUT = -3A -> -10mA
Load Regulation = +6.2mV
V OUT
-10mA
V OUT
V OUT
IOUT
IOUT
IOUT
-3A
Ch1 : VOUT, 20mV/Div, DC,
Offset = 1.250V
Ax1 : IOUT, 1A/Div
Time : 1µS/Div
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
Ch1 : VOUT, 20mV/Div, DC,
Offset = 1.250V
Ax1 : IOUT, 1A/Div
Time : 20µS/Div
11
Ch1 : VOUT, 20mV/Div, DC,
Offset = 1.250V
Ax1 : IOUT, 1A/Div
Time : 1µS/Div
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APL5331
Operating Waveforms (Cont.)
3. Load Transient Response : IOUT = +3A -> -3A -> +3A
- VIN = 2.5V, VCNTL = 3.3V
- VREF is 1.250V supplied by a regulator
- COUT = 470µF/10V, ESR = 30mΩ
- IOUT slew rate = ±3A/µS
IOUT = +3A -> -3A
IOUT = -3A -> +3A
IOUT = +3A -> -3A -> +3A
V OUT
V OUT
V OUT
IOUT
IOUT
+3A
IOUT
Ch1 : VOUT, 50mV/Div, DC,
Offset = 1.250V
Ax1 : IOUT, 2A/Div
Time : 1µS/Div
-3A
Ch1 : VOUT, 50mV/Div, DC,
Offset = 1.250V
Ax1 : IOUT, 2A/Div
Time : 20µS/Div
Ch1 : VOUT, 50mV/Div, DC,
Offset = 1.250V
Ax1 : IOUT, 2A/Div
Time : 1µS/Div
4. Short-Circuit Test
- VIN = 2.5V, VCNTL = 3.3V
VOUT is Shorted to GND
VOUT is Shorted to VIN (2.5V)
IOUT
V OUT
IOUT
V OUT
IOUT
V OUT
Ch1 : VOUT, 500mV/Div, DC,
Ax1 : IOUT, 2A/Div
Time : 5mS/Div
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
Ch1 : VOUT, 500mV/Div, DC,
Ax1 : IOUT, 2A/Div
Time : 5mS/Div
12
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APL5331
Application Information
General
Shutdown and Soft-Start (Cont.)
The APL5331 is a linear regulator and is capable of
and holding a voltage below 0.35V (typ.) to VREF pin
sourcing or sinking current up to 3A. The APL5331
shuts down the output of the regulator. An NPN
has fast transient response, accurate output voltage
transistor or N-channel MOSFET is used to pull down
(small voltage offset, load regulation), active-low
the VREF voltage while applying a “high” signal to
shutdown control and fault protections (current-limit,
turn on the transistor. When shutdown function is
thermal shutdown). The APL5331 is available in several
active, both pass transistors are turned off and the
packages to meet different of power dissipation in
impedance of the VOUT is about 10MΩ (typ.), sourcing
or sinking no current. When release the VREF pin,
requirement various applications.
the current through the resistor divider charges the
Output Voltage Regulation
soft-start capacitor to initiate a soft-start process
The output voltage at VOUT pin tracks the reference
which controls the rise rate of the output voltage and
voltage applied at VREF pin. Two internal NPN pass
limits the input surge current.
transistors controlled by separate high bandwidth
Thermal Shutdown
error amplifiers regulate the output voltage by sourcing
current from VIN pin or sinking current to GND pin.
A thermal shutdown circuit limits the junction
The base currents of the pass transistors are provided
temperature of the APL5331. When the junction
by VCNTL pin. An internal kelvin sensing scheme
temperature exceeds TJ= +183oC, a thermal sensor
senses the output voltage on VOUT pin for perfect
load regulation. To prevent two pass transistors from
turns off both pass transistors, allowing the device to
cool down. The regulator starts to regulate again after
shoot-through, a small voltage offset is created between
the junction temperature reduces by 40oC, resulting
the positive inputs of the two error amplifiers. This
in a pulsed output during continuous thermal overload
results in higher output voltage while the regulator sinks
conditions. The thermal limit designed with a 40oC
load current. Since the APL5331 exhibits very fast load
hysteresis lowers the average TJ during continuous
transient response, lesser amount of capacitors can be
thermal overload conditions, and extends life time of
used. In addition, capacitors with high ESR can also
APL5331.
be used.
Power Inputs
Current Limit
It's not necessary to pay attention to the sequencing
The APL5331 monitors sourcing and sinking output
of the input voltages on VIN and VCNTL pins. However,
currents, and limits the maximum output currents to
do not apply a voltage to VOUT when the VCNTL
prevent damages during overload or short-circuit
voltage is not present. This reason is that the internal
condition. To increase the voltage across the internal
parasitic diodes connected from VOUT to VIN and from
pass transistors will get higher current-limit points.
VOUT to VCNTL will be forward biased. When the VIN
input voltage is not present, the APL5331 can only
Shutdown and Soft-Start
source few current up to 100mA to output. In the same
The VREF pin is a dual-function input pin, acting as
condition, the APL5331 keeps same capability of
reference input and shutdown control input. Applying
sinking output current up to 3A.
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
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APL5331
Application Information (Cont.)
Reference Voltage
Output Capacitor (Cont.)
A reference voltage is applied at the VREF pin by a
Ultra-low-ESR capacitors, such as ceramic chip
resistor divider between VIN and GND pins. Normally,
capacitors, may promote under-damped transient
the bias current flowing out of the VREF pin and is
response, but proper ceramic chip capacitors placed
about 150nA (typ.), creating voltage offset at the
near loads can be used as decoupling capacitors. A
resistor divider and affecting the output voltage
low-ESR solid tantalum and aluminum electrolytic
accuracy. The recommended resistor is 50µF) is recommended. It is not necessary to use low-ESR capacitors.
25
ESR (mΩ)
20
Layout and Thermal Consideration
Stable Region
15
10
The input capacitors for VIN and VCNTL pins are normally
5
placed near each pin for good performances. Ceramic
0
decoupling capacitors for loads must be placed as close
10
100
Capacitance(µF)
to the loads to reduce the parasitic inductors of traces.
1000
It is also recommended that the APL5331 and output
capacitors are placed near the load for good load
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
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APL5331
Application Information (Cont.)
Layout and Thermal Consideration (Cont.)
regulation and load transient response. The negative pins
of the input and output capacitors and the GND pin of
102 mil
the APL5331 should connect to analog ground plane
of the load.
See figure 1. The SOP-8-P utilizes a bottom thermal
118 mil
pad to minimize the thermal resistance of the package,
SOP-8-P
making the package suitable for high current
applications. The thermal pad is soldered to the top
ground pad and is connected to the internal or bottom
Die
ground plane by several vias. The printed circuit board
Thermal
pad
(PCB) forms a heat sink and dissipates most of the
heat into the ambient air. The vias are recommended
Top
ground
pad
Ambient
Air
to have proper size to retain solder, helping heat
Vias
conduction.
Internal Printed
g r o u n d circuit
plane
board
Thermal resistance consists of two main elements,
Figure 1 Package Top and side view
θJC (junction-to-case thermal resistance) and θCA (caseto-ambient thermal resistance). θJC is specified from
and is a two-layer PCB. The size and thickness are
the IC junction to the bottom of the thermal pad
65mm* 65mm and 1.6mm. An area of 140mil*105mil
directly below the die. θCA is the resistance from the
on the top layer is use as a thermal pad for the APL5331
bottom of thermal pad to the ambient air and it includes
and this is connected to the bottom layer by vias. The
θCS (case-to-sink thermal resistance) and θSA (sink-to-
bottom layer using 2 oz. copper acts as the ground
ambient thermal resistance). The specified path for
plane for the system. The PCB and all components on
heat flow is the lowest resistance path and it dissipates
majority of the heat to the ambient air. Typically, θCA is
the board form a heat sink. The θJA of the APL5331
(SOP-8-P) mounted on this demo board is about 37oC/W
the dominant thermal resistance. Therefore, enlarging
in free air. Assuming the TA=25oC and the maximum
the internal or bottom ground plane reduces the
TJ = 150oC (typical thermal limit temperature), the
resistance θ CA . The relationship between power
maximum power dissipation is calculated as :
dissipation and temperatures is the following equation:
PD (max) = (150 - 25) / 37
PD = (TJ - TA) / ≤ θJA
= 3.38W
where,
If the TJ is designed to be below 125oC, the calculated
PD : Power dissipation
power dissipation should be less than :
TJ : Junction Temperature
PD = (125 - 25) / 37
TA : Ambient Temperature
= 2.70W
θJA : Junction-to-Ambient Thermal Resistance
Figure 2 shows a board layout using the SOP-8-P
package. The demo board is made of FR-4 material
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
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APL5331
Application Information (Cont.)
APL5331
Figure 2(a) TopOver layer
Figure 2(c) Bottom layer
APL5331
Figure 2(b) Top layer
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
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APL5331
Packaging Information
E
e1
0.015X45
SOP-8 pin (Reference JEDEC Registration MS-012)
H
e2
D
A1
A
1
L
0.004max.
Dim
Millimeters
Inches
Min.
Max.
Min.
Max.
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.004
0.010
D
4.80
5.00
0.189
0.197
E
3.80
4.00
0.150
0.157
H
5.80
6.20
0.228
0.244
L
0.40
1.27
0.016
0.050
e1
0.33
0.51
0.013
e2
φ1
1.27BSC
0°
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
0.020
0.50BSC
8°
17
0°
8°
www.anpec.com.tw
APL5331
Packaging Information
E1
E
0.015X45
SOP-8-P pin ( Reference JEDEC Registration MS-012)
H
D1
e1
e2
D
A1
A
1
L
0.004max.
Dim
A
Millimeters
Inches
Min.
Max.
Min.
Max.
1.35
1.75
0.053
0.069
A1
0
0.15
0
0.006
D
4.80
5.00
0.189
0.197
D1
E
3.00REF
3.80
E1
0.118REF
4.00
0.150
2.60REF
0.157
0.102REF
H
5.80
6.20
0.228
0.244
L
0.40
1.27
0.016
0.050
e1
0.33
0.51
0.013
0.020
e2
1.27BSC
0.50BSC
φ1
8°
8°
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
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APL5331
Packaging Information
TO-252-5
H
A
J
D
M
C
B
K
L
S
Dim
A
B
C
D
P
S
H
J
K
L
M
P
Millimeters
Min.
6.40
5.20
6.80
2.20
Inches
Max.
6.80
5.50
7.20
2.80
Min.
0.25
0.20
0.26
0.08
0.80
2.40
0.55
0.15
1.50
5.80
0.02
0.08
0.01
0
0.03
0.21
1.27 REF
0.50
2.20
0.45
0
0.90
5.40
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
Max.
0.26
0.21
0.27
0.11
0.05 REF
19
0.03
0.09
0.02
0.006
0.06
0.22
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APL5331
Package Information
TO-263-5
A
C1
L
E
V
B
D
b
L2
L1
A1
C
e
e1
Dim
Millimeters
Inches
Min.
Max.
Min.
Max.
A
4.06
4.83
0.160
0.190
A1
0.00
0.15
0.000
0.006
B
1.40
1.76
0.055
0.069
b
0.50
0.99
0.020
0.039
C
0.310
0.736
0.012
0.029
C1
1.14
1.40
0.045
0.055
D
9.65
10.29
0.380
0.405
E
8.20
9.66
0.323
0.380
e
1.52
1.83
0.060
0.072
e1
6.70
6.90
0.264
0.272
L
14.60
15.88
0.575
0.625
L1
5.08
5.48
0.200
0.216
L2
2.28
2.80
0.090
0.110
V
5.600REF
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
0.220REF
20
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APL5331
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
Critical Zone
T L to T P
Temperature
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25 °C to Peak
Tim e
Classification Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
- Time (tL)
Peak/Classificatioon Temperature (Tp)
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
217°C
60-150 seconds
See table 1
See table 2
10-30 seconds
20-40 seconds
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25°C to Peak Temperature
Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
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APL5331
Classification Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures
3
3
Package Thickness
Volum e m m
Volume mm
100mA
Carrier Tape
t
D
P
Po
E
P1
Bo
F
W
Ko
Ao
D1
T2
J
C
A
B
T1
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
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APL5331
Carrier Tape(Cont.)
Application
SOP- 8
SOP-8-P
A
B
330 ± 1
F
5.5± 1
Application
TO-252
Application
TO-263
J
T1
T2
W
P
E
62 +1.5
C
12.75+
0.15
2 ± 0.5
12.4 ± 0.2
2 ± 0.2
12± 0. 3
8± 0.1
1.75±0.1
D
D1
Po
P1
Ao
Bo
Ko
t
4.0 ± 0.1
2.0 ± 0.1
6.4 ± 0.1
5.2± 0. 1
2.1± 0.1
0.3±0.013
T2
P
E
2.5± 0.5
W
16+ 0.3
- 0.1
8 ± 0.1
1.75± 0.1
1.55 +0.1 1.55+ 0.25
A
B
C
J
330 ±3
100 ± 2
13 ± 0. 5
2 ± 0.5
T1
16.4 + 0.3
-0.2
F
D
D1
Po
P1
Ao
Bo
Ko
t
7.5 ± 0.1
1.5 +0.1
1.5± 0.25
4.0 ± 0.1
2.0 ± 0.1
6.8 ± 0.1
10.4± 0.1
2.5± 0.1
0.3±0.05
A
B
C
J
T1
T2
P
E
380±3
80 ± 2
13 ± 0. 5
2 ± 0.5
24 ± 4
2± 0.3
W
24 + 0.3
- 0.1
16 ± 0.1
1.75± 0.1
F
D
D1
Po
P1
Ao
Bo
Ko
t
11.5 ± 0.1
1.5 +0.1
1.5± 0.25
4.0 ± 0.1
2.0 ± 0.1
10.8 ± 0.1
16.1± 0.1
5.2± 0.1
0.35±0.013
(mm)
Cover Tape Dimensions
Application
SOP- 8 / SOP-8-P
TO- 252
TO- 263
Carrier Width
12
16
24
Cover Tape Width
9.3
13.3
21.3
Devices Per Reel
2500
2500
1000
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright ANPEC Electronics Corp.
Rev. B.3 - Apr., 2006
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