APL5331U5C-TRL

APL5331 3A Bus Termination Regulator Features • • • • Provide Bi-direction Current General Description (Cont.) On-chip thermal shutdown provides protection against any combination of overload that would create excessive junction temperature. The output voltage of APL5331 track the voltage at VREF pin. A resistor divider connected to VIN, GND and VREF pins is used to provide a half voltage of VIN to VREF pin. In addition, an external ceramic capacitor and an opendrain transistor connected to VREF pin provides softstart and shutdown control respectively. Pulling and holding the VREF to GND shuts off the output. The output of APL5331 will be high impedance after being shut down by VREF or thermal shutdown function.  - Sourcing or Sinking Current up to 3A 1.25V/0.9V Output for DDR I/II Applications Fast Transient Response High Output Accuracy - ±20mV over Load, VOUT Offset and Temperature • • • • • Adjustable Output Voltage by External Resistors Current-Limit Protection On-Chip Thermal Shutdown Shutdown for Standby or Suspend Mode Simple SOP-8, SOP-8-P with thermal pad, TO-252- 5 and TO-263-5 Packages Pin Configuration VIN GND Applications • • • DDR I/II SDRAM Termination SSTL-2/3 Termination Voltage Applications Requiring the Regulator with 1 2 3 4 8 7 6 5 VC N TL VCN TL VCN TL VCN TL VOUT VREF VCNTL GND VIN VR EF VO U T TAB is VCNTL SOP-8 (Top View) VIN TO-252-5 (Top View) 5 4 3 2 1 VOUT VREF VCNTL GND VIN Bi-direction 3A Current Capability 1 2 3 4 8 7 6 5 NC NC General Description The APL5331 linear regulator is designed to provide a regulated voltage with bi-directional output current for DDR-SDRAM termination. The APL5331 integrates two power transistors to source or sink current up to 3A. It also incorporate current-limit, thermal shutdown and shutdown control functions into a single chip. Current-limit circuit limits the short-circuit current. GND VREF VOUT TAB is VCNTL VCNTL NC SOP-8-P (Top View) NC = No internal connection TO-263-5 (Top View) = Thermal Pad (connected to GND plane for better heat dissipation) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright  ANPEC Electronics Corp. Rev. A.8 - Oct., 2003 1 www.anpec.com.tw 1 2 3 4 5 APL5331 Ordering and Marking Information APL5331 L e a d F re e C o d e H a n d lin g C o d e Tem p. Range Package Code Package Code K : S O P -8 K A : S O P -8 -P U 5 : T O -2 5 2 -5 G 5 : T O -2 6 3 -5 Tem p. Range C : 0 to 7 0 o C H a n d lin g C o d e TR : Tape & Reel L e a d F re e C o d e L : L e a d F re e D e v ic e B la n k : O rg in a l D e v ic e X X X X X - D a te C o d e A P L 5 3 3 1 K C -T R : A P L 5 3 3 1 K A C -T R : A P L 5 3 3 1 U 5 C -T R : A P L 5 3 3 1 G 5 C -T R : AP L5331 XXXXX AP L5331 XXXXX X X X X X - D a te C o d e Pin Description PIN NAME V IN I/O I DESCRIPTION Main power input pin. Connect this pin to a voltage source and an input c apacitor. The APL5331 sources current to VOUT pin by controlling the upper N PN pass transistor, providing a current path from VIN pin. Power and signal ground. Connect this pin to system ground plane with shortest traces. The APL5331 sinks current from VOUT pin by controlling the lower NPN p ass transistor, providing a current path to GND pin. This pin is also the ground p ath for internal control circuitry. Power input pin for internal control circuitry. Connect this pin to a voltage source, p roviding a bias for the internal control circuitry. A bypass capacitor is usually c onnected near this pin. Reference voltage input and active-low shutdown control pin. Apply a voltage to this pin as a reference voltage for the APL5331. Connect this pin to a resistor d ivider, between VIN and GND, and a capacitor for soft-start and filtering noise p urposes. Applying and holding this pin low by an open-drain transistor to shut d own the output. Output pin of the regulator. Connect this pin to load. Output capacitors c onnected this pin improves stability and transient response. The output voltage tracks the reference voltage and is capable of sourcing or sinking current up to 3 A. G ND O V CNTL I V REF I V OUT O Block Diagram V C N TL V IN  V RE F V o lt a g e R e g u la t io n Th e rm a l L im it C u rre n t L im it V OUT S hutdow n G ND Copyright  ANPEC Electronics Corp. Rev. A.8 - Oct., 2003 2 www.anpec.com.tw APL5331 Absolute Maximum Ratings Symbol V CNTL V IN PD TJ T STG T SDR V ESD Parameter V CNTL Supply Voltage, VCNTL to GND V IN Supply Voltage, VIN to GND P ower Dissipation J unction Temperature S torage Temperature S oldering Temperature, 10 Seconds M inimum ESD Rating (Human Body Mode) Rating -0.2 ~ 7 -0.2 ~ 3.9 Internally Limited 150 -65 ~ 150 300 ±3 Unit V V W o o o C C C kV  Thermal Characteristics Symbol θJA Parameter Thermal Resistance in Free Air SOP-8 SOP-8-P TO-252-5 TO-263-5 Rating 160 80 80 50 Unit °C/W Recommended Operating Conditions Symbol V CNTL V IN V REF IOUT TJ Parameter V CNTL Supply Voltage V IN Supply Voltage V REF Input Voltage V OUT Output Current (Note1, 2) J unction Temperature Range 3.1 ~ 6V 1.6 ~ 3.5 0.8 ~ 1.75 -3 ~ +3 0 ~ 125 Unit V V V A o C Note1 : The symbol “+” means the VOUT sources current to load; the symbol “-“ means the VOUT sinks current to GND. Note2 : The max. IOUT varies with the TJ. Please refer to the typical characteristics.  Copyright  ANPEC Electronics Corp. Rev. A.8 - Oct., 2003 3 www.anpec.com.tw APL5331 Electrical Characteristics Refer to the typical application circuit. These specifications apply over, VCNTL=3.3V, VIN=2.5V/1.8V, VREF=0.5VIN and TJ= 0 to 125°C, unless otherwise specified. Typical values refer to TJ =25°C. S ymbol O utput Voltage V OUT V OUT Output Voltage S ystem Accuracy V OS V OUT Offset Voltage (V OUT –V REF ) L oad Regulation P rotection S ourcing Current (V IN =2.5V) Sinking Current (V IN =2.5V) Sourcing Current (V IN =1.8V) Sinking Current (V IN =1.8V) T J =25°C T J =125°C T J =25°C T J =125°C  T J =25°C T J =125°C T J =25°C T J =125°C  +3.3 -3.3 +2.9 -2.9   2     0.2 +3.6 +3.1 -3.6 -3.1 +3.2 +2.6 -3.2 -2.6 150 40 4.5 50 2.6 150 20 0.35   A     6 110  500 40 0.65 nA µA V mA o o Parameter Test Conditions APL5331 M in Typ V REF -20 -14 -6 -9 2 -3 7 12 8 20 M ax Unit IOUT =0A Over tem perature, VOUT offset, and load regulation IOUT =+10m A IOUT =-10m A IOUT =+10m A to +3A IOUT = - 10m A to -3A V mV mV mV ILIM  Current Lim it T SD   Therm al Shutdown Rising T J  Tem perature Therm al Shutdown Hysteresis  IOUT =0A C C Input Current ICNTL  VCNTL Supply Current IOUT = ± 3A (Norm al Operation), V CNTL =5V V REF =GND (Shutdown) V REF =1.25V/0.9V (Norm al O peration)  IVREF  VREF Bias Current (The current flows out of VREF) V REF =GND (Shutdown)  Shutdown Threshold Voltage   S hutdow n Control   Copyright  ANPEC Electronics Corp. Rev. A.8 - Oct., 2003 4 www.anpec.com.tw APL5331 Typical Application Circuit 1. VOUT=1.25V/0.9V Application VC N TL +3.3V VIN +2.5V/1.8 V R1 1k C IN 4 70 uF Shu tdo w n Q1 GN D R2 1k VR EF C SS 0 .1 uF C C N TL 4 7u F VI N VC N TL VR EF GND VO U T VOU T +1.25 V/0 .9V -3~+3 A C OU T 4 70 uF GN D COUT : 470µF, ESR=25mΩ R1, R2 : 1kΩ, 1% Q1 : APM2300 AC Note : Since R1 and R2 are very small, the voltage offset caused by the bias current of VREF can be ignore. 2. VOUT=1.4V Application VCNT L +5V VIN +2.8V R1 1k C IN 470 µ F R2 1k GND VRE F CSS 0.1 µ F C CNT L 47 µ F C O UT 470 µ F GND VIN VC N TL VR E F GN D VOU T VO UT +1.4V/ -3~+3 A Copyright  ANPEC Electronics Corp. Rev. A.8 - Oct., 2003 5 www.anpec.com.tw APL5331 Typical Characteristics Sourcing Current-Limit vs Junction Temperature 5.0 VCNTL=5V,VIN=2.5V Sinking Current-Limit vs Junction Temperature -2.0 VCNTL=5V,VIN=1.8V VCNTL=3.3V,VIN=1.8V Current-Limit, ILIM (A) 4.0 Current-Limit, ILIM (A) 4.5 VCNTL=3.3V,VIN=2.5V -2.5 -3.0 3.5 3.0 -3.5 -4.0 VCNTL=5V,VIN=2.5V VCNTL=3.3V,VIN=2.5V VCNTL=5V,VIN=1.8V VCNTL=3.3V,VIN=1.8V 2.5 -4.5 2.0 -50 -25 0 25 50 75 100 125 -5.0 -50 -25 0 25 50 75 100 125 Junction Temperature (°C) Junction Temperature (°C) VREF Bias Current vs Junction Temperature 0.40 0.6 VREF Shutdown Threshold vs Junction Temperature VREF Shutdown Threshold (V) VREF Bias Current, IVREF (µA) VREF=1.25V/0.9V 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 -50 -25 0 25 50 75 100 125 0.5 VCNTL=5V 0.4 0.3 VCNTL=3.3V 0.2 0.1 -50 -25 0 25 50 75 100 125 Junction Temperature (°C) Junction Temperature (°C) Copyright  ANPEC Electronics Corp. Rev. A.8 - Oct., 2003 6 www.anpec.com.tw APL5331 Typical Characteristics (Cont.) VOUT Offset Voltage vs Junction Temperature 6 7.0 Quiescent VCNTL Current vs Junction Temperature Quiescent VCNTL Current (mA) 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 VOUT Offset Voltage, VOS (mV) 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16 -50 VREF=1.25V/0.9V IOUT=0A VCNTL=5V IOUT=-10mA VCNTL=3.3V IOUT=+10mA -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Junction Temperature (°C) Junction Temperature (°C) VREF Bias Current vs VREF Supply Voltage 22 VREF Bias Current, IVREF (µA) 20 18 16 14 12 10 8 6 4 2 0 0.0 TJ=25°C 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VREF Supply Votage, VREF (V) Copyright  ANPEC Electronics Corp. Rev. A.8 - Oct., 2003 7 www.anpec.com.tw APL5331 Operating Waveforms 1. Load Transient Response : IOUT = +10mA -> +3A -> +10mA - VIN = 2.5V, VCNTL = 3.3V - VREF is 1.250V supplied by a regulator - COUT = 470µF/10V, ESR = 30mΩ - IOUT slew rate = ±3A/µS IOUT = +10mA -> +3A IOUT = +10mA -> +3A -> +10mA Load Regulation = -2.8mV IOUT = +3A -> +10mA VOUT IOUT VOUT VOUT +3A +10mA IOUT IOUT Ch1 : VOUT, 20mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 1A/Div Time : 1µS/Div Ch1 : VOUT, 20mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 1A/Div Time : 20µS/Div Ch1 : VOUT, 20mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 1A/Div Time : 1µS/Div 2. Load Transient Response : IOUT = -10mA -> -3A -> -10mA - VIN = 2.5V, VCNTL = 3.3V - VREF is 1.250V supplied by a regulator - COUT = 470µF/10V, ESR = 30mΩ - IOUT slew rate = ±3A/µS IOUT = -10mA -> -3A VOUT IOUT = -10mA -> -3A -> -10mA Load Regulation = +6.2mV IOUT = -3A -> -10mA VOUT VOUT -10mA IOUT IOUT IOUT -3A Ch1 : VOUT, 20mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 1A/Div Time : 1µS/Div Copyright  ANPEC Electronics Corp. Rev. A.8 - Oct., 2003 Ch1 : VOUT, 20mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 1A/Div Time : 20µS/Div 8 Ch1 : VOUT, 20mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 1A/Div Time : 1µS/Div www.anpec.com.tw APL5331 Operating Waveforms (Cont.) 3. Load Transient Response : IOUT = +3A -> -3A -> +3A - VIN = 2.5V, VCNTL = 3.3V - VREF is 1.250V supplied by a regulator - COUT = 470µF/10V, ESR = 30mΩ - IOUT slew rate = ±3A/µS IOUT = +3A -> -3A VOUT IOUT = +3A -> -3A -> +3A IOUT = -3A -> +3A VOUT VOUT IOUT +3A IOUT IOUT -3A Ch1 : VOUT, 50mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 2A/Div Time : 1µS/Div Ch1 : VOUT, 50mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 2A/Div Time : 20µS/Div Ch1 : VOUT, 50mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 2A/Div Time : 1µS/Div 4. Short-Circuit Test - VIN = 2.5V, VCNTL = 3.3V VOUT is Shorted to GND IOUT IOUT VOUT is Shorted to VIN (2.5V) VOUT VOUT VOUT IOUT Ch1 : VOUT, 500mV/Div, DC, Ax1 : IOUT, 2A/Div Time : 5mS/Div Ch1 : VOUT, 500mV/Div, DC, Ax1 : IOUT, 2A/Div Time : 5mS/Div Copyright  ANPEC Electronics Corp. Rev. A.8 - Oct., 2003 9 www.anpec.com.tw APL5331 Application Information General The APL5331 is a linear regulator and is capable of sourcing or sinking current up to 3A. The APL5331 has fast transient response, accurate output voltage (small voltage offset, load regulation), active-low shutdown control and fault protections (current-limit, thermal shutdown). The APL5331 is available in several packages to meet different of power dissipation in requirement various applications. Output Voltage Regulation The output voltage at VOUT pin tracks the reference voltage applied at VREF pin. Two internal NPN pass transistors controlled by separate high bandwidth error amplifiers regulate the output voltage by sourcing current from VIN pin or sinking current to GND pin. The base currents of the pass transistors are provided by VCNTL pin. An internal kelvin sensing scheme use at the VOUT pin for perfect load regulation at various load current. To prevent the two pass transistors from shoot-through, a small voltage offset is created between the positive inputs of the two error amplifiers. This results in higher output voltage while the regulator sinks light or heavy load current. Since the APL5331 exhibits very fast load transient response, lesser amount of capacitors can be use. In addition, capacitors with high ESR can also be use. Current Limit The APL5331 monitors sourcing and sinking current, and limits the maximum output current to prevent damages during overload or short-circuit, To increase the input voltage of VIN or VCNTL will get higher current-limit points. Shutdown and Soft-Start The VREF pin is a dual-function input pin, acting as reference input and shutdown control input. Applying and holding a voltage below 0.35V(typ.) to VREF pin shuts down the output of the regulator. An NPN transistor or N-channel MOSFET is used to pull down the VREF while applying a “high” signal to turn on the transistor. When shutdown function is active, the two pass transistors are turned off and the impedance of the VOUT is about 10MΩ (typ.), sourcing or sinking no current. When release the VREF pin, the current through the resistor divider charges the softstart capacitor to initiate a soft-start cycle. The output voltage tracks the rising VREF. The soft start process limits the input surge current. Thermal Shutdown An thermal shutdown circuit limits the junction temperature of the APL5331. When the junction temperature exceeds TJ= +150oC, a thermal sensor turns off both pass transistors, allowing the device to cool down. The regulator starts to regulate again after the junction temperature reduces by 40oC, resulting in a pulsed output during continuous thermal overload conditions. The thermal limit designed with a 40oC hysteresis lowers the average TJ during continuous thermal overload conditions, extend life time of APL5331. Copyright  ANPEC Electronics Corp. Rev. A.8 - Oct., 2003 10 www.anpec.com.tw APL5331 Application Information Power Inputs Input power sequence are not required for VIN and VCNTL. However, do not apply a voltage to VOUT when there is not voltage VCNTL. This is due to the internal parasitic diodes between VOUT to VIN and VOUT to VCNTL which will be forward bias. The APL5331 can source few current or sinks current up to 3A for load when the input Voltage at VIN is not present. Reference Voltage A reference voltage is applied at the VREF pin by a resistor divider between VIN and GND pins. Normally the bias current of the VREF pin flows out of the IC and is about 150nA(typ.), creating voltage offset at the resistor divider and affecting the output voltage accuracy. The recommended resistor is 2 K V, V M M > 2 0 0 V 1 0 m s , I tr > 1 0 0 m A Carrier Tape t P P1 D Po E F W Bo Ao Ko D1 T2 J C A B T1 Copyright  ANPEC Electronics Corp. Rev. A.8 - Oct., 2003 19 www.anpec.com.tw APL5331 Application SOP- 8 SOP-8-P Application A 330 ± 1 F 5.5± 1 A 330 ±3 TO-252 F 7.5 ± 0.1 Application A 380±3 TO-263 F 11.5 ± 0.1 B 62 +1.5 D C 12.75+ 0.15 D1 J 2 ± 0.5 Po 4.0 ± 0.1 J 2 ± 0.5 Po 4.0 ± 0.1 J 2 ± 0.5 Po 4.0 ± 0.1 T1 12.4 ± 0.2 P1 2.0 ± 0.1 T1 16.4 + 0.3 -0.2 P1 2.0 ± 0.1 T1 24 ± 4 P1 2.0 ± 0.1 T2 2 ± 0.2 Ao 6.4 ± 0.1 T2 2.5± 0.5 Ao 6.8 ± 0.1 T2 2± 0.3 Ao 10.8 ± 0.1 W 12± 0. 3 Bo 5.2± 0. 1 W 16+ 0.3 - 0.1 Bo 10.4± 0.1 W 24 + 0.3 - 0.1 Bo 16.1± 0.1 P 8± 0.1 Ko 2.1± 0.1 P 8 ± 0.1 Ko 2.5± 0.1 P 16 ± 0.1 Ko 5.2± 0.1 E 1.75±0.1 t 0.3±0.013 E 1.75± 0.1 t 0.3±0.05 E 1.75± 0.1 t 0.35±0.013 1.55 +0.1 1.55+ 0.25 B 100 ± 2 D 1.5 +0.1 B 80 ± 2 D 1.5 +0.1 C 13 ± 0. 5 D1 1.5± 0.25 C 13 ± 0. 5 D1 1.5± 0.25 Cover Tape Dimensions Application SOP- 8 / SOP-8-P TO- 252 TO- 263 Carrier Width 12 16 24 Cover Tape Width 9.3 13.3 21.3 Devices Per Reel 2500 2500 1000 Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright  ANPEC Electronics Corp. Rev. A.8 - Oct., 2003 20 www.anpec.com.tw