APL5336KAI-TRG

APL5336 Source and Sink, 1.5A, Fast Transient Response Linear Regulator Features • • • • • • • • • • • • Provide Bi-direction Output Currents -Sourcing and Sinking Current up to 1.5A Built-in Soft-Start Power-On-Reset Monitoring on VCNTL and VIN pins Fast Transient Response Stable with Ceramic Output Capacitors ±20mV High System Output Accuracy over Load and Temperature Ranges Adjustable Output Voltage by External Resistors Current-Limit Protection On-Chip Thermal Shutdown Shutdown for Standby or Suspend Mode Simple SOP-8 and SOP-8 with Exposed Pad (SOP-8P) Packages Lead Free and Green Devices Available (RoHS Compliant) General Description The APL5336 linear regulator is designed to provide a regulated voltage with bi-direction output current for DDRSDRAM termination voltage. The APL5336 integrates two power transistors to source or sink load current up to 1.5A. It also features internal soft-start, current-limit, thermal shutdown and enable control functions into a single chip. The internal soft-start controls the rising rate of the output voltage to prevent inrush current during start-up. The current-limit circuit detects the output current and limits the current during short-circuit or current overload conditions. The on-chip thermal shutdown provides thermal protection against any combination of overload that would create excessive junction temperatures. The output voltage of APL5336 is regulated to track the voltage on VREF pin. An proper resistor divider connected to VIN, GND, and VREF pins is used to provide a half voltage of VIN to VREF pin. In addition, connect an external ceramic capacitor and a open-drain transistor to VREF pin for external soft-start and shutdown control. Pulling and holding the voltage on VREF below the enable voltage threshold shuts down the output. The output of APL5336 will be high impedance after being shut down by VREF or the thermal shutdown function. Applications • • • • DDRII/III SDRAM Termination Voltage Motherboard and VGA Card Power Supplies Setop Box SSTL-2/3 Termination Voltage Pin Configuration VIN 1 GND 2 VREF 3 VOUT 4 8 VCNTL 7 VCNTL 6 VCNTL 5 VCNTL Simplified Application Circuit VCNTL +5V VIN +1.8V/+1.5V 1 VIN VCNTL 6 Top View of SOP-8 VOUT 0.9V / 0.75V 3 APL5336 VREF VOUT GND 2 4 VIN 1 GND 2 VREF 3 VOUT 4 8 NC 7 NC 6 VCNTL 5 NC Shutdown Enable Top View of SOP-8P Exposed Pad (connected to GND plane for better heat dissipation) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright © ANPEC Electronics Corp. Rev. A.2 - Apr., 2008 1 www.anpec.com.tw APL5336 Ordering and Marking Information APL5336 Assembly Material Handling Code Temperature Range Package Code Package Code K : SOP-8 KA : SOP-8P Operating Ambient Temperature Range I : -40 to 85 ° C Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device XXXXX - Date Code APL5336 K: APL5336 XXXXX APL5336 KA: APL5336 XXXXX Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol VCNTL VIN VREF VOUT PD TJ TSTG TSDR (Note 1) Rating -0.3 ~ 7 -0.3 ~ 7 -0.3 ~ 7 -0.3 ~ VIN+0.3V Internally Limited 150 -65 ~ 150 260 Unit V V V V W o Parameter VCNTL Supply Voltage (VCNTL to GND) VIN Supply Voltage (VIN to GND) VREF Input Voltage (VREF to GND) VOUT Output Voltage (VOUT to GND) Power Dissipation Junction Temperature Storage Temperature Range Maximum Lead Soldering Temperature, 10 Seconds C C o o C Note 1: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. Thermal Characteristics Symbol Parameter Junction-to-Ambient Thermal Resistance in Free Air (Note 2) SOP-8 SOP-8P θJC Junction-to-Case Thermal Resistance in Free Air (Note 3) SOP-8P Rating 80 55 o Unit °C/W θJA 20 C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Note 3: The exposed pad of SOP-8P is soldered directly on the PCB. The case temperature is measured at the center of the exposed pad on the underside of the SOP-8P package. Recommended Operating Conditions Symbol VCNTL VIN VREF VOUT VCNTL Supply Voltage VIN Supply Voltage VREF Input Voltage VOUT Output Voltage Parameter Range 3.0 ~ 5.5 1.2 ~ 5.5 0.7 ~ VCNTL – 2.2 VREF ± 0.02 Unit V V V V C opyright © A NPEC Electronics Corp. Rev. A.2 - Apr., 2008 2 www.anpec.com.tw APL5336 Recommended Operating Conditions (Cont.) Symbol IOUT CIN VOUT Output Current (Note 4) Capacitance of Input Capacitor Equivalent Series Resistor (ESR) of Input Capacitor COUT Capacitance of Output Multi-layer Ceramic Capacitor (MLCC) Total Output Capacitance (Note 5) TA TJ Ambient Temperature Junction Temperature Parameter Range -1.5 ~ +1.5 10 ~ 100 0 ~ 200 8 ~ 47 10 ~ 330 -40 ~ 85 -40 ~ 125 Unit A µF mΩ µF µF o o C C Note 4: The symbol “+” means the VOUT sources current to load; the symbol “-” means the VOUT sinks current from load to GND. Note 5: It’ necessary to use a multi-layer ceramic capacitor 8µF at least as an output capacitor. Please place the ceramic capacitor near VOUT pin s as close as possible. Besides, the other kinds of capacitors (like Electrolytic, PoSCap, tantalum capacitors) can be used as the output capacitors in parallel. Electrical Characteristics Refer to the typical application circuit. These specifications apply over VCNTL=5V, VIN=1.8V or 1.5V, VREF=0.5VIN, CIN=10µF, COUT=10µF (MLCC) and TA= -40~85°C, unless otherwise specified. Typical values are at TA=25°C. Symbol SUPPLY CURRENT ICNTL IVIN Parameter Test Conditions APL5336 Min Typ 1 Max 2 5 5 Unit VCNTL Supply Current VIN Supply Current at Shutdown IOUT= 0A VREF=0V (Shutdown) VREF = GND (Shutdown) mA µA µA V V POWER-ON-RESET (POR) Rising VCNTL POR Threshold VCNTL POR Hysteresis Rising VIN POR Threshold VIN POR Hysteresis OUTPUT VOLTAGE VOUT VOUT Output Voltage System Accuracy VOS VOUT Offset Voltage (VOUT -VREF) Load Regulation IOUT=0A, VREF=0.7V ~ 2.8V Over temperature and load current ranges IOUT=+10mA IOUT=-10mA IOUT=+10mA ~ +1.5A IOUT=-10mA ~ -1.5A -20 -7 -13 VREF -1 +8 -8 +4 20 +12 +8 V mV mV VIN Rising VCNTL Rising 2.5 0.7 2.75 0.35 0.9 0.3 2.9 1.05 V mV C opyright © A NPEC Electronics Corp. Rev. A.2 - Apr., 2008 3 www.anpec.com.tw APL5336 Electrical Characteristics (Cont.) Refer to the typical application circuit. These specifications apply over VCNTL=5V, VIN=1.8V or 1.5V, VREF=0.5VIN, CIN=10µF, COUT=10µF (MLCC) and TA= -40~85°C, unless otherwise specified. Typical values are at TA=25°C. Symbol PROTECTIONS Parameter Test Conditions APL5336 Min 1.8 1.6 -2 -1.6 1.6 1.1 -1.6 -1.1 0.15 -100 0.1 Typ 2 -2.2 1.8 -1.8 150 40 0.3 0.2 Max 3 -3 2.6 -2.6 0.4 +100 0.4 Unit Sourcing Current (VIN=1.8V) Sinking Current (VIN=1.8V) ILIM Current-Limit Sourcing Current (VIN=1.5V) Sinking Current (VIN=1.5V) TSD Thermal Shutdown Temperature Thermal Shutdown Hysteresis ENABLE and SOFT-START VREF Enable Voltage Threshold IVREF TSS VREF Bias Current Soft-Start Interval TJ rising TJ=25oC TJ=125 C TJ=25oC TJ=125oC TJ=25oC TJ=125oC TJ=25 C TJ=125oC o o A A o C V nA ms C opyright © A NPEC Electronics Corp. Rev. A.2 - Apr., 2008 4 www.anpec.com.tw APL5336 Typical Operating Characteristics VOUT Offset Voltage vs. Junction Temperature 10 Sourcing Current-Limit vs. Junction Temperature 3.5 3 VOUT Offset Voltage,VOS (mV) 8 6 Current-Limit,ILIM (A) IOUT= -10mA 4 2 0 2.5 2 1.5 1 0.5 0 IOUT= 10mA VIN=2.5V VIN=1.8V VIN=1.5V Sourcing Current VREF=0.5xVIN VCNTL=5V -50 -25 0 25 50 75 100 125 -2 -4 -50 VIN=1.5V -25 0 25 50 75 100 125 150 Junction Temperature (TJ ,oC) Sinking Current-Limit vs. Junction Temperature 4 3.5 Junction Temperature (TJ ,oC) 0 -10 VCNTL Power Supply Rejection Ratio (PSRR) VCNTL=5V, COUT=10µF(MLCC) VREF=0.5xVIN Current-Limit,ILIM (A) 2.5 2 1.5 1 0.5 0 -50 VCNTL PSRR (dB) 3 -20 -30 -40 -50 -60 -70 -80 1000 VIN=1.5V,IOUT=1.5A VIN=1.5V,IOUT=0.5A 10000 100000 1000000 VIN=2.5V VIN=1.8V VIN=1.5V Sinking Current VREF=0.5xVIN VCNTL=5V -25 0 25 50 75 100 125 VIN=2.5V,IOUT=1.5A VIN=2.5V,IOUT=0.5A Junction Temperature (TJ ,oC) Frequency (HZ) Sourcing Current-Limit vs. Junction Temperature 2.5 3 Sinking Current-Limit vs. Junction Temperature Current-Limit,ILIM (A) Current-Limit,ILIM (A) 2 VIN=1.8V 2.5 2 1.5 1.5 1 VIN=1.5V VIN=1.8V VIN=1.5V 1 0.5 0 Sourcing Current VREF=0.5xVIN VCNTL=3.3V -50 -25 0 25 50 75 100 125 0.5 Sinking Current VREF=0.5xVIN VCNTL=3.3V -50 -25 0 25 50 75 100 125 0 Junction Temperature (oC) Junction Temperature (oC) C opyright © A NPEC Electronics Corp. Rev. A.2 - Apr., 2008 5 www.anpec.com.tw APL5336 Operating Waveforms VCNTL = 5V, V IN = 1.8V or 1.5V, VREF=0.5xVIN, CIN=COUT=10µF(MLCC) Load Transient Response (VIN=1.8V) IOUT=10mA to 1.5A to 10mA VOUT 1 1 Load Transient Response (VIN=1.8V) IOUT=10mA to 1.5A VOUT IOUT IOUT 2 2 CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 200µs/Div CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 1µs/Div Load Transient Response (VIN=1.8V) IOUT=1.5A to 10mA VOUT 1 Load Transient Response (VIN=1.8V) IOUT=-10mA to -1.5A to -10mA VOUT 1 IOUT 2 IOUT 2 CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 200µs/Div C opyright © A NPEC Electronics Corp. Rev. A.2 - Apr., 2008 6 www.anpec.com.tw APL5336 Operating Waveforms (Cont.) VCNTL = 5V, V IN = 1.8V or 1.5V, VREF=0.5xVIN, CIN=COUT=10µF(MLCC) Load Transient Response (VIN=1.8V) IOUT=-10mA to -1.5A VOUT 1 Load Transient Response (VIN=1.8V) IOUT=-1.5A to -10mA VOUT 1 IOUT 2 IOUT 2 CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 1µs/Div CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 1µs/Div Load Transient Response (VIN=1.5V) IOUT=10mA to 1A to 10mA VOUT 1 1 Load Transient Response (VIN=1.5V) IOUT=10mA to 1A VOUT IOUT IOUT 2 2 CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 200µs/Div CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 1µs/Div C opyright © A NPEC Electronics Corp. Rev. A.2 - Apr., 2008 7 www.anpec.com.tw APL5336 Operating Waveforms (Cont.) VCNTL = 5V, V IN = 1.8V or 1.5V, VREF=0.5xVIN, CIN=COUT=10µF(MLCC) Load Transient Response (VIN=1.5V) IOUT=1A to 10mA VOUT 1 1 Load Transient Response (VIN=1.5V) IOUT=-10mA to -1A to -10mA VOUT 2 IOUT IOUT 2 CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 1µs/Div CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 200µs/Div Load Transient Response (VIN=1.5V) IOUT=-10mA to -1A VOUT 1 1 Load Transient Response (VIN=1.5V) IOUT=-1A to -10mA VOUT 2 2 IOUT IOUT CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 1µs/Div CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 1µs/Div C opyright © A NPEC Electronics Corp. Rev. A.2 - Apr., 2008 8 www.anpec.com.tw APL5336 Operating Waveforms (Cont.) VCNTL = 5V, V IN = 1.8V or 1.5V, VREF=0.5xVIN, CIN=COUT=10µF(MLCC) Power ON Test (VIN=1.8V) RLoad=1 Ω VIN Power OFF Test (VIN=1.8V) RLoad=1 Ω VIN 1 VOUT 1 VOUT 2 3 IOUT 2 3 IOUT CH1: VIN, 1V/Div, DC CH2: VOUT, 500mV/Div, DC CH3: IOUT, 1A/Div, DC TIME: 50ms/Div CH1: VIN, 1V/Div, DC CH2: VOUT, 500mV/Div, DC CH3: IOUT, 1A/Div, DC TIME: 5ms/Div Power ON Test (VIN=1.5V) RLoad=1 Ω VIN Power OFF Test (VIN=1.5V) RLoad=1 Ω VIN 1 VOUT 1 VOUT 2 3 IOUT 2 3 IOUT CH1: VIN, 1V/Div, DC CH2: VOUT, 500mV/Div, DC CH3: IOUT, 1A/Div, DC TIME: 50ms/Div CH1: VIN, 1V/Div, DC CH2: VOUT, 500mV/Div, DC CH3: IOUT, 1A/Div, DC TIME: 5ms/Div C opyright © A NPEC Electronics Corp. Rev. A.2 - Apr., 2008 9 www.anpec.com.tw APL5336 Pin Description PIN NO. 1 PIN NAME VIN FUNCTION Main Power Input Pin. Connect this pin to a voltage source and an input capacitor. The APL5336 sources current to VOUT pin by controlling the upper pass MOSFET, providing a current path from VIN to VOUT. Power and Signal Ground. Connect this pin to system ground plane with shortest traces. The APL5336 sinks current from VOUT pin by controlling the lower pass MOSFET, providing a current path from VOUT to GND. This pin is also the ground path for internal control circuitry. Reference Voltage Input and Active-high Enable Control Pin. Apply a voltage to this pin as a reference voltage for the APL5336. Connect this pin to a resistor diver, between VIN and GND, and a capacitor for filtering noise purpose. Applying and holding the voltage below the enable voltage threshold on this pin by an open-drain transistor shuts down the output. During shutdown, the VOUT pin has high input impedance. Output Pin of The Regulator. Connect this pin to load and output capacitors (>8µF MLCC is necessary) required for stability and improving transient response. The output voltage is regulated to track the reference voltage and capable of sourcing or sinking current up to 1.5A. No Internal Connection. Power Input Pin for Internal Control Circuitry. Connect this pin to a voltage source, providing a bias for the internal control circuitry. A decoupling capacitor is connected near this pin. Chip Substrate Connection of The Chip. Connect this pad to system ground plane for good thermal conductivity. 2 GND 3 VREF 4 VOUT 5, 7, 8 (SOP-8P) 5 ~ 8 (SOP-8) 6 (SOP-8P) Exposed Pad (SOP-8P only) NC VCNTL GND Block Diagram VCNTL VIN Power-OnReset EN VREF Enable POR VREF Error Amplifier and Soft-Start Thermal Shutdown THSD VOUT CurrentLimit GND C opyright © A NPEC Electronics Corp. Rev. A.2 - Apr., 2008 10 www.anpec.com.tw APL5336 Typical Application Circuit VCNTL +5V VIN +1.8V/+1.5V 1 C2 47µF VIN R1 100kΩ VCNTL APL5336 GND VOUT 6 C1 1µF VOUT 0.9V/0.75V C5 10µF C3 100µF (optional) 3 VREF 2 4 Shutdown Q1 Enable VREF R2 100kΩ C4 1µF The ceramic capacitor C5 ( at least 8µF) is necessary for output stability. Function Description Power-On-Reset A Power-On-Reset (POR) circuit monitors both input voltages at VCNTL and VIN pins to prevent wrong logic controls. The POR function initiates a soft-start process after both of the supply voltages exceed their rising POR voltage thresholds during powering on. Output Voltage Regulation The output voltage on VOUT pin is regulated to track the reference voltage applied on VREF pin. Two internal Nchannel power MOSFETs controlled by high bandwidth error amplifiers regulate the output voltage by sourcing current from VIN pin or sinking current to GND pin. An internal output voltage sense pad is bonded to the VOUT pin with a bonding wire for perfect load regulation. For preventing the two power MOSFETs from shootthrough, a small voltage offset between the positive inputs of the two error amplifiers is designed. It results in higher output voltage while the regulator sinks light or heavy load current. The APL5336 provides very fast load transient response at small output capacitance to save total cost. Current-Limit The APL5336 monitors the output current, both sourcing and sinking current, and limits the maximum output current to prevent damages during current overload or shortcircuit (shorted from VOUT to GND or VIN) conditions. Enable The VREF pin is a multi-function input pin which is the reference voltage input pin and the enable control input pin. Applying and holding the voltage (VREF) on VREF beC opyright © A NPEC Electronics Corp. Rev. A.2 - Apr., 2008 11 low 0.3V (typical) shuts down the output of the regulator. In the typical application, an NPN transistor or N-channel MOSFET is used to pull down the VREF while applying a “high” signal to turn on the transistor. When shutdown function is active, both of the internal power MOSFETs are turned off and the impedance of the VOUT pin is larger than 10MΩ. Internal and External Soft-Start The APL5336 is designed with an internal soft-start function to control the rise rate of the output voltage to prevent inrush current during start-up. When release the pull-low transistor connected with VREF pin, the current via the resistor divider charges the external soft-start capacitor (C4) and the VREF starts to rise up. The IC starts a soft-start process when the VREF reaches the enable voltage threshold. The output voltage is regulated to follow the lower voltage, which is either the internal soft-start voltage ramp or the VREF voltage, to rise up. The external soft-start interval is programmable by the resistor-divider and the soft-start capacitor (C4). Thermal Shutdown The thermal shutdown circuit limits the junction temperature of the APL5336. When the junction temperature exceeds 150 C, a thermal sensor turns off the both pass transistors, allowing the device to cool down. The thermal sensor allows the regulator to regulate again after o the junction temperature cools by 40 C, resulting in a pulsed output during continuous thermal overload o conditions. The thermal limit is designed with a 40 C hysteresis to lower the average TJ during continuous thermal overload conditions, increasing lifetime of the APL5336. www.anpec.com.tw o APL5336 Application Information Power Sequencing The input sequence of powers applied for VIN and VCNTL is not necessary to be concerned. Reference Voltage A reference voltage is applied at the VREF pin by a resistor divider between VIN and GND pins. An external bypass capacitor is also connected to VREF. The capacitor and the resistor divider form a low-pass filter to reduce the inherent reference noise from VIN. The capacitor is a 0.1µF or greater ceramic capacitor and connected as close to VREF as possible. More capacitance and large resistor divider will increase the soft-start interval. Do not place any additional loading on this reference input pin. Input Capacitor The APL5336 requires proper input capacitors to supply current surge during stepping load transients to prevent the input rail from dropping. Because the parasitic inductors from the voltage sources or other bulk capacitors to the VIN pin limit the slew rate of the input current, more parasitic inductance needs more input capacitance. For the APL5336, the total capacitance of input capacitors value including MLCC and aluminum electrolytic capacitors should be larger than 10µF. For VCNTL pin, a capacitor of 0.47µF (MLCC) or above is recommended for noise decoupling. Output Capacitor The APL5336 needs a proper output capacitor to maintain circuit stability and improve transient response. In order to insure the circuit stability, a 10µF X5R or X7R MLCC output capacitor is sufficient at all operating temperatures and it must be placed near the VOUT. The maximum distance from output capacitor to VOUT must within 10mm. Total output capacitors value including MLCC and aluminum electrolytic capacitors should be larger than 10µF. Table 1 provides the suitable output capacitors for APL5336 Vendor Murata Description 10µF, 6.3V, X7R, 0805, GRM21BR70J106K 10µF, 6.3V, X5R, 0805, GRM21BR60J106K Murata website: www.murata.com Table 1: Output Capacitor Guide Operation Region and Power Dissipation The APL5336 maximum power dissipation depends on the thermal resistance and temperature difference between the die junction and ambient air. The power dissipation PD across the device is: PD ≤ (TJ − TA ) θJA Where (TJ-TA) is the temperature difference between the junction and ambient air. θJA i s the thermal resistance between junction and ambient air. Assuming the TA=25 C o and maximum TJ=150 C (typical thermal limit threshold), the maximum power dissipation is calculated as: o PD(max) = (150 − 25) 80 = 1.56( W ) o For normal operation, do not exceed the maximum junction temperature of TJ = 125 C. The calculated power dissipation should less than: PD = (125 − 25) 80 = 1.25( W ) PCB Layout Consideration Figure 1 illustrates the layout. Below is a checklist for your layout: 1. Please place the input capacitors close to the VIN. 2. Please place the output capacitors close to the VOUT, a MLCC capacitor larger than 8 µF m ust be p laced near the VOUT. The distance from VOUT to output MLCC must be less than 10mm. 3. To place APL5336 and output capacitors near the load is good for load transient response. C opyright © A NPEC Electronics Corp. Rev. A.2 - Apr., 2008 12 www.anpec.com.tw APL5336 Application Information (Cont.) PCB Layout Consideration (Cont.) 4. Large current paths, the bold lines in Figure 1, must have wide tracks. 5. For SOP-8P package, please solder the thermal pad to the APL5336 to top-layer ground plane. Numerous vias 0.254mm in diameter should be used to connect both top-layer and internal ground planes. The ground planes and PCB form a heat sink to channel major power dissipation of the APL5336 into ambient air. Large ground plane is good for heatsinking. Optimum performance can only be achieved when the device is mounted on a PC board according to the board layout diagrams which are shown as Figure 2. 1 2 0.050 3 4 1 2 0.050 3 4 Recommended Minimum Footprint 0.024 0.072 8 7 6 5 8 7 6 0.024 0.072 0.118 Unit : Inch SOP-8P 5 0.138 0.212 Unit : Inch SOP-8 APL5336 VIN C2 VCNTL VREF VOUT GND C5 C3 (optional) Figure 1 VCNTL For dissipating heat C2 + Ground C5 C3 + VIN SOP-8 200V 10ms, 1tr > 100mA Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Time 25°C to Peak Temperature Sn-Pb Eutectic Assembly 3°C/second max. 100°C 150°C 60-120 seconds 183°C 60-150 seconds See table 1 10-30 seconds 6°C/second max. 6 minutes max. Pb-Free Assembly 3°C/second max. 150°C 200°C 60-180 seconds 217°C 60-150 seconds See table 2 20-40 seconds 6°C/second max. 8 minutes max. Note: All temperatures refer to topside of the package. Measured on the body surface. C opyright © A NPEC Electronics Corp. Rev. A.2 - Apr., 2008 17 www.anpec.com.tw APL5336 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures Package Thickness