APL5610CI-TRG

APL5610/A Low Dropout Linear Regulator Controller Features • • • • • • • • • • Wide Supply Voltage Range from 4.5 to 13.5V High Output Accuracy Over Operating Temperature and Loading Ranges Fast Transient Response Power-On-Reset Monitoring on VCC Internal Soft-Start Function Low Shutdown Current: < 5µA Enable Control Function Under-Voltage Protection Power-OK Output with a Delay Time Two Versions of IC Available: - APL5610: UVP Activated after VOUT is Ready - APL5610A: UVP Activated after VCC is Supplied General Description The APL5610/A is a low dropout linear regulator controller. The APL5610/A could drive an external N-Channel MOSFET and provides an adjustable output by using an external resistive divider. The APL5610/A integrates various functions. For example, a Power-On-Reset (POR) circuit monitors VCC supply voltage to prevent wrong operations; the function of Under-Voltage Protection (UVP) protects the device from short circuit condition. A POK indicates that the output status with time delay which is set internally. It can control other converter for power sequence. Moreover, the APL5610/A can be enabled by other power system; namely, holding the EN above 1.6V enables output and pulling the EN under 0.4 disables output. The APL5610/A is available in SOT-23-6 package. • • SOT-23-6 Package Lead Free and Green Devices Available (RoHS Compliant) Simplified Application Circuit VCC VIN ON EN EN VCC DRV Applications • • Note Book PC Applications Motherboard Applications OFF Pin Configuration APL5610/A EN 1 GND 2 FB 3 SOT-23-6 (Top View) 6 VCC 5 DRV 4 POK APL5610 APL5610A POK POK GND FB VOUT - ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. C opyright © A NPEC Electronics Corp. Rev. A.4 - Sep., 2009 1 www.anpec.com.tw APL5610/A Ordering and Marking Information APL5610 APL5610A Assembly Material Handling Code Temperature Range Package Code APL5610 C: APL5610A C: L10X LA0X Package Code C : SOT-23-6 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device X - Date Code X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1 ) Symbol VCC VFB VDRV TJ TSTG TSDR EN, POK, to GND Voltage FB to GND Voltage DRV to GND Voltage Maximum Junction Temperature Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds Parameter VCC Input Voltage (VCC to GND) Rating -0.3 to 15 -0.3 to 7 -0.3 to 7 -0.3 to VCC+0.3 150 -65 to 150 260 Unit V V V V o C C C o o Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristic Symbol θJA Parameter Junction-to-Ambient Resistance in Free Air (Note 2) Typical Value SOT-23-6 250 Unit o C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions (Note 3) Symbol VCC VEN VOUT TA TJ EN to GND Voltage VOUT Output Voltage (Note4) Ambient Temperature Junction Temperature Parameter VCC Input Voltage (VCC to GND) Range 4.5 to 13.5 0 to 5.5 0.8 ~ VIN - VDROP -40 to 85 -40 to 125 Unit V V V o o C C Note 3: Refer to the typical application circuit. Note 4: VDROP defined as the VIN -VOUT voltage at VOUT = 98% normal VOUT. The linear regulator must provide the output MOSFET with sufficient Gate-to-Source voltage (VGS = VCC - VOUT) to regulate the output voltage. C opyright © A NPEC Electronics Corp. Rev. A.4 - Sep., 2009 2 www.anpec.com.tw APL5610/A Electrical Characteristics Unless otherwise specified, these specifications apply over VCC = 5/12V, TA = -40 to 85 oC. Typical values are at TA =25oC. Symbol SUPPLY CURRENT ICC ISD VCC Supply Current VCC Shutdown Current VCC = 12V VCC = 5V VCC = 12V, EN=GND VCC = 5V, EN=GND VCC POR Threshold VCC POR Hysteresis REFERENCE VOLTAGE VREF Reference Voltage Reference Voltage Accuracy Line Regulation FB Input Current ERROR AMPLIFIER Unity Gain Bandwidth Open Loop DC Gain PSRR Power Supply Rejection Ratio VCC = 5/12V VCC =12V, No Load VCC =12V, 100Hz, No Load VCC =12V, IDRV (SOURCE) = 5mA, VFB = 0.6V VCC =5V, IDRV (SOURCE) = 5mA, VFB = 0.6V VCC =12V, IDRV (SINK) = 5mA, VFB = 1V VCC =5V, IDRV (SINK) = 5mA, VFB = 1V VCC =12V, VDRV =6V, VFB = 0.6V VCC =5V, VDRV =2.5V, VFB = 0.6V VCC =12V, VDRV =6V, VFB = 1V VCC =5V, VDRV =2.5V, VFB = 1V 60 50 11.2 2 80 11.5 4.7 0.5 0.8 50 10 40 10 0.8 50 2 1 MHz dB dB V V mA mA VCC = 12V, TA = 25 oC VCC = 12V, TA = 25 oC VCC = 4.5V to 13.2V -0.5 -1.5 -100 0.8 0.5 1.5 100 V % % nA VCC rising 3.8 0.8 0.8 4.0 0.4 1.0 1.0 5 5 4.2 mA µA Parameter Test Conditions Min. APL5610/A Typ. Max. Unit POWER-ON-RESET (POR) V V VDRV (high) DRV High Voltage VDRV (low) DRV Low Voltage IDRV (source) DRV Source Current IDRV (sink) ENABLE VEN (TH) EN Logic High Threshold Voltage EN Hysteresis EN Shutdown Debounce SOFT-START TSS Soft-Start Interval DRV Sink Current VEN rising - - V mV µs µs % µs % % V µs VEN falling - 100 200 300 UNDER-VOLTAGE PROTECTION (UVP) VUV (TH) Under-Voltage Threshold UVP Debounce Interval POWER-OK AND DELAY VPOK (TH) Rising POK Threshold Voltage POK Threshold Hysteresis POK Pull-Low Voltage POK Debounce Interval VCC =12V, VFB rising VCC =12V VCC =12V, POK sinks 4mA VFB1.6) enables the VOUT; forcing the EN low (VEN IOUT(max) 4. Package Thermal Resistance θ(JA): Select a package of MOSFET that can dissipate the heat, θ(JA) < (TJ – TA)/PD, where TJ is the maximum allowable Junction temperature of MOSFET, TA is the ambient temperature, PD is the maximum power dissipation on MOSFET, calculated as below: PD =(VIN(max) – VOUT(min)) x IOUT(max) Power Sequencing (Only for APL5610A) At start-up, it is necessary to ensure that the VIN (the voltage supplied to MOSFET drain), VCC and V EN a re sequenced correctly to avoid erroneous latch-off. To avoid UVP latch-off happened at start-up due to sequencing issues, the key method is the VIN should be larger than the output under-voltage threshold plus the drop through the pass MOSFET when that output is enabled. Figure 1 and 2 show the two types of power on sequence. Figure 1 shows the VCC comes up before the VIN, and then the output would be enabled when the VEN is applied. Figure 2 shows the VIN comes up before the VCC, and then the output can either be enabled with the VCC or VEN. Recommended power on sequence is shown in Figure1 and 2. MOSFET Selection APL5610/A requires an N-channel MOSFET as a pass element. There are some parameters must be considered in selecting a MOFSET, including: Threshold Voltage VTH, RDS(on ), Continuous IDS current and Package Thermal Resistance. The MOSFET selection guidelines are listed as below: 1. Threshold Voltage VTH: Select the MOSFET VTH rating to meet the following equation: VTH < VCC(min) – VOUT(max) VIN VUV(TH) VEN(TH) VEN VOUT VEN(TH) occurs after VUV(TH) is reached Figure 1. APL5610A supply comes up before MOSFET drain supply C opyright © A NPEC Electronics Corp. Rev. A.4 - Sep., 2009 11 www.anpec.com.tw APL5610/A Application Information (Cont.) Power Sequencing (Only for APL5610A) (Cont.) VCC CVCC CVIN VCC VIN VIN VUV(TH) VCC DRV VEN VEN(TH) VOUT VEN(TH) occurs after VUV(TH) is reached APL5610 APL5610A FB GND R1 Figure 2. MOSFET drain supply comes up before APL5610A supply Short Circuit Concerns (Only for APL5610) R2 COUT Load Figure 3 Since the APL5610 UVP function is activated after the VOUT reaches 90% level, any combinations of sequence among VIN, VCC, and VEN are allowable. However, please note that the advantage of none-power-sequencing brings a drawback. If and only if a short circuit condition of output voltage occurs before VIN supply, the UVP won’ be t activated. Thus, the short circuit current persists to flow and could impair the MOSFET. If in your application the short circuit is most likely to be encountered before VIN supply, we suggest you use the APL5610A instead of the APL5610, who can provide this short circuit protection. Nevertheless, if the V IN s upply can provide the OCP protection, this short circuit won’ be an issue in APL5610. t Layout Consideration Figure 3 illustrates the layout. Below is a checklist for your layout: 1. Please place the input capacitor CVCC close to the VCC pin. 2. Please place the CVIN close to the MOSFET’ drain. s 3. Layout a copper plane for N-channel MOSFET’ drain s to improve the heat dissipation. 4. Output capacitor COUT for load must be placed near the load as close as possible. 5. Large current paths, the bold lines in figure 3, must have wide tracks. C opyright © A NPEC Electronics Corp. Rev. A.4 - Sep., 2009 12 www.anpec.com.tw APL5610/A Package Information SOT-23-6 D e SEE VIEW A E1 b e1 E c 0.25 GAUGE PLANE SEATING PLANE VIEW A SOT-23-6 INCHES MIN. MAX. 0.057 0.000 0.035 0.012 0.003 0.106 0.102 0.055 0.037 BSC 0.075 BSC 0.60 8° 0.012 0° 0.024 8° 0.006 0.051 0.020 0.009 0.122 0.118 0.071 MAX. 1.45 0.15 1.30 0.50 0.22 3.10 3.00 1.80 A2 A1 A S Y M B O L A A1 A2 b c D E E1 e e1 L 0 MILLIMETERS MIN. 0.00 0.90 0.30 0.08 2.70 2.60 1.40 0.95 BSC 1.90 BSC 0.30 0° Note : 1. Follow JEDEC TO-178 AB. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. C opyright © A NPEC Electronics Corp. Rev. A.4 - Sep., 2009 13 0 L www.anpec.com.tw APL5610/A Carrier Tape & Reel Dimensions OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B d Application A 178.0± 2.00 H 50 MIN. P1 4.0± 0.10 H A T1 T1 8.4+2.00 -0.00 P2 2.0± 0.05 C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00 d 1.5 MIN. D1 1.0 MIN. D 20.2 MIN. T 0.6+0.00 -0.40 W 8.0± 0.30 A0 3.20± 0.20 E1 1.75± 0.10 B0 3.10± 0.20 W F 3.5± 0.05 K0 1.50± 0.20 (mm) SOT-23-6 P0 4.0± 0.10 Devices Per Unit Package Type SOT-23-6 Unit Tape & Reel Quantity 3000 C opyright © A NPEC Electronics Corp. Rev. A.4 - Sep., 2009 14 www.anpec.com.tw APL5610/A Taping Direction Information SOT-23-6 USER DIRECTION OF FEED AAAX AAAX AAAX AAAX AAAX AAAX AAAX Classification Profile C opyright © A NPEC Electronics Corp. Rev. A.4 - Sep., 2009 15 www.anpec.com.tw APL5610/A Classification Reflow Profiles Profile Feature Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time (tP)** within 5°C of the specified classification temperature (Tc) Average ramp-down rate (Tp to Tsmax) Time 25°C to peak temperature Sn-Pb Eutectic Assembly 100 °C 150 °C 60-120 seconds 3 °C/second max. 183 °C 60-150 seconds See Classification Temp in table 1 20** seconds 6 °C/second max. 6 minutes max. Pb-Free Assembly 150 °C 200 °C 60-120 seconds 3°C/second max. 217 °C 60-150 seconds See Classification Temp in table 2 30** seconds 6 °C/second max. 8 minutes max. * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness