APL5611CI-TRG

APL5611/A Low Dropout Linear Regulator Controller Features General Description • Wide Supply Voltage Range from 4.5 to 13.5V • High Output Accuracy Over Operating Temperature The APL5611/A is a low dropout linear regulator controller. The APL5611/A could drive an external N-Channel MOSFET and provide an adjustable output by using an external resistive divider. and Loading Ranges • Fast Transient Response • Power-On-Reset Monitoring on VCC • Programmable Soft-Start • Low Shutdown Current • Enable Control Function • Under-Voltage Protection • Two Versions of IC Available: The APL5611/A integrates various functions. For example, a Power-On-Reset (POR) circuit monitors VCC supply voltage to prevent wrong operations; the function of Under-Voltage Protection (UVP) protects the device from short circuit condition. The soft-start of output voltage is adjustable by the external capacitor on SS pin. Moreover, the APL5611/A can be enabled by other power system; namely, holding the EN above 1.6V enables output and - APL5611: UVP Activated after VOUT is Ready - APL5611A: UVP Activated after VCC is Supplied • SOT-23-6 Package • Lead Free and Green Devices Available pulling the EN under 0.4 disables output. The APL5611/A is available in a SOT-23-6 package. (RoHS Compliant) Simplified Application Circuit Applications VCC VIN • Notebook PC Applications • Motherboard Applications SS VCC DRV APL5611/A VOUT ON EN Pin Configuration OFF APL5611/A FB GND - EN 1 6 VCC GND 2 5 DRV FB 3 EN 4 SS SOT-23-6 (Top View) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2012 1 www.anpec.com.tw APL5611/A Ordering and Marking Information Package Code C : SOT-23-6 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APL5611 APL5611A Assembly Material Handling Code Temperature Range Package Code APL5611 C: L11X X - Date Code APL5611A C: LA1X X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1 ) Symbol VCC Parameter Rating Unit VCC Input Voltage (VCC to GND) -0.3 to 15 V EN, SS, to GND Voltage -0.3 to 7 V VFB FB to GND Voltage -0.3 to 7 V VDRV DRV to GND Voltage TJ TSTG TSDR -0.3 to VCC+0.3 Maximum Junction Temperature Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds V 150 o -65 to 150 o 260 o C C C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristic Symbol θJA Parameter Typical Value Junction-to-Ambient Resistance in Free Air (Note 2) SOT-23-6 Unit o 250 C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions (Note 3) Symbol Parameter VCC VCC Input Voltage (VCC to GND) VEN EN to GND Voltage VOUT VOUT Output Voltage TA Ambient Temperature TJ (Note4) Range Unit 4.5 to 13.5 V 0 to 5.5 V 0.8 ~ VIN - VDROP Junction Temperature V -40 to 85 o -40 to 125 o C C Note 3: Refer to the typical application circuit. Note 4: VDROP defined as the VIN -VOUT voltage at VOUT = 98% normal VOUT. The linear regulator must provide the output MOSFET with sufficient Gate-to-Source voltage (VGS = VCC - VOUT) to regulate the output voltage. Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2012 2 www.anpec.com.tw APL5611/A Electrical Characteristics Unless otherwise specified, these specifications apply over VCC = 5/12V, TA = -40 to 85 oC. Typical values are at TA =25oC. Symbol Parameter APL5611/A Test Conditions Unit Min. Typ. Max. VCC = 12V - 0.8 1.0 VCC = 5V - 0.8 1.0 VCC = 12V, EN=GND - - 5 VCC = 5V, EN=GND - - 5 3.8 4.0 4.2 V - 0.4 - V SUPPLY CURRENT ICC VCC Supply Current ISD VCC Shutdown Current mA µA POWER-ON-RESET (POR) VCC POR Threshold VCC rising VCC POR Hysteresis REFERENCE VOLTAGE VREF Reference Voltage VCC = 12V, TA = 25 oC - 0.8 - V Reference Voltage Accuracy VCC = 12V -1 - 1 % Line Regulation VCC = 4.5V to 13.2V FB Input Current -1.5 - 1.5 % -100 - 100 nA ERROR AMPLIFIER PSRR Unity Gain Bandwidth VCC = 5/12V Open Loop DC Gain VCC =12V, No Load Power Supply Rejection Ratio VCC =12V, 100Hz, No Load VDRV (high) DRV High Voltage VDRV (low) DRV Low Voltage IDRV (source) DRV Source Current IDRV (sink) DRV Sink Current - 2 - MHz 60 80 - dB dB 50 - - VCC =12V, IDRV (SOURCE) = 5mA, VFB = 0.6V 11.2 11.5 - VCC =5V, IDRV (SOURCE) = 5mA, VFB = 0.6V - 4.7 - VCC =12V, IDRV (SINK) = 5mA, VFB = 1V - 0.5 1 VCC =5V, IDRV (SINK) = 5mA, VFB = 1V - 0.8 - VCC =12V, VDRV =6V, VFB = 0.6V - 50 - VCC =5V, VDRV =2.5V, VFB = 0.6V - 10 - VCC =12V, VDRV =6V, VFB = 1V - 40 - VCC =5V, VDRV =2.5V, VFB = 1V - 10 - 0.55 0.8 1.05 V - 50 - mV - 2 - µs - 5 - µA 3 4.5 6 µA 68 75 82 % - 5 - µs V V mA mA ENABLE VEN (TH) EN Logic High Threshold Voltage VEN rising, TA=25oC EN Hysteresis EN Shutdown Debounce VEN falling EN Internal Pull High Current SOFT-START ISS SS Current UNDER-VOLTAGE PROTECTION (UVP) VUV (TH) Under-Voltage Threshold VEN =5V, VFB falling UVP Debounce Interval Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2012 3 www.anpec.com.tw APL5611/A Typical Operating Characteristics Feedback Voltage vs. Junction Temperature Supply Current vs. Supply Voltage 0.50 0.900 0.45 Feedback Voltage (V) Supply Current (mA) 0.875 IC Enabled 0.40 0.35 0.30 0.25 0.20 0.15 IC Disabled 0.10 0.850 0.825 0.800 0.775 0.750 0.725 0.05 0.700 -50 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 25 50 75 100 125 Junction Temperature (oC) Supply Voltage (V) DRV Source Current vs. DRV Voltage DRV Sink Current vs. DRV Voltage 70 45 40 60 35 DRV Sink Current (µA) DRV Sink Current (µA) -25 30 25 20 15 10 VIN = 12V, VFB=1V, TA=25oC 5 50 40 30 20 10 VIN = 12V, VFB=0.75V, TA=25oC 0 0 0 2 4 6 8 10 0 12 DRV Voltage (V) Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2012 2 4 6 8 10 12 DRV Voltage (V) 4 www.anpec.com.tw APL5611/A Operating Waveforms The test condition TA= 25oC unless otherwise specified. Turn On Response Turn Off Response VCC VCC V DRV 1 1 VFB 2 VOUT VDRV 2 VFB 3 3 V OUT 4 4 VCC=5V, VIN =5V, VOUT =1.5V, CIN =33µF/ Electrolytic, C OUT =120µF/Electrolytic, CSS =0.01µF CH1: VCC, 2V/Div, DC CH2: VDRV, 2V/Div, DC CH3: VFB, 0.5V/Div, DC CH4: VOUT, 0.5V/Div, DC TIME: 2ms/Div VCC=5V, VIN =5V, VOUT =1.5V, CIN =33µF/ Electrolytic, C OUT =120µF/Electrolytic, CSS =0.01µF CH1: VCC, 2V/Div, DC CH2: VDRV, 2V/Div, DC CH3: VFB, 0.5V/Div, DC CH4: VOUT, 0.5V/Div, DC TIME: 50ms/Div Load Transient Response-1 Load Transient Response-2 V OUT VOUT 1 1 I LOA D ILOA D 2 2 VCC=5V, VIN =5V, VOUT=1.2V, ILOAD =0-5-0A(rising/falling edge=1A/µs ), CIN =22µF/MLCC, C OUT =100µF/Electrolytic, VCC=5V, VIN =5V, VOUT=1.5V, ILOAD =0-5-0A(rising/falling edge=1A/µs ), CIN =22µF/MLCC, C OUT =22µF/MLCC, CH1: VOUT, 50mV/Div, AC CH2: IOUT, 2A/Div, DC CH1: VOUT, 50mV/Div, AC CH2: IOUT, 2A/Div, DC TIME:100µs/Div TIME:20µs/Div Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2012 5 www.anpec.com.tw APL5611/A Operating Waveforms (Cont.) The test condition TA= 25oC unless otherwise specified. Short Circuit Response Load Transient Response-3 VOUT VDRV 1 V OUT 1 2 IOUT 2 IOUT 3 VCC=5V, VIN =5V, VOUT=1.5V, ILOAD =0-0.2-0A(rising/falling edge=1A/µs ), CIN =22µF/MLCC, C OUT =22µF/MLCC, VCC=5V, VIN =5V, VOUT =1.5V, CIN =22µF/MLCC,COUT =22µF/MLCC, CH1: VDRV, 2V/Div, DC CH2: VOUT, 0.5V/Div, DC CH3: IOUT, 20A/Div, DC CH1: VOUT, 20mV/Div, AC CH2: IOUT, 100mA/Div, DC TIME:100µs/Div Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2012 TIME: 50µs/Div 6 www.anpec.com.tw APL5611/A Pin Description PIN FUNCTION NO. NAME 1 EN 2 GND 3 FB Voltage Feedback Pin. Connecting this pin to an external resistor divider receives the feedback voltage of the regulator. 4 SS Connect this pin to a capacitor for soft-start. 5 DRV This pin drives the gate of an external N-channel MOSFET for linear regulator. 6 VCC Power input pin of the device. The voltage at this pin is monitored for Power-On-Reset purpose. Enable control pin. Pulling the EN high enables the VOUT; forcing the EN low (VEN IOUT(max) 4. Package Thermal Resistance θ(JA): Select a package capacitor is 1µF. of MOSFET that can dissipate the heat, θ(JA) < (TJ –TA)/PD, where TJ is the maximum allowable Junction tempera- Output Capacitor ture of MOSFET, TA is the ambient temperature, PD is the maximum power dissipation on MOSFET, calculated as The APL5611/A needs a proper output capacitor to maintain circuit stability and to improve transient response over temperature and current. In order to insure the cir- below: PD =(VIN(max) –VOUT(min)) x IOUT(max) cuit stability, the proper output capacitor value should be larger than 10µF. With X5R and X7R dielectrics, 22µF is sufficient at all operating temperatures. Power Sequencing (Only for APL5611A) Soft-Start Capacitor At start-up, it is necessary to ensure that the VIN (the voltage supplied to MOSFET drain), VCC and V EN are sequenced correctly to avoid erroneous latch-off. To avoid The soft-start capacitor on SS pin can reduce the inrush current and overshoot of output voltage. The capacitor is UVP latch-off happened at start-up due to sequencing issues, the key method is the VIN should be larger than charge to VCC with a constant 4.5µA (typ.) current source, ISS. This results in a linear charge of the soft-start capacitor the output under-voltage threshold plus the drop through the pass MOSFET when that output is enabled. and thus the output voltage. The soft-start period, tss, ends once the capacitor voltage reaches 0.8V (typ.). The Figure 1 and 2 show the two types of power on sequence. Figure 1 shows the VCC comes up before the VIN, and then soft-start capacitor is calculated using the equation: CSS = (ISS x tSS) / 0.8 Where CSS is the soft-start capacitor. ISS is the soft-start the output would be enabled when the VEN is applied. Figure 2 shows the VIN comes up before the VCC, and then current of SS pin. TSS is the soft-start time you set for your application. the output can either be enabled with the VCC or VEN. Recommended power on sequence is shown in Figure1 and 2. Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2012 10 www.anpec.com.tw APL5611/A Application Information (Cont.) Power Sequencing (Only for APL5611A) (Cont.) VCC VIN VCC CVCC VIN CVIN VUV(TH) VEN(TH) VEN VCC DRV VOUT APL5611 APL5611A VEN(TH) occurs after VUV(TH) is reached R1 FB Figure 1. APL5611A supply comes up before MOSFET drain supply GND VCC VIN R2 COUT Load Figure 3 Layout Consideration VUV(TH) Figure 3 illustrates the layout. Below is a checklist for VEN your layout: VEN(TH) 1. Please place the input capacitor CVCC close to the VCC pin. VOUT 2. Please place the CVIN close to the MOSFET’s drain. 3. Layout a copper plane for N-channel MOSFET’s drain VEN(TH) occurs after VUV(TH) is reached to improve the heat dissipation. 4. Output capacitor COUT for load must be placed near the Figure 2. MOSFET drain supply comes up before APL5611A supply load as close as possible. 5. Large current paths, the bold lines in figure 3, must Short Circuit Concerns (Only for APL5611) have wide tracks. Since the APL5611 UVP function is activated after the VOUT reaches 90% level, any combinations of sequence among VIN, VCC, and VEN are allowable. However, please note that the advantage of none-power-sequencing brings a drawback. If and only if a short circuit condition of output voltage occurs before V IN supply, the UVP won’t be activated. Thus, the short circuit current persists to flow and could impair the MOSFET. If in your application the short circuit is most likely to be encountered before VIN supply, we suggest you use the APL5611A instead of the APL5611, who can provide this short circuit protection. Nevertheless, if the V IN supply can provide the OCP protection, this short circuit won’t be an issue in APL5611. Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2012 11 www.anpec.com.tw APL5611/A Package Information SOT-23-6 -T- D SEATING PLANE < 4 mils e E E1 SEE VIEW A b c 0.25 A L 0 GAUGE PLANE SEATING PLANE A1 A2 e1 VIEW A S Y M B O L SOT-23-6 MILLIMETERS MIN. INCHES MAX. A MAX. MIN. 0.057 1.45 0.00 0.15 0.000 0.006 A2 0.90 1.30 0.035 0.051 b 0.30 0.50 0.012 0.020 A1 c 0.08 0.22 0.003 0.009 D 2.70 3.10 0.106 0.122 E 2.60 3.00 0.102 0.118 E1 1.40 1.80 0.055 e 0.95 BSC e1 L 0 0.071 0.037 BSC 1.90 BSC 0.075 BSC 0.30 0.60 0.012 0° 8° 0° 0.024 8° Note : 1. Follow JEDEC TO-178 AB. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2012 12 www.anpec.com.tw APL5611/A Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SOT-23-6 A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.30 1.75±0.10 3.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.0 MIN. 0.6+0.00 -0.40 3.20±0.20 3.10±0.20 1.50±0.20 4.0±0.10 4.0±0.10 (mm) Devices Per Unit Package Type Unit Quantity SOT-23-6 Tape & Reel 3000 Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2012 13 www.anpec.com.tw APL5611/A Taping Direction Information SOT-23-6 USER DIRECTION OF FEED AAAX AAAX AAAX AAAX AAAX AAAX AAAX Classification Profile Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2012 14 www.anpec.com.tw APL5611/A Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness