APL5912_09

APL5912 0.8V Reference Ultra Low Dropout (0.2V@5A) Linear Regulator Features • • • • • • • • • • • • • • • Ultra Low Dropout - 0.2V (Typical) at 5A Output Current Low ESR Output Capacitor (Multi-layer Chip Capacitors (MLCC)) Applicable 0.8V Reference Voltage High Output Accuracy - ±1.5% Over Line, Load and Temperature Fast Transient Response Adjustable Output Voltage by External Resistors Power-On-Reset Monitoring on Both VCNTL and VIN Pins Internal Soft-Start Current-Limit Protection Under-Voltage Protection Thermal Shutdown with Hysteresis Power-OK Output with a Delay Time Shutdown for Standby or Suspend Mode Simple SOP-8P Package with Exposed Pad Lead Free and Green Devices Available (RoHS Compliant) General Description The APL5912 is a 5A ultra low dropout linear regulator. This product is specifically designed to provide well supply voltage for front-side-bus termination on motherboard and NB applications. The IC needs two supply voltages, a control voltage for the circuitry and a main supply voltage for power conversion, to reduce power dissipation and provide extremely low dropout. The APL5912 integrates many functions. A Power-OnReset (POR) circuit monitors both supply voltages to prevent wrong operations. A thermal shutdown and currentlimit functions protect the device against thermal and current over-loads. A POK indicates the output status with time delay which is set internally. It can control other converter for power sequence. The APL5912 is enabled by other power system. Pulling and holding the EN pin below 0.3V shuts off the output. The APL5912 is available in a SOP-8P package which features small size as SOP-8 and an Exposed Pad to reduce the junction-to-case resistance, being applicable in 2~2.5W applications. Pin Configuration GND FB VOUT VOUT 1 2 3 4 8 7 6 5 VIN EN POK VCNTL VIN Applications SOP-8P (Top View) • • • Front Side Bus VTT (1.2V/5A) Note Book PC Applications Motherboard Applications = Exposed Pad (connected to the VIN plane for better heat dissipation) Copyright © ANPEC Electronics Corp. Rev. A.10 - Oct., 2009 1 www.anpec.com.tw APL5912 Ordering and Marking Information APL5912 Assembly Material Handling Code Temperature Range Package Code Package Code KA : SOP-8P Operating Ambient Temperature Range C : 0 to 70 oC Handing Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device XXXXX - Date Code APL5912 KA : APL5912 XXXXX Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol VCNTL VIN VI/O VPOK PD TJ TSTG TSDR Parameter VCNTL Supply Voltage (VCNTL to GND) VIN Supply Voltage (VIN to GND) EN and FB to GND POK to GND Power Dissipation Junction Temperature Storage Temperature (Note 1) Rating -0.3 ~ 7 -0.3 ~ 3.3 -0.3 ~ VCNTL+0.3 -0.3 ~ 7 3 150 -65 ~ 150 260 Unit V V V V W o o o C C C Maximum Lead Soldering Temperature, 10 Seconds Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA θJC Parameter Junction-to-Ambient Thermal Resistance in Free Air Junction-to-Case Thermal Resistance (Note 3) (Note 2) Typical Value SOP-8P SOP-8P 40 17 Unit o C/W C/W o Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8P is soldered directly on the PCB. Note 3: The “Thermal Pad Temperature” is measured on the PCB copper area connected to the thermal pad of package. 1 2 3 4 8 VIN 7 6 5 Measured Point PCB Copper C opyright © A NPEC Electronics Corp. Rev. A.10 - Oct., 2009 2 www.anpec.com.tw APL5912 Recommended Operating Conditions Symbol VCNTL VIN VOUT IOUT TJ VOUT Output Current Junction Temperature VCNTL Supply Voltage VIN Supply Voltage Output Voltage VCNTL=3.3±5% VCNTL=5.0±5% 0.8 ~ 1.2 0.8 ~ VIN-0.2 0~6 -25 ~ 125 V A o Parameter Range 3.1 ~ 6 1.0 ~ 3.3 Unit V V C Electrical Characteristics Refer to “Typical Application Circuits”. These specifications apply over, VCNTL=5V, VIN=1.5V, VOUT = 1.2V and TA=0 to 70°C, unless otherwise specified. Typical values refer to TA =25°C. Symbol SUPPLY CURRENT ICNTL ISD Parameter Test Conditions APL5912 Min. Typ. Max. Unit VCNTL Supply Current VCNTL Shutdown Current EN = VCNTL, VFB is well regulated EN = GND 0.4 - 1 180 2 380 mA µA POWER-ON-RESET VCNTL POR Threshold VCNTL POR Hysteresis VIN POR Threshold VIN POR Hysteresis OUTPUT VOLTAGE VREF Reference Voltage Output Voltage Accuracy Line Regulation Load Regulation DROPOUT VOLTAGE Dropout Voltage PROTECTION VCNTL=5V, TJ= 25oC ILIM Current Limit VCNTL=5V, TJ= -25 ~ 125 C VCNTL=3.3V, TJ= 25 C VCNTL=3.3V, TJ= -25 ~ 125oC TSD Thermal Shutdown Temperature Thermal Shutdown Hysteresis Under-Voltage Threshold VFB Falling TJ Rising o o VCNTL Rising 2.7 - 2.9 0.4 0.9 0.5 3.1 0.99 - V V V V VIN Rising 0.8 - FB =VOUT IOUT=0A ~ 5A, TJ= -25 ~125oC VCNTL=3.3 ~ 5.5V IOUT=0A ~ 5A IOUT = 5A, VCNTL=5V, TJ= 25oC IOUT = 5A, VCNTL=5V, TJ= -25~125 C o -1.5 -0.13 - 0.8 0.06 +1.5 0.13 0.15 V % %/V % - 0.15 - 0.2 0.25 V V 7 6 6.8 6 - 8 7.8 150 50 0.4 9 8.8 - A A A A o o C C V C opyright © A NPEC Electronics Corp. Rev. A.10 - Oct., 2009 3 www.anpec.com.tw APL5912 Electrical Characteristics (Cont.) Refer to “Typical Application Circuits”. These specifications apply over, VCNTL=5V, VIN=1.5V, VOUT = 1.2V and TA=0 to 70°C, unless otherwise specified. Typical values refer to TA =25°C. Symbol Parameter Test Conditions Min. ENABLE AND SOFT-START EN Logic High Threshold Voltage EN Hysteresis EN Pin Pull-Up Current TSS Soft-Start Interval EN=GND VEN Rising 0.3 0.4 30 10 2 0.5 V mV µA ms APL5912 Typ. Max. Unit POWER-OK AND DELAY VPOK VPNOK POK Threshold Voltage for Power OK POK Threshold Voltage for Power Not OK POK Low Voltage TDELAY POK Delay Time VFB Rising VFB Falling POK sinks 5mA 90% 79% 1 92% 81% 0.25 3 94% 83% 0.4 10 VREF VREF V ms C opyright © A NPEC Electronics Corp. Rev. A.10 - Oct., 2009 4 www.anpec.com.tw APL5912 Typical Operating Characteristics VCNTL Supply Current vs. Junction Temperature 1.0 0.9 Current-Limit vs. Junction Temperature 8.6 VCNTL Supply Current, ICNTL (mA) 0.8 0.7 VCNTL= 5V 8.4 8.2 Current-Limit, ILIM (A) VOUT=1.2V VCNTL=5V 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -50 -25 0 25 50 75 100 125 VCNTL= 3.3V 8 7.8 7.6 7.4 7.2 7 -50 -25 0 25 50 75 100 125 Junction Temperature (°C) VCNTL=3.3V Junction Temperature (°C) Dropout Voltage vs. Output Current 250 VCNTL=3.3V VOUT=1.2V TJ=125°C Dropout Voltage vs. Output Current 200 VCNTL=5V VOUT=1.2V TJ=125°C TJ=75°C TJ=25°C 200 Dropout Voltage (mV) 150 TJ=25°C Dropout Voltage (mV) TJ=75°C 150 100 100 TJ=0°C TJ=0°C 50 TJ=-25°C 50 TJ=-25°C 0 0 1 2 3 4 5 0 0 1 2 3 4 5 Output Current, lOUT(A) Output Current, lOUT(A) C opyright © A NPEC Electronics Corp. Rev. A.10 - Oct., 2009 5 www.anpec.com.tw APL5912 Typical Operating Characteristics Reference Voltage vs. Junction Temperature 0.808 0.806 0.804 POK Delay Time vs. Junction Temperature 4.5 4.3 4.1 Reference Voltage, VREF (mV) POK Delay Time (ms) 3.9 3.7 3.5 3.3 3.1 2.9 0.802 0.800 0.798 0.796 0.794 0.792 -50 -25 0 25 50 75 100 125 VCNTL=5V VCNTL=3.3V 2.7 2.5 -50 -25 0 25 50 75 100 125 Junction Temperature (°C) Junction Temperature (°C) VCNTL PSRR 0.00 -10.00 VCNTL = 4.5V~5.5V VIN = 1.5V VOUT = 1.2V IOUT = 5A CIN = 100µF COUT = 330µF(ESR=30mΩ) VIN PSRR 0 VCNTL = 5V VIN = 1.5V(lower bound) VINPK-PK = 100mV CIN = 47µF COUT = 330µF(30m ohm) IOUT = 5A VOUT = 1.2V -10 Ripple Rejection (dB) -20.00 -30.00 -40.00 -50.00 -60.00 -70.00 -20 Amplitude (dB) -30 -40 -50 -60 100 1000 10000 100000 1000000 100 1000 10000 100000 1000000 Frequency (Hz) Frequency (Hz) C opyright © A NPEC Electronics Corp. Rev. A.10 - Oct., 2009 6 www.anpec.com.tw APL5912 Operating Waveforms Test Circuit R4 C2 1µF 5 2.2 L1 1µH +5V C8 R8 8.2K 470pF 7 VCC BOOT OCSET 2 8 1 D1 1N4148 C3 1µF C4 470µF x2 C9 47µF CVCNTL 1µF VCNTL +5V POK 6 Q3 UGATE C6 0.1µF Q1 APM2014N L2 3.3µH VIN +1.5V C5 1000µF x2 VCNTL 5 Shutdown 6 PHASE VIN POK VOUT 7 3 4 R3 1K U2 APW7057 FB 4 LGATE GND Q2 APM2014N CIN 100µF VOUT +1.2V/5A COUT 220µF R5 1.75k EN 8 Enable VOUT U1 APL5912 2 EN FB GND R2 2K 1 1. Load transient Response 1.1 Using an Output Capacitor with ESR≥18mΩ - COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V - IOUT = 10mA to 5A to 10mA, Rise time = Fall time = 1µs IOUT = 10mA ->5A 3 R1 1K R7 2K C7 0.1µF R6 0 C1 33nF IOUT = 10mA -> 5A ->10mA R1=1kΩ, R2=2kΩ, C1=33nF IOUT = 5A ->10mA 1 VOUT 1 VOUT 1 VOUT IOUT IOUT IOUT 2 2 2 Ch1 : VOUT, 50mV/Div Ch2 : IOUT, 2A/Div Time : 2µs/Div Ch1 : VOUT, 50mV/Div Ch2 : IOUT, 2A/Div Time : 20µs/Div Ch1 : VOUT, 50mV/Div Ch2 : IOUT, 2A/Div Time : 2µs/Div C opyright © A NPEC Electronics Corp. Rev. A.10 - Oct., 2009 7 www.anpec.com.tw APL5912 Operating Waveforms (Cont.) 1.2 Using an MLCC as the Output Capacitor - COUT = 22µF/6.3V (ESR = 3mΩ), CIN = 22µF/6.3V - IOUT = 10mA to 5A to 10mA, Rise time = Fall time = 1µs IOUT = 10mA -> 5A IOUT = 10mA -> 5A ->10mA R1=39kΩ, R2=78kΩ, R3=30nF IOUT = 5A ->10mA 1 VOUT 1 VOUT 1 VOUT IOUT IOUT IOUT 2 2 2 Ch1 : VOUT, 100mV/Div Ch2 : IOUT, 2A/Div Time : 2µs/Div Ch1 : VOUT, 100mV/Div Ch2 : IOUT, 2A/Div Time : 20µs/Div Ch1 : VOUT, 100mV/Div Ch2 : IOUT, 2A/Div Time : 2µs/Div 2. Power ON and Power OFF : - VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V - COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL = 1Ω Power ON VIN Ch1 VOUT Ch2 VOUT VOUT VCNTL VPOK Ch3 Ch4 Ch3 Ch4 Ch2 Ch1 Power OFF VIN VIN VCNTL VCNTL VPOK VPOK Ch1 : VIN, 1V/div Ch2 : VOUT,1V/div Ch3 : VPOK,1V/div Ch4 : VCNTL,2V/div Time : 10ms/div Ch1 : VIN, 1V/div Ch2 : VOUT, 1V/div Ch3 : VPOK, 1V/div Ch4 : VCNTL, 2V/div Time : 10ms/div C opyright © A NPEC Electronics Corp. Rev. A.10 - Oct., 2009 8 www.anpec.com.tw APL5912 Operating Waveforms (Cont.) 3. Shutdown and Enable : - VIN = 1.5V, VCNTL = 5V, VOUT = 1.2V - COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL = 1Ω Shutdown Ch1 Enable Ch1 VEN VEN VEN VEN VOUT VOUT Ch2 Ch2 VOUT VOUT IIOUT OUT Ch3 Ch3 IIOUT OUT VPOK VPOK Ch4 Ch4 VPOK VPOK Ch1 : VEN, 5V/div Ch2 : VOUT, 1V/div Ch3 : IOUT, 1A/div Ch4 : VPOK, 1V/div Time : 1ms/div Ch1 : VEN, 5V/div Ch2 : VOUT, 1V/div Ch3 : IOUT, 1A/div Ch4 : VPOK, 1V/div Time : 1ms/div 4. POK Delay : - VIN = 1.5V, VCNTL = 5V, VOUT = 1.2V - COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL = 1Ω VIN VIN Ch1 POK Delay VOUT VOUT Ch2 VPOK VPOK Ch3 Ch1 : VIN, 5V/div Ch2 : VOUT, 1V/div Ch3 : VPOK, 1V/div Time : 1ms/div C opyright © A NPEC Electronics Corp. Rev. A.10 - Oct., 2009 9 www.anpec.com.tw APL5912 Pin Description PIN NO. 1 NAME GND Ground pin of the circuitry. All voltage levels are measured with respect to this pin. Connecting this pin to an external resistor divider receives the feedback voltage of the regulator. The output voltage set by the resistor divider is determined by : R1   VOUT = 0.8 ⋅ 1 +   R2    where R1 is connected from VOUT to FB with Kelvin sensing and R2 is connected from FB to GND. A bypass capacitor may be connected with R1 in parallel to improve load transient response. Output of the regulator. Please connect Pin 3 and 4 together using wide tracks. It is necessary to connect a output capacitor with this pin for closed-loop compensation and improve transient responses. Main supply input pins for power conversions. The Exposed Pad provides a very low impedance input path for the main supply voltage. Please tie the Exposed Pad and VIN Pin (Pin 8) together to reduce the dropout voltage. The voltage at this pins is monitored for Power-On-Reset purpose. Power input pin of the control circuitry. Connecting this pin to a +5V (recommended) supply voltage provides the bias for the control circuitry. The voltage at this pin is monitored for Power-On-Reset purpose. Power-OK signal output pin. This pin is an open-drain output used to indicate status of output voltage by sensing FB voltage. This pin is pulled low when the rising FB voltage is not above the VPOK threshold or the falling FB voltage is below the VPNOK threshold, indicating the output is not OK. Enable control pin. Pulling and holding this pin below 0.3V shuts down the output. When re-enabled, the IC undergoes a new soft-start cycle. When leave this pin open, an internal current source 10µA pulls this pin up to VCNTL voltage, enabling the regulator. Main supply input pins for power conversions. The Exposed Pad provides a very low impedance input path for the main supply voltage. Please tie the Exposed Pad and VIN Pin (Pin 8) together to reduce the dropout voltage. The voltage at this pins is monitored for Power-On-Reset purpose. FUNCTION 2 FB 3,4 VOUT 5 VIN 6 VCNTL 7 POK 8 EN - Exposed Pad Block Diagram EN VCNTL VIN PowerOn-Reset Soft-Start and Control Logic UV 0.4V VREF 0.8V Thermal Limit EAMP VOUT FB POK 90% VREF Delay Current Limit GND POK C opyright © A NPEC Electronics Corp. Rev. A.10 - Oct., 2009 10 www.anpec.com.tw APL5912 Typical Application Circuit 1. Using an Output Capacitor with ESR≥18mΩ CCNTL 1µF VCNTL +5V R3 1k POK 7 POK VCNTL VIN VOUT VOUT 5 3 4 2 R2 2k R1 1k CIN 100µF VIN +1.5V EN Enable 8 APL5912 EN GND 1 FB 6 VOUT +1.2V / 5A COUT 220µF C1 33nF (in the range of 12 ~ 48nF) 2. Using an MLCC as the Output Capacitor CCNTL 1µF 6 R4 10 (in the range of 5.1~15Ω) VCNTL +5V VIN +1.5V R3 1k POK 7 VCNTL POK VIN VOUT VOUT 5 3 4 CIN 22µF APL5912 EN 8 EN GND 1 FB 2 COUT 22µF R2 78k R1 39k C1 30pF VOUT +1.2V / 5A Enable VOUT(V) 1.05 1.5 1.8 R1 (kΩ) 43 27 15 R2 (kΩ) 137.6 30.86 12 C1 (pF) 27 36 68 C opyright © A NPEC Electronics Corp. Rev. A.10 - Oct., 2009 11 www.anpec.com.tw APL5912 Function Description Power-On-Reset A Power-On-Reset (POR) circuit monitors both input voltages at VCNTL and VIN pins to prevent wrong logic controls. The POR function initiates a soft-start process after the two supply voltages exceed their rising POR threshold voltages during powering on. The POR function also pulls low the POK pin regardless the output voltage when the VCNTL voltage falls below its falling POR threshold. Internal Soft-Start An internal soft-start function controls rising rate of the output voltage to limit the current surge at start-up. The typical soft-start interval is about 2ms. Output Voltage Regulation An error amplifier works with a temperature-compensated 0.8V reference and an output NMOS regulates output to the preset voltage. The error amplifier is designed with h igh bandwidth and DC gain provides very fast transient response and less load regulation. It compares the reference with the feedback voltage and amplifies the difference to drive the output NMOS which provides load current from VIN to VOUT. Current-Limit The APL5912 monitors the current via the output NMOS and limits the maximum current to prevent load and APL5912 from damages during overload or short-circuit conditions. Under-Voltage Protection (UVP) The APL5912 monitors the voltage on FB pin after softstart process is finished. Therefore, the UVP is disable during soft-start. When the voltage on FB pin falls below the under-voltage threshold, the UVP circuit shuts off the output immediately. After a while, the APL5912 starts a new soft-start to regulate output. Thermal Shutdown A thermal shutdown circuit limits the junction temperature of APL5912. When the junction temperature exceeds +150°C, a thermal sensor turns off the output NMOS, allowing the device to cool down. The regulator regulates C opyright © A NPEC Electronics Corp. Rev. A.10 - Oct., 2009 12 www.anpec.com.tw the output again through initiation of a new soft-start cycle after the junction temperature cools by 50oC, resulting in a pulsed output during continuous thermal overload conditions. The thermal shutdown is designed with a 50oC hysteresis to lower the average junction temperature during continuous thermal overload conditions, extending lifetime of the device. For normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed +125°C. Enable Control The APL5912 has a dedicated enable pin (EN). A logic low signal (VEN< 0.3V) applied to this pin shuts down the output. Following a shutdown, a logic high signal re-enables the output through initiation of a new soft-start cycle. Left open, this pin is pulled up by an internal current source (10µA typical) to enable operation. It’ not necessary to use s an external transistor to save cost. Power-OK and Delay The APL5912 indicates the status of the output voltage by monitoring the feedback voltage (VFB) on FB pin. As the VFB r ises and reaches the rising Power-OK threshold (VPOK), an internal delay function starts to perform a delay time. At the end of the delay time, the IC turns off the internal NMOS of the POK to indicate the output is OK. As the VFB falls and reaches the falling Power-OK threshold (VPNOK), the IC immediately turns on the NMOS of the POK to indicate the output is not OK without a delay time. APL5912 Application Information Power Sequencing The power sequencing of VIN and VCNTL is not necessary to be concerned. However, do not apply a voltage to VOUT for a long time when the main voltage applied at VIN is not present. The reason is the internal parasitic diode from VOUT to VIN conducts and dissipates power without protections due to the forward-voltage Output Capacitor The APL5912 requires a proper output capacitor to maintain stability and improve transient response over temperature and current. The output capacitor selection is to select proper ESR (equivalent series resistance) and capacitance of the output capacitor for good stability and load transient response. The APL5912 is designed with a programmable feedback compensation adjusted by an external feedback network for the use of wide ranges of ESR and capacitance in all applications. Ultra-low-ESR capacitors (such as ceramic chip capacitors) and low-ESR bulk capacitors (such as solid tantalum, POSCap, and Aluminum electrolytic capacitors) can all be used as an output capacitor. The value of the output capacitors can be increased without limit. During load transients, the output capacitors, depending on the stepping amplitude and slew rate of load current, are used to reduce the slew rate of the current seen by the APL5912 and help the device to minimize the variations of output voltage for good transient response. For the applications with large stepping load current, the lowESR bulk capacitors are normally recommended. Decoupling ceramic capacitors must be placed at the load and ground pins as close as possible and the impedance of the layout must be minimized. R2(kΩ) = R1(kΩ) ⋅ capacitors) and low-ESR bulk capacitors (such as solid tantalum, POSCap, and Aluminum electrolytic capacitors) can all be used as an input capacitor of VIN. For most applications, the recommended input capacitance of VIN is 10 µF at least. If the drop of the input voltage is not cared, the input capacitance can be less than 10µF. More capacitance reduces the variations of the input voltage of VIN pin. Feedback Network Figure 1 shows the feedback network among VOUT, GND, and FB pins. It works with the internal error amplifier to provide proper frequency response for the linear regulator. The ESR is the equivalent series resistance of the output capacitor. The COUT i s ideal capacitance in the output capacitor. The VOUT is the setting of the output voltage. VOUT V OUT APL5912 R1 C1 ESR C OUT R2 V ERR EAMP VREF FB V FB Figure 1 The feedback network selection, depending on the values of the ESR and COUT, has been classified into three conditions : • Condition 1 : Large ESR ( ≥18mΩ) - Select the R1 in the range of 400Ω ~ 2.4kΩ - Calculate the R2 as the following: 0.8(V) .......... (1) VOUT(V) - 0.8(V) Input Capacitor The APL5912 requires proper input capacitors to supply current surge during stepping load transients to prevent the input rail from dropping. Because the parasitic inductor from the voltage sources or other bulk capacitors to the VIN pin limit the slew rate of the surge currents, more parasitic inductance needs more input capacitance. Ultra-low-ESR capacitors (such as ceramic chip C opyright © A NPEC Electronics Corp. Rev. A.10 - Oct., 2009 13 - Calculate the C1 as the following: 10 ⋅ VOUT(V) VOUT(V) ≤ C1(nF) ≤ 40 ⋅ ...... (2) R1(kΩ ) R1(kΩ ) • Condition 2 : Middle ESR - Calculate the R1 as the following: R1(kΩ) = 1500 − 37.5 ⋅ VOUT(V) + 30 ......... (3) ESR(mΩ) www.anpec.com.tw APL5912 Application Information (Cont.) Feedback Network (Cont.) Select a proper R1(selected) to be a little larger than the calculated R1. - Calculate the C1 as the following: C1(pF) = [ESR(mΩ) + 50] ⋅ COUT(µF) ................... (4) R1(kΩ) The reason to have three conditions described above is to optimize the load transient responses for all kinds of the output capacitor. For stability only, the Condition 2, regardless of equation (5), is enough for all kinds of output capacitor. PCB Layout Consideration (See Figure 2) 1. Please solder the Exposed Pad and VIN together on the PCB. The main current flow is through the exposed pad. 2. Please place the input capacitors for VIN and VCNTL pins near pins as close as possible. 3. Ceramic decoupling capacitors for load must be placed near the load as close as possible. 4. To place APL5912 and output capacitors near the load is good for performance. 5. The negative pins of the input and output capacitors and the GND pin of the APL5912 are connected to the ground plane of the load. 6. Please connect PIN 3 and 4 together by a wide track or plane on the Top layer. 7. Large current paths must have wide tracks. 8. See the Typical Application - Connect the one pin of the R2 to the GND of APL5912. VCNTL CCNTL VCNTL VIN APL5912 VOUT VOUT C1 FB GND R2 COUT R1 Load VIN VOUT CIN Where R1=R1(selected) Select a proper C1 (selected) to be a little smaller than the calculated C1. - The C1 calculated from equation (4) must meet the following equation :    37.5 ⋅ VOUT(V)  50 C1(pF) ≥ 5.1 ⋅ 1 +  ⋅ 1 +  .. (5) R1(kΩ)  ESR(mΩ)    Where R1=R1(calculated) from equation (3) If the C1(calculated) can not meet the equation (5), please use the Condition 3. - Use equation (2) to calculate the R2. • Condition 3: Low ESR (eg. Ceramic Capacitors) - Calculate the R1 as the following: R1(k Ω ) = (5.9 ⋅ ESR(m Ω ) + 294) ⋅ COUT (µF) − 37.5 ⋅ VOUT (V) .. (6) Select a proper R1(selected) to be a little larger than the calculated R1. The minimum selected R1 is equal to 1k Ω w hen the calculated R1 is smaller than 1k or negative. - Calculate the C1 as the following : C1(pF) =  37.5 ⋅ VOUT(V)  (0.17 ⋅ ESR(mΩ) + 8.5) ⋅ COUT(µF) ⋅ 1 +  .. (7) R1(kΩ)   Where R1=R1(selected) Select a proper C1(selected) to be a little smaller than the calculated C1. - The C1 calculated from equation (7) must meet the following equation :  1.25 ⋅ VOUT(V)  C1(pF) ≥ 0.033 +  ⋅ ESR(mΩ) ⋅ COUT(µF) .. (8) R1(kΩ)   Figure 2 - Connect the one pin of R1 to the Pin 3 of APL5912 Where R1=R1(calculated) from equation (6) If the C1(calculated) can not meet the equation (8), please use the Condition 2. - Use equation (2) to calculate the R2. C opyright © A NPEC Electronics Corp. Rev. A.10 - Oct., 2009 14 - Connect the one pin of C1 to the Pin 3 of APL5912 www.anpec.com.tw APL5912 Application Information (Cont.) Thermal Consideration See Figure 3. The SOP-8P is a cost-effective package featuring a small size like a standard SOP-8 and a bottom exposed pad to minimize the thermal resistance of the package, being applicable to high current applications. The exposed pad must be soldered to the top VIN plane. The copper of the VIN plane on the Top layer conducts heat into the PCB and air. Please enlarge the area to reduce the case-to-ambient resistance (θCA). 102 mil 1 2 118 mil 8 3 4 SOP-8P 7 6 5 Top VOUT plane Ambient Air Die Exposed Pad Top VIN plane PCB Figure 3 Recommended Minimum Footprint 0.024 0.072 0.118 1 2 0.050 3 4 Unit : Inch 8 7 6 5 0.138 0.212 C opyright © A NPEC Electronics Corp. Rev. A.10 - Oct., 2009 15 www.anpec.com.tw APL5912 Package Information SOP-8P D SEE VIEW A D1 THERMAL PAD E2 E1 E h X 45o e b c A2 A A1 0.25 GAUGE PLANE SEATING PLANE L VIEW A S Y M B O L A A1 A2 b c D D1 E E1 E2 e h L 0 0.25 0.40 0C o SOP-8P MILLIMETERS MIN. MAX. 1.60 0.00 1.25 0.31 0.17 4.80 2.50 5.80 3.80 2.00 1.27 BSC 0.50 1.27 8C o MIN. θ INCHES MAX. 0.063 0.000 0.049 0.51 0.25 5.00 3.50 6.20 4.00 3.00 0.012 0.007 0.189 0.098 0.228 0.150 0.079 0.050 BSC 0.010 0.016 0C o 0.15 0.006 0.020 0.010 0.197 0.138 0.244 0.157 0.118 0.020 0.050 8oC Note : 1. Followed from JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. C opyright © A NPEC Electronics Corp. Rev. A.10 - Oct., 2009 16 www.anpec.com.tw APL5912 Carrier Tape & Reel Dimensions OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B d Application A 330.0± 2.00 H 50 MIN. P1 8.0± 0.10 H A T1 T1 12.4+2.00 -0.00 P2 2.0± 0.05 C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00 d 1.5 MIN. D1 1.5 MIN. D 20.2 MIN. T 0.6+0.00 -0.40 W W E1 F 5.5± 0.05 K0 2.10± 0.20 (mm) 12.0± 0.30 1.75± 0.10 A0 6.40± 0.20 B0 5.20± 0.20 SOP-8P P0 4.0± 0.10 Devices Per Unit Package Type SOP- 8P Unit Tape & Reel Quantity 2500 C opyright © A NPEC Electronics Corp. Rev. A.10 - Oct., 2009 17 www.anpec.com.tw APL5912 Taping Direction Information SOP-8P USER DIRECTION OF FEED Classification Profile C opyright © A NPEC Electronics Corp. Rev. A.10 - Oct., 2009 18 www.anpec.com.tw APL5912 Classification Reflow Profiles Profile Feature Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time (tP)** within 5°C of the specified classification temperature (Tc) Average ramp-down rate (Tp to Tsmax) Time 25°C to peak temperature Sn-Pb Eutectic Assembly 100 °C 150 °C 60-120 seconds 3 °C/second max. 183 °C 60-150 seconds See Classification Temp in table 1 20** seconds 6 °C/second max. 6 minutes max. Pb-Free Assembly 150 °C 200 °C 60-120 seconds 3°C/second max. 217 °C 60-150 seconds See Classification Temp in table 2 30** seconds 6 °C/second max. 8 minutes max. * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness