APL5913-KAC-TRL

APL5913 0.8V Reference Ultra Low Dropout (0.25V@3A) Linear Regulator Features • • • • • • • • • • • • • • • Ultra Low Dropout - 0.25V(typical) at 3A Output Current Low ESR Output Capacitor (Multi-layer Chip Capacitors (MLCC)) Applicable 0.8V Reference Voltage High Output Accuracy - ±1.5% over Line, Load and Temperature Fast Transient Response Adjustable Output Voltage by External Resistors Power-On-Reset Monitoring on Both VCNTL and VIN Pins Internal Soft-Start Current-Limit Protection Under-Voltage Protection Thermal Shutdown with Hysteresis Power-OK Output with a Delay Time Shutdown for Standby or Suspend Mode Simple SOP-8-P Package with Exposed Pad Lead Free Available (RoHS Compliant) General Description The APL5913 is a 3A ultra low dropout linear regulator. This product is specifically designed to provide well supply volatage for front-side-bus termination on motherboards and NB applications. The IC needs two supply voltages, a control voltage for the circuitry and a main supply voltage for power conversion, to reduce power dissipation and provide extremely low dropout. The APL5913 integrates many functions. A Power-OnReset (POR) circuit monitors both supply voltages to prevent wrong operations. A thermal shutdown and current limit functions protect the device against thermal and current over-loads. A POK indicates the output status with time delay which is set internally. It can control other converter for power sequence. The APL5913 can be enabled by other power system. Pulling and holding the EN pin below 0.3V shuts off the output. The APL5913 is available in SOP-8-P package which features small size as SOP-8 and an Exposed Pad to reduce the junction-to-case resistance, being applicable in 2~3W applications. Pin Configuration Applications • • • Front Side Bus VTT (1.2V/3A) Note Book PC Applications Motherboard Applications GND FB VOUT VOUT 1 2 3 4 8 VIN 7 6 5 EN POK VCNTL VIN SOP-8-P (Top View) = Exposed Pad (connected to VIN plane for better heat dissipation) Copyright © ANPEC Electronics Corp. Rev. A.4 - May., 2005 1 www.anpec.com.tw APL5913 Ordering and Marking Information APL5913 Lead Free Code Handling Code Temp. Range Package Code Package Code KA : SOP-8-P Operating Ambient Temp. Range C : 0 to 70°C Handing Code TU : Tube TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device XXXXX - Date Code APL5913 KA : APL5913 XXXXX Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature. Block Diagram EN VCNTL VIN PowerOn-Reset Soft-Start and Control Logic UV Thermal Limit 0.4V VREF 0.8V EAMP VOUT FB POK 90% VREF Current Limit Delay GND POK Copyright © ANPEC Electronics Corp. Rev. A.4 - May., 2005 2 www.anpec.com.tw APL5913 Typical Application Circuit 1. Using an Output Capacitor with ESR≥18mΩ VCNTL +5V VIN +1.5V C CNTL 1uF 6 R3 1k POK 7 VCNTL POK VIN VOUT VOUT 5 C IN 100uF 3 4 APL5913 EN 8 EN GND 1 FB 2 C OUT 220 uF R2 2k R1 1k VOUT +1.2V / 3A Enable C1 33nF (in the range of 12 ~ 48nF) 2. Using an MLCC as the Output Capacitor C CNTL 1uF VCNTL +5V VIN +1.5V 6 R3 1k POK 7 VCNTL POK VIN VOUT VOUT 5 C IN 22uF 3 4 COUT 2 VOUT +1.2V / 3A APL5913 EN 8 22uF R1 39k C1 56pF EN GND 1 FB Enable R2 78k VOUT (V) 1.05 1.5 1.8 R1 (kΩ) 43 27 15 R2 (kΩ) 137.6 30.86 12 C1 (pF) 47 82 150 Copyright © ANPEC Electronics Corp. Rev. A.4 - May., 2005 3 www.anpec.com.tw APL5913 Absolute Maximum Ratings Symbol VCNTL VIN VI/O VPOK PD PPEAK TJ TSTG TSDR VESD Parameter VCNTL Supply Voltage (VCNTL to GND) VIN Supply Voltage (VIN to GND) EN and FB to GND POK to GND Average Power Dissipation Peak Power Dissipation ( 3A 3 Enable R2 2k R1 1k C1 33nF R7 2k C7 0.1uF R6 0 IOUT = 10mA -> 3A ->10mA R1=1kΩ, R2=2k Ω, C1=33nF IOUT = 3A -> 10mA VOUT VOUT VOUT 1 IOUT IOUT IOUT 2 Ch1 : VOUT, 50mV/Div Ch2 : IOUT, 1A/Div Time : 2µS/Div Ch1 : VOUT, 50mV/Div Ch2 : IOUT, 1A/Div Time : 20µS/Div Ch1 : VOUT, 50mV/Div Ch2 : IOUT, 1A/Div Time : 2µS/Div Copyright © ANPEC Electronics Corp. Rev. A.4 - May., 2005 8 www.anpec.com.tw APL5913 Operating Waveforms (Cont.) 1.2 Using an MLCC as the Output Capacitor - COUT = 22µF/6.3V (ESR = 3mΩ ), CIN = 22µF/6.3V - IOUT = 10mA to 3A to 10mA, Rise time = Fall time = 1µS IOUT = 10mA -> 3A IOUT = 10mA -> 3A ->10mA R1=39kΩ, R2=78k Ω C1=56pF VOUT IOUT = 3A -> 10mA VOUT 1 VOUT 1 1 2 IOUT IOUT IOUT 2 2 Ch1 : VOUT, 100mV/Div Ch2 : IOUT, 1A/Div Time : 2µS/Div Ch1 : VOUT, 100mV/Div Ch2 : IOUT, 1A/Div Time : 20µS/Div Ch1 : VOUT, 100mV/Div Ch2 : IOUT, 1A/Div Time : 2µS/Div 2. Power ON / Power OFF : - VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V - COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL=1Ω Power ON VIN Ch1 VOUT Ch2 VCNTL VPOK Ch3 Ch4 Ch3 Ch4 VOUT Ch2 VCNTL VPOK Ch1 VIN Power OFF Ch1 : VIN,1V/div Ch2 : VOUT,1V/div Ch3 : VPOK,1V/div Ch4 : VCNTL ,2V/div Time : 10ms/div Ch1 : V IN,1V/div Ch2 : V OUT,1V/div Ch3 : V POK,1V/div Ch4 : V CNTL,2V/div Time : 10ms/div Copyright © ANPEC Electronics Corp. Rev. A.4 - May., 2005 9 www.anpec.com.tw APL5913 Operating Waveforms (Cont.) 3. Shutdown and Enable : - VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V - COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL=1Ω Shutdown Ch1 VEN Enable Ch1 VEN VOUT Ch2 VOUT Ch2 I OUT Ch3 VPOK Ch4 I OUT Ch3 VPOK Ch4 Ch1 : V EN ,5V/div Ch2 : V OUT,1V/div Ch3 : IOUT,1A/div Ch4 : V POK,1V/div Time : 1ms/div Ch1 : V EN ,5V/div Ch2 : V OUT,1V/div Ch3 : IOUT,1A/div Ch4 : V POK,1V/div Time : 1ms/div 4. POK Delay : - VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V - COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL=1Ω VIN Ch1 POK Delay VOUT Ch2 VPOK Ch3 Ch1 : V IN,1V/div Ch2 : V OUT,1V/div Ch3 : V POK,1V/div Time : 1ms/div Copyright © ANPEC Electronics Corp. Rev. A.4 - May., 2005 10 www.anpec.com.tw APL5913 Functional Pin Description GND (Pin 1) Ground pin of the circuitry. All voltage levels are measured with respect to this pin. FB (Pin 2) Connecting this pin to an external resistor divider receives the feedback voltage of the regulator. The output voltage set by the resistor divider is determined by: R1   V OUT = 0.8 ⋅  1 +  (V)  R2  where R1 is connected from VOUT to FB with Kelvin sensing and R2 is connected from FB to GND. A bypass capacitor may be connected with R1in parallel to improve load transient response. The recommended R2 and R1 are in the range of 100~10kΩ. VOUT (Pin 3,4) Output of the regulator. Please connect Pin 3 and 4 together using wide tracks. It is necessary to connect a output capacitor with this pin for closed-loop compensation and improving transient responses. VIN (Pin 5) and Exposed Pad Main supply input pins for power conversions. The Exposed Pad provide a very low impedance input path for the main supply voltage. Please tie the Exposed Pad and VIN Pin (Pin 8) together to reduce the dropout voltage. The voltage at this pins is monitored for PowerOn Reset purpose. VCNTL (Pin 6) Power input pin of the control circuitry. Connecting this pin to a +5V (recommended) supply voltage provides the bias for the control circuitry. The voltage at this pin is monitored for Power-On Reset purpose. POK (Pin 7) Power-OK signal output pin. This pin is an open-drain output used to indicate status of output voltage by sensing FB voltage. This pin is pulled low when the rising FB voltage is not above the VPOK threshold or the falling FB voltage is below the VPNOK threshold, indicating the output is not OK. EN (Pin 8) Enable control pin. Pulling and holding this pin below 0.3V shuts down the output. When re-enabled, the IC undergoes a new soft-start cycle . Left this pin open, an internal current source 10mA pulls this pin up to VCNTL voltage, enabling the regulator. Functional Description Power-On-Reset A Power-On-Reset (POR) circuit monitors both input voltages at VCNTL and VIN pins to prevent wrong logic controls. The POR function initiates a soft-start process after the two supply voltages exceed their rising POR threshold voltages during powering on. The POR function also pulls low the POK pin regardless the output voltage when the VCNTL voltage falls below it’ s falling POR threshold. Internal Soft-Start An internal soft-start function controls rise rate of the output voltage to limit the current surge at start-up. The typical soft-start interval is about 2mS. Output Voltage Regulation An error amplifier working with a temperaturecompensated 0.8V reference and an output NMOS regulates output to the preset voltage. The error amplifier designed with high bandwidth and DC gain 11 www.anpec.com.tw Copyright © ANPEC Electronics Corp. Rev. A.4 - May., 2005 APL5913 Functional Description (Cont.) Output Voltage Regulation (Cont.) provides very fast transient response and less load regulation. It compares the reference with the feedback voltage and amplifies the difference to drive the output NMOS which provides load current from VIN to VOUT. Current-Limit The APL5913 monitors the current via the output NMOS and limits the maximum current to prevent load and APL5913 from damages during overload or shortcircuit conditions. Under-Voltage Protection (UVP) The APL5913 monitors the voltage on FB pin after soft-start process is finished. Therefore the UVP is disable during soft-start. When the voltage on FB pin falls below the under-voltage threshold, the UVP circuit shuts off the output immediately. After a while, the APL5913 starts a new soft-start to regulate output. Thermal Shutdown A thermal shutdown circuit limits the junction temperature of APL5913. When the junction temperature exceeds +150°C, a thermal sensor turns off the output NMOS, allowing the device to cool down. The regulator regulates the output again through initiation of a new soft-start cycle after the junction temperature cools by 50°C, resulting in a pulsed output during continuous thermal overload conditions. The thermal shutdown designed with a 50oC hysteresis lowers the average junction temperature during continuous thermal overload conditions, extending life time of the device. For normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed +125°C. Enable Control The APL5913 has a dedicated enable pin (EN). A logic low signal (VEN< 0.3V) applied to this pin shuts down the output. Following a shutdown, a logic high signal re-enables the output through initiation of a new softstart cycle. Left open, this pin is pulled up by an internal current source (10µA typical) to enable operation. It’ not necessary to use an external transistor s to save cost. Power-OK and Delay The APL5913 indicates the status of the output voltage by monitoring the feedback voltage (VFB) on FB pin. As the VFB rises and reaches the rising Power-OK threshold (VPOK), an internal delay function starts to perform a delay time. At the end of the delay time, the IC turns off the internal NMOS of the POK to indicate the output is OK. As the VFB f alls and reaches the falling Power-OK threshold (VPNOK), the IC immediately turns on the NMOS of the POK to indicate the output is not OK without a delay time. Application Information Power Sequencing The power sequencing of VIN and VCNTL is not necessary to be concerned. But do not apply a voltage to VOUT for a long time when the main voltage applied at VIN is not present. The reason is the internal parasitic diode from VOUT to VIN conducts and dissipates power without protections due to the forward-voltage. Output Capacitor The APL5913 requires a proper output capacitor to maintain stability and improve transient response over temperature and current. The output capacitor selection is to select proper ESR(equivalent series resistance) and capacitance of the output capacitor for good stability and load transient response. Copyright © ANPEC Electronics Corp. Rev. A.4 - May., 2005 12 www.anpec.com.tw APL5913 Application Information (Cont.) Output Capacitor (Cont.) The APL5913 is designed with a programmable feedback compensation adjusted by an external feedback network for the use of wide ranges of ESR and capacitance in all applications. Ultra-low-ESR capacitors (such as ceramic chip capacitors), low-ESR bulk capacitors (such as solid Tantalum, POSCap, and Aluminum electrolytic capacitors) all can be used as an output capacitor. The value of the output capacitors can be increased without limit. During load transients, the output capacitors, depending on the stepping amplitude and slew rate of load current, are used to reduce the slew rate of the current seen by the APL5913 and help the device to minimize the variations of output voltage for good transient response. For the applications with large stepping load current, the low-ESR bulk capacitors are normally recommended. Decoupling ceramic capacitors must be placed at the load and ground pins as close as possible and the impedance of the layout must be minimized. Input Capacitor The APL5913 requires proper input capacitors to supply current surge during stepping load transients to prevent the input rail from dropping . Because the parasitic inductor from the voltage sources or other bulk capacitors to the VIN pin limit the slew rate of the surge currents. More parasitic inductance needs more input capacitance. Ultra-low-ESR capacitors, such as ceramic chip capacitors, are very good for the input capacitors An aluminum electrolytic capacitor (>100mF, ESR 2000 < 1.6 mm 260 +0 ° C* 260 +0 ° C* 260 +0 ° C* 1 .6 mm – 2.5 mm 260 +0 ° C* 250 +0 ° C* 245 +0 ° C* ≥ 2.5 mm 250 +0 ° C* 245 +0 ° C* 245 +0 ° C* * Tolerance: The device manufacturer/supplier s hall a ssure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0 ° C. For example 260 ° C+0 ° C) at the rated MSL level. Reliability Test Program Test item SOLDERABILITY HOLT P CT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 SEC 1000 Hrs Bias @125° C 168 Hrs, 100% RH, 121° C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 1 00mA Carrier Tape & Reel Dimensions t P P1 D Po E F W Bo Ao Ko D1 Copyright © ANPEC Electronics Corp. Rev. A.4 - May., 2005 18 www.anpec.com.tw APL5913 Carrier Tape & Reel Dimensions(Cont.) T2 J C A B T1 Application A 330 ± 1 B 62 +1.5 D 1.55 +0.1 C 12.75+ 0.15 D1 1.55+ 0.25 J 2 ± 0.5 Po 4.0 ± 0.1 T1 T2 W 12± 0 . 3 Bo P 8± 0.1 Ko E 1.75±0.1 t 12.4 ± 0.2 2 ± 0.2 P1 Ao SOP- 8/-P F 5.5± 1 2.0 ± 0.1 6.4 ± 0.1 5.2± 0. 1 2.1± 0.1 0.3±0.013 (mm) Cover Tape Dimensions Application SOP- 8/-P Carrier Width 12 Cover Tape Width 9.3 Devices Per Reel 2500 Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright © ANPEC Electronics Corp. Rev. A.4 - May., 2005 19 www.anpec.com.tw