APW1683JC-TU

APW1683 3-Channel Power Supply Supervisor Features Over Voltage Protection and Lock Out for ! 3.3 V, 5 V, and 12 V General Description The APW1683 is designed to minimize the external components of personal-computer switching power supply systems. It provides protection circuits, power good indicator, fault protection output FPO and PSON control. OVP (over voltage protection) monitors 3.3V, 5 V, and 12 V (12 V OV detects via V CC terminal). UVP (under voltage protection) monitors 3.3V and 5V. When an OV or UV condition is detected, the PGO (power good output) is set to low and FPO is latched to high. PSON from low to high resets the protection latch. There is a 2.3ms turn-off delay from PSON to FPO . There is no delay during turn on. Power good feature monitors PGI, 3.3V and 5V under voltages, and issues a power good signal when they are ready. • • ! Under Voltage Protection and Lock Out for 3.3 V and 5 V Fault Protection Output with Open Drain Output Stage Open Drain Power Good Output Signal for Power Good Input, 3.3 V and 5 V 300 ms Power Good Delay 2.3 ms PSON Control to FPO Turn-Off Delay • • ! • • • • • • • 38 ms PSON Control Debounce 75 ms Delay for 3.3V and 5V Under Voltage ! Protection 73 µs Width Noise Deglitches Wide Power Supply Voltage Range from 4 V to 15 V Intelligent Under Voltage Protection to Pre vent Instantaneously AC Power Black Out Pin Description PGI GND 1 2 3 4 8 7 6 5 PGO VCC VS5 VS33 Applications • PC Switching Power Supply FPO PSON Ordering Information APW1683 Handling Code Temp. Range Package Code Package Code J : DIP - 8 Temp. Range C : 0 to 70 °C Handling Code TU : Tube ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright  ANPEC Electronics Corp. Rev. P.2 - Aug., 2001 1 www.anpec.com.tw APW1683 Block Diagram VCC VREF + 12 OV POR Reset Vreg VDD=3.5V Bandgap Reference VREF 1.192V RL=100kΩ VS5 R VREF + 5 OV 73µs Debounce 73µs Debounce RR SQ Reset Dominent Latch RTT FPO RL=100kΩ VS33 R VDD Reset 38ms Debounce PSON 2.3 ms Delay EN VREF 3.3 OV + 75ms Delay EN Counter 3.3 UV R R RL=100kΩ VREF + + + PGO EN 300ms Delay Counter GND VREF 5 UV 73µs Debounce 1.15V PGI 0.95V PGI1 + PGI2 150µs Debounce and 4.8ms delay Absolute Maximum Ratings Sym bol V CC VS5, VS33 FPO PSO N PG I PG O TA T STG TL Param eter Supply Voltage 5V and 3.3V Input Voltage(Note 1) Fault Protection O utput Voltage O N/O FF Control Input Voltage(Note 1) Power G ood Input Voltage(Note 1) Power G ood O utput Voltage(Note 1) Am bient Tem perature Range Storage Tem perature R ange Lead Tem perature (Soldering, 10 second) Rating 16 8 16 8 8 8 0 to 70 -65 to +150 260 Unit V V V V V V °C °C °C Note 1: For a short period (