APW6021AKC-TRL

APW6021A Advanced PWM and Triple Linear Power Controllers Functional • 4 Regulated Voltages are provided • Microprocessor Core (1.3V to 3.5V) • AGP Bus (1.5V or 3.3V) • Memory (1.8V) / GTL Bus (1.5V) Applications • Motherboard Power Regulation for Computers General Description The APW6021A provides the power control and protection for four output voltages in high-performance, graphics intensive microprocessor and computer applications. The IC integrates voltage-mode PWM controller and three linear controllers, as well as the monitoring and protection functions into a 28-pin SOIC package. The synchronous-rectified buck converter includes an Intel-compatible , TTL 5-input digital-toanalog converter (DAC)that adjusts the core PWM output voltage from 1.3VDC to 2.05VDC in 0.05V steps and from 2.1VDC to 3.5VDC in 0.1V increments. the precision reference and voltage-mode control provide ±1% static regulation. A TTL-compatible signal applied to the SELECT pin dictates which method of control is used for the AGP bus power : a low state results in linear control of the AGP bus to 1.5V , while a high state transitions the output through a linearly controlled softstart to 3.3V , followed by full enhancement of the external MOSFET to pass the input voltage. The other two linear regulators provide fixed output voltages of 1.5V GTL bus power and 1.8V power for the North/South Bridge core and/or cache memory. These levels are user-adjustable by means of an external resistor divider and pulling the FIX pin low. All linear controllers can employ either N-Channel MOSFETs or bipolar NPNs for the pass transistor. The APW6021A monitors all the output voltages. A single Power Good signal is issued when the core is within ±10% of the DAC setting and all other outputs are above their under-voltage levels. Additional builtin over-voltage protection for the core output uses the lower MOSFET to prevent output voltages above 115% of the DAC setting. The PWM controller’s overcurrent function monitors the output current by using the voltage drop across the upper MOSFET’s rDS(ON) . • • • • Linear Controllers Drives with both MOSFET and Bipolar Series Pass Transistors Fixed or Externally Resistor-Adjustable Linear Outputs (FIX Pin) Voltage-Mode PWM Control Fast PWM Converter Transient Response • High-Bandwidth Error Amplifier • Full 0% to 100% Duty Ratio • Excellent Output Voltage Regulation • Core PWM Output: ± 1% Over Temperature • Other Outputs: ± 3% Over Temperature • TTL-Compatible 5- Bit DAC Microprocessor Core Output Voltage Selection • Shutdown Feature Removed When All Inputs High • Wide Range - 1.3VDC to 3.5 VDC • • Power-Good Output Voltage Monitor Over-Voltage and Over-Current Fault Monitors • Switching Regulator Does Not Require Extra Current Sensing Element, Uses Upper MOSFET’s r DS(ON) • Small Converter Size • Constant Frequency Operation • 200kHz Free-Running Oscillator; Programmable From 50kHz to Over 1MHz ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright  ANPEC Electronics Corp. Rev. A.1 - Mar., 2001 1 www.anpec.com.tw APW6021A Pin Description DRIVE2 FIX VID4 VID3 VID2 VID1 VID0 PGOOD SD VSEN2 SELECT SS FAULT/ RT VSEN4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC UGATE PHASE LGATE PGND OCSET VSEN1 FB COMP VSEN3 DRIVE3 GND VAUX DRIVE4 Ordering Information APW 6021A L e a d F re e C o d e H a n d lin g C o d e Tem p. Range Package C ode Package C ode K : SO P - 28 Tem p. Range C : 0 to 7 0 ° C H a n d lin g C o d e TU : Tube TR : Tape & Reel L e a d F re e C o d e L : L e a d F r e e D e v ic e B la n k : O r ig in a l D e v ic e Absolute Maximum Ratings Symbol VCC VBOOT –VPHASE VI , VO TA TJ TSTG TS Supply Voltage Boot Voltage Input , Output or I/O Voltage Operating Ambient Temperature Range Junction Temperature Range Storage Temperature Range Soldering Temperature Parameter Rating 15 15 GND -0.3 V to VCC +0.3 0 to 70 0 to 125 -65 to +150 300 ,10 seconds Unit V V V °C °C °C °C Copyright  ANPEC Electronics Corp. Rev. A.1 - Mar., 2001 2 www.anpec.com.tw APW6021A Thermal Characteristics Symbol R θJA Parameter Thermal Resistance in Free Air SOIC SOIC (with 3in2 of Copper) Value 75 65 Unit °C/W Block Diagram VSEN3 VAUX Power-on Reset (POR) FIX SD VSEN1 OCSET VCC DRIVE3 DRIVE 4 VSEN 4 DRIVE2 VSEN2 SELECT Copyright  ANPEC Electronics Corp. Rev. A.1 - Mar., 2001 + + + 1.26V × 0 .75 + × 1 .10 VAUX + × 0 .90 LUV 200 µA + LINEAR UNDERVOLTAGE + PGOOD × 1 .15 + VCC DRIVER1 OC1 OV INHIBIT SOFT START & FAULT LOGIC FAULT UGATE + INHIBIT + + - PHASE GATE CONTROL + ERROR AMP1 × 0 .75 VCC DACOUT - + PWM COMP1 PWM1 VCC + - 1.5V or 3.3v OSCILLATOR 28 µA 4.5V TTL D/A CONVERTER (DAC) SYNCH DRIVE LGATE PGND GND FAULT/ RT SS FB COMP VID0 VID1 VID2 VID3 VID4 3 www.anpec.com.tw APW6021A Electrical Characteristics (Recommended operating conditions, Unless otherwise noted) Refer to Block and Simplified Power System Diagrams, and Typical Application Schematic APW6021A Symbol VCC Supply Current ICC Nominal Supply Current UGATE, LGATE, DRIVE2, DRIVE3, and DRIVE4 open Vocset=4.5V Vocset=4.5V Vocset=4.5V Vocset=4.5V 8.2 2.5 0.5 1.26 RT= Open RT= Open 185 200 1.9 215 9 mA Parameter Test Conditions Min. Typ. Max. Unit Power-on Reset Rising VCC Threshold Falling VCC Threshold Rising VAUX Threshold VAUX Threshold Hysteresis Rising VOCSET Threshold Oscillator FOCS ∆VOSC Free Running Frequency Ramp Amplitude kHz VP-P 10.4 V V V V V DAC and Bandgap Reference DAC(VID0-VID4) Input Low Voltage DAC(VID0-VID4) Input High Voltage DACOUT Voltage accuracy VBG Bandgap Reference Voltage Bandgap Reference Tolerance Linear Regulators (OUT2, OUT3, and OUT4) Regulation (All Linears) VREG2 VSEN2 Regulation Voltage VREG3 VSEN3 Regulation Voltage VREG4 VSEN4 Regulation Voltage Under-Voltage Level (VSEN/ VSEN Rising VRENUV VREG) Under-Voltage Hysteresis (VSEN/ VSEN Falling VREG) Output Drive Current (All Liners) VAUX-VDRIVE >0.6V Select < 0.8V 0.8 2.0 -1.0 1.265 -2.5 3 1.5 1.5 1.8 75 7 20 40 +2.5 0.8 +1.0 V V % V % % V V V % % mA Copyright  ANPEC Electronics Corp. Rev. A.1 - Mar., 2001 4 www.anpec.com.tw APW6021A Electrical Characteristics Cont. APW6021A Symbol Parameter Test Conditions Min. Typ. 88 15 COMP=10pF VCC=12V, VUGATE =6V VUGATE1-PHASE =1V VCC=12V, VLGATE =1V VLGATE= 1V 1 3 6 1 3.5 Max. Synchronous PWM Controller Error Amplifier DC Gain GBWP Gain-Bandwidth Product SR Slew Rate PWM Controller Gate Driver IUGATE UGATE Source RUGATE ILGATE RLGATE UGATE Sink LGATE Source LGATE Sink dB MHz V/µs A Ω A Ω Unit Protection VSEN1 Over-Voltage (VSEN1/DACOUT) IOVP FAULT Souring Current IOCSET ISS OCSET1 Current Source Soft Start Current VSEN1 Rising VFAULT/RT=2.0V VOCSET= 4.5VDC 170 115 8.5 200 28 120 % mA µA µA 230 Power Good VSEN1 Upper Threshold (VSEN1/DACOUT) VSEN1 Under Voltage (VSEN1/DACOUT) VSEN1 Hysteresis (VSEN1 /DACOUT) VPGOOD PGOOD Voltage Low VSEN1 Rising VSEN1 Rising Upper /Lower Threshold IPGOOD= -4mA 108 92 2 110 94 % % % 0.8 V Functional Pin Description DRIVE2 (Pin 1) Connect this pin to the gate of an external MOSFET. This pin provides the drive for the AGP regulator’s pass transistor. FIX (Pin 2) Grounding this pin bypasses the internal resistor dividers that set the output voltage of the 1.5V and 1. 8V linear regulators. This way, the output voltage of the two regulators can be adjusted from 1.26V up to the input voltage (+3.3V or +5V) by way of an external resistor divider connected at the corresponding VSEN pin. The new output voltage set by the external resistor divider can be determined using the following formula: VOUT =1.265V × [1+ROUT/ RGND ] where R OUT is the resistor connected from VSEN to the output of the regulator, and RGND is the resistor connected from VSEN to ground. Left open, the FIX pin is pulled high, enabling fixed output voltage operation. Copyright  ANPEC Electronics Corp. Rev. A.1 - Mar., 2001 5 www.anpec.com.tw APW6021A Functional Pin Description Cont. VID4, VID3, VID2, VID1, VID0 (Pins 3, 4, 5, 6 and 7) VID0-4 are the TTL-compatible input pins to the 5-bit DAC. The logic states of these five pins program the internal voltage reference (DACOUT). The level of DACOUT sets the microprocessor core converter output voltage, as well as the corresponding PGOOD and OVP thresholds. PGOOD (Pin 8) PGOOD is an open collector output used to indicate the status of the output voltages. This pin is pulled low when the synchronous regulator output is not within ±10% of the DACOUT reference voltage or when any of the other outputs are below their undervoltage thresholds. The PGOOD output is open for“11111” VID code. SD (Pin 9) This pin shuts down all the outputs. A TTLcompatible, logic level high signal applied at this pin immediately discharges the soft-start capacitor, disabling all the outputs. Dedicated internal circuitry insures the core output voltage does not go negative during this process. When re-enabled, the IC undergoes a new soft-start cycle. Left open, this pin is pulled low by an internal pull-down resistor, enabling operation. VSEN2 (Pin 10) Connect this pin to the output of the AGP linear regulator. The voltage at this pin is regulated to the level predetermined by the logic-level status of the SELECT pin. This pin is also monitored for undervoltage events. SELECT (Pin 11) This pin determines the output voltage of the AGP bus linear regulator. A low TTL input sets the output voltage to 1.5V, and the linear controller regulates this voltage to within ±3%. A high TTL input turns Q3 on continuously , providing a DC current path from the input (+3.3VIN) to the output (VOUT2) of the AGP controller. SS (Pin 12) Connect a capacitor from this pin to ground. This capacitor, along with an internal 28µA current source, sets the soft-start interval of the converter. FAULT / RT (Pin 13) This pin provides oscillator switching frequency adjustment. By placing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased according to the following equation: Fs =200kHz + 5 × 10 6 / RT (kΩ) (RT to GND) Conversely, connecting a resistor from this pin to VCC reduces the switching frequency according to the following equation: Fs =200kHz + 4 × 10 7 / RT (kΩ) (RT to 12V) Nominally, the voltage at this pin is 1.26V. In the event of an over-voltage or over-current condition, this pin is internally pulled to VCC. VSEN4 (Pin 14) Connect this pin to the output of the linear 1.8V regulator. This pin is monitored for undervoltage events. DRIVE4 (Pin 15) Connect this pin to the gate of an external MOSFET. This pin provides the drive for the 1.8V regulator’s pass transistor. VAUX (Pin 16) This pin provides boost current for the linear regulators’ output drives in the event bipolar NPN transistors (instead of N-channel MOSFETs) are employed as pass elements. The voltage at this pin is monitored for power-on reset (POR) purposes. Copyright  ANPEC Electronics Corp. Rev. A.1 - Mar., 2001 6 www.anpec.com.tw APW6021A Functional Pin Description Cont. GND (Pin 17) Signal ground for the IC. All voltage levels are measured with respect to this pin. DRIVE3 (Pin 18) Connect this pin to the gate of an external MOSFET. This pin provides the drive for the 1.5V regulator’s pass transistor. VSEN3 (Pin 19) Connect this pin to the output of the 1.5V linear regulator. This pin is monitored for under-voltage events. COMP and FB (Pin 20, and 21) COMP and FB are the available external pins of the PWM converter error amplifier. The FB pin is the inverting input of the error amplifier. Similarly, the COMP pin is the error amplifier output. These pins are used to compensate the voltage-mode control feedback loop of the synchronous PWM converter. VSEN1 (Pin 22) This pin is connected to the PWM converter’s output voltage. The PGOOD and OVP comparator circuits use this signal to report output voltage status and for over- voltage protection. OCSET (Pin 23) Connect a resistor from this pin to the drain of the respective upper MOSFET. This resistor, an internal 200µA current source, and the upper MOSFET’s onresistance set the converter over-current trip point. An over-current trip cycles the soft-start function. The voltage at this pin is monitored for power-on reset (POR) purposes and pulling this pin low with an open drain device will shutdown the IC. PGND (Pin 24) This is the power ground connection. Tie the synchronous PWM converter’s lower MOSFET source Copyright  ANPEC Electronics Corp. Rev. A.1 - Mar., 2001 7 www.anpec.com.tw to this pin. LGATE (Pin 25) Connect LGATE to the PWM converter ’ s lower MOSFET gate. This pin provides the gate drive for the lower MOSFET. PHASE (Pin 26) Connect the PHASE pin to the PWM converter’s upper MOSFET source. This pin represents the gate drive return current path and is used to monitor the voltage drop across the upper MOSFET for over-current protection. UGATE (Pin 27) Connect UGATE pin to the PWM converter’s upper MOSFET gate. This pin provides the gate drive for the upper MOSFET. VCC (Pin 28) Provide a 12V bias supply for the IC to this pin. This pin also provides the gate bias charge for all the MOSFETs controlled by the IC. The voltage at this pin is monitored for Power-On Reset (POR) purposes. APW6021A Table 1 Output Voltage Program Pin Name VID4 VID3 VID2 VID1 VID0 Nominal Output Voltage Dacout VID4 VID3 Pin Name VID2 VID1 VID0 Nominal Output Voltage Dacout 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.90 1.95 2.00 2.05 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 Simplified Power System Diagram + 5 V IN + 3 . 3 V IN V OUT2 Q1 Q3 Linear Controller APW6021A Q4 V OUT3 Linear Controller Linear Controller Q5 V OUT4 PWM Controller V OUT1 Q2 Copyright  ANPEC Electronics Corp. Rev. A.1 - Mar., 2001 8 www.anpec.com.tw APW6021A Typical Application +12V IN +5V IN L IN C IN VCC OCSET PGOOD POWER GOOD Q1 LOUT1 C OUT1 +3.3V IN V OUT2 1.5V or 3.3V Q3 DRIVE2 VSEN2 C OUT2 TYPEDET SELECT VAUX Q4 V OUT3 1.5V C OUT3 Q5 V OUT4 1.8V C OUT4 C SS DRIVE3 VSEN3 FIX DRIVE4 VSEN4 SS APW6021A UGATE PHASE V OUT1 1.3V to 3.5V LGATE PGND VSEN1 FB COMP Q2 FAULT/ RT VID0 VID1 VID2 VID3 VID4 GND Copyright  ANPEC Electronics Corp. Rev. A.1 - Mar., 2001 9 www.anpec.com.tw APW6021A Package Information SO – 300mil ( Reference JEDEC Registration MS-013) D N H E GAUGE PLANE 123 A e B A1 L 1 Millimeters Dim A A1 B D E e H L N φ1 Min. 2.35 0.10 0.33 Max. 2.65 0.30 0.51 Variations- D Variations SO-16 SO-18 SO-20 SO-24 SO-28 SO-14 Min. 10.10 11.35 12.60 15.20 17.70 8.80 Max. 10.50 11.76 13 15.60 18.11 9.20 Dim A A1 B D E e H L N φ1 Inches Min. 0.093 0.004 0.013 Max. 0.1043 0.0120 0.020 Variations- D Variations SO-16 SO-18 SO-20 SO-24 SO-28 SO-14 Min. 0.398 0.447 0.496 0.599 0.697 0.347 Max. 0.413 0.463 0.512 0.614 0.713 0.362 See variations 7.40 7.60 See variations 0.2914 0.2992 1.27BSC 10 0.40 10.65 1.27 0.050BSC 0.394 0.016 0.419 0.050 See variations 0° 8° See variations 0° 8° Copyright  ANPEC Electronics Corp. Rev. A.1 - Mar., 2001 10 www.anpec.com.tw APW6021A Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Reflow Condition TP (IR/Convection or VPR Reflow) tp C ritical Zone T L to T P R am p-up T e m p e ra tu re TL T sm ax tL T sm in R am p-down ts Preheat 25 t 25 °C to Peak T im e Classificatin Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Large Body Small Body Pb-Free Assembly Large Body Small Body 3°C/second max. 150°C 200°C 60-180 seconds 3°C/second max 217°C 60-150 seconds 245 +0/-5°C 250 +0/-5°C 10-30 seconds 20-40 seconds 6°C/second max. 8 minutes max. www.anpec.com.tw Average ramp-up rate 3°C/second max. (TL to TP) Preheat - Temperature Min (Tsmin) 100°C - Temperature Mix (Tsmax) 150°C - Time (min to max)(ts) 60-120 seconds Tsmax to TL - Ramp-up Rate Tsmax to TL - Temperature(TL) 183°C - Time (tL) 60-150 seconds Peak Temperature(Tp) 225 +0/-5°C 240 +0/-5°C Time within 5°C of actual Peak 10-30 seconds 10-30 seconds Temperature(tp) Ramp-down Rate 6°C/second max. 6 minutes max. Time 25°C to Peak Temperature Copyright  ANPEC Electronics Corp. Rev. A.1 - Mar., 2001 11 Note: All temperatures refer to topside of the package. Measured on the body surface. APW6021A Reliability test program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C , 5 SEC 1000 Hrs Bias @ 125 °C 168 Hrs, 100 % RH , 121°C -65°C ~ 150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms , Itr > 100mA Tape & Reel Dimensions t Po P P1 D E F W Bo Ao Ko D1 T2 J C A B T1 Application SOP- 28 Application SOP- 28 A 330±1 F B 62 ±1.5 D C 12.75 ± 0. 5 D1 1.5+ 0.25 J 2 ± 0.6 Po 4.0 ± 0.1 T1 24.4 ± 0.2 P1 T2 2± 0.2 Ao W 24 ± 0.3 Bo P 12 ± 0.1 Ko E 1.75± 0.1 t 11.5 ± 0.1 1.5 +0.1 2.0 ± 0.1 10.85 ± 0.1 18.34± 0.1 2.97± 0.1 0.35±0.01 (mm) Copyright  ANPEC Electronics Corp. Rev. A.1 - Mar., 2001 12 www.anpec.com.tw APW6021A Cover Tape Dimensions Application SOP- 28 Carrier Width 24 Cover Tape Width 21.3 Devices Per Reel 1000 Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright  ANPEC Electronics Corp. Rev. A.1 - Mar., 2001 13 www.anpec.com.tw